diff --git a/src/V3AstNodes.h b/src/V3AstNodes.h index 6511f1268..727c29c2d 100644 --- a/src/V3AstNodes.h +++ b/src/V3AstNodes.h @@ -142,6 +142,11 @@ public: m_littleEndian = false; setOp2p(new AstConst(fl,msb)); setOp3p(new AstConst(fl,lsb)); } + AstRange(FileLine* fl, VNumRange range) + :AstNode(fl) { + m_littleEndian = range.littleEndian(); + setOp2p(new AstConst(fl,range.hi())); setOp3p(new AstConst(fl,range.lo())); + } ASTNODE_NODE_FUNCS(Range, RANGE) AstNode* msbp() const { return op2p()->castNode(); } // op2 = Msb expression AstNode* lsbp() const { return op3p()->castNode(); } // op3 = Lsb expression diff --git a/src/V3WidthSel.cpp b/src/V3WidthSel.cpp index a84bef91b..d9aab723a 100644 --- a/src/V3WidthSel.cpp +++ b/src/V3WidthSel.cpp @@ -284,6 +284,31 @@ private: newp->length((msb - lsb) + 1); nodep->replaceWith(newp); pushDeletep(nodep); nodep=NULL; } + else if (AstPackArrayDType* adtypep = ddtypep->castPackArrayDType()) { + // SELEXTRACT(array, msb, lsb) -> SEL(array, lsb*width-of-subindex, width-of-subindex*(msb-lsb)) + if (!fromRange.elements() || (adtypep->width() % fromRange.elements())!=0) + adtypep->v3fatalSrc("Array extraction with width miscomputed " + <width()<<"/"<width() / fromRange.elements(); + AstSel* newp = new AstSel (nodep->fileline(), + fromp, + new AstConst(nodep->fileline(),AstConst::Unsized32(),lsb*elwidth), + new AstConst(nodep->fileline(),AstConst::Unsized32(),(msb-lsb+1)*elwidth)); + newp->declRange(fromRange); + newp->declElWidth(elwidth); + if (fromRange.elements() == (msb-lsb+1)) { // Extracting whole of original array + newp->dtypeFrom(adtypep); + } else { + // Need a slice data type, which is an array of the extracted type, but with (presumably) different size + AstNodeDType* vardtypep = new AstPackArrayDType(nodep->fileline(), + adtypep->subDTypep(), // Need to strip off array reference + new AstRange(nodep->fileline(), fromRange)); + v3Global.rootp()->typeTablep()->addTypesp(vardtypep); + newp->dtypeFrom(vardtypep); + } + if (debug()>=9) newp->dumpTree(cout,"--EXTBTn: "); + nodep->replaceWith(newp); pushDeletep(nodep); nodep=NULL; + } else if (ddtypep->castBasicDType()) { if (fromRange.littleEndian()) { // Below code assumes big bit endian; just works out if we swap @@ -324,6 +349,7 @@ private: else { // NULL=bad extract, or unknown node type nodep->v3error("Illegal range select; type already selected, or bad dimension: type is " <prettyName()); + UINFO(1," Related ddtype: "<replaceWith(fromp); pushDeletep(nodep); nodep=NULL; } diff --git a/test_regress/t/t_inst_missing.pl b/test_regress/t/t_inst_missing.pl new file mode 100755 index 000000000..42325c365 --- /dev/null +++ b/test_regress/t/t_inst_missing.pl @@ -0,0 +1,18 @@ +#!/usr/bin/perl +if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2003-2009 by Wilson Snyder. This program is free software; you can +# redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. + +compile ( + v_flags2 => ["--lint-only --Wall -Wno-DECLFILENAME"], + verilator_make_gcc => 0, + make_top_shell => 0, + make_main => 0, + ); + +ok(1); +1; diff --git a/test_regress/t/t_inst_missing.v b/test_regress/t/t_inst_missing.v new file mode 100644 index 000000000..e5291a805 --- /dev/null +++ b/test_regress/t/t_inst_missing.v @@ -0,0 +1,15 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2012 by Wilson Snyder. + +module t (/*AUTOARG*/); + wire ok = 1'b0; + // verilator lint_off PINNOCONNECT + sub sub (.ok(ok), .nc()); + // verilator lint_on PINNOCONNECT +endmodule + +module sub (input ok, input nc); + initial if (ok&&nc) begin end // No unused warning +endmodule diff --git a/test_regress/t/t_struct_portsel.pl b/test_regress/t/t_struct_portsel.pl new file mode 100755 index 000000000..f91289753 --- /dev/null +++ b/test_regress/t/t_struct_portsel.pl @@ -0,0 +1,18 @@ +#!/usr/bin/perl +if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2003 by Wilson Snyder. This program is free software; you can +# redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. + +compile ( + ); + +execute ( + check_finished=>1, + ); + +ok(1); +1; diff --git a/test_regress/t/t_struct_portsel.v b/test_regress/t/t_struct_portsel.v new file mode 100644 index 000000000..d9bbb3040 --- /dev/null +++ b/test_regress/t/t_struct_portsel.v @@ -0,0 +1,106 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2013 by Wilson Snyder. + +module t (/*AUTOARG*/ + // Inputs + clk + ); + input clk; + + integer cyc=0; + reg [63:0] crc; + reg [63:0] sum; + + // Take CRC data and apply to testblock inputs + wire [19:0] in = crc[19:0]; + + /*AUTOWIRE*/ + // Beginning of automatic wires (for undeclared instantiated-module outputs) + wire [19:0] out; // From test of Test.v + // End of automatics + + Test test (/*AUTOINST*/ + // Outputs + .out (out[19:0]), + // Inputs + .in (in[19:0])); + + // Aggregate outputs into a single result vector + wire [63:0] result = {44'h0, out}; + + // Test loop + always @ (posedge clk) begin +`ifdef TEST_VERBOSE + $write("[%0t] cyc==%0d crc=%x result=%x\n",$time, cyc, crc, result); +`endif + cyc <= cyc + 1; + crc <= {crc[62:0], crc[63]^crc[2]^crc[0]}; + sum <= result ^ {sum[62:0],sum[63]^sum[2]^sum[0]}; + if (cyc==0) begin + // Setup + crc <= 64'h5aef0c8d_d70a4497; + sum <= 64'h0; + end + else if (cyc<10) begin + sum <= 64'h0; + end + else if (cyc<90) begin + end + else if (cyc==99) begin + $write("[%0t] cyc==%0d crc=%x sum=%x\n",$time, cyc, crc, sum); + if (crc !== 64'hc77bb9b3784ea091) $stop; + // What checksum will we end up with (above print should match) +`define EXPECTED_SUM 64'hdb7bc61592f31b99 + if (sum !== `EXPECTED_SUM) $stop; + $write("*-* All Finished *-*\n"); + $finish; + end + end + +endmodule + +typedef struct packed { + logic [7:0] cn; + logic vbfval; + logic vabval; +} rel_t; + +module Test (/*AUTOARG*/ + // Outputs + out, + // Inputs + in + ); + + input [19:0] in; + output [19:0] out; + + rel_t [1:0] i; // From ifb0 of ifb.v, ... + rel_t [1:0] o; // From ifb0 of ifb.v, ... + + assign i = in; + assign out = o; + + sub sub + ( + .i (i[1:0]), + .o (o[1:0])); +endmodule + +module sub (/*AUTOARG*/ + // Outputs + o, + // Inputs + i + ); + + input rel_t [1:0] i; + output rel_t [1:0] o; + assign o = i; +endmodule + +// Local Variables: +// verilog-typedef-regexp: "_t$" +// End: