From 5c72f015984d9e2f32c6d608322f979d7750c2a7 Mon Sep 17 00:00:00 2001 From: Wilson Snyder Date: Mon, 30 Mar 2020 18:13:51 -0400 Subject: [PATCH] Fix assertions with unique case inside, #2199. --- Changes | 4 ++ src/V3Assert.cpp | 13 +++--- test_regress/t/t_assert_inside_cond.pl | 21 ++++++++++ test_regress/t/t_assert_inside_cond.v | 46 +++++++++++++++++++++ test_regress/t/t_assert_inside_cond_bad.out | 3 ++ test_regress/t/t_assert_inside_cond_bad.pl | 25 +++++++++++ 6 files changed, 107 insertions(+), 5 deletions(-) create mode 100755 test_regress/t/t_assert_inside_cond.pl create mode 100644 test_regress/t/t_assert_inside_cond.v create mode 100644 test_regress/t/t_assert_inside_cond_bad.out create mode 100755 test_regress/t/t_assert_inside_cond_bad.pl diff --git a/Changes b/Changes index d0db43c5e..33b16aba5 100644 --- a/Changes +++ b/Changes @@ -19,6 +19,10 @@ The contributors that suggested a given feature are shown in []. Thanks! **** Fix duplicate typedefs in generate for, #2205. [hdzhangdoc] +**** Fix MinW portability, #2114. [Sean Cross] + +**** Fix assertions with unique case inside, #2199. [hdzhangdoc] + * Verilator 4.030 2020-03-08 diff --git a/src/V3Assert.cpp b/src/V3Assert.cpp index a108e203c..593cad4c0 100644 --- a/src/V3Assert.cpp +++ b/src/V3Assert.cpp @@ -254,12 +254,15 @@ private: // Not parallel, but harmlessly so. } else { AstNode* propp = NULL; - for (AstCaseItem* itemp = nodep->itemsp(); - itemp; itemp=VN_CAST(itemp->nextp(), CaseItem)) { - for (AstNode* icondp = itemp->condsp(); - icondp!=NULL; icondp=icondp->nextp()) { + for (AstCaseItem* itemp = nodep->itemsp(); itemp; + itemp = VN_CAST(itemp->nextp(), CaseItem)) { + for (AstNode* icondp = itemp->condsp(); icondp; icondp = icondp->nextp()) { AstNode* onep; - if (nodep->casex() || nodep->casez() || nodep->caseInside()) { + if (AstInsideRange* rcondp = VN_CAST(icondp, InsideRange)) { + onep = rcondp->newAndFromInside(nodep->exprp(), + rcondp->lhsp()->cloneTree(true), + rcondp->rhsp()->cloneTree(true)); + } else if (nodep->casex() || nodep->casez() || nodep->caseInside()) { onep = AstEqWild::newTyped(itemp->fileline(), nodep->exprp()->cloneTree(false), icondp->cloneTree(false)); diff --git a/test_regress/t/t_assert_inside_cond.pl b/test_regress/t/t_assert_inside_cond.pl new file mode 100755 index 000000000..90950ed85 --- /dev/null +++ b/test_regress/t/t_assert_inside_cond.pl @@ -0,0 +1,21 @@ +#!/usr/bin/perl +if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +scenarios(simulator => 1); + +compile( + verilator_flags2 => ["-x-assign 0 --assert +define+T_ASSERT_INSIDE_COND"], + ); + +execute( + ); + +ok(1); +1; diff --git a/test_regress/t/t_assert_inside_cond.v b/test_regress/t/t_assert_inside_cond.v new file mode 100644 index 000000000..6f12ec6d7 --- /dev/null +++ b/test_regress/t/t_assert_inside_cond.v @@ -0,0 +1,46 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2020 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 + +module t (/*AUTOARG*/ + // Outputs + hit, + // Inputs + clk + ); + + input clk; + output logic hit; + + logic [31:0] addr; + int cyc; + + initial addr = 32'h380; + + always @ (posedge clk) begin + cyc <= cyc + 1; +`ifdef T_ASSERT_INSIDE_COND + addr <= 32'h380; +`elsif T_ASSERT_INSIDE_COND_BAD + addr <= 32'h389; +`else + `error "Bad test define" +`endif + if (cyc == 9) begin + $write("*-* All Finished *-*\n"); + $finish; + end + end + + always_comb begin + hit = 0; + unique case (addr[11:0]) inside + [12'h380 : 12'h388]: begin + hit = 1; + end + endcase + end + +endmodule diff --git a/test_regress/t/t_assert_inside_cond_bad.out b/test_regress/t/t_assert_inside_cond_bad.out new file mode 100644 index 000000000..5defe9702 --- /dev/null +++ b/test_regress/t/t_assert_inside_cond_bad.out @@ -0,0 +1,3 @@ +[10] %Error: t_assert_inside_cond.v:39: Assertion failed in top.t: synthesis parallel_case, but multiple matches found +%Error: t/t_assert_inside_cond.v:39: Verilog $stop +Aborting... diff --git a/test_regress/t/t_assert_inside_cond_bad.pl b/test_regress/t/t_assert_inside_cond_bad.pl new file mode 100755 index 000000000..d715dbf2e --- /dev/null +++ b/test_regress/t/t_assert_inside_cond_bad.pl @@ -0,0 +1,25 @@ +#!/usr/bin/perl +if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2019 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +scenarios(vlt => 1); + +top_filename("t/t_assert_inside_cond.v"); + +compile( + verilator_flags2 => ["-x-assign 0 --assert +define+T_ASSERT_INSIDE_COND_BAD"], + ); + +execute( + fails => 1, + expect_filename => $Self->{golden_filename}, + ); + +ok(1); +1;