diff --git a/Changes b/Changes
index db26be63a..8535878e6 100644
--- a/Changes
+++ b/Changes
@@ -15,6 +15,8 @@ The contributors that suggested a given feature are shown in []. Thanks!
 
 ****  Fix VCD open with empty filename, #2198. [Julius Baxter]
 
+****  Fix packages as enum base types, #2202. [Driss Hafdi]
+
 
 * Verilator 4.030 2020-03-08
 
diff --git a/src/verilog.y b/src/verilog.y
index f0130d76a..14ac2ec20 100644
--- a/src/verilog.y
+++ b/src/verilog.y
@@ -1788,7 +1788,12 @@ enum_base_typeE<dtypep>:	// IEEE: enum_base_type
 	|	integer_vector_type signingE rangeListE	{ $1->setSignedState($2); $$ = GRAMMARP->addRange($1,$3,true); }
 	//			// below can be idAny or yaID__aTYPE
 	//			// IEEE requires a type, though no shift conflict if idAny
-	|	idAny rangeListE			{ $$ = GRAMMARP->createArray(new AstRefDType($<fl>1, *$1), $2, true); }
+	//			// IEEE: type_identifier [ packed_dimension ]
+	//			// however other simulators allow [ class_scope | package_scope ] type_identifier
+	|	idAny rangeListE
+			{ $$ = GRAMMARP->createArray(new AstRefDType($<fl>1, *$1), $2, true); }
+	|	package_scopeIdFollows idRefDType rangeListE
+			{ $2->packagep($1); $$ = GRAMMARP->createArray($2, $3, true); }
 	;
 
 enum_nameList<nodep>:
diff --git a/test_regress/t/t_typedef_package.pl b/test_regress/t/t_typedef_package.pl
new file mode 100755
index 000000000..1d046ed3f
--- /dev/null
+++ b/test_regress/t/t_typedef_package.pl
@@ -0,0 +1,21 @@
+#!/usr/bin/perl
+if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2003 by Wilson Snyder. This program is free software; you
+# can redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
+
+scenarios(simulator => 1);
+
+compile(
+    );
+
+execute(
+    check_finished => 1,
+    );
+
+ok(1);
+1;
diff --git a/test_regress/t/t_typedef_package.v b/test_regress/t/t_typedef_package.v
new file mode 100644
index 000000000..d3ce84cca
--- /dev/null
+++ b/test_regress/t/t_typedef_package.v
@@ -0,0 +1,24 @@
+// DESCRIPTION: Verilator: Verilog Test module
+//
+// This file ONLY is placed into the Public Domain, for any use,
+// without warranty, 2020 by Driss Hafdi.
+// SPDX-License-Identifier: CC0-1.0
+
+package pkg1;
+   typedef logic [7:0] uint8_t;
+endpackage
+
+package pkg2;
+   typedef enum pkg1::uint8_t {
+      a = 8'd1,
+      b = 8'd2
+   } opts;
+endpackage
+
+module t (/*AUTOARG*/);
+  initial begin
+     $display("%d", pkg2::a);
+     $write("*-* All Finished *-*\n");
+     $finish;
+  end
+endmodule