diff --git a/src/V3LinkResolve.cpp b/src/V3LinkResolve.cpp
index d50262616..d12da2db1 100644
--- a/src/V3LinkResolve.cpp
+++ b/src/V3LinkResolve.cpp
@@ -100,7 +100,7 @@ private:
     virtual void visit(AstSenItem* nodep, AstNUser*) {
 	// Remove bit selects, and bark if it's not a simple variable
 	nodep->iterateChildren(*this);
-	if (AstSel* selp = nodep->sensp()->castSel()) {
+	while (AstNodeSel* selp = nodep->sensp()->castNodeSel()) {
 	    AstNode* fromp = selp->fromp()->unlinkFrBack();
 	    selp->replaceWith(fromp); selp->deleteTree(); selp=NULL;
 	}
diff --git a/test_regress/t/t_mem.v b/test_regress/t/t_mem.v
index 195ad9f12..3b73e234c 100644
--- a/test_regress/t/t_mem.v
+++ b/test_regress/t/t_mem.v
@@ -27,6 +27,13 @@ module t (/*AUTOARG*/
       end
    end
    
+   reg [7:0] memory8_16_4;
+   reg [7:0] memory8_16_5;
+   always @ (memory8_16[4] or memory8_16[5]) begin
+      memory8_16_4 = memory8_16[4];
+      memory8_16_5 = memory8_16[5];
+   end
+
    always @ (posedge clk) begin
       m_we <= 0;
       if (cyc!=0) begin
@@ -47,8 +54,8 @@ module t (/*AUTOARG*/
 	    m_data <= 16'h0bad;
 	 end
 	 if (cyc==5) begin
-	    if (memory8_16[4] != 8'h44) $stop;
-	    if (memory8_16[5] != 8'h55) $stop;
+	    if (memory8_16_4  != 8'h44) $stop;
+	    if (memory8_16_5  != 8'h55) $stop;
 	    if (memory8_16[6] != 8'hfe) $stop;
 	    if (memory8_16[7] != 8'h77) $stop;
 	    $write("*-* All Finished *-*\n");