From 58bc98c82bdba6f568648294bde1d1ebb06cbc4a Mon Sep 17 00:00:00 2001 From: em2machine Date: Sun, 21 Dec 2025 19:19:04 +0100 Subject: [PATCH] rest of common variants --- test_regress/t/t_multidriven_simple2.py | 18 +++++++ test_regress/t/t_multidriven_simple2.v | 62 +++++++++++++++++++++++++ test_regress/t/t_multidriven_simple3.py | 18 +++++++ test_regress/t/t_multidriven_simple3.v | 62 +++++++++++++++++++++++++ test_regress/t/t_multidriven_simple4.py | 18 +++++++ test_regress/t/t_multidriven_simple4.v | 61 ++++++++++++++++++++++++ 6 files changed, 239 insertions(+) create mode 100755 test_regress/t/t_multidriven_simple2.py create mode 100644 test_regress/t/t_multidriven_simple2.v create mode 100755 test_regress/t/t_multidriven_simple3.py create mode 100644 test_regress/t/t_multidriven_simple3.v create mode 100755 test_regress/t/t_multidriven_simple4.py create mode 100644 test_regress/t/t_multidriven_simple4.v diff --git a/test_regress/t/t_multidriven_simple2.py b/test_regress/t/t_multidriven_simple2.py new file mode 100755 index 000000000..c6e56559a --- /dev/null +++ b/test_regress/t/t_multidriven_simple2.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2025 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile(verilator_flags2=["--binary"]) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_multidriven_simple2.v b/test_regress/t/t_multidriven_simple2.v new file mode 100644 index 000000000..15f80e1e5 --- /dev/null +++ b/test_regress/t/t_multidriven_simple2.v @@ -0,0 +1,62 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty. +// SPDX-License-Identifier: CC0-1.0 + +// task writes through an argument (output argument of a task) + +// verilog_format: off +`define stop $stop +`define checkd(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got=%0d exp=%0d (%s !== %s)\n", `__FILE__,`__LINE__, (gotv), (expv), `"gotv`", `"expv`"); `stop; end while(0); +// verilog_format: on + +module mod #()( + input logic sel + ,output logic val +); + + logic l0; + + task automatic do_stuff(output logic q); + q = 1'b1; + endtask + + always_comb begin + l0 = 1'b0; + if (sel) do_stuff(l0); + end + + assign val = l0; + +endmodule + +module m_tb#()(); + + logic sel, val; + + mod m( + .sel(sel) + ,.val(val) + ); + + initial begin + #1; + sel = 'b0; + `checkd(val, 1'b0); + #1; + sel = 'b1; + `checkd(val, 1'b1); + #1; + sel = 'b0; + `checkd(val, 1'b0); + #1; + end + + initial begin + #5; + $write("*-* All Finished *-*\n"); + $finish; + end + +endmodule diff --git a/test_regress/t/t_multidriven_simple3.py b/test_regress/t/t_multidriven_simple3.py new file mode 100755 index 000000000..c6e56559a --- /dev/null +++ b/test_regress/t/t_multidriven_simple3.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2025 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile(verilator_flags2=["--binary"]) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_multidriven_simple3.v b/test_regress/t/t_multidriven_simple3.v new file mode 100644 index 000000000..7ea624d45 --- /dev/null +++ b/test_regress/t/t_multidriven_simple3.v @@ -0,0 +1,62 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty. +// SPDX-License-Identifier: CC0-1.0 + +// function call that writes + +// verilog_format: off +`define stop $stop +`define checkd(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got=%0d exp=%0d (%s !== %s)\n", `__FILE__,`__LINE__, (gotv), (expv), `"gotv`", `"expv`"); `stop; end while(0); +// verilog_format: on + +module mod #()( + input logic sel + ,output logic val +); + + logic l0; + +function automatic void do_func(); + l0 = 1'b1; +endfunction + +always_comb begin + l0 = 1'b0; + if (sel) do_func(); +end + + assign val = l0; + +endmodule + +module m_tb#()(); + + logic sel, val; + + mod m( + .sel(sel) + ,.val(val) + ); + + initial begin + #1; + sel = 'b0; + `checkd(val, 1'b0); + #1; + sel = 'b1; + `checkd(val, 1'b1); + #1; + sel = 'b0; + `checkd(val, 1'b0); + #1; + end + + initial begin + #5; + $write("*-* All Finished *-*\n"); + $finish; + end + +endmodule diff --git a/test_regress/t/t_multidriven_simple4.py b/test_regress/t/t_multidriven_simple4.py new file mode 100755 index 000000000..c6e56559a --- /dev/null +++ b/test_regress/t/t_multidriven_simple4.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2025 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile(verilator_flags2=["--binary"]) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_multidriven_simple4.v b/test_regress/t/t_multidriven_simple4.v new file mode 100644 index 000000000..475c8589b --- /dev/null +++ b/test_regress/t/t_multidriven_simple4.v @@ -0,0 +1,61 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty. +// SPDX-License-Identifier: CC0-1.0 + +// verilog_format: off +`define stop $stop +`define checkd(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got=%0d exp=%0d (%s !== %s)\n", `__FILE__,`__LINE__, (gotv), (expv), `"gotv`", `"expv`"); `stop; end while(0); +// verilog_format: on + +module mod #()( + input logic sel + ,output logic val +); + + logic l0; + + task automatic set1(); l0 = 1'b1; endtask + task automatic set0(); l0 = 1'b0; endtask + + always_comb begin + set0(); + if (sel) begin + set1(); + end + end + + assign val = l0; + +endmodule + +module m_tb#()(); + + logic sel, val; + + mod m( + .sel(sel) + ,.val(val) + ); + + initial begin + #1; + sel = 'b0; + `checkd(val, 1'b0); + #1; + sel = 'b1; + `checkd(val, 1'b1); + #1; + sel = 'b0; + `checkd(val, 1'b0); + #1; + end + + initial begin + #5; + $write("*-* All Finished *-*\n"); + $finish; + end + +endmodule