From 5771ea48ef8cdbf6f937a993310999a9b1583dec Mon Sep 17 00:00:00 2001 From: Wilson Snyder Date: Mon, 14 Jul 2008 10:42:58 -0400 Subject: [PATCH] Fix IMPURE errors due to X-assignment temporary variables. --- Changes | 2 + src/V3Ast.h | 5 +- src/V3AstNodes.h | 3 +- src/V3Task.cpp | 3 +- src/V3Unknown.cpp | 3 +- test_regress/t/t_func_noinl.pl | 17 +++++ test_regress/t/t_func_noinl.v | 115 +++++++++++++++++++++++++++++++++ 7 files changed, 143 insertions(+), 5 deletions(-) create mode 100755 test_regress/t/t_func_noinl.pl create mode 100644 test_regress/t/t_func_noinl.v diff --git a/Changes b/Changes index 04f077caf..01527e68f 100644 --- a/Changes +++ b/Changes @@ -11,6 +11,8 @@ indicates the contributor was also the author of the fix; Thanks! **** Fix verilator_includer not being installed properly. [Holger Waechtler] +**** Fix IMPURE errors due to X-assignment temporary variables. [Steve Tong] + **** Internal changes to how $displays get compiled and executed. * Verilator 3.665 2008/06/25 diff --git a/src/V3Ast.h b/src/V3Ast.h index ba93596b7..b7e0f0c21 100644 --- a/src/V3Ast.h +++ b/src/V3Ast.h @@ -197,7 +197,8 @@ public: TRIWIRE, BLOCKTEMP, MODULETEMP, - STMTTEMP + STMTTEMP, + XTEMP }; enum en m_e; inline AstVarType () {}; @@ -209,7 +210,7 @@ public: "?","GPARAM","LPARAM","GENVAR", "INTEGER","INPUT","OUTPUT","INOUT", "SUPPLY0","SUPPLY1","WIRE","IMPLICIT","REG","TRIWIRE", - "BLOCKTEMP","MODULETEMP","STMTTEMP"}; + "BLOCKTEMP","MODULETEMP","STMTTEMP","XTEMP"}; return names[m_e];}; }; inline bool operator== (AstVarType lhs, AstVarType rhs) { return (lhs.m_e == rhs.m_e); } diff --git a/src/V3AstNodes.h b/src/V3AstNodes.h index 93b2269f8..e32ad2775 100644 --- a/src/V3AstNodes.h +++ b/src/V3AstNodes.h @@ -335,9 +335,10 @@ public: bool isSignal() const { return (varType()==AstVarType::WIRE || varType()==AstVarType::IMPLICIT || varType()==AstVarType::REG || varType()==AstVarType::INTEGER); } bool isTemp() const { return (varType()==AstVarType::BLOCKTEMP || varType()==AstVarType::MODULETEMP - || varType()==AstVarType::STMTTEMP); } + || varType()==AstVarType::STMTTEMP || varType()==AstVarType::XTEMP); } bool isStatementTemp() const { return (varType()==AstVarType::STMTTEMP); } bool isMovableToBlock() const { return (varType()==AstVarType::BLOCKTEMP || isFuncLocal()); } + bool isPure() const { return (varType()==AstVarType::XTEMP); } bool isParam() const { return (varType()==AstVarType::LPARAM || varType()==AstVarType::GPARAM); } bool isGParam() const { return (varType()==AstVarType::GPARAM); } bool isGenVar() const { return (varType()==AstVarType::GENVAR); } diff --git a/src/V3Task.cpp b/src/V3Task.cpp index a1ab0307a..560815c0a 100644 --- a/src/V3Task.cpp +++ b/src/V3Task.cpp @@ -208,7 +208,8 @@ private: virtual void visit(AstVarRef* nodep, AstNUser*) { nodep->iterateChildren(*this); if (nodep->varp()->user4p() != m_curVxp) { - if (m_curVxp->pure()) { + if (m_curVxp->pure() + && !nodep->varp()->isPure()) { m_curVxp->impure(nodep); } } diff --git a/src/V3Unknown.cpp b/src/V3Unknown.cpp index 9f485961b..c380a3e2f 100644 --- a/src/V3Unknown.cpp +++ b/src/V3Unknown.cpp @@ -191,10 +191,11 @@ private: UINFO(4," -> "<varNumGetInc())); AstVar* newvarp - = new AstVar (nodep->fileline(), AstVarType::MODULETEMP, newvarname, + = new AstVar (nodep->fileline(), AstVarType::XTEMP, newvarname, new AstRange(nodep->fileline(), nodep->width()-1, 0)); m_statUnkVars++; AstNRelinker replaceHandle; diff --git a/test_regress/t/t_func_noinl.pl b/test_regress/t/t_func_noinl.pl new file mode 100755 index 000000000..e2a0c97fa --- /dev/null +++ b/test_regress/t/t_func_noinl.pl @@ -0,0 +1,17 @@ +#!/usr/bin/perl +if (!$::Driver) { use FindBin; exec("./driver.pl", @ARGV, $0); die; } +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2003 by Wilson Snyder. This program is free software; you can +# redistribute it and/or modify it under the terms of either the GNU +# General Public License or the Perl Artistic License. + +compile ( + ); + +execute ( + check_finished=>1, + ); + +ok(1); +1; diff --git a/test_regress/t/t_func_noinl.v b/test_regress/t/t_func_noinl.v new file mode 100644 index 000000000..0f552efe8 --- /dev/null +++ b/test_regress/t/t_func_noinl.v @@ -0,0 +1,115 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2008 by Wilson Snyder. + +module t (/*AUTOARG*/ + // Inputs + clk + ); + input clk; + + integer cyc=0; + reg [63:0] crc; + reg [63:0] sum; + + wire [31:0] inp = crc[31:0]; + wire reset = (cyc < 5); + + /*AUTOWIRE*/ + // Beginning of automatic wires (for undeclared instantiated-module outputs) + wire [31:0] outp; // From test of Test.v + // End of automatics + + Test test (/*AUTOINST*/ + // Outputs + .outp (outp[31:0]), + // Inputs + .reset (reset), + .clk (clk), + .inp (inp[31:0])); + + // Aggregate outputs into a single result vector + wire [63:0] result = {32'h0, outp}; + + // What checksum will we end up with +`define EXPECTED_SUM 64'ha7f0a34f9cf56ccb + + // Test loop + always @ (posedge clk) begin +`ifdef TEST_VERBOSE + $write("[%0t] cyc==%0d crc=%x result=%x\n",$time, cyc, crc, result); +`endif + cyc <= cyc + 1; + crc <= {crc[62:0], crc[63]^crc[2]^crc[0]}; + sum <= result ^ {sum[62:0],sum[63]^sum[2]^sum[0]}; + if (cyc==0) begin + // Setup + crc <= 64'h5aef0c8d_d70a4497; + end + else if (cyc<10) begin + sum <= 64'h0; + end + else if (cyc<90) begin + end + else if (cyc==99) begin + $write("[%0t] cyc==%0d crc=%x sum=%x\n",$time, cyc, crc, sum); + if (crc !== 64'hc77bb9b3784ea091) $stop; + if (sum !== `EXPECTED_SUM) $stop; + $write("*-* All Finished *-*\n"); + $finish; + end + end + +endmodule + +module Test (/*AUTOARG*/ + // Outputs + outp, + // Inputs + reset, clk, inp + ); + + input reset; + input clk; + input [31:0] inp; + output [31:0] outp; + + function [31:0] no_inline_function; + input [31:0] var1; + input [31:0] var2; + /*verilator no_inline_task*/ + reg [31*2:0] product1 ; + reg [31*2:0] product2 ; + integer i; + reg [31:0] tmp; + + begin + product2 = {(31*2+1){1'b0}}; + + for (i = 0; i < 32; i = i + 1) + if (var2[i]) begin + product1 = { {31*2+1-32{1'b0}}, var1} << i; + product2 = product2 ^ product1; + end + no_inline_function = 0; + + for (i= 0; i < 31; i = i + 1 ) + no_inline_function[i+1] = no_inline_function[i] ^ product2[i] ^ var1[i]; + end + endfunction + + reg [31:0] outp; + reg [31:0] inp_d; + + always @( posedge clk ) begin + if( reset ) begin + outp <= 0; + end + else begin + inp_d <= inp; + outp <= no_inline_function(inp, inp_d); + end + end + +endmodule