From 56de6f1a9f3cccb6ecd45d8ad54e9cc8fb092f34 Mon Sep 17 00:00:00 2001
From: Wilson Snyder <wsnyder@wsnyder.org>
Date: Tue, 14 Mar 2023 20:40:58 -0400
Subject: [PATCH] Fix min/typ/max internal error

---
 src/verilog.y | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/verilog.y b/src/verilog.y
index ec68a46e4..33288f922 100644
--- a/src/verilog.y
+++ b/src/verilog.y
@@ -2944,7 +2944,7 @@ delay_control<delayp>:   //== IEEE: delay_control
         |       '#' '(' minTypMax ',' minTypMax ')'
                         { $$ = new AstDelay{$<fl>1, $3, false}; RISEFALLDLYUNSUP($3); DEL($5); }
         |       '#' '(' minTypMax ',' minTypMax ',' minTypMax ')'
-                        { $$ = new AstDelay{$<fl>1, $3, false}; RISEFALLDLYUNSUP($5); DEL($3); DEL($7); }
+                        { $$ = new AstDelay{$<fl>1, $5, false}; RISEFALLDLYUNSUP($5); DEL($3); DEL($7); }
         ;
 
 delay_value<nodeExprp>:         // ==IEEE:delay_value