diff --git a/src/V3Width.cpp b/src/V3Width.cpp
index f68b2dc6f..271f878a2 100644
--- a/src/V3Width.cpp
+++ b/src/V3Width.cpp
@@ -2242,7 +2242,10 @@ private:
 		    nodep = newp;  // Process new node instead
 		}
 	    }
-	    iterateCheck(nodep,"LHS",nodep->lhsp(),CONTEXT,FINAL,subDTypep,EXTEND_EXP);
+	    bool warnOn = true;
+	    // No warning if "X = 1'b1<<N"; assume user is doing what they want
+	    if (nodep->lhsp()->isOne() && nodep->backp()->castNodeAssign()) warnOn = false;
+	    iterateCheck(nodep,"LHS",nodep->lhsp(),CONTEXT,FINAL,subDTypep,EXTEND_EXP,warnOn);
 	    if (nodep->rhsp()->width()>32) {
 		AstConst* shiftp = nodep->rhsp()->castConst();
 		if (shiftp && shiftp->num().mostSetBitP1() <= 32) {
diff --git a/test_regress/t/t_math_width.pl b/test_regress/t/t_math_width.pl
new file mode 100755
index 000000000..f91289753
--- /dev/null
+++ b/test_regress/t/t_math_width.pl
@@ -0,0 +1,18 @@
+#!/usr/bin/perl
+if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2003 by Wilson Snyder. This program is free software; you can
+# redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+
+compile (
+    );
+
+execute (
+    check_finished=>1,
+    );
+
+ok(1);
+1;
diff --git a/test_regress/t/t_math_width.v b/test_regress/t/t_math_width.v
new file mode 100644
index 000000000..693f034f7
--- /dev/null
+++ b/test_regress/t/t_math_width.v
@@ -0,0 +1,39 @@
+// DESCRIPTION: Verilator: Verilog Test module
+//
+// This file ONLY is placed into the Public Domain, for any use,
+// without warranty, 2014 by Wilson Snyder.
+
+module t ();
+
+   // See also t_lint_width
+
+   b #(.B_WIDTH(48)) b ();
+
+   reg [4:0] c;
+   integer    c_i;
+   initial begin
+      c_i = 3;
+      c = 1'b1 << c_i;  // No width warning when not embedded in expression, as is common syntax
+      if (c != 5'b1000) $stop;
+   end
+
+   initial begin
+      $write("*-* All Finished *-*\n");
+      $finish;
+   end
+
+endmodule
+
+
+module b;
+   parameter B_WIDTH = 1;
+   localparam B_VALUE0 = {B_WIDTH{1'b0}};
+   localparam B_VALUE1 = {B_WIDTH{1'b1}};
+   reg [47:0] b_val;
+   initial begin
+      b_val = B_VALUE0;
+      if (b_val != 48'b0) $stop;
+      b_val = B_VALUE1;
+      if (b_val != ~48'b0) $stop;
+   end
+endmodule