From 5634e96bb6151b7a1d7f70e57ab81186d74d3793 Mon Sep 17 00:00:00 2001
From: Wilson Snyder <wsnyder@wsnyder.org>
Date: Sat, 19 Nov 2022 22:43:10 -0500
Subject: [PATCH] Tests: Remove unsupported() in tests, instead check whatever
 is current behavior

---
 test_regress/driver.pl                        |  71 ++++-------
 test_regress/t/t_class_dead.pl                |   7 +-
 test_regress/t/t_dpi_shortcircuit.out         |  18 +++
 test_regress/t/t_dpi_shortcircuit.pl          |   9 +-
 test_regress/t/t_dpi_shortcircuit.v           |  10 +-
 test_regress/t/t_dpi_shortcircuit2.v          |  13 +--
 test_regress/t/t_dpi_shortcircuit_c.cpp       |   5 +-
 test_regress/t/t_genvar_misuse_bad.pl         |   6 +-
 test_regress/t/t_inst_aport.pl                |  22 ----
 test_regress/t/t_inst_aport.v                 | 110 ------------------
 test_regress/t/t_interface_down_gen.pl        |  23 ----
 test_regress/t/t_interface_down_gen.v         |  79 -------------
 .../t/t_interface_modport_dir_bad.out         |  17 +--
 test_regress/t/t_interface_modport_dir_bad.pl |   2 -
 test_regress/t/t_interface_modport_export.out |   8 ++
 test_regress/t/t_interface_modport_export.pl  |   5 +-
 test_regress/t/t_interface_param2.out         |   8 ++
 test_regress/t/t_interface_param2.pl          |   6 +-
 test_regress/t/t_interface_param_loop_bad.pl  |   7 +-
 .../t/t_interface_parent_scope_bad.pl         |   7 +-
 test_regress/t/t_mem_bound_bad.pl             |   5 +-
 test_regress/t/t_param_width_loc_bad.out      |  22 +---
 test_regress/t/t_param_width_loc_bad.pl       |   2 -
 test_regress/t/t_param_width_loc_bad.v        |   1 +
 test_regress/t/t_tri_array.out                |  21 ++++
 test_regress/t/t_tri_array.pl                 |   7 +-
 26 files changed, 128 insertions(+), 363 deletions(-)
 create mode 100644 test_regress/t/t_dpi_shortcircuit.out
 delete mode 100755 test_regress/t/t_inst_aport.pl
 delete mode 100644 test_regress/t/t_inst_aport.v
 delete mode 100755 test_regress/t/t_interface_down_gen.pl
 delete mode 100644 test_regress/t/t_interface_down_gen.v
 create mode 100644 test_regress/t/t_interface_modport_export.out
 create mode 100644 test_regress/t/t_interface_param2.out
 create mode 100644 test_regress/t/t_tri_array.out

diff --git a/test_regress/driver.pl b/test_regress/driver.pl
index 1f227d341..3507e013d 100755
--- a/test_regress/driver.pl
+++ b/test_regress/driver.pl
@@ -87,7 +87,6 @@ my $opt_stop;
 my $opt_trace;
 my $opt_verbose;
 my $Opt_Verilated_Debug;
-our $Opt_Unsupported;
 our $Opt_Verilation = 1;
 our @Opt_Driver_Verilator_Flags;
 
@@ -111,7 +110,6 @@ if (! GetOptions(
           "site!"       => \$opt_site,
           "stop!"       => \$opt_stop,
           "trace!"      => \$opt_trace,
-          "unsupported!"=> \$Opt_Unsupported,
           "verbose!"    => \$opt_verbose,
           "verilation!"         => \$Opt_Verilation,  # Undocumented debugging
           "verilated-debug!"    => \$Opt_Verilated_Debug,
@@ -197,8 +195,7 @@ if ($opt_rerun && $runner->fail_count) {
         quiet => 0,
         fail1_cnt => $orig_runner->fail_count,
         ok_cnt => $orig_runner->{ok_cnt},
-        skip_cnt => $orig_runner->{skip_cnt},
-        unsup_cnt => $orig_runner->{unsup_cnt});
+        skip_cnt => $orig_runner->{skip_cnt});
     foreach my $test (@{$orig_runner->{fail_tests}}) {
         $test->clean;
         # Reschedule test
@@ -313,7 +310,6 @@ sub new {
         fail1_cnt => 0,
         fail_cnt => 0,
         skip_cnt => 0,
-        unsup_cnt => 0,
         skip_msgs => [],
         fail_msgs => [],
         fail_tests => [],
@@ -374,8 +370,6 @@ sub one_test {
                  push @{$self->{skip_msgs}},
                      ("\t#" . $test->soprint("-Skip:  $test->{skips}\n"));
                  $self->{skip_cnt}++;
-             } elsif ($test->unsupporteds && !$test->errors) {
-                 $self->{unsup_cnt}++;
              } else {
                  $test->oprint("FAILED: $test->{errors}\n");
                  my $j = ($opt_jobs > 1 ? " -j" : "");
@@ -485,7 +479,6 @@ sub sprint_summary {
     $out .= "  Failed $self->{fail_cnt}";
     $out .= "  Failed-First $self->{fail1_cnt}" if $self->{fail1_cnt};
     $out .= "  Skipped $self->{skip_cnt}" if $self->{skip_cnt};
-    $out .= "  Unsup $self->{unsup_cnt}";
     $out .= sprintf("  Eta %d:%02d", int($eta / 60), $eta % 60) if $self->{left_cnt} > 10 && $eta > 10;
     $out .= sprintf("  Time %d:%02d", int($delta / 60), $delta % 60);
     return $out;
@@ -751,16 +744,6 @@ sub skip {
     $self->{skips} ||= "Skip: " . $msg;
 }
 
-sub unsupported {
-    my $self = (ref $_[0] ? shift : $Self);
-    my $msg = join('', @_);
-    # Called from tests as: unsupported("Reason message"[, ...]);
-    warn "-Unsupported: $self->{scenario}/$self->{name}: " . $msg . "\n";
-    if (!$::Opt_Unsupported) {
-        $self->{unsupporteds} ||= "Unsupported: " . $msg;
-    }
-}
-
 sub scenarios {
     my $self = (ref $_[0] ? shift : $Self);
     my %params = (@_);
@@ -815,8 +798,6 @@ sub _exit {
         $self->oprint("Self PASSED\n");
     } elsif ($self->skips && !$self->errors) {
         $self->oprint("-Skip: $self->{skips}\n");
-    } elsif ($self->unsupporteds && !$self->errors) {
-        $self->oprint("%Unsupported: $self->{unsupporteds}\n");
     } else {
         $self->error("Missing ok\n") if !$self->errors;
         $self->oprint("%Error: $self->{errors}\n");
@@ -882,7 +863,7 @@ sub clean_objs {
 sub compile_vlt_cmd {
     my $self = (ref $_[0] ? shift : $Self);
     my %param = (%{$self}, @_);  # Default arguments are from $self
-    return 1 if $self->errors || $self->skips || $self->unsupporteds;
+    return 1 if $self->errors || $self->skips;
 
     my @vlt_cmd = (
         "perl", "$ENV{VERILATOR_ROOT}/bin/verilator",
@@ -897,7 +878,7 @@ sub compile_vlt_cmd {
 sub compile_vlt_flags {
     my $self = (ref $_[0] ? shift : $Self);
     my %param = (%{$self}, @_);  # Default arguments are from $self
-    return 1 if $self->errors || $self->skips || $self->unsupporteds;
+    return 1 if $self->errors || $self->skips;
 
     my $checkflags = join(' ', @{$param{v_flags}},
                           @{$param{v_flags2}},
@@ -971,7 +952,7 @@ sub compile {
     my $self = (ref $_[0] ? shift : $Self);
     my %param = (tee => 1,
                  %{$self}, @_);  # Default arguments are from $self
-    return 1 if $self->errors || $self->skips || $self->unsupporteds;
+    return 1 if $self->errors || $self->skips;
     $self->oprint("Compile\n") if $self->{verbose};
 
     die "%Error: 'threads =>' argument must be <= 1 for vlt scenario" if $param{vlt} && $param{threads} > 1;
@@ -1139,7 +1120,7 @@ sub compile {
                         expect_filename => $param{expect_filename},
                         verilator_run => 1,
                         cmd => \@vlt_cmd) if $::Opt_Verilation;
-            return 1 if $self->errors || $self->skips || $self->unsupporteds;
+            return 1 if $self->errors || $self->skips;
         }
 
         if ($param{verilator_make_cmake}) {
@@ -1168,7 +1149,7 @@ sub compile {
                                 "-DTEST_OPT_GLOBAL=\"" . ($param{benchmark} ? "-Os" : "-O0") . "\"",
                                 "-DTEST_VERILATION=\"" . $::Opt_Verilation . "\"",
                         ]);
-            return 1 if $self->errors || $self->skips || $self->unsupporteds;
+            return 1 if $self->errors || $self->skips;
         }
 
         if (!$param{fails} && $param{verilator_make_gmake}) {
@@ -1220,7 +1201,7 @@ sub compile {
 
 sub execute {
     my $self = (ref $_[0] ? shift : $Self);
-    return 1 if $self->errors || $self->skips || $self->unsupporteds;
+    return 1 if $self->errors || $self->skips;
     my %param = (%{$self}, @_);  # Default arguments are from $self
     # params may be expect or {tool}_expect
     $self->oprint("Run\n") if $self->{verbose};
@@ -1367,7 +1348,7 @@ sub setenv {
 
 sub inline_checks {
     my $self = (ref $_[0] ? shift : $Self);
-    return 1 if $self->errors || $self->skips || $self->unsupporteds;
+    return 1 if $self->errors || $self->skips;
     return 1 if !$self->{vlt_all};
 
     my %param = (%{$self}, @_);  # Default arguments are from $self
@@ -1412,13 +1393,13 @@ sub inline_checks {
 sub ok {
     my $self = (ref $_[0] ? shift : $Self);
     $self->{ok} = $_[0] if defined $_[0];
-    $self->{ok} = 0 if $self->{errors} || $self->{errors_keep_going} || $self->{skips} || $self->unsupporteds;
+    $self->{ok} = 0 if $self->{errors} || $self->{errors_keep_going} || $self->{skips};
     return $self->{ok};
 }
 
 sub continuing {
     my $self = (ref $_[0] ? shift : $Self);
-    return !($self->errors || $self->skips || $self->unsupporteds);
+    return !($self->errors || $self->skips);
 }
 
 sub errors {
@@ -1442,11 +1423,6 @@ sub skips {
     return $self->{skips};
 }
 
-sub unsupporteds {
-    my $self = (ref $_[0] ? shift : $Self);
-    return $self->{unsupporteds};
-}
-
 sub top_filename {
     my $self = (ref $_[0] ? shift : $Self);
     $self->{top_filename} = shift if defined $_[0];
@@ -1662,7 +1638,7 @@ sub _run {
     if ($param{fails} && !$status) {
         $self->error("Exec of $param{cmd}[0] ok, but expected to fail\n");
     }
-    return if $self->errors || $self->skips || $self->unsupporteds;
+    return if $self->errors || $self->skips;
 
     # Read the log file a couple of times to allow for NFS delays
     if ($param{check_finished} || $param{expect}) {
@@ -2186,7 +2162,7 @@ sub files_identical {
     my $fn1 = shift;
     my $fn2 = shift;
     my $fn1_is_logfile = shift;
-    return 1 if $self->errors || $self->skips || $self->unsupporteds;
+    return 1 if $self->errors || $self->skips;
 
   try:
     for (my $try = $self->tries - 1; $try >= 0; $try--) {
@@ -2263,7 +2239,7 @@ sub files_identical_sorted {
     my $fn1 = shift;
     my $fn2 = shift;
     my $fn1_is_logfile = shift;
-    return 1 if $self->errors || $self->skips || $self->unsupporteds;
+    return 1 if $self->errors || $self->skips;
     # Set LC_ALL as suggested in the sort manpage to avoid sort order
     # changes from the locale.
     setenv('LC_ALL', "C");
@@ -2287,7 +2263,7 @@ sub vcd_identical {
     my $self = (ref $_[0] ? shift : $Self);
     my $fn1 = shift;
     my $fn2 = shift;
-    return 0 if $self->errors || $self->skips || $self->unsupporteds;
+    return 0 if $self->errors || $self->skips;
     if (!-r $fn1) { $self->error("Vcd_identical file does not exist $fn1\n"); return 0; }
     if (!-r $fn2) { $self->error("Vcd_identical file does not exist $fn2\n"); return 0; }
     {
@@ -2350,7 +2326,7 @@ sub fst_identical {
     my $self = (ref $_[0] ? shift : $Self);
     my $fn1 = shift;
     my $fn2 = shift;
-    return 0 if $self->errors || $self->skips || $self->unsupporteds;
+    return 0 if $self->errors || $self->skips;
     my $tmp = $fn1 . ".vcd";
     fst2vcd($fn1, $tmp);
     return vcd_identical($tmp, $fn2);
@@ -2424,7 +2400,7 @@ sub glob_all {
 sub glob_one {
     my $self = (ref $_[0] ? shift : $Self);
     my $pattern = shift;
-    return if $self->errors || $self->skips || $self->unsupporteds;
+    return if $self->errors || $self->skips;
 
     my @files = glob($pattern);
     my $n = scalar @files;
@@ -2446,7 +2422,7 @@ sub file_grep_not {
     my $filename = shift;
     my $regexp = shift;
     my $expvalue = shift;
-    return if $self->errors || $self->skips || $self->unsupporteds;
+    return if $self->errors || $self->skips;
     !defined $expvalue or $self->error("file_grep_not: Unexpected 3rd argument: $expvalue");
 
     my $contents = $self->file_contents($filename);
@@ -2461,7 +2437,7 @@ sub file_grep {
     my $filename = shift;
     my $regexp = shift;
     my $expvalue = shift;
-    return if $self->errors || $self->skips || $self->unsupporteds;
+    return if $self->errors || $self->skips;
 
     my $contents = $self->file_contents($filename);
     return if ($contents eq "_Already_Errored_");
@@ -2477,7 +2453,7 @@ sub file_grep_any {
     my @filenames = @{$_[0]}; shift;
     my $regexp = shift;
     my $expvalue = shift;
-    return if $self->errors || $self->skips || $self->unsupporteds;
+    return if $self->errors || $self->skips;
 
     foreach my $filename (@filenames) {
         my $contents = $self->file_contents($filename);
@@ -2674,9 +2650,8 @@ driver.pl - Run regression tests
 
 driver.pl invokes Verilator or another simulator on each test file.
 
-The driver reports the number of tests which pass, fail, skipped (some
-resource required by the test is not available, such as SystemC), or are
-unsupported (buggy or require a feature change before will pass.)
+The driver reports the number of tests which pass, fail, or skipped (some
+resource required by the test is not available, such as SystemC).
 
 There are hundreds of tests, and for faster completion you may want to run
 the regression tests with OBJCACHE enabled and in parallel on a machine
@@ -2976,10 +2951,6 @@ Stop on the first error.
 
 Set the simulator specific flags to request waveform tracing.
 
-=item --unsupported
-
-Run tests even if marked as unsupported.
-
 =item --verbose
 
 Compile and run the test in verbose mode. This means C<TEST_VERBOSE> will
diff --git a/test_regress/t/t_class_dead.pl b/test_regress/t/t_class_dead.pl
index fd702254d..0ba7b4fd1 100755
--- a/test_regress/t/t_class_dead.pl
+++ b/test_regress/t/t_class_dead.pl
@@ -8,8 +8,6 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); di
 # Version 2.0.
 # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
 
-$Self->{vlt_all} and unsupported("Verilator unsupported, class dead");
-
 scenarios(simulator => 1);
 
 compile(
@@ -19,7 +17,10 @@ execute(
     check_finished => 1,
     );
 
-file_grep_not("$Self->{obj_dir}/V$Self->{name}__Syms.h", qr/dead/ix);
+# bug2227, Verilator unsupported, class dead
+# This is what we really want:
+#   file_grep_not("$Self->{obj_dir}/V$Self->{name}__Syms.h", qr/dead/ix);
+file_grep("$Self->{obj_dir}/V$Self->{name}__Syms.h", qr/dead/ix);
 
 ok(1);
 1;
diff --git a/test_regress/t/t_dpi_shortcircuit.out b/test_regress/t/t_dpi_shortcircuit.out
new file mode 100644
index 000000000..e1463672b
--- /dev/null
+++ b/test_regress/t/t_dpi_shortcircuit.out
@@ -0,0 +1,18 @@
+%Error: Line 60: Bad result, got=1 expect=0
+%Error: Line 64: Bad result, got=1 expect=0
+%Error: Line 75: Bad result, got=0 expect=1
+%Error: Line 98: Bad result, got=1 expect=0
+%Error: Line 102: Bad result, got=1 expect=0
+%Error: Line 112: Bad result, got=0 expect=1
+%Error: Line 132: Bad result, got=1 expect=0
+%Error: Line 136: Bad result, got=1 expect=0
+%Error: Line 150: Bad result, got=1 expect=0
+%Error: Line 154: Bad result, got=1 expect=0
+%Error: Line 163: Bad result, got=0 expect=1
+%Error: Line 203: Bad result, got=64 expect=32
+%Error: Line 204: Bad result, got=64 expect=16
+%Error: Line 205: Bad result, got=64 expect=16
+%Error: Line 206: Bad result, got=64 expect=36
+%Error: Line 207: Bad result, got=64 expect=46
+%Error: t/t_dpi_shortcircuit.v:209: Verilog $stop
+Aborting...
diff --git a/test_regress/t/t_dpi_shortcircuit.pl b/test_regress/t/t_dpi_shortcircuit.pl
index d0b657ca1..ee25e9d79 100755
--- a/test_regress/t/t_dpi_shortcircuit.pl
+++ b/test_regress/t/t_dpi_shortcircuit.pl
@@ -8,17 +8,18 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); di
 # Version 2.0.
 # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
 
-scenarios(simulator => 1);
-$Self->{vlt_all} and unsupported("Verilator unsupported, bug413 short circuit");
+scenarios(vlt => 1);
 
 compile(
-    # Amazingly VCS, NC and Verilator all just accept the C file here!
     v_flags2 => ["t/t_dpi_shortcircuit_c.cpp"],
     verilator_flags2 => ["-Wno-DECLFILENAME"],
     );
 
 execute(
-    check_finished => 1,
+    # Should pass, Verilator unsupported, bug413 short circuit");
+    fails => $Self->{vlt},
+    check_finished => !$Self->{vlt},
+    expect_filename => $Self->{golden_filename},
     );
 
 ok(1);
diff --git a/test_regress/t/t_dpi_shortcircuit.v b/test_regress/t/t_dpi_shortcircuit.v
index 6aeb3a5e7..b89cdffd4 100644
--- a/test_regress/t/t_dpi_shortcircuit.v
+++ b/test_regress/t/t_dpi_shortcircuit.v
@@ -19,11 +19,11 @@
 module t (/*AUTOARG*/);
 
    // Note these are NOT pure.
-   import "DPI-C" function int dpii_clear ();
-   import "DPI-C" function int dpii_count (input int ctr);
-   import "DPI-C" function bit dpii_inc0  (input int ctr);
-   import "DPI-C" function bit dpii_inc1  (input int ctr);
-   import "DPI-C" function bit dpii_incx  (input int ctr, input bit value);
+   import "DPI-C" function void dpii_clear();
+   import "DPI-C" function int dpii_count(input int ctr);
+   import "DPI-C" function bit dpii_inc0(input int ctr);
+   import "DPI-C" function bit dpii_inc1(input int ctr);
+   import "DPI-C" function bit dpii_incx(input int ctr, input bit value);
 
    integer i;
    integer j;
diff --git a/test_regress/t/t_dpi_shortcircuit2.v b/test_regress/t/t_dpi_shortcircuit2.v
index 07b90a38e..2fcd47c7d 100644
--- a/test_regress/t/t_dpi_shortcircuit2.v
+++ b/test_regress/t/t_dpi_shortcircuit2.v
@@ -19,11 +19,11 @@
 module t (/*AUTOARG*/);
 
    // Note these are NOT pure.
-   import "DPI-C" function int dpii_clear ();
-   import "DPI-C" function int dpii_count (input int ctr);
-   import "DPI-C" function bit dpii_inc0  (input int ctr);
-   import "DPI-C" function bit dpii_inc1  (input int ctr);
-   import "DPI-C" function bit dpii_incx  (input int ctr, input bit value);
+   import "DPI-C" function void dpii_clear();
+   import "DPI-C" function int dpii_count(input int ctr);
+   import "DPI-C" function bit dpii_inc0(input int ctr);
+   import "DPI-C" function bit dpii_inc1(input int ctr);
+   import "DPI-C" function bit dpii_incx(input int ctr, input bit value);
 
    integer i;
    integer j;
@@ -46,10 +46,7 @@ module t (/*AUTOARG*/);
 
    // Test loop
    initial begin
-      // bug963
-      // verilator lint_off IGNOREDRETURN
       dpii_clear();
-      // verilator lint_on IGNOREDRETURN
       j = 0;
       for (i=0; i<64; i++) begin
          if (i[0])
diff --git a/test_regress/t/t_dpi_shortcircuit_c.cpp b/test_regress/t/t_dpi_shortcircuit_c.cpp
index 9abe7e53d..12ff41438 100644
--- a/test_regress/t/t_dpi_shortcircuit_c.cpp
+++ b/test_regress/t/t_dpi_shortcircuit_c.cpp
@@ -36,7 +36,7 @@
 
 #ifdef NEED_EXTERNS
 extern "C" {
-extern int dpii_clear();
+extern void dpii_clear();
 extern int dpii_count(int idx);
 extern unsigned char dpii_inc0(int idx);
 extern unsigned char dpii_inc1(int idx);
@@ -49,9 +49,8 @@ extern unsigned char dpii_incx(int idx, unsigned char value);
 #define COUNTERS 16
 static int global_count[COUNTERS];
 
-int dpii_clear() {
+void dpii_clear() {
     for (int i = 0; i < COUNTERS; ++i) global_count[i] = 0;
-    return 0;
 }
 int dpii_count(int idx) { return (idx >= 0 && idx < COUNTERS) ? global_count[idx] : -1; }
 unsigned char dpii_incx(int idx, unsigned char value) {
diff --git a/test_regress/t/t_genvar_misuse_bad.pl b/test_regress/t/t_genvar_misuse_bad.pl
index 18a57407e..05585a90b 100755
--- a/test_regress/t/t_genvar_misuse_bad.pl
+++ b/test_regress/t/t_genvar_misuse_bad.pl
@@ -9,11 +9,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); di
 # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
 
 scenarios(linter => 1);
-$Self->{vlt_all} and unsupported("Verilator unsupported, bug408");
 
 lint(
-    fails => 1,
-    expect_filename => $Self->{golden_filename},
+    # Should fail, but bug408, Verilator unsupported
+    fails => !$Self->{vlt},
+    # expect_filename => $Self->{golden_filename},
     );
 
 ok(1);
diff --git a/test_regress/t/t_inst_aport.pl b/test_regress/t/t_inst_aport.pl
deleted file mode 100755
index 9a383863d..000000000
--- a/test_regress/t/t_inst_aport.pl
+++ /dev/null
@@ -1,22 +0,0 @@
-#!/usr/bin/env perl
-if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
-# DESCRIPTION: Verilator: Verilog Test driver/expect definition
-#
-# Copyright 2003 by Wilson Snyder. This program is free software; you
-# can redistribute it and/or modify it under the terms of either the GNU
-# Lesser General Public License Version 3 or the Perl Artistic License
-# Version 2.0.
-# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
-
-scenarios(simulator => 1);
-unsupported("Verilator/commercial slice unsupported, bug711");
-
-compile(
-    );
-
-execute(
-    check_finished => 1,
-    );
-
-ok(1);
-1;
diff --git a/test_regress/t/t_inst_aport.v b/test_regress/t/t_inst_aport.v
deleted file mode 100644
index e14dcea1a..000000000
--- a/test_regress/t/t_inst_aport.v
+++ /dev/null
@@ -1,110 +0,0 @@
-// DESCRIPTION: Verilator: Verilog Test module
-//
-// This file ONLY is placed under the Creative Commons Public Domain, for
-// any use, without warranty, 2014 by Wilson Snyder.
-// SPDX-License-Identifier: CC0-1.0
-
-module t (/*AUTOARG*/
-   // Inputs
-   clk
-   );
-   input clk;
-
-   integer      cyc = 0;
-   reg [63:0]   crc;
-   reg [63:0]   sum;
-
-   // Take CRC data and apply to testblock inputs
-   wire [31:0]  in = crc[31:0];
-
-   /*AUTOWIRE*/
-   // Beginning of automatic wires (for undeclared instantiated-module outputs)
-   wire [15:0]          out;                    // From test of Test.v
-   // End of automatics
-
-   Test test (/*AUTOINST*/
-              // Outputs
-              .out                      (out[15:0]),
-              // Inputs
-              .in                       (in[31:0]));
-
-   // Aggregate outputs into a single result vector
-   wire [63:0] result = {48'h0, out};
-
-   // Test loop
-   always @ (posedge clk) begin
-`ifdef TEST_VERBOSE
-      $write("[%0t] cyc==%0d crc=%x result=%x\n", $time, cyc, crc, result);
-`endif
-      cyc <= cyc + 1;
-      crc <= {crc[62:0], crc[63] ^ crc[2] ^ crc[0]};
-      sum <= result ^ {sum[62:0], sum[63] ^ sum[2] ^ sum[0]};
-      if (cyc==0) begin
-         // Setup
-         crc <= 64'h5aef0c8d_d70a4497;
-         sum <= 64'h0;
-      end
-      else if (cyc<10) begin
-         sum <= 64'h0;
-      end
-      else if (cyc<90) begin
-      end
-      else if (cyc==99) begin
-         $write("[%0t] cyc==%0d crc=%x sum=%x\n", $time, cyc, crc, sum);
-         if (crc !== 64'hc77bb9b3784ea091) $stop;
-         // What checksum will we end up with (above print should match)
-`define EXPECTED_SUM 64'h4afe43fb79d7b71e
-         if (sum !== `EXPECTED_SUM) $stop;
-         $write("*-* All Finished *-*\n");
-         $finish;
-      end
-   end
-
-endmodule
-
-module callee (input [7:0] port [7:0], output [7:0] o);
-   assign o = ^{port[0], port[1], port[2], port[3],
-                port[4], port[5], port[6], port[7]};
-endmodule // callee
-
-module Test (/*AUTOARG*/
-   // Outputs
-   out,
-   // Inputs
-   in
-   );
-
-   input [31:0] in;
-   output reg [15:0] out;
-
-   wire [7:0] port [15:0];
-   wire [7:0] goodport [7:0];
-
-   always_comb begin
-      port[0][7:0] = in[7:0];
-      port[1][7:0] = in[16:8];
-      port[2] = '0;
-      port[3] = '0;
-      port[4] = '0;
-      port[5] = '0;
-      port[6] = '0;
-      port[7] = '0;
-   end
-
-   always_comb begin
-      goodport[0][7:0] = in[7:0];
-      goodport[1][7:0] = in[16:8];
-      goodport[2] = '0;
-      goodport[3] = '0;
-      goodport[4] = '0;
-      goodport[5] = '0;
-      goodport[6] = '0;
-      goodport[7] = '0;
-   end
-
-   callee good (.port(goodport), .o(out[7:0]));
-
-   // This is a slice, unsupported by other tools, bug711
-   callee bad (.port(port[7:0]), .o(out[15:8]));
-
-endmodule
diff --git a/test_regress/t/t_interface_down_gen.pl b/test_regress/t/t_interface_down_gen.pl
deleted file mode 100755
index d0a85e8ea..000000000
--- a/test_regress/t/t_interface_down_gen.pl
+++ /dev/null
@@ -1,23 +0,0 @@
-#!/usr/bin/env perl
-if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
-# DESCRIPTION: Verilator: Verilog Test driver/expect definition
-#
-# Copyright 2003-2009 by Wilson Snyder. This program is free software; you
-# can redistribute it and/or modify it under the terms of either the GNU
-# Lesser General Public License Version 3 or the Perl Artistic License
-# Version 2.0.
-# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
-
-scenarios(simulator => 1);
-$Self->{vlt_all} and unsupported("Verilator unsupported, interface generates changing types");
-$Self->{vcs} and unsupported("Commercially unsupported, interface crossrefs");
-
-compile(
-    );
-
-execute(
-    check_finished => 1,
-    );
-
-ok(1);
-1;
diff --git a/test_regress/t/t_interface_down_gen.v b/test_regress/t/t_interface_down_gen.v
deleted file mode 100644
index fb65dae46..000000000
--- a/test_regress/t/t_interface_down_gen.v
+++ /dev/null
@@ -1,79 +0,0 @@
-// DESCRIPTION: Verilator: Verilog Test module
-//
-// This file ONLY is placed under the Creative Commons Public Domain, for
-// any use, without warranty, 2013 by Wilson Snyder.
-// SPDX-License-Identifier: CC0-1.0
-
-// This test demonstrates how not only parameters but the type of a parent
-// interface could propagate down to child modules, changing their data type
-// determinations.  Note presently unsupported in all commercial simulators.
-
-interface ifc;
-   parameter MODE = 0;
-   generate
-      // Note block must be named per SystemVerilog 2005
-      if (MODE==1) begin : g
-         integer value;
-      end
-      else if (MODE==2) begin : g
-         real value;
-      end
-   endgenerate
-endinterface
-
-module t (/*AUTOARG*/
-   // Inputs
-   clk
-   );
-
-   input clk;
-   integer cyc=1;
-
-   ifc #(1) itop1a();
-   ifc #(1) itop1b();
-   ifc #(2) itop2a();
-   ifc #(2) itop2b();
-
-   wrapper  c1 (.isuba(itop1a),
-                .isubb(itop1b),
-                .i_valuea(14.1),
-                .i_valueb(15.2));
-   wrapper  c2 (.isuba(itop2a),
-                .isubb(itop2b),
-                .i_valuea(24.3),
-                .i_valueb(25.4));
-
-   always @ (posedge clk) begin
-      cyc <= cyc + 1;
-      if (cyc==20) begin
-         if (itop1a.g.value != 14) $stop;
-         if (itop1b.g.value != 15) $stop;
-         if (itop2a.g.value != 24) $stop;
-         if (itop2b.g.value != 25) $stop;
-         $write("*-* All Finished *-*\n");
-         $finish;
-      end
-   end
-endmodule
-
-module wrapper
-  (
-   ifc isuba,
-   ifc isubb,
-   input real i_valuea,
-   input real i_valueb
-   );
-   lower subsuba (.isub(isuba), .i_value(i_valuea));
-   lower subsubb (.isub(isubb), .i_value(i_valueb));
-endmodule
-
-module lower
-  (
-   ifc isub,
-   input real i_value
-   );
-   always @* begin
-`error Commercial sims choke on cross ref here
-      isub.g.value = i_value;
-   end
-endmodule
diff --git a/test_regress/t/t_interface_modport_dir_bad.out b/test_regress/t/t_interface_modport_dir_bad.out
index 927f0c16e..d7783d86d 100644
--- a/test_regress/t/t_interface_modport_dir_bad.out
+++ b/test_regress/t/t_interface_modport_dir_bad.out
@@ -1,12 +1,5 @@
-Expecting something along the line of:
-
-%Error: t/t_interface_modport_dir_bad.v:36: Attempt to drive input-only modport: 'data'
-: ... In instance t.source_i.source_i
-ctrl.data <= ~ctrl.data;
-^~~~
-%Error: Exiting due to 1 error(s)
-%Error: t/t_interface_modport_dir_bad.v:37: Attempt to drive input-only modport: 'valid'
-: ... In instance t.source_i.source_i
-ctrl.valid<= ~ctrl.valid;
-^~~~
-%Error: Exiting due to 1 error(s)
+%Error: t/t_interface_modport_dir_bad.v:52:25: Port connection 'ctrl' expected 'source' interface modport on pin connection but got 'sink' modport.
+                                             : ... In instance t.source_i
+   52 |    sourceMod source_i (.ctrl);
+      |                         ^~~~
+%Error: Exiting due to
diff --git a/test_regress/t/t_interface_modport_dir_bad.pl b/test_regress/t/t_interface_modport_dir_bad.pl
index f6a127931..27159da5b 100755
--- a/test_regress/t/t_interface_modport_dir_bad.pl
+++ b/test_regress/t/t_interface_modport_dir_bad.pl
@@ -8,8 +8,6 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); di
 # Version 2.0.
 # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
 
-$Self->{vlt_all} and unsupported("Verilator unsupported, bug1622");
-
 scenarios(linter => 1);
 
 lint(
diff --git a/test_regress/t/t_interface_modport_export.out b/test_regress/t/t_interface_modport_export.out
new file mode 100644
index 000000000..27cf64600
--- /dev/null
+++ b/test_regress/t/t_interface_modport_export.out
@@ -0,0 +1,8 @@
+%Error-UNSUPPORTED: t/t_interface_modport_export.v:12:4: Unsupported: extern function
+   12 |    extern function myfunc (input logic val);
+      |    ^~~~~~
+                    ... For error description see https://verilator.org/warn/UNSUPPORTED?v=latest
+%Error-UNSUPPORTED: t/t_interface_modport_export.v:51:31: Unsupported: Out of block function declaration
+   51 |    function automatic logic ie.myfunc (input logic val);
+      |                               ^
+%Error: Exiting due to
diff --git a/test_regress/t/t_interface_modport_export.pl b/test_regress/t/t_interface_modport_export.pl
index 6d4d94235..be66c40e6 100755
--- a/test_regress/t/t_interface_modport_export.pl
+++ b/test_regress/t/t_interface_modport_export.pl
@@ -9,14 +9,15 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); di
 # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
 
 scenarios(simulator => 1);
-$Self->{vlt_all} and unsupported("Verilator unsupported, bug696");
 
 compile(
+    fails => $Self->{vlt_all},
+    expect_filename => $Self->{golden_filename},
     );
 
 execute(
     check_finished => 1,
-    );
+    ) if !$Self->{vlt_all};
 
 ok(1);
 1;
diff --git a/test_regress/t/t_interface_param2.out b/test_regress/t/t_interface_param2.out
new file mode 100644
index 000000000..916fc7f29
--- /dev/null
+++ b/test_regress/t/t_interface_param2.out
@@ -0,0 +1,8 @@
+%Error-UNSUPPORTED: t/t_interface_param2.v:38:12: Unsupported: generic interfaces
+   38 | module mem(interface a);
+      |            ^~~~~~~~~
+                    ... For error description see https://verilator.org/warn/UNSUPPORTED?v=latest
+%Error-UNSUPPORTED: t/t_interface_param2.v:49:12: Unsupported: generic interfaces
+   49 | module cpu(interface b);
+      |            ^~~~~~~~~
+%Error: Exiting due to
diff --git a/test_regress/t/t_interface_param2.pl b/test_regress/t/t_interface_param2.pl
index 2319ed539..b5f2e4dd2 100755
--- a/test_regress/t/t_interface_param2.pl
+++ b/test_regress/t/t_interface_param2.pl
@@ -9,14 +9,16 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); di
 # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
 
 scenarios(simulator => 1);
-$Self->{vlt_all} and unsupported("Verilator unsupported, bug1104");
 
 compile(
+    # Verilator unsupported, bug1104
+    fails => $Self->{vlt_all},
+    expect_filename => $Self->{golden_filename},
     );
 
 execute(
     check_finished => 1,
-    );
+    ) if !$Self->{vlt_all};
 
 ok(1);
 1;
diff --git a/test_regress/t/t_interface_param_loop_bad.pl b/test_regress/t/t_interface_param_loop_bad.pl
index 538506b75..485e44130 100755
--- a/test_regress/t/t_interface_param_loop_bad.pl
+++ b/test_regress/t/t_interface_param_loop_bad.pl
@@ -8,13 +8,12 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); di
 # Version 2.0.
 # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
 
-$Self->{vlt_all} and unsupported("Verilator unsupported, bug1626");
-
 scenarios(linter => 1);
 
 lint(
-    fails => 1,
-    expect_filename => $Self->{golden_filename},
+    # Should fail, Verilator unsupported, bug1626");
+    fails => !$Self->{vlt},
+    # expect_filename => $Self->{golden_filename},
     );
 
 ok(1);
diff --git a/test_regress/t/t_interface_parent_scope_bad.pl b/test_regress/t/t_interface_parent_scope_bad.pl
index 85d8dd9a3..2d88dbd1b 100755
--- a/test_regress/t/t_interface_parent_scope_bad.pl
+++ b/test_regress/t/t_interface_parent_scope_bad.pl
@@ -8,13 +8,12 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); di
 # Version 2.0.
 # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
 
-$Self->{vlt_all} and unsupported("Verilator unsupported, bug1623");
-
 scenarios(linter => 1);
 
 lint(
-    fails => 1,
-    expect_filename => $Self->{golden_filename},
+    # Should fail, Verilator unsupported, bug1623
+    fails => !$Self->{vlt},
+    # expect_filename => $Self->{golden_filename},
     );
 
 ok(1);
diff --git a/test_regress/t/t_mem_bound_bad.pl b/test_regress/t/t_mem_bound_bad.pl
index 6f9cc9875..d86162476 100755
--- a/test_regress/t/t_mem_bound_bad.pl
+++ b/test_regress/t/t_mem_bound_bad.pl
@@ -8,13 +8,10 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); di
 # Version 2.0.
 # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
 
-$Self->{vlt_all} and unsupported("Verilator unsupported, bug528");
-
 scenarios(linter => 1);
 
 lint(
-    fails => 1,
-    expect_filename => $Self->{golden_filename},
+    fails => !$Self->{vlt_all},  # Should fail, but doesn't
     );
 
 ok(1);
diff --git a/test_regress/t/t_param_width_loc_bad.out b/test_regress/t/t_param_width_loc_bad.out
index f29a54f07..3fed6e9b7 100644
--- a/test_regress/t/t_param_width_loc_bad.out
+++ b/test_regress/t/t_param_width_loc_bad.out
@@ -1,19 +1,7 @@
-%Warning-WIDTH: t/t_param_width_loc_bad.v:22: Operator VAR 'param' expects 1 bits on the Initial value, but Initial value's CONST '32'h0' generates 32 bits.
-                                              : ... In instance t.test_i
-    parameter logic param = 1'b0
-                    ^~~~~
+%Warning-WIDTH: t/t_param_width_loc_bad.v:25:21: Operator VAR 'param' expects 1 bits on the Initial value, but Initial value's CONST '32'h0' generates 32 bits.
+                                               : ... In instance t.test_i
+   25 |     parameter logic param = 1'b0
+      |                     ^~~~~
+                ... For warning description see https://verilator.org/warn/WIDTH?v=latest
                 ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.
 %Error: Exiting due to
-
-# I believe this warning message should be pointing to line 12 instead, i.e., wherever the wrongly sized parameter is given as an input rather than the parameter definition.
-# It would be more informative if it looked like this:
-
-%Warning-WIDTH: t/t_param_width_loc_bad.v:12: Operator VAR 'param' expects 1 bits on the Initial value, but Initial value's CONST '32'h0' generates 32 bits.
-      test #(.param(32'd0)) test_i;
-                    ^~~~
-                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.
-%Error: Exiting due to
-
-
-
-
diff --git a/test_regress/t/t_param_width_loc_bad.pl b/test_regress/t/t_param_width_loc_bad.pl
index 1ce49be3f..27159da5b 100755
--- a/test_regress/t/t_param_width_loc_bad.pl
+++ b/test_regress/t/t_param_width_loc_bad.pl
@@ -8,8 +8,6 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); di
 # Version 2.0.
 # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
 
-$Self->{vlt_all} and unsupported("Verilator unsupported, bug1624");
-
 scenarios(linter => 1);
 
 lint(
diff --git a/test_regress/t/t_param_width_loc_bad.v b/test_regress/t/t_param_width_loc_bad.v
index 5923bc497..3d61f5d93 100644
--- a/test_regress/t/t_param_width_loc_bad.v
+++ b/test_regress/t/t_param_width_loc_bad.v
@@ -11,6 +11,7 @@ module t (/*AUTOARG*/
 
    input clk;
 
+   // bug1624
    test #(.param(32'd0)) test_i;
 
    initial begin
diff --git a/test_regress/t/t_tri_array.out b/test_regress/t/t_tri_array.out
new file mode 100644
index 000000000..35c846494
--- /dev/null
+++ b/test_regress/t/t_tri_array.out
@@ -0,0 +1,21 @@
+%Error-UNSUPPORTED: t/t_tri_array.v:25:25: Unsupported LHS tristate construct: ARRAYSEL
+                                         : ... In instance t
+   25 |       Pad pad1 (.pad(pad[g]),
+      |                         ^
+                    ... For error description see https://verilator.org/warn/UNSUPPORTED?v=latest
+%Error-UNSUPPORTED: t/t_tri_array.v:28:25: Unsupported LHS tristate construct: ARRAYSEL
+                                         : ... In instance t
+   28 |       Pad pad0 (.pad(pad[g]),
+      |                         ^
+%Error: t/t_tri_array.v:25:25: Select from non-array BASICDTYPE 'bit'
+                             : ... In instance t
+   25 |       Pad pad1 (.pad(pad[g]),
+      |                         ^
+%Error: t/t_tri_array.v:28:25: Select from non-array BASICDTYPE 'bit'
+                             : ... In instance t
+   28 |       Pad pad0 (.pad(pad[g]),
+      |                         ^
+%Error: Internal Error: t/t_tri_array.v:25:22: ../V3Dfg.h:529: DfgVertex is not of expected type, but instead has type 'VARPACKED'
+   25 |       Pad pad1 (.pad(pad[g]),
+      |                      ^~~
+                        ... See the manual at https://verilator.org/verilator_doc.html for more assistance.
diff --git a/test_regress/t/t_tri_array.pl b/test_regress/t/t_tri_array.pl
index afd57d2de..be66c40e6 100755
--- a/test_regress/t/t_tri_array.pl
+++ b/test_regress/t/t_tri_array.pl
@@ -10,15 +10,14 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); di
 
 scenarios(simulator => 1);
 
-# When fix, update ifdefs in t_sv_cpu files; search for t_tri_array
-$Self->{vlt_all} and unsupported("Verilator unsupported, tristate arrays");
-
 compile(
+    fails => $Self->{vlt_all},
+    expect_filename => $Self->{golden_filename},
     );
 
 execute(
     check_finished => 1,
-    );
+    ) if !$Self->{vlt_all};
 
 ok(1);
 1;