diff --git a/src/V3AstNodes.h b/src/V3AstNodes.h
index 03b5a5497..8346eb5f1 100644
--- a/src/V3AstNodes.h
+++ b/src/V3AstNodes.h
@@ -204,6 +204,7 @@ class AstTypedef : public AstNode {
 private:
     string	m_name;
     bool	m_attrPublic;
+    string	m_tag;  // Holds the string of the verilator tag -- used in XML output.
 public:
     AstTypedef(FileLine* fl, const string& name, AstNode* attrsp, VFlagChildDType, AstNodeDType* dtp)
 	: AstNode(fl), m_name(name) {
@@ -227,6 +228,8 @@ public:
     void name(const string& flag) { m_name = flag; }
     bool attrPublic() const { return m_attrPublic; }
     void attrPublic(bool flag) { m_attrPublic = flag; }
+    virtual void tag(const string& text) { m_tag = text;}
+    virtual string tag() const { return m_tag; }
 };
 
 class AstTypedefFwd : public AstNode {
diff --git a/src/verilog.y b/src/verilog.y
index f6ac5aec4..95822da31 100644
--- a/src/verilog.y
+++ b/src/verilog.y
@@ -1626,15 +1626,15 @@ type_declaration<nodep>:	// ==IEEE: type_declaration
 	//			// Use idAny, as we can redeclare a typedef on an existing typedef
 		yTYPEDEF data_type idAny variable_dimensionListE dtypeAttrListE ';'
 	/**/	{ $$ = new AstTypedef($<fl>1, *$3, $5, VFlagChildDType(), GRAMMARP->createArray($2,$4,false));
-		  SYMP->reinsert($$); }
+		  SYMP->reinsert($$); PARSEP->tagNodep($$); }
 	//UNSUP	yTYPEDEF id/*interface*/ '.' idAny/*type*/ idAny/*type*/ ';'	{ $$ = NULL; $1->v3error("Unsupported: SystemVerilog 2005 typedef in this context"); } //UNSUP
 	//			// Combines into above "data_type id" rule
 	//			// Verilator: Not important what it is in the AST, just need to make sure the yaID__aTYPE gets returned
-	|	yTYPEDEF id ';'				{ $$ = NULL; $$ = new AstTypedefFwd($<fl>1, *$2); SYMP->reinsert($$); }
-	|	yTYPEDEF yENUM idAny ';'		{ $$ = NULL; $$ = new AstTypedefFwd($<fl>1, *$3); SYMP->reinsert($$); }
-	|	yTYPEDEF ySTRUCT idAny ';'		{ $$ = NULL; $$ = new AstTypedefFwd($<fl>1, *$3); SYMP->reinsert($$); }
-	|	yTYPEDEF yUNION idAny ';'		{ $$ = NULL; $$ = new AstTypedefFwd($<fl>1, *$3); SYMP->reinsert($$); }
-	//UNSUP	yTYPEDEF yCLASS idAny ';'		{ $$ = NULL; $$ = new AstTypedefFwd($<fl>1, *$3); SYMP->reinsert($$); }
+	|	yTYPEDEF id ';'				{ $$ = NULL; $$ = new AstTypedefFwd($<fl>1, *$2); SYMP->reinsert($$); PARSEP->tagNodep($$); }
+	|	yTYPEDEF yENUM idAny ';'		{ $$ = NULL; $$ = new AstTypedefFwd($<fl>1, *$3); SYMP->reinsert($$); PARSEP->tagNodep($$); }
+	|	yTYPEDEF ySTRUCT idAny ';'		{ $$ = NULL; $$ = new AstTypedefFwd($<fl>1, *$3); SYMP->reinsert($$); PARSEP->tagNodep($$); }
+	|	yTYPEDEF yUNION idAny ';'		{ $$ = NULL; $$ = new AstTypedefFwd($<fl>1, *$3); SYMP->reinsert($$); PARSEP->tagNodep($$); }
+	//UNSUP	yTYPEDEF yCLASS idAny ';'		{ $$ = NULL; $$ = new AstTypedefFwd($<fl>1, *$3); SYMP->reinsert($$); PARSEP->tagNodep($$); }
 	;
 
 dtypeAttrListE<nodep>:
diff --git a/test_regress/t/t_xml_tag.out b/test_regress/t/t_xml_tag.out
index 57d962264..007c517ec 100644
--- a/test_regress/t/t_xml_tag.out
+++ b/test_regress/t/t_xml_tag.out
@@ -13,8 +13,8 @@
       <var fl="e8" name="clk_ip" tag="clk_ip" dtype_id="1"/>
       <var fl="e9" name="rst_ip" dtype_id="1"/>
       <var fl="e10" name="foo_op" tag="foo_op" dtype_id="1"/>
-      <typedef fl="e14" name="my_struct" dtype_id="2"/>
-      <var fl="e23" name="this_struct" dtype_id="3"/>
+      <typedef fl="e14" name="my_struct" tag="my_struct" dtype_id="2"/>
+      <var fl="e23" name="this_struct" tag="this_struct" dtype_id="3"/>
     </module>
     <typetable fl="a0">
       <basicdtype  fl="e23" id="4" name="logic" left="31" right="0"/>
diff --git a/test_regress/t/t_xml_tag.v b/test_regress/t/t_xml_tag.v
index d644ad559..196e18cd1 100644
--- a/test_regress/t/t_xml_tag.v
+++ b/test_regress/t/t_xml_tag.v
@@ -16,10 +16,10 @@ module m
       logic 	  k;      /* verilator lint_off UNUSED */
       logic 	  enable; // verilator tag enable
       logic 	  data;   // verilator tag data
-   } my_struct;
+   } my_struct;  // verilator tag my_struct
 
    // This is a comment
 
-   my_struct this_struct [2];
+   my_struct this_struct [2];  // verilator tag this_struct
 
 endmodule