diff --git a/test_regress/t/t_config_rules.out b/test_regress/t/t_config_rules.out
deleted file mode 100644
index a8fab7a2c..000000000
--- a/test_regress/t/t_config_rules.out
+++ /dev/null
@@ -1,26 +0,0 @@
-%Error-UNSUPPORTED: t/t_config_rules.v:33:3: Unsupported: config inst use rule
-   33 |   instance t.m20 liblist;   
-      |   ^~~~~~~~
-                    ... For error description see https://verilator.org/warn/UNSUPPORTED?v=latest
-%Error-UNSUPPORTED: t/t_config_rules.v:34:3: Unsupported: config inst liblist rule
-   34 |   instance t.m21 liblist libc;
-      |   ^~~~~~~~
-%Error-UNSUPPORTED: t/t_config_rules.v:35:3: Unsupported: config inst liblist rule
-   35 |   instance t.m22 liblist libc libd;   
-      |   ^~~~~~~~
-%Error-UNSUPPORTED: t/t_config_rules.v:36:3: Unsupported: config inst liblist rule
-   36 |   instance t.m23 liblist libc libd;   
-      |   ^~~~~~~~
-%Error-UNSUPPORTED: t/t_config_rules.v:37:3: Unsupported: config inst liblist rule
-   37 |   instance t.m24 liblist libc libd;   
-      |   ^~~~~~~~
-%Error-UNSUPPORTED: t/t_config_rules.v:40:3: Unsupported: config inst use rule
-   40 |   instance t.m30 use cell_identifier;
-      |   ^~~~~~~~
-%Error-UNSUPPORTED: t/t_config_rules.v:41:3: Unsupported: config inst use rule
-   41 |   instance t.m31 use lib_id.cell_id;
-      |   ^~~~~~~~
-%Error-UNSUPPORTED: t/t_config_rules.v:42:3: Unsupported: config inst use rule
-   42 |   instance t.m32 use #();
-      |   ^~~~~~~~
-%Error: Exiting due to
diff --git a/test_regress/t/t_display_wide_bad.out b/test_regress/t/t_display_wide_bad.out
deleted file mode 100644
index 1276d3d05..000000000
--- a/test_regress/t/t_display_wide_bad.out
+++ /dev/null
@@ -1,5 +0,0 @@
-%Error-UNSUPPORTED: t/t_display_wide_bad.v:23:7: Unsupported: Exceeded limit of 8192 bits for any $display-like arguments
-   23 |       $write("[%0t] cyc==%0d crc=%d\n", $time, cyc, {crc, crc, crc, crc});   
-      |       ^~~~~~
-                    ... For error description see https://verilator.org/warn/UNSUPPORTED?v=latest
-%Error: Exiting due to
diff --git a/test_regress/t/t_func_lib_sub_timing.py b/test_regress/t/t_func_lib_sub_timing.py
index 6ec93499c..706390916 100755
--- a/test_regress/t/t_func_lib_sub_timing.py
+++ b/test_regress/t/t_func_lib_sub_timing.py
@@ -14,6 +14,6 @@ test.top_filename = "t/t_func_lib_sub.v"
 
 test.compile(verilator_flags2=["--binary"])
 
-#test.execute()
+test.execute()
 
 test.passes()
diff --git a/test_regress/t/t_inside_unpacked.out b/test_regress/t/t_inside_unpacked.out
deleted file mode 100644
index d46038344..000000000
--- a/test_regress/t/t_inside_unpacked.out
+++ /dev/null
@@ -1,9 +0,0 @@
-%Error: t/t_inside_unpacked.v:17:35: Unsupported: inside (set membership operator) on unpacked array
-                                   : ... note: In instance 't'
-   17 |    localparam HIT_INSIDE = HIT_LP inside {CHECKLIST_P};
-      |                                   ^~~~~~
-%Error: t/t_inside_unpacked.v:18:37: Unsupported: inside (set membership operator) on unpacked array
-                                   : ... note: In instance 't'
-   18 |    localparam MISS_INSIDE = MISS_LP inside {CHECKLIST_P};
-      |                                     ^~~~~~
-%Error: Exiting due to
diff --git a/test_regress/t/t_interface_localparam.out b/test_regress/t/t_interface_localparam.out
deleted file mode 100644
index 21c7ae04c..000000000
--- a/test_regress/t/t_interface_localparam.out
+++ /dev/null
@@ -1,3 +0,0 @@
-*-* All Finished *-*
-top.t.intf: symbolsPerBeat 16, symbolsPerBeatDivBy2 8, mismatch 0
-top.t.theCore.core_intf: symbolsPerBeat 64, symbolsPerBeatDivBy2 32, mismatch 0
diff --git a/test_regress/t/t_interface_typedef.out b/test_regress/t/t_interface_typedef.out
deleted file mode 100644
index fe9d6e06f..000000000
--- a/test_regress/t/t_interface_typedef.out
+++ /dev/null
@@ -1,5 +0,0 @@
-%Error: t/t_interface_typedef.v:49:11: Unsupported: SystemVerilog 2005 interface typedef
-   49 |   typedef ifc_if.struct_t struct_t;
-      |           ^~~~~~
-        ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance.
-%Error: Exiting due to
diff --git a/test_regress/t/t_interface_typedef2.out b/test_regress/t/t_interface_typedef2.out
deleted file mode 100644
index 7f8fee0bd..000000000
--- a/test_regress/t/t_interface_typedef2.out
+++ /dev/null
@@ -1,11 +0,0 @@
-%Error: t/t_interface_typedef2.v:37:11: Unsupported: SystemVerilog 2005 interface typedef
-   37 |   typedef p1.stage_t stage1_t;   
-      |           ^~
-        ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance.
-%Error: t/t_interface_typedef2.v:40:11: Unsupported: SystemVerilog 2005 interface typedef
-   40 |   typedef p2.stage_t stage2_t;   
-      |           ^~
-%Error: t/t_interface_typedef2.v:25:11: Unsupported: SystemVerilog 2005 interface typedef
-   25 |   typedef p1.stage_t stage_t;   
-      |           ^~
-%Error: Exiting due to
diff --git a/test_regress/t/t_lint_latch_5.out b/test_regress/t/t_lint_latch_5.out
deleted file mode 100644
index 30dab57fe..000000000
--- a/test_regress/t/t_lint_latch_5.out
+++ /dev/null
@@ -1,13 +0,0 @@
-%Warning-COMBDLY: t/t_lint_latch_5.v:13:13: Non-blocking assignment '<=' in combinational logic process
-                                          : ... This will be executed as a blocking assignment '='!
-   13 |        z[0] <= a[0];
-      |             ^~
-                  ... For warning description see https://verilator.org/warn/COMBDLY?v=latest
-                  ... Use "/* verilator lint_off COMBDLY */" and lint_on around source to disable this message.
-                  *** See https://verilator.org/warn/COMBDLY before disabling this,
-                  else you may end up with different sim results.
-%Warning-COMBDLY: t/t_lint_latch_5.v:17:13: Non-blocking assignment '<=' in combinational logic process
-                                          : ... This will be executed as a blocking assignment '='!
-   17 |        z[1] <= a[1];
-      |             ^~
-%Error: Exiting due to
diff --git a/test_regress/t/t_opt_slice_element_limit_bad.out b/test_regress/t/t_opt_slice_element_limit_bad.out
index 675cf617c..7d4081e22 100644
--- a/test_regress/t/t_opt_slice_element_limit_bad.out
+++ b/test_regress/t/t_opt_slice_element_limit_bad.out
@@ -1,2 +1,2 @@
 %Error: --fslice-element-limit must be >= 0: -100
-        ... See the manual at https://verilator.org/verilator_doc.html?v=5.043 for more assistance.
\ No newline at end of file
+        ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance.
diff --git a/test_regress/t/t_opt_slice_element_limit_bad.py b/test_regress/t/t_opt_slice_element_limit_bad.py
index e64abba0f..d07269b4c 100755
--- a/test_regress/t/t_opt_slice_element_limit_bad.py
+++ b/test_regress/t/t_opt_slice_element_limit_bad.py
@@ -16,6 +16,6 @@ test.golden_filename = "t/t_opt_slice_element_limit_bad.out"
 
 test.lint(fails=True,
           verilator_flags2=['--stats', '--fslice-element-limit', '-100'],
-          except_filename=test.golden_filename)
+          expect_filename=test.golden_filename)
 
 test.passes()
diff --git a/test_regress/t/t_process_std.out b/test_regress/t/t_process_std.out
deleted file mode 100644
index ab04bc4e8..000000000
--- a/test_regress/t/t_process_std.out
+++ /dev/null
@@ -1,3 +0,0 @@
-[0] %Error: verilated_std.sv:154: Assertion failed in top.std.process.set_randstate: std::process::set_randstate() not supported
-%Error: verilated_std.sv:154: Verilog $stop
-Aborting...
diff --git a/test_regress/t/t_protect_ids_key.out b/test_regress/t/t_protect_ids_key.out
index 2c815ea62..110f826c1 100644
--- a/test_regress/t/t_protect_ids_key.out
+++ b/test_regress/t/t_protect_ids_key.out
@@ -11,9 +11,8 @@
   <map from="PSfqIT" to="__PVT__secret_cyc_r"/>
   <map from="PStVCQ" to="__PVT__secret_r"/>
   <map from="PSfqS0" to="__PVT__t__DOT__secret_inst"/>
-  <map from="PSS0mv" to="__VactContinue"/>
-  <map from="PSb9ZF" to="__VactExecute"/>
   <map from="PSF5NB" to="__VactIterCount"/>
+  <map from="PSkICD" to="__VactPhaseResult"/>
   <map from="PSScAO" to="__VactTriggered"/>
   <map from="PSx9Nt" to="__Vconfigure"/>
   <map from="PSrjMj" to="__Vdly__secret_cyc"/>
@@ -23,19 +22,17 @@
   <map from="PSxbIE" to="__Vdpiimwrap_dpii_a_func_TOP__t__DOT__secret_inst"/>
   <map from="PSIv2l" to="__Vdpiimwrap_dpii_a_task_TOP__t__DOT__secret_inst"/>
   <map from="PS76My" to="__Vfunc_dpii_a_func__0__Vfuncout"/>
-  <map from="PSPVnC" to="__VnbaContinue"/>
+  <map from="PSZAsk" to="__Vinline__nba_sequent__TOP__0___Vdly__t__DOT__secret_inst2__DOT__secret_cyc"/>
   <map from="PSo9XV" to="__VnbaExecute"/>
   <map from="PSEtOH" to="__VnbaIterCount"/>
+  <map from="PSeNXP" to="__VnbaPhaseResult"/>
   <map from="PSmzsT" to="__VnbaTriggered"/>
-  <map from="PSHzgK" to="__VpreTriggered"/>
-  <map from="PSEGxK" to="__Vscope_t__secret_inst"/>
+  <map from="PSJZmm" to="__Vscopep_t__secret_inst"/>
   <map from="PS25fg" to="__Vtask_dpix_a_task__1__i"/>
   <map from="PSJN3f" to="__Vtrigprevexpr___TOP__clk__0"/>
   <map from="PSyTg5" to="_ctor_var_reset"/>
   <map from="PSvIGv" to="_dump_triggers__act"/>
-  <map from="PSYUIn" to="_dump_triggers__nba"/>
   <map from="PS8lsQ" to="_eval"/>
-  <map from="PSL96q" to="_eval_act"/>
   <map from="PSKZ7c" to="_eval_debug_assertions"/>
   <map from="PSEZzj" to="_eval_final"/>
   <map from="PSABAY" to="_eval_initial"/>
@@ -44,16 +41,24 @@
   <map from="PSfNDT" to="_eval_phase__nba"/>
   <map from="PSBUJ6" to="_eval_settle"/>
   <map from="PS0mmd" to="_eval_static"/>
-  <map from="PS9gCw" to="_eval_triggers__act"/>
+  <map from="PSf5GY" to="_eval_triggers_vec__act"/>
   <map from="PSgp53" to="_nba_sequent__TOP__0"/>
   <map from="PSoFVg" to="_nba_sequent__TOP__t__DOT__secret_inst__0"/>
+  <map from="PSMRXn" to="_trigger_anySet__act"/>
+  <map from="PSBKaZ" to="_trigger_clear__act"/>
+  <map from="PSB9K0" to="_trigger_orInto__act_vec_vec"/>
   <map from="PScyq8" to="clk"/>
+  <map from="PSawda" to="in"/>
+  <map from="PSMlYB" to="n"/>
+  <map from="PSmk5h" to="out"/>
   <map from="PSnRoO" to="secret_inst"/>
   <map from="PSS3Gk" to="secret_sub"/>
   <map from="PSxvlA" to="t"/>
   <map from="PSBSVV" to="t/t_protect_ids.v"/>
   <map from="PSB07q" to="t__DOT__secret_inst2__DOT__secret_cyc"/>
+  <map from="PSjTE4" to="tag"/>
   <map from="this" to="this"/>
+  <map from="PSCSr7" to="triggers"/>
   <map from="vlSelf" to="vlSelf"/>
   <map from="vlSymsp" to="vlSymsp"/>
 </verilator_id_map>
diff --git a/test_regress/t/t_protect_ids_key.py b/test_regress/t/t_protect_ids_key.py
index 09316d28c..c472b6c31 100755
--- a/test_regress/t/t_protect_ids_key.py
+++ b/test_regress/t/t_protect_ids_key.py
@@ -16,6 +16,7 @@ test.compile(verilator_flags2=["--protect-ids --protect-key SECRET_KEY", "t/t_pr
 
 test.execute()
 
-# Since using a named key, we can check for always identical maptest.files_identical(test.obj_dir + "/"+test.vm_prefix+"__idmap.xml", test.golden_filename)
+# Since using a named key, we can check for always identical map
+test.files_identical(test.obj_dir + "/" + test.vm_prefix + "__idmap.xml", test.golden_filename)
 
 test.passes()
diff --git a/test_regress/t/t_randsequence_recurse.out b/test_regress/t/t_randsequence_recurse.out
deleted file mode 100644
index c7af7993e..000000000
--- a/test_regress/t/t_randsequence_recurse.out
+++ /dev/null
@@ -1,5 +0,0 @@
-%Error-UNSUPPORTED: t/t_randsequence_recurse.v:21:5: Unsupported: randsequence
-   21 |     randsequence(main)
-      |     ^~~~~~~~~~~~
-                    ... For error description see https://verilator.org/warn/UNSUPPORTED?v=latest
-%Error: Exiting due to
diff --git a/test_regress/t/t_savable_open_bad2.out b/test_regress/t/t_savable_open_bad2.out
deleted file mode 100644
index 45efafe23..000000000
--- a/test_regress/t/t_savable_open_bad2.out
+++ /dev/null
@@ -1,2 +0,0 @@
-%Error: unknown:0: Testbench C called 'dpix_task' but scope wasn't set, perhaps due to dpi import call without 'context', or missing svSetScope. See IEEE 1800-2023 35.5.3.
-Aborting...
diff --git a/test_regress/t/t_static_in_loop_unsup.out b/test_regress/t/t_static_in_loop_unsup.out
deleted file mode 100644
index 48eb55263..000000000
--- a/test_regress/t/t_static_in_loop_unsup.out
+++ /dev/null
@@ -1,6 +0,0 @@
-%Warning-STATICVAR: t/t_static_in_loop.v:13:20: Static variable with assignment declaration declared in a loop converted to automatic
-   13 |         static int a = 0;
-      |                    ^
-                    ... For warning description see https://verilator.org/warn/STATICVAR?v=latest
-                    ... Use "/* verilator lint_off STATICVAR */" and lint_on around source to disable this message.
-%Error: Exiting due to
diff --git a/test_regress/t/t_struct_packed_init_bad.py b/test_regress/t/t_struct_packed_init_bad.py
index 0a4563d37..1952b53a1 100755
--- a/test_regress/t/t_struct_packed_init_bad.py
+++ b/test_regress/t/t_struct_packed_init_bad.py
@@ -13,6 +13,4 @@ test.scenarios('linter')
 
 test.lint(fails=test.vlt_all, expect_filename=test.golden_filename)
 
-#test.execute()
-
 test.passes()
diff --git a/test_regress/t/t_trace_ub_misaligned_address.out b/test_regress/t/t_trace_ub_misaligned_address.out
deleted file mode 100644
index e69de29bb..000000000
diff --git a/test_regress/t/t_union_soft.out b/test_regress/t/t_union_soft.out
deleted file mode 100644
index 35fd986e9..000000000
--- a/test_regress/t/t_union_soft.out
+++ /dev/null
@@ -1,5 +0,0 @@
-%Error-UNSUPPORTED: t/t_union_soft.v:9:10: Unsupported: 'union soft'
-    9 |    union soft {
-      |          ^~~~
-                    ... For error description see https://verilator.org/warn/UNSUPPORTED?v=latest
-%Error: Exiting due to
diff --git a/test_regress/t/t_vlcov_merge.py b/test_regress/t/t_vlcov_merge.py
index 44639a512..962af2512 100755
--- a/test_regress/t/t_vlcov_merge.py
+++ b/test_regress/t/t_vlcov_merge.py
@@ -24,9 +24,11 @@ test.run(cmd=[
 ],
          verilator_run=True)
 
-# Not deleted e.g. parsed --no-unlink properlytest.files_identical(test.t_dir + "/t_vlcov_data_a.dat", test.t_dir + "/t_vlcov_data_a.dat")
+# Not deleted e.g. parsed --no-unlink properly
+test.files_identical(test.t_dir + "/t_vlcov_data_a.dat", test.t_dir + "/t_vlcov_data_a.dat")
 
 # Older clib's didn't properly sort maps, but the coverage data doesn't
-# really care about ordering. So avoid false failures by sorting.test.files_identical_sorted(test.obj_dir + "/coverage.dat", test.golden_filename)
+# really care about ordering. So avoid false failures by sorting.
+test.files_identical_sorted(test.obj_dir + "/coverage.dat", test.golden_filename)
 
 test.passes()