From 555408b5d3246eef122cdb0621b1148e162d0539 Mon Sep 17 00:00:00 2001 From: James Hanlon Date: Mon, 3 Aug 2020 16:44:47 +0100 Subject: [PATCH] Fix V3Unknown from running with flat XML output (#2494) * Prevent V3Unknown pass from being run Co-authored-by: James Hanlon --- src/Verilator.cpp | 4 + test_regress/t/t_xml_flat_vlvbound.out | 200 +++++++++++++++++++++++++ test_regress/t/t_xml_flat_vlvbound.pl | 25 ++++ test_regress/t/t_xml_flat_vlvbound.v | 27 ++++ 4 files changed, 256 insertions(+) create mode 100644 test_regress/t/t_xml_flat_vlvbound.out create mode 100755 test_regress/t/t_xml_flat_vlvbound.pl create mode 100644 test_regress/t/t_xml_flat_vlvbound.v diff --git a/src/Verilator.cpp b/src/Verilator.cpp index 66800410b..dc040cc50 100644 --- a/src/Verilator.cpp +++ b/src/Verilator.cpp @@ -193,12 +193,16 @@ static void process() { // Expand inouts, stage 2 // Also simplify pin connections to always be AssignWs in prep for V3Unknown V3Tristate::tristateAll(v3Global.rootp()); + } + if (!v3Global.opt.xmlOnly()) { // Move assignments from X into MODULE temps. // (Before flattening, so each new X variable is shared between all scopes of that module.) V3Unknown::unknownAll(v3Global.rootp()); v3Global.constRemoveXs(true); + } + if (!(v3Global.opt.xmlOnly() && !v3Global.opt.flatten())) { // Module inlining // Cannot remove dead variables after this, as alias information for final // V3Scope's V3LinkDot is in the AstVar. diff --git a/test_regress/t/t_xml_flat_vlvbound.out b/test_regress/t/t_xml_flat_vlvbound.out new file mode 100644 index 000000000..ae5da8f13 --- /dev/null +++ b/test_regress/t/t_xml_flat_vlvbound.out @@ -0,0 +1,200 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/test_regress/t/t_xml_flat_vlvbound.pl b/test_regress/t/t_xml_flat_vlvbound.pl new file mode 100755 index 000000000..9c51c5674 --- /dev/null +++ b/test_regress/t/t_xml_flat_vlvbound.pl @@ -0,0 +1,25 @@ +#!/usr/bin/env perl +if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2012 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +scenarios(vlt => 1); + +my $out_filename = "$Self->{obj_dir}/V$Self->{name}.xml"; + +compile( + verilator_flags2 => ['--xml-only', '--flatten'], + verilator_make_gmake => 0, + make_top_shell => 0, + make_main => 0, + ); + +files_identical("$out_filename", $Self->{golden_filename}); + +ok(1); +1; diff --git a/test_regress/t/t_xml_flat_vlvbound.v b/test_regress/t/t_xml_flat_vlvbound.v new file mode 100644 index 000000000..9ed0db0cf --- /dev/null +++ b/test_regress/t/t_xml_flat_vlvbound.v @@ -0,0 +1,27 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2012 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 + +module vlvbound_test + ( + input logic [15:0] i_a, + input logic [15:0] i_b, + output logic [6:0] o_a, + output logic [6:0] o_b + ); + + function automatic logic [6:0] foo(input logic [15:0] val); + logic [6:0] ret; + integer i; + for (i=0 ; i < 7; i++) begin + ret[i] = (val[i*2 +: 2] == 2'b00); + end + return ret; + endfunction + + assign o_a = foo(i_a); + assign o_b = foo(i_b); + +endmodule