diff --git a/Changes b/Changes
index f6b8d1355..7886b9f3f 100644
--- a/Changes
+++ b/Changes
@@ -7,6 +7,8 @@ indicates the contributor was also the author of the fix; Thanks!
 
 **** Support SystemVerilog ==? and !=? operators.
 
+**** Fix SC_LIBS missing from generated makefiles. [Ding Xiaoliang]
+
 * Verilator 3.652 6/21/2007
 
 **** Report as many warning types as possible before exiting.
diff --git a/src/V3EmitMk.cpp b/src/V3EmitMk.cpp
index 43632647a..cce7cc52c 100644
--- a/src/V3EmitMk.cpp
+++ b/src/V3EmitMk.cpp
@@ -138,7 +138,7 @@ public:
 
 	    of.puts("\n# Link rules...\n");
 	    of.puts(v3Global.opt.prefix()+": $(VK_USER_OBJS) $(SP_SRCS) $(VM_PREFIX)__ALL.a\n");
-	    of.puts("\t$(LINK) $(LDFLAGS) $^ $(LOADLIBES) $(LDLIBS) -o $@ $(LIBS) 2>&1 | c++filt\n");
+	    of.puts("\t$(LINK) $(LDFLAGS) $^ $(LOADLIBES) $(LDLIBS) -o $@ $(LIBS) $(SC_LIBS) 2>&1 | c++filt\n");
 	    of.puts("\n");
 	}