diff --git a/src/V3Udp.cpp b/src/V3Udp.cpp
index 1570a2614..bc325fc88 100644
--- a/src/V3Udp.cpp
+++ b/src/V3Udp.cpp
@@ -110,7 +110,6 @@ class UdpVisitor final : public VNVisitor {
         }
         AstNode* iNodep = nodep->iFieldsp();
         AstNode* oNodep = nodep->oFieldsp();
-        uint32_t inputvars = 0;
         AstSenTree* edgetrigp = nullptr;
 
         AstLogAnd* logandp = new AstLogAnd{fl, new AstConst{fl, AstConst::BitTrue{}},
@@ -118,7 +117,6 @@ class UdpVisitor final : public VNVisitor {
 
         for (AstVar* itr : m_inputVars) {
             if (!iNodep) break;
-            inputvars++;
             if (AstUdpTableLineVal* linevalp = VN_CAST(iNodep, UdpTableLineVal)) {
                 string valName = linevalp->name();
                 AstVarRef* const referencep = new AstVarRef{fl, itr, VAccess::READ};
@@ -141,6 +139,10 @@ class UdpVisitor final : public VNVisitor {
             }
             iNodep = iNodep->nextp();
         }
+
+        uint32_t inputvars = 0;
+        for (const AstNode* icountp = nodep->iFieldsp(); icountp; icountp = icountp->nextp())
+            ++inputvars;
         if (inputvars != m_inputVars.size()) {
             nodep->v3error("Incorrect number of input values, expected " << m_inputVars.size()
                                                                          << ", got " << inputvars);
diff --git a/test_regress/t/t_udp_bad_line_inputs.out b/test_regress/t/t_udp_bad_line_inputs.out
new file mode 100644
index 000000000..be1d64be4
--- /dev/null
+++ b/test_regress/t/t_udp_bad_line_inputs.out
@@ -0,0 +1,5 @@
+%Error: t/t_udp_bad_line_inputs.v:9:5: Incorrect number of input values, expected 1, got 5
+    9 |     ? 1 ? 0 0 : 0;   
+      |     ^
+        ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance.
+%Error: Exiting due to
diff --git a/test_regress/t/t_udp_bad_line_inputs.py b/test_regress/t/t_udp_bad_line_inputs.py
new file mode 100755
index 000000000..55203b6c9
--- /dev/null
+++ b/test_regress/t/t_udp_bad_line_inputs.py
@@ -0,0 +1,16 @@
+#!/usr/bin/env python3
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2025 by Wilson Snyder. This program is free software; you
+# can redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
+
+import vltest_bootstrap
+
+test.scenarios('linter')
+
+test.lint(fails=True, expect_filename=test.golden_filename)
+
+test.passes()
diff --git a/test_regress/t/t_udp_bad_line_inputs.v b/test_regress/t/t_udp_bad_line_inputs.v
new file mode 100644
index 000000000..98489c285
--- /dev/null
+++ b/test_regress/t/t_udp_bad_line_inputs.v
@@ -0,0 +1,11 @@
+// DESCRIPTION: Verilator: Verilog Test module
+//
+// This file ONLY is placed under the Creative Commons Public Domain, for
+// any use, without warranty, 2025 by Wilson Snyder.
+// SPDX-License-Identifier: CC0-1.0
+
+primitive udp_0(output o, input i);
+  table
+    ? 1 ? 0 0 : 0;  // <--- BAD too many inputs
+  endtable
+endprimitive
diff --git a/test_regress/t/t_udp_bad_line_outputs.out b/test_regress/t/t_udp_bad_line_outputs.out
new file mode 100644
index 000000000..3ff068646
--- /dev/null
+++ b/test_regress/t/t_udp_bad_line_outputs.out
@@ -0,0 +1,9 @@
+%Error: t/t_udp_bad_line_outputs.v:9:11: syntax error, unexpected UDP table field, expecting : or UDP table line end
+    9 |     ? : 0 0 : 0;   
+      |           ^
+        ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance.
+%Error: t/t_udp_bad_line_outputs.v:15:15: syntax error, unexpected UDP table field, expecting UDP table line end
+   15 |     ? : 0 : 0 0;   
+      |               ^
+%Error: Cannot continue
+        ... This fatal error may be caused by the earlier error(s); resolve those first.
diff --git a/test_regress/t/t_udp_bad_line_outputs.py b/test_regress/t/t_udp_bad_line_outputs.py
new file mode 100755
index 000000000..55203b6c9
--- /dev/null
+++ b/test_regress/t/t_udp_bad_line_outputs.py
@@ -0,0 +1,16 @@
+#!/usr/bin/env python3
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2025 by Wilson Snyder. This program is free software; you
+# can redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
+
+import vltest_bootstrap
+
+test.scenarios('linter')
+
+test.lint(fails=True, expect_filename=test.golden_filename)
+
+test.passes()
diff --git a/test_regress/t/t_udp_bad_line_outputs.v b/test_regress/t/t_udp_bad_line_outputs.v
new file mode 100644
index 000000000..42c2186ba
--- /dev/null
+++ b/test_regress/t/t_udp_bad_line_outputs.v
@@ -0,0 +1,17 @@
+// DESCRIPTION: Verilator: Verilog Test module
+//
+// This file ONLY is placed under the Creative Commons Public Domain, for
+// any use, without warranty, 2025 by Wilson Snyder.
+// SPDX-License-Identifier: CC0-1.0
+
+primitive udp_1(output reg o, input i);
+  table
+    ? : 0 0 : 0;  // <--- BAD too many recirc
+  endtable
+endprimitive
+
+primitive udp_2(output reg o, input i);
+  table
+    ? : 0 : 0 0;  // <--- BAD too many outputs
+  endtable
+endprimitive