From 549bf876e4a59de194543a26c9e934748ec5d5c3 Mon Sep 17 00:00:00 2001
From: Wilson Snyder <wsnyder@wsnyder.org>
Date: Tue, 1 Apr 2008 19:26:06 +0000
Subject: [PATCH] Ignore delays attached to gate UDPs.  [Stefan Thiede]

git-svn-id: file://localhost/svn/verilator/trunk/verilator@1019 77ca24e4-aefa-0310-84f0-b9a241c72d87
---
 Changes                       |  2 ++
 src/verilog.y                 | 20 ++++++++++----------
 test_regress/t/t_gate_basic.v |  4 ++--
 3 files changed, 14 insertions(+), 12 deletions(-)

diff --git a/Changes b/Changes
index f7b778f71..43dde1928 100644
--- a/Changes
+++ b/Changes
@@ -12,6 +12,8 @@ indicates the contributor was also the author of the fix; Thanks!
 
 ***  Add --top-module option to select between multiple tops. [Stefan Thiede]
 
+**** Ignore delays attached to gate UDPs.  [Stefan Thiede]
+
 **** Fix SystemVerilog parameterized defines with `` expansion,
      and fix extra whitespace inserted on substitution.  [Vladimir Matveyenko]
 
diff --git a/src/verilog.y b/src/verilog.y
index 0daa4990b..f995df9b8 100644
--- a/src/verilog.y
+++ b/src/verilog.y
@@ -707,8 +707,8 @@ dlyTerm:	yaID 					{ $$ = NULL; }
 	;
 
 // IEEE: mintypmax_expression and constant_mintypmax_expression
-minTypMax:	expr					{ $$ = $1; } /* ignored */
-	|	expr ':' expr ':' expr			{ $$ = $1; } /* ignored */
+minTypMax:	dlyTerm					{ $$ = $1; } /* ignored */
+	|	dlyTerm ':' dlyTerm ':' dlyTerm		{ $$ = $1; } /* ignored */
 	;
 
 sigAndAttr:	sigId sigAttrListE			{ $$ = $1; }
@@ -1124,14 +1124,14 @@ commaEListE:	/* empty */				{ $$ = NULL; }
 //************************************************
 // Gate declarations
 
-gateDecl: 	yBUF  gateBufList ';'			{ $$ = $2; }
-	|	yNOT  gateNotList ';'			{ $$ = $2; }
-	|	yAND  gateAndList ';'			{ $$ = $2; }
-	|	yNAND gateNandList ';'			{ $$ = $2; }
-	|	yOR   gateOrList ';'			{ $$ = $2; }
-	|	yNOR  gateNorList ';'			{ $$ = $2; }
-	|	yXOR  gateXorList ';'			{ $$ = $2; }
-	|	yXNOR gateXnorList ';'			{ $$ = $2; }
+gateDecl: 	yBUF  delayE gateBufList ';'		{ $$ = $3; }
+	|	yNOT  delayE gateNotList ';'		{ $$ = $3; }
+	|	yAND  delayE gateAndList ';'		{ $$ = $3; }
+	|	yNAND delayE gateNandList ';'		{ $$ = $3; }
+	|	yOR   delayE gateOrList ';'		{ $$ = $3; }
+	|	yNOR  delayE gateNorList ';'		{ $$ = $3; }
+	|	yXOR  delayE gateXorList ';'		{ $$ = $3; }
+	|	yXNOR delayE gateXnorList ';'		{ $$ = $3; }
 	;
 
 gateBufList:	gateBuf 				{ $$ = $1; }
diff --git a/test_regress/t/t_gate_basic.v b/test_regress/t/t_gate_basic.v
index c70f0f76b..f8a3a4fbd 100644
--- a/test_regress/t/t_gate_basic.v
+++ b/test_regress/t/t_gate_basic.v
@@ -20,8 +20,8 @@ module t (/*AUTOARG*/
 
    // verilator lint_off IMPLICIT
    not   NT0 (nt0, a[0]);
-   and   AN0 (an0, a[0], b[0]);
-   nand  ND0 (nd0, a[0], b[0], b[1]);
+   and   #1       AN0 (an0, a[0], b[0]);
+   nand  #(2,3,4) ND0 (nd0, a[0], b[0], b[1]);
    or    OR0 (or0, a[0], b[0]);
    nor   NR0 (nr0, a[0], b[0], b[2]);
    xor       (xo0, a[0], b[0]);