diff --git a/test_regress/t/t_timing_clkgen.pl b/test_regress/t/t_timing_clkgen.pl
new file mode 100755
index 000000000..e1998178c
--- /dev/null
+++ b/test_regress/t/t_timing_clkgen.pl
@@ -0,0 +1,29 @@
+#!/usr/bin/env perl
+if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2019 by Wilson Snyder. This program is free software; you
+# can redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
+
+scenarios(simulator => 1);
+
+$Self->{vlt_all} and unsupported("Verilator unsupported, clocking");
+
+compile(
+    #verilator_flags2 => ['--exe --build --main --timing'],  # Unsupported
+    verilator_flags2 => ['--exe --build --main --bbox-unsup -Wno-STMTDLY -Wno-INITIALDLY'],
+    verilator_make_cmake => 0,
+    verilator_make_gmake => 0,
+    make_main => 0,
+    make_top => 1,
+    );
+
+execute(
+    check_finished => 1,
+    );
+
+ok(1);
+1;
diff --git a/test_regress/t/t_timing_clkgen.v b/test_regress/t/t_timing_clkgen.v
new file mode 100644
index 000000000..12cc19a41
--- /dev/null
+++ b/test_regress/t/t_timing_clkgen.v
@@ -0,0 +1,41 @@
+// DESCRIPTION: Verilator: Verilog Test module
+//
+// This file ONLY is placed under the Creative Commons Public Domain, for
+// any use, without warranty, 2020 by Wilson Snyder.
+// SPDX-License-Identifier: CC0-1.0
+
+module clkgen(output bit clk);
+   initial begin
+      #(8.0:5:3) clk = 1;  // Middle is default
+      forever begin
+         #5 clk = ~clk;
+      end
+   end
+endmodule
+
+module t(/*AUTOARG*/);
+   wire logic clk;
+
+   clkgen clkgen (.clk);
+
+   int  cyc;
+   always @ (posedge clk) begin
+      cyc <= cyc + 1;
+`ifdef TEST_VERBOSE
+      $display("[%0t] cyc=%0d", $time, cyc);
+`endif
+      if (cyc == 0) begin
+         if ($time != 5) $stop;
+      end
+      else if (cyc == 1) begin
+         if ($time != 15) $stop;
+      end
+      else if (cyc == 2) begin
+         if ($time != 25) $stop;
+      end
+      else if (cyc == 9) begin
+         $write("*-* All Finished *-*\n");
+         $finish;
+      end
+   end
+endmodule
diff --git a/test_regress/t/t_timing_long.pl b/test_regress/t/t_timing_long.pl
new file mode 100755
index 000000000..031575331
--- /dev/null
+++ b/test_regress/t/t_timing_long.pl
@@ -0,0 +1,71 @@
+#!/usr/bin/env perl
+if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2003 by Wilson Snyder. This program is free software; you
+# can redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
+use IO::File;
+
+scenarios(simulator => 1);
+
+# Look for O(n^2) problems in process handling
+
+sub gen {
+    my $filename = shift;
+
+    my $fh = IO::File->new(">$filename");
+    $fh->print("// Generated by t_timing_long.pl\n");
+
+    $fh->print("\n");
+    $fh->print("`ifdef TEST_VERBOSE\n");
+    $fh->print(" `define MSG(m) \$display m\n");
+    $fh->print("`else\n");
+    $fh->print(" `define MSG(m)\n");
+    $fh->print("`endif\n");
+    $fh->print("\n");
+
+    $fh->print("module t;\n");
+    $fh->print("\n");
+    $fh->print("  int cnt;\n");
+    $fh->print("\n");
+    $fh->print("  initial begin\n");
+
+    my $n = 100;
+    for (my $i=1; $i<$n; ++$i) {
+        # If statement around the timing is important to make the code scheduling
+        # mostly unpredictable
+        $fh->printf("    if (cnt == %d) begin\n", $i-1);
+        $fh->printf("      #1; ++cnt; `MSG((\"[%0t] cnt?=${i}\", \$time));"
+                    ." if (cnt != %d) \$stop;\n", $i);
+        $fh->printf("    end\n");
+    }
+
+    $fh->print("\n");
+    $fh->print('    $write("*-* All Finished *-*\n");',"\n");
+    $fh->print('    $finish;',"\n");
+    $fh->print("  end\n");
+    $fh->print("endmodule\n");
+}
+
+top_filename("$Self->{obj_dir}/t_timing_long.v");
+
+gen($Self->{top_filename});
+
+compile(
+    #verilator_flags2=>["--exe --build --main --timing"],  # Unsupported
+    verilator_flags2=>["--exe --build --main -Wno-STMTDLY"],
+    verilator_make_cmake => 0,
+    verilator_make_gmake => 0,
+    make_main => 0,
+    make_top => 1,
+    );
+
+execute(
+    check_finished => 1,
+    );
+
+ok(1);
+1;
diff --git a/test_regress/t/t_timing_reentry.pl b/test_regress/t/t_timing_reentry.pl
new file mode 100755
index 000000000..cf634ac0e
--- /dev/null
+++ b/test_regress/t/t_timing_reentry.pl
@@ -0,0 +1,28 @@
+#!/usr/bin/env perl
+if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2019 by Wilson Snyder. This program is free software; you
+# can redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
+
+scenarios(simulator => 1);
+
+compile(
+    #verilator_flags2 => ['--exe --build --main --timing'],  # Unsupported
+    verilator_flags2 => ['--exe --build --main --bbox-unsup -Wno-STMTDLY -Wno-INITIALDLY'],
+    verilator_make_cmake => 0,
+    verilator_make_gmake => 0,
+    make_main => 0,
+    make_top => 1,
+    );
+
+# Will fail, unsupported
+#execute(
+#    check_finished => 1,
+#    );
+
+ok(1);
+1;
diff --git a/test_regress/t/t_timing_reentry.v b/test_regress/t/t_timing_reentry.v
new file mode 100644
index 000000000..c3a7bb16d
--- /dev/null
+++ b/test_regress/t/t_timing_reentry.v
@@ -0,0 +1,35 @@
+// DESCRIPTION: Verilator: Verilog Test module
+//
+// This file ONLY is placed under the Creative Commons Public Domain, for
+// any use, without warranty, 2020 by Wilson Snyder.
+// SPDX-License-Identifier: CC0-1.0
+
+module t(/*AUTOARG*/);
+   event a, b;
+
+   int   order = 0;
+
+   initial begin
+      order++; if (order != 1) $stop;
+      #10;
+      $display("[%0t]%0d -> a", $time, order);
+      order++; if (order != 2) $stop;
+      -> a;
+      #10;
+      $display("[%0t]%0d -> b", $time, order);
+      order++; if (order != 4) $stop;
+      -> b;
+      #100;
+      order++; if (order != 6) $stop;
+      $write("*-* All Finished *-*\n");
+      $finish;
+   end
+
+   always @ (a or b) begin
+      $display("[%0t]%0d entering", $time, order);
+      order++; if (order != 3) $stop;
+      #15;
+      $display("[%0t]%0d 15 later", $time, order);
+      order++; if (order != 5) $stop;
+   end
+endmodule