diff --git a/src/V3Width.cpp b/src/V3Width.cpp index 7e2f4af83..109875ae2 100644 --- a/src/V3Width.cpp +++ b/src/V3Width.cpp @@ -4680,17 +4680,17 @@ class WidthVisitor final : public VNVisitor { "Assignment pattern key not supported/understood: " << patp->keyp()->prettyTypeName()); } - } else { + } else if (memp) { // constant expr - if (memp) { - const std::pair ret - = patmap.emplace(memp, patp); - if (!ret.second) { - patp->v3error("Assignment pattern contains duplicate entry: " - << VN_AS(patp->keyp(), Text)->text()); - } - memp = VN_AS(memp->nextp(), MemberDType); + const std::pair ret = patmap.emplace(memp, patp); + if (!ret.second) { + patp->v3error("Assignment pattern contains duplicate entry: " + << VN_AS(patp->keyp(), Text)->text()); } + memp = VN_AS(memp->nextp(), MemberDType); + } else { + patp->v3error( + "Assignment pattern contains more entries than structure members"); } } while (false); diff --git a/test_regress/t/t_struct_pat_toomany_bad.out b/test_regress/t/t_struct_pat_toomany_bad.out new file mode 100644 index 000000000..b3789facf --- /dev/null +++ b/test_regress/t/t_struct_pat_toomany_bad.out @@ -0,0 +1,6 @@ +%Error: t/t_struct_pat_toomany_bad.v:12:18: Assignment pattern contains more entries than structure members + : ... note: In instance 't' + 12 | } sp = '{1, 2, 3}; + | ^ + ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. +%Error: Exiting due to diff --git a/test_regress/t/t_struct_pat_toomany_bad.py b/test_regress/t/t_struct_pat_toomany_bad.py new file mode 100755 index 000000000..55203b6c9 --- /dev/null +++ b/test_regress/t/t_struct_pat_toomany_bad.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2025 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') + +test.lint(fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_struct_pat_toomany_bad.v b/test_regress/t/t_struct_pat_toomany_bad.v new file mode 100644 index 000000000..2bc918d09 --- /dev/null +++ b/test_regress/t/t_struct_pat_toomany_bad.v @@ -0,0 +1,18 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2025 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 + +module t; + + struct packed { + int m_i; + byte m_b; + } sp = '{1, 2, 3}; // BAD, too many elements + + initial begin + $display("FAILED"); + end + +endmodule