From 52900625498a41fecc0d3bd5e14e56e46c0cb909 Mon Sep 17 00:00:00 2001 From: Krzysztof Bieganski Date: Mon, 3 May 2021 23:59:41 +0200 Subject: [PATCH] Fix bounds check in VL_SEL_IWII (#2910) --- include/verilated.h | 2 +- test_regress/t/t_emit_constw.v | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/include/verilated.h b/include/verilated.h index f9a15307c..7df6e08de 100644 --- a/include/verilated.h +++ b/include/verilated.h @@ -2705,7 +2705,7 @@ static inline IData VL_BITSEL_IWII(int, int lbits, int, int, WDataInP lwp, IData static inline IData VL_SEL_IWII(int, int lbits, int, int, WDataInP lwp, IData lsb, IData width) VL_MT_SAFE { int msb = lsb + width - 1; - if (VL_UNLIKELY(msb > lbits)) { + if (VL_UNLIKELY(msb >= lbits)) { return ~0; // Spec says you can go outside the range of a array. Don't coredump if so. } else if (VL_BITWORD_E(msb) == VL_BITWORD_E(static_cast(lsb))) { return VL_BITRSHIFT_W(lwp, lsb); diff --git a/test_regress/t/t_emit_constw.v b/test_regress/t/t_emit_constw.v index e49d532de..ae9774734 100644 --- a/test_regress/t/t_emit_constw.v +++ b/test_regress/t/t_emit_constw.v @@ -62,7 +62,7 @@ module t (/*AUTOARG*/ ^ bytehash(w17)); // verilator lint_on WIDTH -`define EXPECTED_SUM 64'hb6fdb64085fc17f5 +`define EXPECTED_SUM 64'h2bc7c2a98a302891 // Test loop always @ (posedge clk) begin