diff --git a/test_regress/t/t_split_var_0.v b/test_regress/t/t_split_var_0.v index 724a89215..649fd61b4 100644 --- a/test_regress/t/t_split_var_0.v +++ b/test_regress/t/t_split_var_0.v @@ -182,6 +182,26 @@ module barshift_bitslice #(parameter depth = 2, localparam width = 2**depth) ( endmodule +module var_decl_with_init(); + + /*verilator lint_off LITENDIAN*/ +logic [-1:30] var0 = {4'd0, 4'd1, 4'd2, 4'd3, 4'd4, 4'd5, 4'd6, 4'd7}; /* verilator split_var */ +logic [-1:30] var2; /* verilator split_var */ + /*verilator lint_on LITENDIAN*/ +logic [30:-1] var1 = {4'd0, 4'd1, 4'd2, 4'd3, 4'd4, 4'd5, 4'd6, 4'd7}; /* verilator split_var */ +logic [30:-1] var3; /* verilator split_var */ + +initial begin + var2[-1:2] = 4'd2; + var3[2:-1] = 4'd3; + $display("%x %x", var0, var1); + $display("%x %x", var2, var3); + var0[-1:5] = 7'd0; + var1[10:3] = 8'd2; +end + +endmodule + module t(/*AUTOARG*/ clk); input clk; localparam depth = 3; @@ -200,6 +220,7 @@ module t(/*AUTOARG*/ clk); barshift_2d_packed_array_le #(.depth(depth)) shifter5(.in(in), .out(out[5]), .shift(shift)); barshift_1d_packed_struct shifter6(.in(in), .out(out[6]), .shift(shift)); barshift_bitslice #(.depth(depth)) shifter7(.in(in), .out(out[7]), .shift(shift)); + var_decl_with_init i_var_decl_with_init(); assign in = 8'b10001110; /*verilator lint_off LITENDIAN*/ @@ -207,7 +228,7 @@ module t(/*AUTOARG*/ clk); 8'b10001110, 8'b01000111, 8'b10100011, 8'b11010001, 8'b11101000, 8'b01110100, 8'b00111010, 8'b00011101}; /*verilator lint_on LITENDIAN*/ - always @(posedge clk) begin + always @(posedge clk) begin : always_block automatic bit failed = 0; $display("in:%b shift:%d exp:%b", in, shift, exp[7-shift]); for (int i = 0; i < numsub; ++i) begin diff --git a/test_regress/t/t_split_var_1_bad.out b/test_regress/t/t_split_var_1_bad.out index 7d38b33f5..ea8686501 100644 --- a/test_regress/t/t_split_var_1_bad.out +++ b/test_regress/t/t_split_var_1_bad.out @@ -23,15 +23,15 @@ : ... In instance t.i_sub3 cannot_split1 = cannot_split0; ^~~~~~~~~~~~~ -%Warning-SPLITVAR: t/t_split_var_1_bad.v:5: Pragma split_var is specified on a variable whose type is not supported. Packed portion must be an aggregate type of bit or logic. +%Warning-SPLITVAR: t/t_split_var_1_bad.v:5: Pragma split_var is specified on a variable whose type is unsupported or public. Packed portion must be an aggregate type of bit or logic. : ... In instance t real should_show_warning0; /*verilator split_var*/ ^~~~~~~~~~~~~~~~~~~~~~~ -%Warning-SPLITVAR: t/t_split_var_1_bad.v:6: Pragma split_var is specified on a variable whose type is not supported. Packed portion must be an aggregate type of bit or logic. +%Warning-SPLITVAR: t/t_split_var_1_bad.v:6: Pragma split_var is specified on a variable whose type is unsupported or public. Packed portion must be an aggregate type of bit or logic. : ... In instance t string should_show_warning1[0:2]; /*verilator split_var*/ ^~~~~~~~~~~~~~~~~~~~ -%Warning-SPLITVAR: t/t_split_var_1_bad.v:7: Pragma split_var is specified on a variable whose type is not supported. Packed portion must be an aggregate type of bit or logic. +%Warning-SPLITVAR: t/t_split_var_1_bad.v:7: Pragma split_var is specified on a variable whose type is unsupported or public. Packed portion must be an aggregate type of bit or logic. : ... In instance t wire should_show_warning2; /*verilator split_var*/ ^~~~~~~~~~~~~~~~~~~~~~~ diff --git a/test_regress/t/t_split_var_2_trace.out b/test_regress/t/t_split_var_2_trace.out new file mode 100644 index 000000000..0166905ec --- /dev/null +++ b/test_regress/t/t_split_var_2_trace.out @@ -0,0 +1,505 @@ +$version Generated by VerilatedVcd $end +$date Wed Jan 8 23:03:07 2020 + $end +$timescale 1ns $end + + $scope module top $end + $var wire 1 Y# clk $end + $scope module t $end + $var wire 1 Y# clk $end + $var wire 32 a# depth [31:0] $end + $var wire 64 y# exp [63:0] $end + $var wire 8 q# in [7:0] $end + $var wire 32 i# numsub [31:0] $end + $var wire 8 C out(0) [7:0] $end + $var wire 8 D out(1) [7:0] $end + $var wire 8 E out(2) [7:0] $end + $var wire 8 F out(3) [7:0] $end + $var wire 8 G out(4) [7:0] $end + $var wire 8 H out(5) [7:0] $end + $var wire 8 I out(6) [7:0] $end + $var wire 8 J out(7) [7:0] $end + $var wire 3 %! shift [2:0] $end + $var wire 32 i# width [31:0] $end + $scope module always_block $end + $var wire 1 I# failed $end + $scope module unnamedblk1 $end + $var wire 32 Q# i [31:0] $end + $upscope $end + $upscope $end + $scope module i_var_decl_with_init $end + $var wire 32 # var0 [-1:30] $end + $var wire 32 3 var1 [30:-1] $end + $var wire 32 + var2 [-1:30] $end + $var wire 32 ; var3 [30:-1] $end + $upscope $end + $scope module shifter0 $end + $var wire 32 a# depth [31:0] $end + $var wire 8 q# in [7:0] $end + $var wire 32 +$ offset [31:0] $end + $var wire 8 -! out [7:0] $end + $var wire 3 %! shift [2:0] $end + $var wire 8 =! tmp(-1)[7:0] [7:0] $end + $var wire 8 5! tmp(-2)[7:0] [7:0] $end + $var wire 8 q# tmp(-3)[7:0] [7:0] $end + $var wire 8 -! tmp(0)[7:0] [7:0] $end + $var wire 32 i# width [31:0] $end + $upscope $end + $scope module shifter1 $end + $var wire 32 a# depth [31:0] $end + $var wire 8 q# in [7:0] $end + $var wire 32 3$ offset [31:0] $end + $var wire 8 E! out [7:0] $end + $var wire 3 %! shift [2:0] $end + $var wire 8 q# tmp(1)[7:0] [7:0] $end + $var wire 8 M! tmp(2)[7:0] [7:0] $end + $var wire 8 U! tmp(3)[7:0] [7:0] $end + $var wire 8 E! tmp(4)[7:0] [7:0] $end + $var wire 32 i# width [31:0] $end + $upscope $end + $scope module shifter2 $end + $var wire 32 a# depth [31:0] $end + $var wire 8 q# in [7:0] $end + $var wire 32 a# n [31:0] $end + $var wire 32 3$ offset [31:0] $end + $var wire 8 ]! out [7:0] $end + $var wire 3 %! shift [2:0] $end + $var wire 8 q# tmp(1)(1)[7:0] [7:0] $end + $var wire 8 q# tmp(1)(2)[7:0] [7:0] $end + $var wire 8 q# tmp(1)(3)[7:0] [7:0] $end + $var wire 8 e! tmp(2)(1)[7:0] [7:0] $end + $var wire 8 m! tmp(2)(2)[7:0] [7:0] $end + $var wire 8 u! tmp(2)(3)[7:0] [7:0] $end + $var wire 8 }! tmp(3)(1)[7:0] [7:0] $end + $var wire 8 '" tmp(3)(2)[7:0] [7:0] $end + $var wire 8 /" tmp(3)(3)[7:0] [7:0] $end + $var wire 8 ]! tmp(4)(1)[7:0] [7:0] $end + $var wire 8 7" tmp(4)(2)[7:0] [7:0] $end + $var wire 8 ?" tmp(4)(3)[7:0] [7:0] $end + $var wire 32 i# width [31:0] $end + $upscope $end + $scope module shifter3 $end + $var wire 32 a# depth [31:0] $end + $var wire 8 q# in [7:0] $end + $var wire 32 ;$ offset [31:0] $end + $var wire 8 G" out [7:0] $end + $var wire 24 K$ pad [23:0] $end + $var wire 3 %! shift [2:0] $end + $var wire 32 C$ tmp(2)[31:0] [31:0] $end + $var wire 32 O" tmp(3)[31:0] [31:0] $end + $var wire 32 W" tmp(4)[31:0] [31:0] $end + $var wire 32 _" tmp(5)[31:0] [31:0] $end + $var wire 32 i# width [31:0] $end + $upscope $end + $scope module shifter4 $end + $var wire 32 a# depth [31:0] $end + $var wire 8 q# in [7:0] $end + $var wire 32 S$ offset [31:0] $end + $var wire 8 g" out [7:0] $end + $var wire 3 %! shift [2:0] $end + $var wire 32 o" tmp [31:0] $end + $var wire 32 i# width [31:0] $end + $upscope $end + $scope module shifter5 $end + $var wire 32 a# depth [31:0] $end + $var wire 8 q# in [7:0] $end + $var wire 32 S$ offset [31:0] $end + $var wire 8 w" out [7:0] $end + $var wire 3 %! shift [2:0] $end + $var wire 32 !# tmp [31:0] $end + $var wire 32 i# width [31:0] $end + $upscope $end + $scope module shifter6 $end + $var wire 32 a# depth [31:0] $end + $var wire 8 q# in [7:0] $end + $var wire 8 )# out [7:0] $end + $var wire 3 %! shift [2:0] $end + $var wire 32 1# tmp [31:0] $end + $var wire 32 i# width [31:0] $end + $upscope $end + $scope module shifter7 $end + $var wire 32 a# depth [31:0] $end + $var wire 8 q# in [7:0] $end + $var wire 8 9# out [7:0] $end + $var wire 3 %! shift [2:0] $end + $var wire 32 A# tmp [0:31] $end + $var wire 32 i# width [31:0] $end + $upscope $end + $upscope $end + $upscope $end +$enddefinitions $end + + +#0 +b00000001001000110100010101100111 # +b00100000000000000000000000000000 + +b00000001001000110100000000100111 3 +b00000000000000000000000000000011 ; +b10001110 C +b10001110 D +b10001110 E +b10001110 F +b10001110 G +b10001110 H +b10001110 I +b10001110 J +b000 %! +b10001110 -! +b10001110 5! +b10001110 =! +b10001110 E! +b10001110 M! +b10001110 U! +b10001110 ]! +b10001110 e! +b10001110 m! +b10001110 u! +b10001110 }! +b10001110 '" +b10001110 /" +b10001110 7" +b10001110 ?" +b10001110 G" +b00000000000000000000000010001110 O" +b00000000000000000000000010001110 W" +b00000000000000000000000010001110 _" +b10001110 g" +b10001110100011101000111010001110 o" +b10001110 w" +b10001110100011101000111010001110 !# +b10001110 )# +b10001110100011101000111010001110 1# +b10001110 9# +b10001110100011101000111010001110 A# +0I# +b00000000000000000000000000000000 Q# +0Y# +b00000000000000000000000000000011 a# +b00000000000000000000000000001000 i# +b10001110 q# +b1000111001000111101000111101000111101000011101000011101000011101 y# +b11111111111111111111111111111101 +$ +b00000000000000000000000000000001 3$ +b00000000000000000000000000000010 ;$ +b00000000000000000000000010001110 C$ +b000000000000000000000000 K$ +b11111111111111111111111111111110 S$ +#10 +b01000111 C +b01000111 D +b01000111 E +b01000111 F +b01000111 G +b01000111 H +b01000111 I +b01000111 J +b001 %! +b01000111 -! +b01000111 5! +b01000111 =! +b01000111 E! +b01000111 M! +b01000111 U! +b01000111 ]! +b01000111 e! +b01000111 m! +b01000111 u! +b01000111 }! +b01000111 '" +b01000111 /" +b01000111 7" +b01000111 ?" +b01000111 G" +b00000000000000000000000001000111 O" +b00000000000000000000000001000111 W" +b00000000000000000000000001000111 _" +b01000111 g" +b10001110010001110100011101000111 o" +b01000111 w" +b10001110010001110100011101000111 !# +b01000111 )# +b10001110010001110100011101000111 1# +b01000111 9# +b10001110010001110100011101000111 A# +b00000000000000000000000000001000 Q# +1Y# +#15 +0Y# +#20 +b10100011 C +b10100011 D +b10100011 E +b10100011 F +b10100011 G +b10100011 H +b10100011 I +b10100011 J +b010 %! +b10100011 -! +b10001110 5! +b10100011 =! +b10100011 E! +b10001110 M! +b10100011 U! +b10100011 ]! +b10001110 e! +b10001110 m! +b10001110 u! +b10100011 }! +b10100011 '" +b10100011 /" +b10100011 7" +b10100011 ?" +b10100011 G" +b00000000000000000000000010001110 O" +b00000000000000000000000010100011 W" +b00000000000000000000000010100011 _" +b10100011 g" +b10001110100011101010001110100011 o" +b10100011 w" +b10001110100011101010001110100011 !# +b10100011 )# +b10001110100011101010001110100011 1# +b10100011 9# +b10001110100011101010001110100011 A# +1Y# +#25 +0Y# +#30 +b11010001 C +b11010001 D +b11010001 E +b11010001 F +b11010001 G +b11010001 H +b11010001 I +b11010001 J +b011 %! +b11010001 -! +b01000111 5! +b11010001 =! +b11010001 E! +b01000111 M! +b11010001 U! +b11010001 ]! +b01000111 e! +b01000111 m! +b01000111 u! +b11010001 }! +b11010001 '" +b11010001 /" +b11010001 7" +b11010001 ?" +b11010001 G" +b00000000000000000000000001000111 O" +b00000000000000000000000011010001 W" +b00000000000000000000000011010001 _" +b11010001 g" +b10001110010001111101000111010001 o" +b11010001 w" +b10001110010001111101000111010001 !# +b11010001 )# +b10001110010001111101000111010001 1# +b11010001 9# +b10001110010001111101000111010001 A# +1Y# +#35 +0Y# +#40 +b11101000 C +b11101000 D +b11101000 E +b11101000 F +b11101000 G +b11101000 H +b11101000 I +b11101000 J +b100 %! +b11101000 -! +b10001110 5! +b10001110 =! +b11101000 E! +b10001110 M! +b10001110 U! +b11101000 ]! +b10001110 e! +b10001110 m! +b10001110 u! +b10001110 }! +b10001110 '" +b10001110 /" +b11101000 7" +b11101000 ?" +b11101000 G" +b00000000000000000000000010001110 O" +b00000000000000000000000010001110 W" +b00000000000000000000000011101000 _" +b11101000 g" +b10001110100011101000111011101000 o" +b11101000 w" +b10001110100011101000111011101000 !# +b11101000 )# +b10001110100011101000111011101000 1# +b11101000 9# +b10001110100011101000111011101000 A# +1Y# +#45 +0Y# +#50 +b01110100 C +b01110100 D +b01110100 E +b01110100 F +b01110100 G +b01110100 H +b01110100 I +b01110100 J +b101 %! +b01110100 -! +b01000111 5! +b01000111 =! +b01110100 E! +b01000111 M! +b01000111 U! +b01110100 ]! +b01000111 e! +b01000111 m! +b01000111 u! +b01000111 }! +b01000111 '" +b01000111 /" +b01110100 7" +b01110100 ?" +b01110100 G" +b00000000000000000000000001000111 O" +b00000000000000000000000001000111 W" +b00000000000000000000000001110100 _" +b01110100 g" +b10001110010001110100011101110100 o" +b01110100 w" +b10001110010001110100011101110100 !# +b01110100 )# +b10001110010001110100011101110100 1# +b01110100 9# +b10001110010001110100011101110100 A# +1Y# +#55 +0Y# +#60 +b00111010 C +b00111010 D +b00111010 E +b00111010 F +b00111010 G +b00111010 H +b00111010 I +b00111010 J +b110 %! +b00111010 -! +b10001110 5! +b10100011 =! +b00111010 E! +b10001110 M! +b10100011 U! +b00111010 ]! +b10001110 e! +b10001110 m! +b10001110 u! +b10100011 }! +b10100011 '" +b10100011 /" +b00111010 7" +b00111010 ?" +b00111010 G" +b00000000000000000000000010001110 O" +b00000000000000000000000010100011 W" +b00000000000000000000000000111010 _" +b00111010 g" +b10001110100011101010001100111010 o" +b00111010 w" +b10001110100011101010001100111010 !# +b00111010 )# +b10001110100011101010001100111010 1# +b00111010 9# +b10001110100011101010001100111010 A# +1Y# +#65 +0Y# +#70 +b00011101 C +b00011101 D +b00011101 E +b00011101 F +b00011101 G +b00011101 H +b00011101 I +b00011101 J +b111 %! +b00011101 -! +b01000111 5! +b11010001 =! +b00011101 E! +b01000111 M! +b11010001 U! +b00011101 ]! +b01000111 e! +b01000111 m! +b01000111 u! +b11010001 }! +b11010001 '" +b11010001 /" +b00011101 7" +b00011101 ?" +b00011101 G" +b00000000000000000000000001000111 O" +b00000000000000000000000011010001 W" +b00000000000000000000000000011101 _" +b00011101 g" +b10001110010001111101000100011101 o" +b00011101 w" +b10001110010001111101000100011101 !# +b00011101 )# +b10001110010001111101000100011101 1# +b00011101 9# +b10001110010001111101000100011101 A# +1Y# +#75 +0Y# +#80 +b10001110 C +b10001110 D +b10001110 E +b10001110 F +b10001110 G +b10001110 H +b10001110 I +b10001110 J +b000 %! +b10001110 -! +b10001110 5! +b10001110 =! +b10001110 E! +b10001110 M! +b10001110 U! +b10001110 ]! +b10001110 e! +b10001110 m! +b10001110 u! +b10001110 }! +b10001110 '" +b10001110 /" +b10001110 7" +b10001110 ?" +b10001110 G" +b00000000000000000000000010001110 O" +b00000000000000000000000010001110 W" +b00000000000000000000000010001110 _" +b10001110 g" +b10001110100011101000111010001110 o" +b10001110 w" +b10001110100011101000111010001110 !# +b10001110 )# +b10001110100011101000111010001110 1# +b10001110 9# +b10001110100011101000111010001110 A# +1Y# diff --git a/test_regress/t/t_split_var_2_trace.pl b/test_regress/t/t_split_var_2_trace.pl new file mode 100755 index 000000000..3cc2063e9 --- /dev/null +++ b/test_regress/t/t_split_var_2_trace.pl @@ -0,0 +1,24 @@ +#!/usr/bin/perl +if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2003 by Wilson Snyder. This program is free software; you can +# redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. + +scenarios(simulator => 1); +top_filename("t/t_split_var_0.v"); + +compile( + verilator_flags2 => ['--cc --trace'], + ); + +execute( + check_finished => 1, + ); + +vcd_identical("$Self->{obj_dir}/simx.vcd", $Self->{golden_filename}); + +ok(1); +1;