From 51c36818596202e6ee5deb1c93293ab59d15fed2 Mon Sep 17 00:00:00 2001 From: Yilou Wang Date: Wed, 1 Jul 2026 15:55:19 +0200 Subject: [PATCH] Inherit default clocking for a sequence used as an event control --- src/V3AssertNfa.cpp | 7 +++++- test_regress/t/t_assert_seq_event.v | 24 ++++++++++++++++----- test_regress/t/t_assert_seq_event_unsup.out | 12 +++++------ test_regress/t/t_assert_seq_event_unsup.v | 9 ++------ 4 files changed, 33 insertions(+), 19 deletions(-) diff --git a/src/V3AssertNfa.cpp b/src/V3AssertNfa.cpp index 07ba3e27f..2f404fed3 100644 --- a/src/V3AssertNfa.cpp +++ b/src/V3AssertNfa.cpp @@ -2762,7 +2762,12 @@ class AssertNfaVisitor final : public VNVisitor { VL_DO_DANGLING(pushDeletep(specp), specp); return; } - // A clockless sequence has no sampling edge; require an explicit clock. + // Inherit the module default clocking (IEEE 14.12, 16.15) when the + // sequence has none of its own. + if (!specp->sensesp() && m_defaultClockingp) { + specp->sensesp(m_defaultClockingp->sensesp()->cloneTree(true)); + } + // A clockless sequence with no default clocking has no sampling edge. if (!specp->sensesp()) { specp->v3warn(E_UNSUPPORTED, "Unsupported: '@' event control on a sequence without a clocking event"); diff --git a/test_regress/t/t_assert_seq_event.v b/test_regress/t/t_assert_seq_event.v index 2f912c5b4..c752f5758 100644 --- a/test_regress/t/t_assert_seq_event.v +++ b/test_regress/t/t_assert_seq_event.v @@ -16,7 +16,7 @@ module t ( bit a, b, c; bit a1, a2, b1; int cyc = 0; - int seq_hits = 0, seq_hits2 = 0, ref_hits = 0, one_hits = 0; + int seq_hits = 0, seq_hits2 = 0, ref_hits = 0, one_hits = 0, dc_hits = 0; // verilog_format: off // verible does not support clocking events inside sequence declarations sequence seq; @@ -28,6 +28,15 @@ module t ( endsequence // verilog_format: on + // seq_dc has no clocking event, so it inherits the default clocking and must + // behave identically to the explicitly-clocked seq above. + default clocking @(posedge clk); + endclocking + + sequence seq_dc; + a ##1 b ##1 c; + endsequence + // A sequence used as an `@` event control resumes once per sequence end point // (IEEE 1800-2023 9.4.2.4). seq_hits/seq_hits2 are two waiters on the same // multi-cycle sequence; ref_hits is an independent shift-register oracle (end @@ -44,6 +53,10 @@ module t ( @seq_one; one_hits = one_hits + 1; end + initial forever begin + @seq_dc; + dc_hits = dc_hits + 1; + end always @(posedge clk) begin if (a2 && b1 && c) ref_hits = ref_hits + 1; @@ -66,10 +79,11 @@ module t ( // Counts read in final (Postponed) to avoid same-timestep races. final begin - `checkd(seq_hits, 14); // Questa: 14 - `checkd(seq_hits2, 14); // Questa: 14 - `checkd(ref_hits, 14); // Questa: 14 - `checkd(one_hits, 30); // Questa: 30 + `checkd(seq_hits, 14); + `checkd(seq_hits2, 14); + `checkd(ref_hits, 14); + `checkd(one_hits, 30); + `checkd(dc_hits, 14); $write("*-* All Finished *-*\n"); end endmodule diff --git a/test_regress/t/t_assert_seq_event_unsup.out b/test_regress/t/t_assert_seq_event_unsup.out index 27270c9fc..3dcb6e752 100644 --- a/test_regress/t/t_assert_seq_event_unsup.out +++ b/test_regress/t/t_assert_seq_event_unsup.out @@ -1,11 +1,11 @@ -%Error-UNSUPPORTED: t/t_assert_seq_event_unsup.v:33:6: Unsupported: '@' event control on a sequence without a clocking event - 33 | @s_unclocked; +%Error-UNSUPPORTED: t/t_assert_seq_event_unsup.v:28:6: Unsupported: '@' event control on a sequence without a clocking event + 28 | @s_clockless; | ^~~~~~~~~~~ ... For error description see https://verilator.org/warn/UNSUPPORTED?v=latest -%Error-UNSUPPORTED: t/t_assert_seq_event_unsup.v:24:5: Unsupported: non-edge clocking event on a sequence; use an edge such as @(posedge clk) - 24 | @(g) a ##1 b; +%Error-UNSUPPORTED: t/t_assert_seq_event_unsup.v:19:5: Unsupported: non-edge clocking event on a sequence; use an edge such as @(posedge clk) + 19 | @(g) a ##1 b; | ^ -%Error-UNSUPPORTED: t/t_assert_seq_event_unsup.v:35:6: Unsupported: this sequence form referenced by an '@' event control - 35 | @s_noncons; +%Error-UNSUPPORTED: t/t_assert_seq_event_unsup.v:30:6: Unsupported: this sequence form referenced by an '@' event control + 30 | @s_noncons; | ^~~~~~~~~ %Error: Exiting due to diff --git a/test_regress/t/t_assert_seq_event_unsup.v b/test_regress/t/t_assert_seq_event_unsup.v index 131372125..886611d2e 100644 --- a/test_regress/t/t_assert_seq_event_unsup.v +++ b/test_regress/t/t_assert_seq_event_unsup.v @@ -10,13 +10,8 @@ module t ( bit a, b; logic g = 0; - // Clockless `@seq` stays E_UNSUPPORTED even under a default clocking, matching - // Questa; whether 9.4.2.4 should inherit it here is an open PR question. - default clocking @(posedge clk); - endclocking - // verilog_format: off - sequence s_unclocked; + sequence s_clockless; a ##1 b; endsequence @@ -30,7 +25,7 @@ module t ( // verilog_format: on initial begin - @s_unclocked; + @s_clockless; @s_nonedge; @s_noncons; end