From 51616ecf2f13220296318fbe6bb30c67b539731b Mon Sep 17 00:00:00 2001 From: Wilson Snyder Date: Sun, 4 May 2025 14:57:10 -0400 Subject: [PATCH] Internals: Rename to instances, and other minor cleanups --- docs/guide/exe_verilator.rst | 2 +- src/V3Class.cpp | 2 +- src/V3ParseImp.cpp | 6 +- src/V3ParseImp.h | 4 +- src/verilog.y | 80 ++++++++++++++------------ test_regress/t/t_config_libmap.map | 5 ++ test_regress/t/t_config_libmap.out | 33 ++++++----- test_regress/t/t_config_libmap_inc.map | 1 + test_regress/t/t_param_type_bad.out | 2 +- 9 files changed, 75 insertions(+), 60 deletions(-) diff --git a/docs/guide/exe_verilator.rst b/docs/guide/exe_verilator.rst index 3024d07f0..fad7ec37e 100644 --- a/docs/guide/exe_verilator.rst +++ b/docs/guide/exe_verilator.rst @@ -183,7 +183,7 @@ Summary: With :vlopt:`--clk`, the specified signal is marked as a clock signal. The provided signal name is specified using a RTL hierarchy path. For - example, v.foo.bar. If the signal is the input to top-module, then + example, v.foo.bar. If the signal is the input to the top-module, then directly provide the signal name. Alternatively, use a :option:`/*verilator&32;clocker*/` metacomment in RTL file to mark the signal directly. diff --git a/src/V3Class.cpp b/src/V3Class.cpp index 656ce3db2..3139ded69 100644 --- a/src/V3Class.cpp +++ b/src/V3Class.cpp @@ -40,7 +40,7 @@ class ClassVisitor final : public VNVisitor { const VNUser1InUse m_inuser1; // MEMBERS - string m_prefix; // String prefix to add to name based on hier + string m_prefix; // String prefix to add to class name based on hier V3UniqueNames m_names; // For unique naming of structs and unions AstNodeModule* m_modp = nullptr; // Current module AstNodeModule* m_classPackagep = nullptr; // Package moving into diff --git a/src/V3ParseImp.cpp b/src/V3ParseImp.cpp index d1686aaf9..d71d6a090 100644 --- a/src/V3ParseImp.cpp +++ b/src/V3ParseImp.cpp @@ -415,7 +415,7 @@ const V3ParseBisonYYSType* V3ParseImp::tokenPeekp(size_t depth) { return &m_tokensAhead.at(depth); } -size_t V3ParseImp::tokenPipeScanIdCell(size_t depthIn) { +size_t V3ParseImp::tokenPipeScanIdInst(size_t depthIn) { // Search around IEEE module_instantiation/interface_instantiation/program_instantiation // Return location of following token, or input if not found // yaID/*module_identifier*/ [ '#' '('...')' ] yaID/*name_of_instance*/ [ '['...']' ] '(' ... @@ -533,7 +533,7 @@ int V3ParseImp::tokenPipelineId(int token) { VL_RESTORER(yylval); // Remember value, as about to read ahead if (m_tokenLastBison.token != '@' && m_tokenLastBison.token != '#' && m_tokenLastBison.token != '.') { - if (const size_t depth = tokenPipeScanIdCell(0)) return yaID__aCELL; + if (const size_t depth = tokenPipeScanIdInst(0)) return yaID__aINST; } if (nexttok == '#') { // e.g. class_type parameter_value_assignment '::' const size_t depth = tokenPipeScanParam(0, false); @@ -757,7 +757,7 @@ std::ostream& operator<<(std::ostream& os, const V3ParseBisonYYSType& rhs) { if (rhs.token == yaID__ETC // || rhs.token == yaID__CC // || rhs.token == yaID__LEX // - || rhs.token == yaID__aCELL // + || rhs.token == yaID__aINST // || rhs.token == yaID__aTYPE) { os << " strp='" << *(rhs.strp) << "'"; } diff --git a/src/V3ParseImp.h b/src/V3ParseImp.h index 916bdb48c..e6ebcbc92 100644 --- a/src/V3ParseImp.h +++ b/src/V3ParseImp.h @@ -314,9 +314,9 @@ private: void tokenPipeline() VL_MT_DISABLED; // Internal; called from tokenToBison int tokenPipelineId(int token) VL_MT_DISABLED; void tokenPipelineSym() VL_MT_DISABLED; - size_t tokenPipeScanIdCell(size_t depth) VL_MT_DISABLED; + size_t tokenPipeScanIdInst(size_t depth) VL_MT_DISABLED; size_t tokenPipeScanBracket(size_t depth) VL_MT_DISABLED; - size_t tokenPipeScanParam(size_t depth, bool forCell) VL_MT_DISABLED; + size_t tokenPipeScanParam(size_t depth, bool forInst) VL_MT_DISABLED; size_t tokenPipeScanTypeEq(size_t depth) VL_MT_DISABLED; const V3ParseBisonYYSType* tokenPeekp(size_t depth) VL_MT_DISABLED; void preprocDumps(std::ostream& os, bool forInputs) VL_MT_DISABLED; diff --git a/src/verilog.y b/src/verilog.y index ebe90b364..126c2089c 100644 --- a/src/verilog.y +++ b/src/verilog.y @@ -430,7 +430,7 @@ BISONPRE_VERSION(3.7,%define api.header.include {"V3ParseBison.h"}) %token yaID__ETC "IDENTIFIER" %token yaID__CC "IDENTIFIER-::" %token yaID__LEX "IDENTIFIER-in-lex" -%token yaID__aCELL "IDENTIFIER-for-cell" +%token yaID__aINST "IDENTIFIER-for-instance" %token yaID__aTYPE "IDENTIFIER-for-type" // Can't predecode aFUNCTION, can declare after use // Can't predecode aINTERFACE, can declare after use @@ -1444,7 +1444,7 @@ parameter_value_assignmentClassE: // IEEE: [ parameter_value_assignme ; parameter_value_assignmentInst: // IEEE: parameter_value_assignment for instance - '#' '(' cellparamListE ')' { $$ = $3; } + '#' '(' instParamListE ')' { $$ = $3; } // // Parentheses are optional around a single parameter // // IMPORTANT: Below hardcoded in tokenPipeScanParam | '#' yaINTNUM { $$ = new AstPin{$2, 1, "", new AstConst{$2, *$2}}; } @@ -1459,7 +1459,7 @@ parameter_value_assignmentInst: // IEEE: parameter_value_assignment parameter_value_assignmentClass: // IEEE: parameter_value_assignment (for classes) // // Like parameter_value_assignment, but for classes only, which always have #() - '#' '(' cellparamListE ')' { $$ = $3; } + '#' '(' instParamListE ')' { $$ = $3; } ; parameter_port_listE: // IEEE: parameter_port_list + empty == parameter_value_assignment @@ -3017,7 +3017,7 @@ loop_generate_construct: // ==IEEE: loop_generate_construct initp->unlinkFrBackWithNext(); // Detach 2nd from varp, make 1st init blkp->addStmtsp(varp); } - // Statements are under 'genforp' as cells under this + // Statements are under 'genforp' as instances under this // for loop won't get an extra layer of hierarchy tacked on blkp->genforp(new AstGenFor{$1, initp, $5, $7, lowerNoBegp}); $$ = blkp; @@ -3324,8 +3324,8 @@ etcInst: // IEEE: module_instantiation + gate_instantiati instDecl: // // Disambigurated from data_declaration based on - // // idCell which is found as IEEE requires a later '(' - idCell parameter_value_assignmentInstE + // // idInst which is found as IEEE requires a later '(' + idInst parameter_value_assignmentInstE /*mid*/ { INSTPREP($1, *$1, $2); } /*cont*/ instnameList ';' { $$ = $4; @@ -3358,12 +3358,12 @@ instnameList: ; instnameParen: - id instRangeListE '(' cellpinListE ')' + id instRangeListE '(' instPinListE ')' { $$ = GRAMMARP->createCell($1, *$1, $4, $2); } ; instnameParenUdpn: // IEEE: part of udp_instance when no name_of_instance - '(' cellpinListE ')' // When UDP has empty name, unpacked dimensions must not be used + '(' instPinListE ')' // When UDP has empty name, unpacked dimensions must not be used { $$ = GRAMMARP->createCell($1, "", $2, nullptr); } ; @@ -3384,31 +3384,31 @@ instRange: { $$ = new AstRange{$1, $2, $4}; } ; -cellparamListE: - { GRAMMARP->pinPush(); } cellparamItListE { $$ = $2; GRAMMARP->pinPop(CRELINE()); } +instParamListE: + { GRAMMARP->pinPush(); } instParamItListE { $$ = $2; GRAMMARP->pinPop(CRELINE()); } ; -cellpinListE: - { VARRESET_LIST(UNKNOWN); } cellpinItListE { $$ = $2; VARRESET_NONLIST(UNKNOWN); } +instPinListE: + { VARRESET_LIST(UNKNOWN); } instPinItListE { $$ = $2; VARRESET_NONLIST(UNKNOWN); } ; -cellparamItListE: // IEEE: list_of_parameter_value_assignments/list_of_parameter_assignments +instParamItListE: // IEEE: list_of_parameter_value_assignments/list_of_parameter_assignments // // Empty gets a node, to track class reference of #() /*empty*/ { $$ = new AstPin{CRELINE(), PINNUMINC(), "", nullptr}; } - | cellparamItList { $$ = $1; } + | instParamItList { $$ = $1; } ; -cellparamItList: // IEEE: list_of_parameter_value_assignments/list_of_parameter_assignments - cellparamItem { $$ = $1; } - | cellparamItList ',' cellparamItem { $$ = addNextNull($1, $3); } +instParamItList: // IEEE: list_of_parameter_value_assignments/list_of_parameter_assignments + instParamItem { $$ = $1; } + | instParamItList ',' instParamItem { $$ = addNextNull($1, $3); } ; -cellpinItListE: // IEEE: list_of_port_connections - cellpinItemE { $$ = $1; } - | cellpinItListE ',' cellpinItemE { $$ = addNextNull($1, $3); } +instPinItListE: // IEEE: list_of_port_connections + instPinItemE { $$ = $1; } + | instPinItListE ',' instPinItemE { $$ = addNextNull($1, $3); } ; -cellparamItem: // IEEE: named_parameter_assignment + empty +instParamItem: // IEEE: named_parameter_assignment + empty // // Note empty is not allowed in parameter lists yP_DOTSTAR { $$ = new AstPin{$1, PINNUMINC(), ".*", nullptr}; } | '.' idAny '(' ')' @@ -3446,7 +3446,7 @@ cellparamItem: // IEEE: named_parameter_assignment + empty //UNSUP $$ = new AstPin{FILELINE_OR_CRE($3), PINNUMINC(), "", $3}; } ; -cellpinItemE: // IEEE: named_port_connection + empty +instPinItemE: // IEEE: named_port_connection + empty // // Note empty can match either () or (,); V3LinkCells cleans up () /* empty: ',,' is legal */ { $$ = new AstPin{CRELINE(), PINNUMINC(), "", nullptr}; } | yP_DOTSTAR { $$ = new AstPin{$1, PINNUMINC(), ".*", nullptr}; } @@ -4719,12 +4719,12 @@ funcId: // IEEE: function_data_type_or_implicit + part o { $$ = $2; $$->fvarp($1); SYMP->pushNewUnderNodeOrCurrent($$, $2); } - | packageClassScopeE idCellType packed_dimensionListE fIdScoped + | packageClassScopeE idInstType packed_dimensionListE fIdScoped { AstRefDType* const refp = new AstRefDType{$2, *$2, $1, nullptr}; $$ = $4; $$->fvarp(GRAMMARP->createArray(refp, $3, true)); SYMP->pushNewUnderNodeOrCurrent($$, $4); } - | packageClassScopeE idCellType parameter_value_assignmentClass packed_dimensionListE fIdScoped + | packageClassScopeE idInstType parameter_value_assignmentClass packed_dimensionListE fIdScoped { AstRefDType* const refp = new AstRefDType{$2, *$2, $1, $3}; $$ = $5; $$->fvarp(GRAMMARP->createArray(refp, $4, true)); @@ -5901,18 +5901,24 @@ id: | idRandomize { $$ = $1; $$ = $1; } ; -idAny: // Any kind of identifier +idAny: // Any kind of identifier yaID__ETC { $$ = $1; $$ = $1; } - | yaID__aCELL { $$ = $1; $$ = $1; } + | yaID__aINST { $$ = $1; $$ = $1; } | yaID__aTYPE { $$ = $1; $$ = $1; } | idRandomize { $$ = $1; $$ = $1; } ; -idCell: // IEEE: instance_identifier or similar with another id then '(' - // // See V3ParseImp::tokenPipeScanIdCell +idAnyAsParseRef: // Any kind of identifier as a ParseRef + idAny + { $$ = new AstParseRef{$1, VParseRefExp::PX_TEXT, *$1}; } + ; + + +idInst: // IEEE: instance_identifier or similar with another id then '(' + // // See V3ParseImp::tokenPipeScanIdInst // // [^': '@' '.'] yaID/*module_id*/ [ '#' '('...')' ] yaID/*name_of_instance*/ [ '['...']' ] '(' ... // // [^':' @' '.'] yaID/*module_id*/ [ '#' id|etc ] yaID/*name_of_instance*/ [ '['...']' ] '(' ... - yaID__aCELL { $$ = $1; $$ = $1; } + yaID__aINST { $$ = $1; $$ = $1; } ; idType: // IEEE: class_identifier or other type identifier @@ -5920,8 +5926,8 @@ idType: // IEEE: class_identifier or other type identifi yaID__aTYPE { $$ = $1; $$ = $1; } ; -idCellType: // type_identifier for functions which have a following id then '(' - yaID__aCELL { $$ = $1; $$ = $1; } +idInstType: // type_identifier for functions which have a following id then '(' + yaID__aINST { $$ = $1; $$ = $1; } | yaID__aTYPE { $$ = $1; $$ = $1; } ; @@ -6171,8 +6177,8 @@ list_of_clocking_decl_assign: // IEEE: list_of_clocking_decl_assign ; clocking_decl_assign: // IEEE: clocking_decl_assign - idAny/*new-signal_identifier*/ exprEqE - { AstParseRef* const refp = new AstParseRef{$1, VParseRefExp::PX_TEXT, *$1, nullptr, nullptr}; + idAnyAsParseRef/*new-signal_identifier*/ exprEqE + { AstParseRef* const refp = $1; $$ = refp; if ($2) $$ = new AstAssign{$2, refp, $2}; } ; @@ -6196,8 +6202,8 @@ clocking_skew: // IEEE: clocking_skew cycle_delay: // IEEE: cycle_delay yP_POUNDPOUND yaINTNUM { $$ = new AstDelay{$1, new AstConst{$2, *$2}, true}; } - | yP_POUNDPOUND idAny - { $$ = new AstDelay{$1, new AstParseRef{$2, VParseRefExp::PX_TEXT, *$2, nullptr, nullptr}, true}; } + | yP_POUNDPOUND idAnyAsParseRef + { $$ = new AstDelay{$1, $2, true}; } | yP_POUNDPOUND '(' expr ')' { $$ = new AstDelay{$1, $3, true}; } ; @@ -7295,8 +7301,8 @@ checker_generate_item: // ==IEEE: checker_generate_item //UNSUPchecker_instantiation: //UNSUP // // Only used for procedural_assertion_item's //UNSUP // // Version in concurrent_assertion_item looks like etcInst -//UNSUP // // Thus instead of *_checker_port_connection we can use etcInst's cellpinListE -//UNSUP id/*checker_identifier*/ id '(' cellpinListE ')' ';' { } +//UNSUP // // Thus instead of *_checker_port_connection we can use etcInst's instPinListE +//UNSUP id/*checker_identifier*/ id '(' instPinListE ')' ';' { } //UNSUP ; //********************************************************************** diff --git a/test_regress/t/t_config_libmap.map b/test_regress/t/t_config_libmap.map index fe1f6e3f2..e2d7e6e46 100644 --- a/test_regress/t/t_config_libmap.map +++ b/test_regress/t/t_config_libmap.map @@ -1,3 +1,4 @@ +// -*- Verilog -*- // DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for @@ -12,6 +13,10 @@ library rtllib2 *.v, *.sv; library rtllib3 *.v -incdir *.vh; library rtllib4 *.v -incdir *.vh, *.svh; +// Note this does not start a comment +library gatelib ./*.vg; +// */ + config cfg; design t; endconfig diff --git a/test_regress/t/t_config_libmap.out b/test_regress/t/t_config_libmap.out index d86495d89..0415f7ac2 100644 --- a/test_regress/t/t_config_libmap.out +++ b/test_regress/t/t_config_libmap.out @@ -1,29 +1,32 @@ -%Error-UNSUPPORTED: t/t_config_libmap.map:8:1: Unsupported: Verilog 2001-config lib.map reserved word not implemented: 'include' +%Error-UNSUPPORTED: t/t_config_libmap.map:9:1: Unsupported: Verilog 2001-config lib.map reserved word not implemented: 'include' : ... Suggest unless in a lib.map file, want `include instead - 8 | include ./t_config_libmap_inc.map + 9 | include ./t_config_libmap_inc.map | ^~~~~~~ ... For error description see https://verilator.org/warn/UNSUPPORTED?v=latest -%Error: t/t_config_libmap.map:8:9: syntax error, unexpected '.' - 8 | include ./t_config_libmap_inc.map +%Error: t/t_config_libmap.map:9:9: syntax error, unexpected '.' + 9 | include ./t_config_libmap_inc.map | ^ ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. -%Error-UNSUPPORTED: t/t_config_libmap.map:10:1: Unsupported: Verilog 2001-config lib.map reserved word not implemented: 'library' - 10 | library rtllib *.v; - | ^~~~~~~~~~~~~~ %Error-UNSUPPORTED: t/t_config_libmap.map:11:1: Unsupported: Verilog 2001-config lib.map reserved word not implemented: 'library' - 11 | library rtllib2 *.v, *.sv; + 11 | library rtllib *.v; | ^~~~~~~~~~~~~~ %Error-UNSUPPORTED: t/t_config_libmap.map:12:1: Unsupported: Verilog 2001-config lib.map reserved word not implemented: 'library' - 12 | library rtllib3 *.v -incdir *.vh; + 12 | library rtllib2 *.v, *.sv; | ^~~~~~~~~~~~~~ -%Error-UNSUPPORTED: t/t_config_libmap.map:12:29: Unsupported: Verilog 2001-config lib.map reserved word not implemented: 'incdir' %Error-UNSUPPORTED: t/t_config_libmap.map:13:1: Unsupported: Verilog 2001-config lib.map reserved word not implemented: 'library' - 13 | library rtllib4 *.v -incdir *.vh, *.svh; + 13 | library rtllib3 *.v -incdir *.vh; | ^~~~~~~~~~~~~~ %Error-UNSUPPORTED: t/t_config_libmap.map:13:29: Unsupported: Verilog 2001-config lib.map reserved word not implemented: 'incdir' - 13 | library rtllib4 *.v -incdir *.vh, *.svh; +%Error-UNSUPPORTED: t/t_config_libmap.map:14:1: Unsupported: Verilog 2001-config lib.map reserved word not implemented: 'library' + 14 | library rtllib4 *.v -incdir *.vh, *.svh; + | ^~~~~~~~~~~~~~ +%Error-UNSUPPORTED: t/t_config_libmap.map:14:29: Unsupported: Verilog 2001-config lib.map reserved word not implemented: 'incdir' + 14 | library rtllib4 *.v -incdir *.vh, *.svh; | ^~~~~~~~~~~~ -%Error-UNSUPPORTED: t/t_config_libmap.map:15:1: Unsupported: Verilog 2001-config reserved word not implemented: 'config' -%Error-UNSUPPORTED: t/t_config_libmap.map:16:4: Unsupported: Verilog 2001-config reserved word not implemented: 'design' -%Error-UNSUPPORTED: t/t_config_libmap.map:17:1: Unsupported: Verilog 2001-config reserved word not implemented: 'endconfig' +%Error-UNSUPPORTED: t/t_config_libmap.map:17:1: Unsupported: Verilog 2001-config lib.map reserved word not implemented: 'library' + 17 | library gatelib . + | ^~~~~~~~~~~~~~ +%Error-UNSUPPORTED: t/t_config_libmap.map:20:1: Unsupported: Verilog 2001-config reserved word not implemented: 'config' +%Error-UNSUPPORTED: t/t_config_libmap.map:21:4: Unsupported: Verilog 2001-config reserved word not implemented: 'design' +%Error-UNSUPPORTED: t/t_config_libmap.map:22:1: Unsupported: Verilog 2001-config reserved word not implemented: 'endconfig' %Error: Exiting due to diff --git a/test_regress/t/t_config_libmap_inc.map b/test_regress/t/t_config_libmap_inc.map index fe1f6e3f2..44a8994ce 100644 --- a/test_regress/t/t_config_libmap_inc.map +++ b/test_regress/t/t_config_libmap_inc.map @@ -1,3 +1,4 @@ +// -*- Verilog -*- // DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for diff --git a/test_regress/t/t_param_type_bad.out b/test_regress/t/t_param_type_bad.out index f7f374e6f..a9bf7634b 100644 --- a/test_regress/t/t_param_type_bad.out +++ b/test_regress/t/t_param_type_bad.out @@ -1,4 +1,4 @@ -%Error: t/t_param_type_bad.v:9:27: syntax error, unexpected INTEGER NUMBER, expecting IDENTIFIER or IDENTIFIER-for-cell or IDENTIFIER-for-type or randomize +%Error: t/t_param_type_bad.v:9:27: syntax error, unexpected INTEGER NUMBER, expecting IDENTIFIER or IDENTIFIER-for-instance or IDENTIFIER-for-type or randomize 9 | localparam type bad2 = 2; | ^ ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance.