From 51422e3ee80c873afd5659e3c4f1e9fa3a2923de Mon Sep 17 00:00:00 2001
From: Wilson Snyder <wsnyder@wsnyder.org>
Date: Wed, 9 May 2018 18:32:12 -0400
Subject: [PATCH] Fix parsing error on bad missing #, bug1308.

---
 Changes                                |  2 ++
 src/verilog.y                          |  9 +++++----
 test_regress/t/t_lint_mod_paren_bad.pl | 24 ++++++++++++++++++++++++
 test_regress/t/t_lint_mod_paren_bad.v  | 18 ++++++++++++++++++
 4 files changed, 49 insertions(+), 4 deletions(-)
 create mode 100755 test_regress/t/t_lint_mod_paren_bad.pl
 create mode 100644 test_regress/t/t_lint_mod_paren_bad.v

diff --git a/Changes b/Changes
index de8932d59..d4f9ad955 100644
--- a/Changes
+++ b/Changes
@@ -8,6 +8,8 @@ The contributors that suggested a given feature are shown in []. Thanks!
 
 ****  Fix parsing "output signed" in V2K port list, msg2540. [James Jung]
 
+****  Fix parsing error on bad missing #, bug1308. [Dan Kirkham]
+
 
 * Verilator 3.922 2018-03-17
 
diff --git a/src/verilog.y b/src/verilog.y
index ab1bc264d..ef5a1174e 100644
--- a/src/verilog.y
+++ b/src/verilog.y
@@ -956,13 +956,13 @@ port<nodep>:			// ==IEEE: port
 			{ $$=$2; /*VARDTYPE-same*/ $$->addNextNull(VARDONEP($$,$3,$4)); }
 	//
 	|	portDirNetE data_type           portSig variable_dimensionListE sigAttrListE '=' constExpr
-			{ $$=$3; VARDTYPE($2); AstVar* vp=VARDONEP($$,$4,$5); $$->addNextNull(vp); vp->valuep($7); }
+			{ $$=$3; VARDTYPE($2); if (AstVar* vp=VARDONEP($$,$4,$5)) { $$->addNextNull(vp); vp->valuep($7); } }
 	|	portDirNetE yVAR data_type      portSig variable_dimensionListE sigAttrListE '=' constExpr
-			{ $$=$4; VARDTYPE($3); AstVar* vp=VARDONEP($$,$5,$6); $$->addNextNull(vp); vp->valuep($8); }
+			{ $$=$4; VARDTYPE($3); if (AstVar* vp=VARDONEP($$,$5,$6)) { $$->addNextNull(vp); vp->valuep($8); } }
 	|	portDirNetE yVAR implicit_typeE portSig variable_dimensionListE sigAttrListE '=' constExpr
-			{ $$=$4; VARDTYPE($3); AstVar* vp=VARDONEP($$,$5,$6); $$->addNextNull(vp); vp->valuep($8); }
+			{ $$=$4; VARDTYPE($3); if (AstVar* vp=VARDONEP($$,$5,$6)) { $$->addNextNull(vp); vp->valuep($8); } }
 	|	portDirNetE /*implicit*/        portSig variable_dimensionListE sigAttrListE '=' constExpr
-			{ $$=$2; /*VARDTYPE-same*/ AstVar* vp=VARDONEP($$,$3,$4); $$->addNextNull(vp); vp->valuep($6); }
+			{ $$=$2; /*VARDTYPE-same*/ if (AstVar* vp=VARDONEP($$,$3,$4)) { $$->addNextNull(vp); vp->valuep($6); } }
  	;
 
 portDirNetE:			// IEEE: part of port, optional net type and/or direction
@@ -3845,6 +3845,7 @@ vltOnFront<errcodeen>:
 %%
 
 int V3ParseImp::bisonParse() {
+    // Use --debugi-bison 9 to enable this
     if (PARSEP->debugBison()>=9) yydebug = 1;
     return yyparse();
 }
diff --git a/test_regress/t/t_lint_mod_paren_bad.pl b/test_regress/t/t_lint_mod_paren_bad.pl
new file mode 100755
index 000000000..5fc313e61
--- /dev/null
+++ b/test_regress/t/t_lint_mod_paren_bad.pl
@@ -0,0 +1,24 @@
+#!/usr/bin/perl
+if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2008 by Wilson Snyder. This program is free software; you can
+# redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+
+scenarios(vlt => 1);
+
+compile(
+    verilator_flags2 => ["--lint-only -Wno-DECLFILENAME"],
+    fails => 1,
+    verilator_make_gcc => 0,
+    make_top_shell => 0,
+    make_main => 0,
+    expect =>
+q{%Error: t/t_lint_mod_paren_bad.v:\d+: syntax error, unexpected '\(', expecting ';'
+%Error: Exiting due to .*},
+    );
+
+ok(1);
+1;
diff --git a/test_regress/t/t_lint_mod_paren_bad.v b/test_regress/t/t_lint_mod_paren_bad.v
new file mode 100644
index 000000000..353dd2a64
--- /dev/null
+++ b/test_regress/t/t_lint_mod_paren_bad.v
@@ -0,0 +1,18 @@
+// DESCRIPTION: Verilator: Verilog Test module
+//
+// This file ONLY is placed into the Public Domain, for any use,
+// without warranty, 2018 by Wilson Snyder.
+
+// Should have been:
+//module t #(
+
+module t
+  (
+   FOO=1
+   ) (
+      output bar
+      );
+
+   assign bar = FOO;
+
+endmodule