diff --git a/Changes b/Changes
index a26f3be44..89ca8a8a3 100644
--- a/Changes
+++ b/Changes
@@ -9,6 +9,8 @@ indicates the contributor was also the author of the fix; Thanks!
 
 **** Fix "cloning" error with -y/--top-module, bug76. [Dimitris Nalbantis]
 
+**** Fix segfault with error on bad --top-module, bug79. [Dimitris Nalbantis]
+
 **** Fix GCC 4.3.2 compile warnings.
 
 * Verilator 3.702 2009/03/28
diff --git a/src/V3LinkCells.cpp b/src/V3LinkCells.cpp
index 166b9468d..4f44c9fec 100644
--- a/src/V3LinkCells.cpp
+++ b/src/V3LinkCells.cpp
@@ -124,7 +124,11 @@ private:
 	for (V3GraphVertex* itp = m_graph.verticesBeginp(); itp; itp=itp->verticesNextp()) {
 	    if (LinkCellsVertex* vvertexp = dynamic_cast<LinkCellsVertex*>(itp)) {
 		// +1 so we leave level 1  for the new wrapper we'll make in a moment
-		vvertexp->modp()->level(vvertexp->rank()+1);
+		AstModule* modp = vvertexp->modp();
+		modp->level(vvertexp->rank()+1);
+		if (vvertexp == m_topVertexp && modp->level() != 2) {
+		    v3error("Specified --top-module '"<<v3Global.opt.topModule()<<"' isn't at the top level, it's under another cell.");
+		}
 	    }
 	}
 	if (v3Global.opt.topModule()!=""
@@ -137,7 +141,11 @@ private:
 	m_modp = nodep;
 	UINFO(2,"Link Module: "<<nodep<<endl);
 	bool topMatch = (v3Global.opt.topModule()==nodep->name());
-	if (topMatch) m_topVertexp = vertex(nodep);
+	if (topMatch) {
+	    m_topVertexp = vertex(nodep);
+	    UINFO(2,"Link --top-module: "<<nodep<<endl);
+	    nodep->inLibrary(false);   // Safer to make sure it doesn't disappear
+	}
 	if (v3Global.opt.topModule()==""
 	    ? nodep->inLibrary()   // Library cells are lower
 	    : !topMatch) {  // Any non-specified module is lower
diff --git a/src/V3LinkLevel.cpp b/src/V3LinkLevel.cpp
index 86a25f592..5b6938cf0 100644
--- a/src/V3LinkLevel.cpp
+++ b/src/V3LinkLevel.cpp
@@ -84,6 +84,7 @@ void V3LinkLevel::wrapTop(AstNetlist* netlistp) {
     UINFO(2,__FUNCTION__<<": "<<endl);
     // We do ONLY the top module
     AstModule* oldmodp = netlistp->modulesp();
+    if (!oldmodp) netlistp->v3fatalSrc("No module found to process");
     AstModule* newmodp = new AstModule(oldmodp->fileline(), (string)"TOP_"+oldmodp->name());
     // Make the new module first in the list
     oldmodp->unlinkFrBackWithNext();
diff --git a/test_regress/driver.pl b/test_regress/driver.pl
index 3905bb222..86c98c1f0 100755
--- a/test_regress/driver.pl
+++ b/test_regress/driver.pl
@@ -167,7 +167,7 @@ sub parameter {
 	$_Parameter_Next_Level = $param;
     }
     else {
-	warn "%Error: Unknown parameter: $param\n";
+	die "%Error: Unknown parameter: $param\n";
     }
 }
 
diff --git a/test_regress/t/t_flag_topmod2_bad.pl b/test_regress/t/t_flag_topmod2_bad.pl
new file mode 100755
index 000000000..eeb7e124c
--- /dev/null
+++ b/test_regress/t/t_flag_topmod2_bad.pl
@@ -0,0 +1,19 @@
+#!/usr/bin/perl
+if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2008 by Wilson Snyder. This program is free software; you can
+# redistribute it and/or modify it under the terms of either the GNU
+# General Public License or the Perl Artistic License.
+
+compile (
+	 v_flags2 => ["--top-module a "],
+	 fails=>$Self->{v3},
+	 nc=>0,  # Need to get it not to give the prompt
+	 expect=>
+'%Error: Specified --top-module \'a\' isn.t at the top level, it.s under another cell.
+%Error: Exiting due to.*',
+	 ) if $Self->{v3};
+
+ok(1);
+1;
diff --git a/test_regress/t/t_flag_topmod2_bad.v b/test_regress/t/t_flag_topmod2_bad.v
new file mode 100644
index 000000000..9933baf82
--- /dev/null
+++ b/test_regress/t/t_flag_topmod2_bad.v
@@ -0,0 +1,31 @@
+// DESCRIPTION: Verilator: Verilog Test module
+//
+// This file ONLY is placed into the Public Domain, for any use,
+// without warranty, 2008 by Wilson Snyder.
+
+module a_top;
+   a a ();
+   initial begin
+      $write("Bad top modules\n");
+      $stop;
+   end
+endmodule
+
+module a;
+   b b ();
+   c c ();
+   d d ();
+endmodule
+
+module b;
+endmodule
+
+module c;
+endmodule
+
+module d;
+   initial begin
+      $write("*-* All Finished *-*\n");
+      $finish;
+   end
+endmodule