diff --git a/Changes b/Changes
index a4066df85..1fbcb5859 100644
--- a/Changes
+++ b/Changes
@@ -20,6 +20,7 @@ Verilator 5.041 devel
 * Add error on localparam value from hierarchical path (#6456). [Luca Rufer]
 * Deprecate sensitivity list on public_flat_rw attributes (#6443). [Geza Lore]
 * Support modports referencing clocking blocks (#4555) (#6436). [Ryszard Rozak, Antmicro Ltd.]
+* Support digits in `$sscanf` field width formats (#6083). [Iztok Jeras]
 * Support pure functions in sensitivity lists (#6393). [Krzysztof Bieganski, Antmicro Ltd.]
 * Improve automatic selection of logic for DFG synthesis (#6370). [Geza Lore]
 * Improve `covergroup with function sample` handling  (#6387). [Jakub Wasilewski]
diff --git a/include/verilated.cpp b/include/verilated.cpp
index 6774557bb..18ab07f15 100644
--- a/include/verilated.cpp
+++ b/include/verilated.cpp
@@ -1322,6 +1322,19 @@ IData _vl_vsscanf(FILE* fp,  // If a fscanf
                 _vl_vsss_advance(fp, floc);
                 break;
             }
+            case '0':  // FALLTHRU
+            case '1':  // FALLTHRU
+            case '2':  // FALLTHRU
+            case '3':  // FALLTHRU
+            case '4':  // FALLTHRU
+            case '5':  // FALLTHRU
+            case '6':  // FALLTHRU
+            case '7':  // FALLTHRU
+            case '8':  // FALLTHRU
+            case '9': {
+                inPct = true;
+                break;
+            }
             case '*':
                 inPct = true;
                 inIgnore = true;
diff --git a/test_regress/t/t_sys_sscanf.py b/test_regress/t/t_sys_sscanf.py
new file mode 100755
index 000000000..f989a35fb
--- /dev/null
+++ b/test_regress/t/t_sys_sscanf.py
@@ -0,0 +1,18 @@
+#!/usr/bin/env python3
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2025 by Wilson Snyder. This program is free software; you
+# can redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
+
+import vltest_bootstrap
+
+test.scenarios('simulator')
+
+test.compile()
+
+test.execute()
+
+test.passes()
diff --git a/test_regress/t/t_sys_sscanf.v b/test_regress/t/t_sys_sscanf.v
new file mode 100644
index 000000000..53e809960
--- /dev/null
+++ b/test_regress/t/t_sys_sscanf.v
@@ -0,0 +1,30 @@
+// DESCRIPTION: Verilator: Verilog Test module
+//
+// This file ONLY is placed under the Creative Commons Public Domain, for
+// any use, without warranty, 2025 by Wilson Snyder.
+// SPDX-License-Identifier: CC0-1.0
+
+// verilog_format: off
+`define stop $stop
+`define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d:  got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0);
+// verilog_format: on
+
+module t;
+
+  localparam int unsigned XLEN = 32;
+
+  string pkt;
+  int unsigned idx;
+  logic [XLEN-1:0] val;
+  int code;
+
+  initial begin
+    // All digits after % is to get line coverage in verilated.cpp
+    code = $sscanf("P20=4cff0000", "P%h=%80123456789h", idx, val);
+    `checkh(code, 2);
+    `checkh(idx, 32'h20);
+    `checkh(val, 32'h4cff0000);
+    $finish;
+  end
+
+endmodule