diff --git a/include/verilated_trace.h b/include/verilated_trace.h
index d0c2ff4e3..7e8694b70 100644
--- a/include/verilated_trace.h
+++ b/include/verilated_trace.h
@@ -447,7 +447,9 @@ public:
         if (VL_UNLIKELY(diff)) fullIData(oldp, newval, bits);
     }
     VL_ATTR_ALWINLINE void chgQData(uint32_t* oldp, QData newval, int bits) {
-        const uint64_t diff = *reinterpret_cast<QData*>(oldp) ^ newval;
+        QData old;
+        std::memcpy(&old, oldp, sizeof(old));
+        const uint64_t diff = old ^ newval;
         if (VL_UNLIKELY(diff)) fullQData(oldp, newval, bits);
     }
     VL_ATTR_ALWINLINE void chgWData(uint32_t* oldp, const WData* newvalp, int bits) {
@@ -460,8 +462,9 @@ public:
     }
     VL_ATTR_ALWINLINE void chgEvent(uint32_t* oldp, VlEvent newval) { fullEvent(oldp, newval); }
     VL_ATTR_ALWINLINE void chgDouble(uint32_t* oldp, double newval) {
-        // cppcheck-suppress invalidPointerCast
-        if (VL_UNLIKELY(*reinterpret_cast<double*>(oldp) != newval)) fullDouble(oldp, newval);
+        double old;
+        std::memcpy(&old, oldp, sizeof(old));
+        if (VL_UNLIKELY(old != newval)) fullDouble(oldp, newval);
     }
 };
 
diff --git a/include/verilated_trace_imp.h b/include/verilated_trace_imp.h
index f7d03fc99..9f5792127 100644
--- a/include/verilated_trace_imp.h
+++ b/include/verilated_trace_imp.h
@@ -872,7 +872,7 @@ void VerilatedTraceBuffer<VL_BUF_T>::fullIData(uint32_t* oldp, IData newval, int
 template <>
 void VerilatedTraceBuffer<VL_BUF_T>::fullQData(uint32_t* oldp, QData newval, int bits) {
     const uint32_t code = oldp - m_sigs_oldvalp;
-    *reinterpret_cast<QData*>(oldp) = newval;
+    std::memcpy(oldp, &newval, sizeof(newval));
     if (VL_UNLIKELY(m_sigs_enabledp && !(VL_BITISSET_W(m_sigs_enabledp, code)))) return;
     emitQData(code, newval, bits);
 }
@@ -888,7 +888,7 @@ void VerilatedTraceBuffer<VL_BUF_T>::fullWData(uint32_t* oldp, const WData* newv
 template <>
 void VerilatedTraceBuffer<VL_BUF_T>::fullDouble(uint32_t* oldp, double newval) {
     const uint32_t code = oldp - m_sigs_oldvalp;
-    *reinterpret_cast<double*>(oldp) = newval;
+    std::memcpy(oldp, &newval, sizeof(newval));
     if (VL_UNLIKELY(m_sigs_enabledp && !(VL_BITISSET_W(m_sigs_enabledp, code)))) return;
     // cppcheck-suppress invalidPointerCast
     emitDouble(code, newval);
diff --git a/test_regress/t/t_trace_ub_misaligned_address.out b/test_regress/t/t_trace_ub_misaligned_address.out
new file mode 100644
index 000000000..1fe9f3feb
--- /dev/null
+++ b/test_regress/t/t_trace_ub_misaligned_address.out
@@ -0,0 +1 @@
+*-* All Finished *-*
diff --git a/test_regress/t/t_trace_ub_misaligned_address.pl b/test_regress/t/t_trace_ub_misaligned_address.pl
new file mode 100755
index 000000000..6a37a1511
--- /dev/null
+++ b/test_regress/t/t_trace_ub_misaligned_address.pl
@@ -0,0 +1,38 @@
+#!/usr/bin/env perl
+if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2023 by Wilson Snyder. This program is free software; you
+# can redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
+
+scenarios(simulator => 1);
+
+if (!$Self->have_coroutines) {
+    skip("No coroutine support");
+}
+else {
+    top_filename("t/t_trace_ub_misaligned_address.v");
+
+    compile(
+        verilator_flags2 => ["--binary --timing --trace",
+                             "-CFLAGS -fsanitize=address,undefined",
+                             "-LDFLAGS -fsanitize=address,undefined"],
+        verilator_make_cmake => 0,
+        verilator_make_gmake => 0,
+        make_main => 0,
+        );
+
+    execute(
+        check_finished => 1,
+        );
+
+# Make sure that there are no additional messages (such as runtime messages
+# regarding undefined behavior).
+    files_identical("$Self->{obj_dir}/vlt_sim.log", $Self->{golden_filename}, "logfile");
+}
+
+ok(1);
+1;
diff --git a/test_regress/t/t_trace_ub_misaligned_address.v b/test_regress/t/t_trace_ub_misaligned_address.v
new file mode 100644
index 000000000..379412d3a
--- /dev/null
+++ b/test_regress/t/t_trace_ub_misaligned_address.v
@@ -0,0 +1,92 @@
+// DESCRIPTION: Verilator: Verilog Test module
+//
+// When compiled using -fsanitize=address,undefined this triggered:
+//
+//   verilated_trace_imp.h:875:5: runtime error: store to misaligned address ...
+//   verilated_trace.h:450:31: runtime error: load of misaligned address ...
+//
+// due to 32 bit aligned addresses being used for types which require
+// stricter alignment.
+//
+// This file ONLY is placed under the Creative Commons Public Domain, for
+// any use, without warranty, 2023 by John Wehle.
+// SPDX-License-Identifier: CC0-1.0
+
+`define STRINGIFY(x) `"x`"
+
+module t;
+
+  wire [2:0] out;
+  reg        in;
+  reg [39:0] p;
+  reg        rst;
+  reg        clk;
+
+  initial begin
+    $dumpfile(`STRINGIFY(`TEST_DUMPFILE));
+    $dumpvars(0, test);
+
+    clk = 0;
+    rst = 0;
+
+    for (int i = 0; i < 2; i++)
+      begin
+        #10 rst = 1;
+        #10 rst = 0;
+
+        p = 40'b0000000000111111111111111111110000000000;
+
+        in = i[0];
+
+        for (int k = 0; k < 31; k++)
+          begin
+            in = p[39 - k] ^ i[0];
+            #1;
+          end
+
+        end
+
+    #30 $write("*-* All Finished *-*\n");
+    $finish;
+  end
+
+  always begin
+    #10 clk <= !clk;
+  end
+
+  Test test(.out(out), .in(in),
+	    .clk(clk), .rst(rst));
+endmodule
+
+
+module Test(/*AUTOARG*/
+  // Outputs
+  out,
+  // Inputs
+  clk, in, rst
+  );
+
+  input             clk;
+  input             in;
+  input             rst;
+  output wire [2:0] out;
+
+  reg [2:0] s;
+  reg       sin;
+
+  assign out = s;
+
+  always @(posedge clk, posedge rst)
+    begin
+      s[0] <= s[2];
+      s[2] <= in;
+      s[1] <= sin;
+    end
+
+  always @(negedge clk, posedge rst)
+    if (rst)
+      sin <= 1'b0;
+    else
+      sin <= in;
+
+endmodule