diff --git a/include/verilated_random.cpp b/include/verilated_random.cpp index 3419b1506..4aded2610 100644 --- a/include/verilated_random.cpp +++ b/include/verilated_random.cpp @@ -443,7 +443,7 @@ bool VlRandomizer::next(VlRNG& rngr) { std::iostream& os = getSolver(); if (!os) return false; - // Soft constraint relaxation (IEEE 1800-2017 18.5.13, last-wins priority): + // Soft constraint relaxation (IEEE 1800-2023 18.5.13, last-wins priority): // Try hard + soft[0..N-1], then hard + soft[1..N-1], ..., then hard only. // First SAT phase wins. If hard-only is UNSAT, report via unsat-core. os << "(set-option :produce-models true)\n"; @@ -726,7 +726,7 @@ void VlRandomizer::soft(std::string&& constraint, const char* /*filename*/, uint } void VlRandomizer::disable_soft(const std::string& varName) { - // IEEE 1800-2017 18.5.13: Remove all soft constraints referencing the variable + // IEEE 1800-2023 18.5.13: Remove all soft constraints referencing the variable m_softConstraints.erase( std::remove_if(m_softConstraints.begin(), m_softConstraints.end(), [&](const std::string& c) { return c.find(varName) != std::string::npos; }), diff --git a/include/verilated_types.h b/include/verilated_types.h index bae054c5f..8f070c6c7 100644 --- a/include/verilated_types.h +++ b/include/verilated_types.h @@ -2083,7 +2083,7 @@ public: VlClassRef dynamicCast() const { return VlClassRef{dynamic_cast(m_objp)}; } - // Polymorphic shallow clone (IEEE 1800-2017 8.7: new preserves runtime type) + // Polymorphic shallow clone (IEEE 1800-2023 8.7: new preserves runtime type) VlClassRef clone(VlDeleter& deleter) const { VlClass* clonedp = m_objp->clone(); if (VL_UNLIKELY(!clonedp)) return {}; diff --git a/include/verilated_vpi.cpp b/include/verilated_vpi.cpp index 8e2b5da05..412988cc0 100644 --- a/include/verilated_vpi.cpp +++ b/include/verilated_vpi.cpp @@ -3187,7 +3187,7 @@ void vl_vpi_get_value(const VerilatedVpioVarBase* vop, p_vpi_value valuep) { valuep->value.integer = get_word(vop, 32, 0); return; } else if (valuep->format == vpiRealVal) { - // Only cover the scalar case, since reals cannot be packed (IEEE 1800, section 7.4.1), and + // Only cover the scalar case, since reals cannot be packed (IEEE 1800-2023 7.4.1), and // unpacked arrays are not supported for forcing in Verilator (#4735). if (vop->varp()->isForceable() && *forceEnableSignalVop->varCDatap()) valuep->value.real = *forceValueSignalVop->varRealDatap(); diff --git a/src/V3AssertPre.cpp b/src/V3AssertPre.cpp index f65ca8b24..570811240 100644 --- a/src/V3AssertPre.cpp +++ b/src/V3AssertPre.cpp @@ -15,7 +15,7 @@ //************************************************************************* // Pre steps: // Attach clocks to each assertion -// Substitute property references by property body (IEEE 1800-2012 16.12.1). +// Substitute property references by property body (IEEE 1800-2023 16.12.1). // Transform clocking blocks into imperative logic //************************************************************************* diff --git a/src/V3EmitCFunc.h b/src/V3EmitCFunc.h index d24f33765..3f77aaef2 100644 --- a/src/V3EmitCFunc.h +++ b/src/V3EmitCFunc.h @@ -1532,7 +1532,7 @@ public: } void visit(AstNewCopy* nodep) override { // Polymorphic shallow clone: preserves runtime type via virtual clone() - // VL_NULL_CHECK enforces null check per IEEE 1800-2017 8.7 + // VL_NULL_CHECK enforces null check per IEEE 1800-2023 8.7 putns(nodep, "VL_NULL_CHECK("); if (VN_IS(nodep->rhsp(), Const) && VN_AS(nodep->rhsp(), Const)->isNull()) { // V3Const folded rhs to null: emit a typed empty ref so VL_NULL_CHECK fires diff --git a/src/V3LinkParse.cpp b/src/V3LinkParse.cpp index 4e238c75f..36c7136c2 100644 --- a/src/V3LinkParse.cpp +++ b/src/V3LinkParse.cpp @@ -340,7 +340,7 @@ class LinkParseVisitor final : public VNVisitor { cleanFileline(nodep); UINFO(9, "VAR " << nodep); if (nodep->valuep()) nodep->hasUserInit(true); - // IEEE 1800-2026 6.21: for loop variables are automatic. verilog.y is + // IEEE 1800-2023 6.21: for loop variables are automatic. verilog.y is // responsible for marking those. if (nodep->valuep() && nodep->lifetime().isNone() && m_lifetime.isStatic() && !nodep->isIO() diff --git a/src/V3Randomize.cpp b/src/V3Randomize.cpp index ba0266a88..4a782d821 100644 --- a/src/V3Randomize.cpp +++ b/src/V3Randomize.cpp @@ -2146,7 +2146,7 @@ class ConstraintExprVisitor final : public VNVisitor { } void visit(AstConstraintExpr* nodep) override { - // IEEE 1800-2017 18.5.13: "disable soft" removes all soft constraints + // IEEE 1800-2023 18.5.13: "disable soft" removes all soft constraints // referencing the specified variable. Pass the variable name directly // instead of going through SMT lowering. if (nodep->isDisableSoft()) { @@ -2171,7 +2171,7 @@ class ConstraintExprVisitor final : public VNVisitor { VL_DO_DANGLING(nodep->deleteTree(), nodep); return; } - // IEEE 1800-2017 18.5.1: A bare expression used as a constraint is + // IEEE 1800-2023 18.5.1: A bare expression used as a constraint is // implicitly treated as "expr != 0" when wider than 1 bit. // Must wrap before iterateChildren, which converts to SMT format. { @@ -2191,7 +2191,7 @@ class ConstraintExprVisitor final : public VNVisitor { VL_DO_DANGLING(nodep->deleteTree(), nodep); return; } - // Emit as soft or hard constraint per IEEE 1800-2017 18.5.13 + // Emit as soft or hard constraint per IEEE 1800-2023 18.5.13 const VCMethod method = nodep->isSoft() ? VCMethod::RANDOMIZER_SOFT : VCMethod::RANDOMIZER_HARD; AstCMethodHard* const callp = new AstCMethodHard{ diff --git a/src/verilog.y b/src/verilog.y index 6495b78e5..de6ebe74f 100644 --- a/src/verilog.y +++ b/src/verilog.y @@ -1478,7 +1478,7 @@ port: // ==IEEE: port // // IEEE: '.' port_identifier '(' [ expression ] ')' | portDirNetE /*implicit*/ '.' portSig '(' expr ')' { $$ = $3; DEL($5); - BBUNSUP($2, "Unsupported: complex ports (IEEE 1800-2017 23.2.2.1/2)"); } + BBUNSUP($2, "Unsupported: complex ports (IEEE 1800-2023 23.2.2.1/2)"); } // // IEEE: part of (non-ansi) port_reference | '{' port_expressionList '}' { $$ = $2; } @@ -2545,7 +2545,7 @@ type_declaration: // ==IEEE: type_declaration { AstNodeDType* const dtp = $2; $$ = GRAMMARP->createTypedef($3, *$3, $5, dtp, $4); } - // IEEE 1800-2017 6.18 typedef: dotted or arrayed type identifier + // IEEE 1800-2023 6.18 typedef: dotted or arrayed type identifier // Handles interface typedef references like if0.rq_t and if0[0].rq_t (arrays allowed after first component) | yTYPEDEF idDottedOrArrayed /*cont*/ idAny variable_dimensionListE dtypeAttrListE ';' @@ -2557,7 +2557,7 @@ type_declaration: // ==IEEE: type_declaration varp->valuep($2); $$ = varp; } - // IEEE 1800-2017 6.18 typedef with hierarchical type identifier + // IEEE 1800-2023 6.18 typedef with hierarchical type identifier // Special-case array on first component requiring a '.' after ']' to disambiguate from packed dims // Examples: typedef if0[0].rq_t my_t; typedef if0[0].x_if.rq_t my_t; | yTYPEDEF id '[' expr ']' '.' idDottedSelMore @@ -2586,7 +2586,7 @@ type_declaration: // ==IEEE: type_declaration { AstRefDType* const refp = new AstRefDType{$2, *$2, nullptr, nullptr}; $$ = GRAMMARP->createTypedef($3, *$3, $5, refp, $4); } - // IEEE 1800-2017 6.18.2 typedef with packed dimensions on an existing type identifier + // IEEE 1800-2023 6.18.2 typedef with packed dimensions on an existing type identifier // Disambiguated from interface array access by requiring ':' inside the brackets // (applies to both plain identifiers and type identifiers) | yTYPEDEF id '[' constExpr ':' constExpr ']' packed_dimensionListE diff --git a/test_regress/t/TestVpiMain.cpp b/test_regress/t/TestVpiMain.cpp index 8f25ce24e..f6578bd85 100644 --- a/test_regress/t/TestVpiMain.cpp +++ b/test_regress/t/TestVpiMain.cpp @@ -152,7 +152,7 @@ int main(int argc, char** argv) { // Call registered timed callbacks (e.g. clock timer) // These are called at the beginning of the time step - // before the iterative regions (IEEE 1800-2012 4.4.1) + // before the iterative regions (IEEE 1800-2023 4.4.1) VerilatedVpi::callTimedCbs(); settle_value_callbacks(); } diff --git a/test_regress/t/t_assert_disable_bad.v b/test_regress/t/t_assert_disable_bad.v index 775ec72b8..4f19ddb4d 100644 --- a/test_regress/t/t_assert_disable_bad.v +++ b/test_regress/t/t_assert_disable_bad.v @@ -21,6 +21,6 @@ module t ( endproperty // Test should fail due to duplicated disable iff statements - // (IEEE 1800-2012 16.12.1). + // (IEEE 1800-2023 16.12.1). assert property (disable iff (val == 0) check(1, 1)); endmodule diff --git a/test_regress/t/t_class_nested.v b/test_regress/t/t_class_nested.v index 7c87dc94c..8de5cdff7 100644 --- a/test_regress/t/t_class_nested.v +++ b/test_regress/t/t_class_nested.v @@ -26,7 +26,7 @@ class NodeTree; Node root; endclass -// Based on IEEE 1800-2017 section 8.23 Nested classes +// Based on IEEE 1800-2023 8.23 Nested classes class Outer; int outerProp; local int outerLocalProp; diff --git a/test_regress/t/t_class_new_copy_polymorphism.v b/test_regress/t/t_class_new_copy_polymorphism.v index ba0a530e1..37a2c90d1 100644 --- a/test_regress/t/t_class_new_copy_polymorphism.v +++ b/test_regress/t/t_class_new_copy_polymorphism.v @@ -5,7 +5,7 @@ // SPDX-License-Identifier: CC0-1.0 // Test that `new ` (shallow copy) preserves the runtime type -// of the source object, per IEEE 1800-2017 8.7. +// of the source object, per IEEE 1800-2023 8.7. // verilog_format: off `define stop $stop diff --git a/test_regress/t/t_constraint_mode_static.v b/test_regress/t/t_constraint_mode_static.v index 1acb7506f..488bc3826 100644 --- a/test_regress/t/t_constraint_mode_static.v +++ b/test_regress/t/t_constraint_mode_static.v @@ -4,7 +4,7 @@ // SPDX-FileCopyrightText: 2026 PlanV GmbH. // SPDX-License-Identifier: CC0-1.0 -// Test static constraint_mode() support per IEEE 1800-2017 Section 18.4, 18.8 +// Test static constraint_mode() support per IEEE 1800-2023 18.4, 18.8 // Static constraint mode should be shared across all instances. class StaticConstraintTest; diff --git a/test_regress/t/t_constraint_solve_before.v b/test_regress/t/t_constraint_solve_before.v index a415f7432..f91d9c061 100644 --- a/test_regress/t/t_constraint_solve_before.v +++ b/test_regress/t/t_constraint_solve_before.v @@ -10,7 +10,7 @@ `define check_range(gotv,minv,maxv) do if ((gotv) < (minv) || (gotv) > (maxv)) begin $write("%%Error: %s:%0d: got=%0d exp=%0d-%0d\n", `__FILE__,`__LINE__, (gotv), (minv), (maxv)); `stop; end while(0); // verilog_format: on -// Test solve...before constraint (IEEE 1800-2017 18.5.11) +// Test solve...before constraint (IEEE 1800-2023 18.5.11) // Verifies phased solving: 'before' variables are determined first, // then 'after' variables are solved with all constraints applied. diff --git a/test_regress/t/t_constraint_sysfunc.v b/test_regress/t/t_constraint_sysfunc.v index 4b458c18a..efb29d45e 100644 --- a/test_regress/t/t_constraint_sysfunc.v +++ b/test_regress/t/t_constraint_sysfunc.v @@ -5,7 +5,7 @@ // SPDX-License-Identifier: CC0-1.0 // Test: System functions ($onehot, $onehot0, $countbits, $clog2) inside -// constraint blocks (IEEE 1800-2017 Section 18.5.12) +// constraint blocks (IEEE 1800-2023 18.5.12) class test_onehot; rand bit [7:0] value; diff --git a/test_regress/t/t_inst_port_complex_unsup.out b/test_regress/t/t_inst_port_complex_unsup.out index e2f245c5f..67d380d20 100644 --- a/test_regress/t/t_inst_port_complex_unsup.out +++ b/test_regress/t/t_inst_port_complex_unsup.out @@ -1,47 +1,47 @@ -%Error-UNSUPPORTED: t/t_inst_port_complex_unsup.v:9:9: Unsupported: complex ports (IEEE 1800-2017 23.2.2.1/2) +%Error-UNSUPPORTED: t/t_inst_port_complex_unsup.v:9:9: Unsupported: complex ports (IEEE 1800-2023 23.2.2.1/2) 9 | input .ai_rename(ai), .bi_rename(b), | ^ ... For error description see https://verilator.org/warn/UNSUPPORTED?v=latest -%Error-UNSUPPORTED: t/t_inst_port_complex_unsup.v:9:26: Unsupported: complex ports (IEEE 1800-2017 23.2.2.1/2) +%Error-UNSUPPORTED: t/t_inst_port_complex_unsup.v:9:26: Unsupported: complex ports (IEEE 1800-2023 23.2.2.1/2) 9 | input .ai_rename(ai), .bi_rename(b), | ^ -%Error-UNSUPPORTED: t/t_inst_port_complex_unsup.v:10:15: Unsupported: complex ports (IEEE 1800-2017 23.2.2.1/2) +%Error-UNSUPPORTED: t/t_inst_port_complex_unsup.v:10:15: Unsupported: complex ports (IEEE 1800-2023 23.2.2.1/2) 10 | output wire .ao_rename(ao), .bo_rename(bo) | ^ -%Error-UNSUPPORTED: t/t_inst_port_complex_unsup.v:10:32: Unsupported: complex ports (IEEE 1800-2017 23.2.2.1/2) +%Error-UNSUPPORTED: t/t_inst_port_complex_unsup.v:10:32: Unsupported: complex ports (IEEE 1800-2023 23.2.2.1/2) 10 | output wire .ao_rename(ao), .bo_rename(bo) | ^ -%Error-UNSUPPORTED: t/t_inst_port_complex_unsup.v:17:3: Unsupported: complex ports (IEEE 1800-2017 23.2.2.1/2) +%Error-UNSUPPORTED: t/t_inst_port_complex_unsup.v:17:3: Unsupported: complex ports (IEEE 1800-2023 23.2.2.1/2) 17 | .ai_rename(ai), .bi_rename(bi), | ^ -%Error-UNSUPPORTED: t/t_inst_port_complex_unsup.v:17:19: Unsupported: complex ports (IEEE 1800-2017 23.2.2.1/2) +%Error-UNSUPPORTED: t/t_inst_port_complex_unsup.v:17:19: Unsupported: complex ports (IEEE 1800-2023 23.2.2.1/2) 17 | .ai_rename(ai), .bi_rename(bi), | ^ -%Error-UNSUPPORTED: t/t_inst_port_complex_unsup.v:18:3: Unsupported: complex ports (IEEE 1800-2017 23.2.2.1/2) +%Error-UNSUPPORTED: t/t_inst_port_complex_unsup.v:18:3: Unsupported: complex ports (IEEE 1800-2023 23.2.2.1/2) 18 | .ao_rename(ao), .bo_rename(bo) | ^ -%Error-UNSUPPORTED: t/t_inst_port_complex_unsup.v:18:19: Unsupported: complex ports (IEEE 1800-2017 23.2.2.1/2) +%Error-UNSUPPORTED: t/t_inst_port_complex_unsup.v:18:19: Unsupported: complex ports (IEEE 1800-2023 23.2.2.1/2) 18 | .ao_rename(ao), .bo_rename(bo) | ^ -%Error-UNSUPPORTED: t/t_inst_port_complex_unsup.v:30:9: Unsupported: complex ports (IEEE 1800-2017 23.2.2.1/2) +%Error-UNSUPPORTED: t/t_inst_port_complex_unsup.v:30:9: Unsupported: complex ports (IEEE 1800-2023 23.2.2.1/2) 30 | input .ci_30(ci[3:0]), .ci_74(ci[7:4]), | ^ -%Error-UNSUPPORTED: t/t_inst_port_complex_unsup.v:30:26: Unsupported: complex ports (IEEE 1800-2017 23.2.2.1/2) +%Error-UNSUPPORTED: t/t_inst_port_complex_unsup.v:30:26: Unsupported: complex ports (IEEE 1800-2023 23.2.2.1/2) 30 | input .ci_30(ci[3:0]), .ci_74(ci[7:4]), | ^ -%Error-UNSUPPORTED: t/t_inst_port_complex_unsup.v:31:15: Unsupported: complex ports (IEEE 1800-2017 23.2.2.1/2) +%Error-UNSUPPORTED: t/t_inst_port_complex_unsup.v:31:15: Unsupported: complex ports (IEEE 1800-2023 23.2.2.1/2) 31 | output wire .co_30(co[3:0]), .co_74(co[7:4]) | ^ -%Error-UNSUPPORTED: t/t_inst_port_complex_unsup.v:31:33: Unsupported: complex ports (IEEE 1800-2017 23.2.2.1/2) +%Error-UNSUPPORTED: t/t_inst_port_complex_unsup.v:31:33: Unsupported: complex ports (IEEE 1800-2023 23.2.2.1/2) 31 | output wire .co_30(co[3:0]), .co_74(co[7:4]) | ^ -%Error-UNSUPPORTED: t/t_inst_port_complex_unsup.v:56:3: Unsupported: complex ports (IEEE 1800-2017 23.2.2.1/2) +%Error-UNSUPPORTED: t/t_inst_port_complex_unsup.v:56:3: Unsupported: complex ports (IEEE 1800-2023 23.2.2.1/2) 56 | .abi({ai, bi}), | ^ -%Error-UNSUPPORTED: t/t_inst_port_complex_unsup.v:57:3: Unsupported: complex ports (IEEE 1800-2017 23.2.2.1/2) +%Error-UNSUPPORTED: t/t_inst_port_complex_unsup.v:57:3: Unsupported: complex ports (IEEE 1800-2023 23.2.2.1/2) 57 | .abo({ao, bo}) | ^ -%Error-UNSUPPORTED: t/t_inst_port_complex_unsup.v:70:30: Unsupported: complex ports (IEEE 1800-2017 23.2.2.1/2) +%Error-UNSUPPORTED: t/t_inst_port_complex_unsup.v:70:30: Unsupported: complex ports (IEEE 1800-2023 23.2.2.1/2) 70 | module nansi_mixed_direction(.aio({ai, ao})); | ^ %Error: Exiting due to diff --git a/test_regress/t/t_randc_constraint.v b/test_regress/t/t_randc_constraint.v index 3d5819d50..b64d91d24 100644 --- a/test_regress/t/t_randc_constraint.v +++ b/test_regress/t/t_randc_constraint.v @@ -5,7 +5,7 @@ // SPDX-License-Identifier: CC0-1.0 // Test: randc variables with additional constraints limiting values -// IEEE 1800 Section 18.4.2: randc cyclic behavior over constrained domain +// IEEE 1800-2023 18.4.2: randc cyclic behavior over constrained domain // verilog_format: off `define stop $stop diff --git a/test_regress/t/t_randomize_prepost_nested.v b/test_regress/t/t_randomize_prepost_nested.v index 4ce6c32ed..1f55d0d0d 100644 --- a/test_regress/t/t_randomize_prepost_nested.v +++ b/test_regress/t/t_randomize_prepost_nested.v @@ -10,7 +10,7 @@ // verilog_format: on // Test: pre/post_randomize callbacks on nested rand class objects and inherited methods -// Covers: IEEE 1800-2017 Section 18.4.1 recursive callback invocation +// Covers: IEEE 1800-2023 18.4.1 recursive callback invocation // --- Inherited callbacks (no override) --- diff --git a/test_regress/t/t_randomize_soft.v b/test_regress/t/t_randomize_soft.v index 2fe4cfa1c..ab7b44324 100644 --- a/test_regress/t/t_randomize_soft.v +++ b/test_regress/t/t_randomize_soft.v @@ -4,7 +4,7 @@ // SPDX-FileCopyrightText: 2026 PlanV GmbH // SPDX-License-Identifier: CC0-1.0 -// Test soft constraint solving per IEEE 1800-2017 section 18.5.13 +// Test soft constraint solving per IEEE 1800-2023 18.5.13 // verilog_format: off `define stop $stop diff --git a/test_regress/t/t_stream_unpack_lhs.v b/test_regress/t/t_stream_unpack_lhs.v index 9896adfd1..26730c543 100644 --- a/test_regress/t/t_stream_unpack_lhs.v +++ b/test_regress/t/t_stream_unpack_lhs.v @@ -1,5 +1,5 @@ // DESCRIPTION: Verilator: Verilog Test module -// Ref. to IEEE Std 1800-2017 11.4.14 & A.8.1 +// Ref. to IEEE 1800-2023 11.4.14, A.8.1 // // This file ONLY is placed under the Creative Commons Public Domain. // SPDX-FileCopyrightText: 2020 Victor Besyakov diff --git a/test_regress/t/t_typename.v b/test_regress/t/t_typename.v index 9adf23ce2..a9a17a3ce 100644 --- a/test_regress/t/t_typename.v +++ b/test_regress/t/t_typename.v @@ -6,7 +6,7 @@ `define printtype(mytype, expec) $write({"\"", $typename(mytype), "\" ==? \"", expec, "\"\n"}); -// Copied from 20.6.1 Type name function in IEEE 1800-2017 +// Copied from IEEE 1800-2023 20.6.1 Type name function // source code // $typename would return typedef bit node; // "bit" node [2:0] X; // "bit [2:0]"