From 4ff518de6133c8b1b3f6420d1f43307e38d79bdd Mon Sep 17 00:00:00 2001
From: Veripool API Bot <57024651+veripoolbot@users.noreply.github.com>
Date: Wed, 4 Mar 2026 20:12:10 -0500
Subject: [PATCH] Verilog format

---
 .../t/t_constraint_array_index_unsup.v        | 16 ++---
 test_regress/t/t_constraint_array_limit.v     |  6 +-
 test_regress/t/t_constraint_array_sum_with.v  | 14 +++--
 test_regress/t/t_interface_tristate_hier.v    | 14 ++---
 .../t/t_lint_multidriven_coverage_bad.v       |  6 +-
 test_regress/t/t_lparam_pkg_assign.v          | 10 +--
 test_regress/t/t_lparam_pkg_assign2.v         | 12 ++--
 test_regress/t/t_lparam_pkg_assign3.v         | 12 ++--
 test_regress/t/t_lparam_pkg_assign4.v         | 18 ++++--
 test_regress/t/t_lparam_pkg_assign5.v         | 24 ++++---
 test_regress/t/t_tri_hier_ref_unsup.v         |  4 +-
 .../t/t_tri_iface_eqcase_modport_bad.v        | 11 ++--
 test_regress/t/t_tri_iface_semantics.v        | 63 ++++++++++++-------
 test_regress/t/t_tri_root_ref.v               |  4 +-
 14 files changed, 130 insertions(+), 84 deletions(-)

diff --git a/test_regress/t/t_constraint_array_index_unsup.v b/test_regress/t/t_constraint_array_index_unsup.v
index c22469a75..d23621857 100644
--- a/test_regress/t/t_constraint_array_index_unsup.v
+++ b/test_regress/t/t_constraint_array_index_unsup.v
@@ -9,21 +9,21 @@ class Packet;
   rand bit [3:0] data[5];
 
   constraint c {
-     // This should trigger unsupported warning
-     data.sum() with (item.index) <= 10;
+    // This should trigger unsupported warning
+    data.sum() with (item.index) <= 10;
   }
 endclass
 
 module t;
   initial begin
-     Packet p;
-     int i;
+    Packet p;
+    int i;
 
-     p = new;
+    p = new;
 
-     i = p.randomize();
+    i = p.randomize();
 
-     $write("*-* All Finished *-*\n");
-     $finish;
+    $write("*-* All Finished *-*\n");
+    $finish;
   end
 endmodule
diff --git a/test_regress/t/t_constraint_array_limit.v b/test_regress/t/t_constraint_array_limit.v
index 6683227cf..476daac4c 100644
--- a/test_regress/t/t_constraint_array_limit.v
+++ b/test_regress/t/t_constraint_array_limit.v
@@ -5,15 +5,15 @@
 // SPDX-License-Identifier: CC0-1.0
 
 // Test that array reduction constraints are ignored when array size exceeds --constraint-array-limit
+// verilog_format: off
 `define stop $stop
 `define checkd(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d:  got=%0d exp=%0d\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0);
+// verilog_format: on
 
 class Packet;
   rand int data[32];
 
-  constraint c {
-    data.sum() with (item) < 1000;
-  }
+  constraint c {data.sum() with (item) < 1000;}
 
   function void verify();
     int i;
diff --git a/test_regress/t/t_constraint_array_sum_with.v b/test_regress/t/t_constraint_array_sum_with.v
index 01e7dfa71..49b719082 100644
--- a/test_regress/t/t_constraint_array_sum_with.v
+++ b/test_regress/t/t_constraint_array_sum_with.v
@@ -5,8 +5,10 @@
 // SPDX-License-Identifier: CC0-1.0
 
 // Test case for array reduction methods with 'with' clause in constraints (issue #6455)
+// verilog_format: off
 `define stop $stop
 `define checkd(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d:  got=%0d exp=%0d\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0);
+// verilog_format: on
 
 class test_sum;
   rand byte array[5];
@@ -14,11 +16,11 @@ class test_sum;
 
   constraint c {
     // Ensure exactly 3 occurrences of repeated_value using sum
-    array.sum() with (int'(item==repeated_value)) == 3;
+    array.sum() with (int'(item == repeated_value)) == 3;
 
     // All other values should appear exactly once
-    foreach(array[i]) {
-      array[i] != repeated_value -> array.sum() with (int'(item==array[i])) == 1;
+    foreach (array[i]) {
+      array[i] != repeated_value -> array.sum() with (int'(item == array[i])) == 1;
     }
   }
 
@@ -44,7 +46,8 @@ class test_sum;
                  repeated_value, repeated_count);
         $stop;
       end
-    end else begin
+    end
+    else begin
       $display("%%Error: sum test - repeated_value=%0d doesn't appear in array", repeated_value);
       $stop;
     end
@@ -52,7 +55,8 @@ class test_sum;
     // Check all other values appear exactly once
     foreach (count_map[val]) begin
       if (val != repeated_value && count_map[val] != 1) begin
-        $display("%%Error: sum test - value=%0d appears %0d times, expected 1", val, count_map[val]);
+        $display("%%Error: sum test - value=%0d appears %0d times, expected 1", val,
+                 count_map[val]);
         $stop;
       end
     end
diff --git a/test_regress/t/t_interface_tristate_hier.v b/test_regress/t/t_interface_tristate_hier.v
index f159b86d0..105c37aff 100644
--- a/test_regress/t/t_interface_tristate_hier.v
+++ b/test_regress/t/t_interface_tristate_hier.v
@@ -24,38 +24,38 @@ interface ifc_multi;
 endinterface
 
 module bot (
-  ifc io_ifc
+    ifc io_ifc
 );
   assign io_ifc.d = io_ifc.we2 ? 16'hd2 : 16'hzzzz;
 endmodule
 
 module passthru (
-  ifc io_ifc
+    ifc io_ifc
 );
   bot u_bot (.*);
 endmodule
 
 module bot_a (
-  ifc_multi io_ifc
+    ifc_multi io_ifc
 );
   assign io_ifc.d = io_ifc.wea ? 16'hd2 : 16'hzzzz;
 endmodule
 
 module bot_b (
-  ifc_multi io_ifc
+    ifc_multi io_ifc
 );
   assign io_ifc.d = io_ifc.web ? 16'hd2 : 16'hzzzz;
 endmodule
 
 module passthru_multi_c (
-  ifc_multi io_ifc
+    ifc_multi io_ifc
 );
   bot_a u_bot_a (.*);
   bot_b u_bot_b (.*);
 endmodule
 
 module passthru_deep (
-  ifc io_ifc
+    ifc io_ifc
 );
   passthru u_inner (.*);
 endmodule
@@ -66,7 +66,7 @@ module t;
   ifc io_ifc_b0 ();
   ifc io_ifc_b1 ();
   ifc_multi io_ifc_mc ();
-  ifc io_arr [1:0]();
+  ifc io_arr[1:0] ();
   ifc io_ifc_deep ();
 
   // Test top assignment
diff --git a/test_regress/t/t_lint_multidriven_coverage_bad.v b/test_regress/t/t_lint_multidriven_coverage_bad.v
index 4ea05186e..07367bd1e 100644
--- a/test_regress/t/t_lint_multidriven_coverage_bad.v
+++ b/test_regress/t/t_lint_multidriven_coverage_bad.v
@@ -5,9 +5,9 @@
 // SPDX-License-Identifier: CC0-1.0
 
 module t (
-  input logic a,
-  input logic b,
-  output logic [1:0] y
+    input logic a,
+    input logic b,
+    output logic [1:0] y
 );
 
   logic [1:0] w;
diff --git a/test_regress/t/t_lparam_pkg_assign.v b/test_regress/t/t_lparam_pkg_assign.v
index d1190c23f..48d055455 100644
--- a/test_regress/t/t_lparam_pkg_assign.v
+++ b/test_regress/t/t_lparam_pkg_assign.v
@@ -17,17 +17,19 @@ package pkg;
   endfunction
 endpackage
 
-interface ifc();
+interface ifc ();
   localparam int PARAM = 1;
 endinterface
 
-module mod(ifc i);
+module mod (
+    ifc i
+);
   localparam bit lpbit = pkg::fn(i.PARAM);
 endmodule
 
 module t;
-  ifc i();
-  mod m(.i);
+  ifc i ();
+  mod m (.i);
 
   initial begin
     `checkd(m.lpbit, 1'b1);
diff --git a/test_regress/t/t_lparam_pkg_assign2.v b/test_regress/t/t_lparam_pkg_assign2.v
index 4a7ee7dfb..4a5d186fd 100644
--- a/test_regress/t/t_lparam_pkg_assign2.v
+++ b/test_regress/t/t_lparam_pkg_assign2.v
@@ -17,20 +17,24 @@ package pkg;
   endfunction
 endpackage
 
-interface ifc #(parameter int WIDTH = 8);
+interface ifc #(
+    parameter int WIDTH = 8
+);
   localparam int DEPTH = $clog2(WIDTH);
   localparam int COMPUTED = DEPTH * 2;
 endinterface
 
-module mod(ifc i);
+module mod (
+    ifc i
+);
   // LPARAM references i.COMPUTED which depends on i.DEPTH which depends on WIDTH
   localparam bit lpbit = pkg::fn(i.COMPUTED);
   localparam int lpval = i.COMPUTED + 1;
 endmodule
 
 module t;
-  ifc #(.WIDTH(64)) i();
-  mod m(.i);
+  ifc #(.WIDTH(64)) i ();
+  mod m (.i);
 
   initial begin
     // DEPTH = $clog2(64) = 6, COMPUTED = 6*2 = 12
diff --git a/test_regress/t/t_lparam_pkg_assign3.v b/test_regress/t/t_lparam_pkg_assign3.v
index 89640a45e..b7e24f3ad 100644
--- a/test_regress/t/t_lparam_pkg_assign3.v
+++ b/test_regress/t/t_lparam_pkg_assign3.v
@@ -17,7 +17,9 @@ package pkg;
   endfunction
 endpackage
 
-interface ifc #(parameter type some_type) ();
+interface ifc #(
+    parameter type some_type
+) ();
   localparam int PARAM = 1;
   localparam int TYPE_WIDTH = $bits(some_type);
 endinterface
@@ -27,14 +29,16 @@ function automatic bit assert_func(bit value);
   return value;
 endfunction
 
-module mod(ifc i);
+module mod (
+    ifc i
+);
   localparam bit lpbit = pkg::fn(i.PARAM);
   localparam bit test = assert_func(i.TYPE_WIDTH == 32);
 endmodule
 
 module t;
-  ifc #(.some_type(int)) i();
-  mod m(.i);
+  ifc #(.some_type(int)) i ();
+  mod m (.i);
 
   initial begin
     `checkd(m.lpbit, 1'b1);  // fn(1) returns 1 since 1 > 0
diff --git a/test_regress/t/t_lparam_pkg_assign4.v b/test_regress/t/t_lparam_pkg_assign4.v
index 751991ee4..92eba51d9 100644
--- a/test_regress/t/t_lparam_pkg_assign4.v
+++ b/test_regress/t/t_lparam_pkg_assign4.v
@@ -17,25 +17,31 @@ package pkg;
   endfunction
 endpackage
 
-interface ifc #(parameter int WIDTH = 8);
+interface ifc #(
+    parameter int WIDTH = 8
+);
   localparam int DEPTH = $clog2(WIDTH);
   localparam int DECODED = pkg::decode_width(DEPTH);
 endinterface
 
-module producer(ifc i);
+module producer (
+    ifc i
+);
   localparam int BUF_SIZE = pkg::decode_width(i.DEPTH);
   localparam int OUT_W = i.DECODED + 1;
 endmodule
 
-module consumer(ifc i);
+module consumer (
+    ifc i
+);
   localparam int HALF = i.DECODED / 2;
   localparam int TAG_W = pkg::decode_width(i.DEPTH) + i.DECODED;
 endmodule
 
 module t;
-  ifc #(.WIDTH(64)) bus[2]();
-  producer p(.i(bus[0]));
-  consumer c(.i(bus[1]));
+  ifc #(.WIDTH(64)) bus[2] ();
+  producer p (.i(bus[0]));
+  consumer c (.i(bus[1]));
 
   initial begin
     // WIDTH=64, DEPTH=$clog2(64)=6, DECODED=decode_width(6)=12
diff --git a/test_regress/t/t_lparam_pkg_assign5.v b/test_regress/t/t_lparam_pkg_assign5.v
index 783e32245..deb631cd2 100644
--- a/test_regress/t/t_lparam_pkg_assign5.v
+++ b/test_regress/t/t_lparam_pkg_assign5.v
@@ -17,30 +17,38 @@ package pkg;
   endfunction
 endpackage
 
-interface ifc #(parameter int WIDTH = 8);
+interface ifc #(
+    parameter int WIDTH = 8
+);
   localparam int DEPTH = $clog2(WIDTH);
   localparam int DECODED = pkg::decode_width(DEPTH);
 endinterface
 
 // Leaf module: uses interface LPARAM in a FUNCREF-based localparam
-module leaf(ifc i);
+module leaf (
+    ifc i
+);
   localparam int BUF_SIZE = pkg::decode_width(i.DEPTH);
   localparam int OUT_W = i.DECODED + 1;
 endmodule
 
 // Intermediate wrapper: passes interface through to leaf
-module wrapper(ifc i);
-  leaf u_leaf(.i);
+module wrapper (
+    ifc i
+);
+  leaf u_leaf (.i);
 endmodule
 
 // Second level wrapper: adds another layer of hierarchy
-module subsystem(ifc bus);
-  wrapper u_wrap(.i(bus));
+module subsystem (
+    ifc bus
+);
+  wrapper u_wrap (.i(bus));
 endmodule
 
 module t;
-  ifc #(.WIDTH(64)) bus();
-  subsystem u_sub(.bus);
+  ifc #(.WIDTH(64)) bus ();
+  subsystem u_sub (.bus);
 
   initial begin
     // WIDTH=64, DEPTH=$clog2(64)=6, DECODED=decode_width(6)=12
diff --git a/test_regress/t/t_tri_hier_ref_unsup.v b/test_regress/t/t_tri_hier_ref_unsup.v
index e8cd1165a..319f04d12 100644
--- a/test_regress/t/t_tri_hier_ref_unsup.v
+++ b/test_regress/t/t_tri_hier_ref_unsup.v
@@ -18,7 +18,7 @@
 // verilator lint_off MULTIDRIVEN
 
 module sub_with_tri (
-  input we_internal
+    input we_internal
 );
   tri [7:0] bus;
   // Internal driver: drives 8'hAA when we_internal is high
@@ -27,7 +27,7 @@ endmodule
 
 module t;
   logic sub_we_internal;
-  sub_with_tri u_sub(.we_internal(sub_we_internal));
+  sub_with_tri u_sub (.we_internal(sub_we_internal));
 
   logic hier_we;
   // Drive u_sub.bus hierarchically from this module
diff --git a/test_regress/t/t_tri_iface_eqcase_modport_bad.v b/test_regress/t/t_tri_iface_eqcase_modport_bad.v
index cf95b5427..f90517341 100644
--- a/test_regress/t/t_tri_iface_eqcase_modport_bad.v
+++ b/test_regress/t/t_tri_iface_eqcase_modport_bad.v
@@ -13,12 +13,12 @@
 interface ifc;
   logic we;
   tri [7:0] d;
-  modport no_d_mp (input we);  // d is NOT exposed
+  modport no_d_mp(input we);  // d is NOT exposed
 endinterface
 
 module chk_bad (
-  ifc.no_d_mp io_ifc,
-  output logic is_z
+    ifc.no_d_mp io_ifc,
+    output logic is_z
 );
   assign is_z = (io_ifc.d === 8'hzz);
 endmodule
@@ -26,6 +26,9 @@ endmodule
 module t;
   ifc i ();
   logic is_z;
-  chk_bad u (.io_ifc(i), .is_z(is_z));
+  chk_bad u (
+      .io_ifc(i),
+      .is_z(is_z)
+  );
   initial $finish;
 endmodule
diff --git a/test_regress/t/t_tri_iface_semantics.v b/test_regress/t/t_tri_iface_semantics.v
index 629edc12f..39f2058f8 100644
--- a/test_regress/t/t_tri_iface_semantics.v
+++ b/test_regress/t/t_tri_iface_semantics.v
@@ -20,17 +20,17 @@ interface ifc_cmp;
 endinterface
 
 module drv_cmp (
-  ifc_cmp io_ifc
+    ifc_cmp io_ifc
 );
   assign io_ifc.d = io_ifc.we ? 8'h5A : 8'hzz;
 endmodule
 
 module chk_cmp (
-  ifc_cmp io_ifc,
-  output logic is_z,
-  output logic is_5a,
-  output logic not_z,
-  output logic not_5a
+    ifc_cmp io_ifc,
+    output logic is_z,
+    output logic is_5a,
+    output logic not_z,
+    output logic not_5a
 );
   assign is_z = (io_ifc.d === 8'hzz);
   assign is_5a = (io_ifc.d === 8'h5A);
@@ -41,22 +41,22 @@ endmodule
 interface ifc_cmp_mp;
   logic we;
   tri [7:0] d;
-  modport drv_mp (input we, inout d);
-  modport chk_mp (input we, inout d);
+  modport drv_mp(input we, inout d);
+  modport chk_mp(input we, inout d);
 endinterface
 
 module drv_cmp_mp (
-  ifc_cmp_mp.drv_mp io_ifc
+    ifc_cmp_mp.drv_mp io_ifc
 );
   assign io_ifc.d = io_ifc.we ? 8'h5A : 8'hzz;
 endmodule
 
 module chk_cmp_mp (
-  ifc_cmp_mp.chk_mp io_ifc,
-  output logic is_z,
-  output logic is_5a,
-  output logic not_z,
-  output logic not_5a
+    ifc_cmp_mp.chk_mp io_ifc,
+    output logic is_z,
+    output logic is_5a,
+    output logic not_z,
+    output logic not_5a
 );
   assign is_z = (io_ifc.d === 8'hzz);
   assign is_5a = (io_ifc.d === 8'h5A);
@@ -65,7 +65,7 @@ module chk_cmp_mp (
 endmodule
 
 module passthru_cmp (
-  ifc_cmp io_ifc
+    ifc_cmp io_ifc
 );
   drv_cmp u_drv (.*);
 endmodule
@@ -79,7 +79,7 @@ interface ifc_mix;
 endinterface
 
 module drv_mix (
-  ifc_mix io_ifc
+    ifc_mix io_ifc
 );
   assign io_ifc.d = io_ifc.we_ext ? 8'h3C : 8'hzz;
 endmodule
@@ -88,12 +88,12 @@ interface ifc_mix_mp;
   logic we_local;
   logic we_ext;
   tri [7:0] d;
-  modport drv_mp (input we_ext, inout d);
+  modport drv_mp(input we_ext, inout d);
   assign d = we_local ? 8'hA5 : 8'hzz;
 endinterface
 
 module drv_mix_mp (
-  ifc_mix_mp.drv_mp io_ifc
+    ifc_mix_mp.drv_mp io_ifc
 );
   assign io_ifc.d = io_ifc.we_ext ? 8'h3C : 8'hzz;
 endmodule
@@ -103,22 +103,37 @@ module t;
   ifc_cmp i_cmp ();
   logic is_z, is_5a, not_z, not_5a;
   drv_cmp u_drv_cmp (.io_ifc(i_cmp));
-  chk_cmp u_chk_cmp (.io_ifc(i_cmp), .is_z(is_z), .is_5a(is_5a),
-                     .not_z(not_z), .not_5a(not_5a));
+  chk_cmp u_chk_cmp (
+      .io_ifc(i_cmp),
+      .is_z(is_z),
+      .is_5a(is_5a),
+      .not_z(not_z),
+      .not_5a(not_5a)
+  );
 
   // ---- Compare semantics: modport ----
   ifc_cmp_mp i_cmp_mp ();
   logic mp_is_z, mp_is_5a, mp_not_z, mp_not_5a;
   drv_cmp_mp u_drv_cmp_mp (.io_ifc(i_cmp_mp));
-  chk_cmp_mp u_chk_cmp_mp (.io_ifc(i_cmp_mp), .is_z(mp_is_z), .is_5a(mp_is_5a),
-                           .not_z(mp_not_z), .not_5a(mp_not_5a));
+  chk_cmp_mp u_chk_cmp_mp (
+      .io_ifc(i_cmp_mp),
+      .is_z(mp_is_z),
+      .is_5a(mp_is_5a),
+      .not_z(mp_not_z),
+      .not_5a(mp_not_5a)
+  );
 
   // ---- Compare semantics: deep hierarchy ----
   ifc_cmp i_cmp_deep ();
   logic deep_is_z, deep_is_5a, deep_not_z, deep_not_5a;
   passthru_cmp u_cmp_deep (.io_ifc(i_cmp_deep));
-  chk_cmp u_chk_cmp_deep (.io_ifc(i_cmp_deep), .is_z(deep_is_z), .is_5a(deep_is_5a),
-                          .not_z(deep_not_z), .not_5a(deep_not_5a));
+  chk_cmp u_chk_cmp_deep (
+      .io_ifc(i_cmp_deep),
+      .is_z(deep_is_z),
+      .is_5a(deep_is_5a),
+      .not_z(deep_not_z),
+      .not_5a(deep_not_5a)
+  );
 
   // ---- Mixed contributors ----
   ifc_mix i_mix ();
diff --git a/test_regress/t/t_tri_root_ref.v b/test_regress/t/t_tri_root_ref.v
index 44dc14d29..1dc92baa7 100644
--- a/test_regress/t/t_tri_root_ref.v
+++ b/test_regress/t/t_tri_root_ref.v
@@ -15,7 +15,7 @@
 // verilog_format: on
 
 module sub_root_reader (
-  output logic [7:0] val
+    output logic [7:0] val
 );
   assign val = $root.t.root_bus;
 endmodule
@@ -26,7 +26,7 @@ module t;
   assign root_bus = root_we ? 8'hCC : 8'hzz;
 
   logic [7:0] root_readback;
-  sub_root_reader u_reader(.val(root_readback));
+  sub_root_reader u_reader (.val(root_readback));
 
   initial begin
     #1;