diff --git a/Changes b/Changes index 9dced9b36..206d397d3 100644 --- a/Changes +++ b/Changes @@ -3,13 +3,21 @@ Revision history for Verilator The contributors that suggested a given feature are shown in []. [by ...] indicates the contributor was also the author of the fix; Thanks! -* Verilator 3.813**** +* Verilator 3.814**** + +*** Support disable for loop escapes. + +* Verilator 3.813 2011/06/28 + +*** Support bit vectors > 64 bits wide in DPI import and exports. + +*** Fix out of memory on slice syntax error, bug354. [Alex Solomatnikov] **** Fix error on enum references to other packages, bug339. [Alex Solomatnikov] **** Fix DPI undeclared svBitVecVal compile error, bug346. [Chandan Egbert] -**** Fix DPI bit vector compile errors, bug347. [Chandan Egbert] +**** Fix DPI bit vector compile errors, bug347, bug359. [Chandan Egbert] **** Fix CDCRSTLOGIC report showing endpoint flops without resets. diff --git a/bin/verilator b/bin/verilator index 538dfc26a..8f9598f7c 100755 --- a/bin/verilator +++ b/bin/verilator @@ -2258,6 +2258,13 @@ not arrays nor structs. Treated as a "longint"; does not yet warn about operations that are specified as illegal on chandles. +=item disable + +Disable statements may be used only if the block being disabled is a block +the disable statement itself is inside. This is commonly used to provide +loop break and continue functionality before SystemVerilog added the break +and continue keywords. + =item priority if, unique if Priority and unique if's are treated as normal ifs and not asserted to be diff --git a/include/verilated.h b/include/verilated.h index f1d1c3a40..b5ff1b3a0 100644 --- a/include/verilated.h +++ b/include/verilated.h @@ -1633,6 +1633,6 @@ static inline WDataOutP VL_CONST_W_9X(int obits, WDataOutP o, #undef _END -// Debugging +//====================================================================== #endif /*_VERILATED_H_*/ diff --git a/include/verilated_dpi.cpp b/include/verilated_dpi.cpp index 2b50191cd..d0d7731f5 100644 --- a/include/verilated_dpi.cpp +++ b/include/verilated_dpi.cpp @@ -25,6 +25,7 @@ #define _VERILATED_DPI_CPP_ #include "verilatedos.h" +#include "verilated_dpi.h" #include "verilated_imp.h" // On MSVC++ we need svdpi.h to declare exports, not imports diff --git a/include/verilated_dpi.h b/include/verilated_dpi.h new file mode 100644 index 000000000..2aac27973 --- /dev/null +++ b/include/verilated_dpi.h @@ -0,0 +1,64 @@ +// -*- C++ -*- +//************************************************************************* +// +// Copyright 2003-2011 by Wilson Snyder. This program is free software; you can +// redistribute it and/or modify it under the terms of either the GNU +// Lesser General Public License Version 3 or the Perl Artistic License. +// Version 2.0. +// +// Verilator is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +//************************************************************************* +/// +/// \file +/// \brief Verilator: Common include for all Verilated C files that use DPI +/// +/// This file is included automatically by Verilator at the top of +/// all C++ files it generates where DPI is used. It contains +/// DPI interface functions required by the Verilated code. +/// +/// Code available from: http://www.veripool.org/verilator +/// +//************************************************************************* + + +#ifndef _VERILATED_DPI_H_ +#define _VERILATED_DPI_H_ 1 ///< Header Guard + +#include "verilated.h" // Presumed done by caller +#include "svdpi.h" + +//=================================================================== +// SETTING OPERATORS + +/// Return svBitVecVal from WData +static inline void VL_SET_W_SVBV(int obits, WDataOutP owp, svBitVecVal* lwp) { + int words = VL_WORDS_I(obits); + for (int i=0; i 32-bits"); if (basicp()->isBitLogic()) { if (widthMin() == 1) { arg = "unsigned char"; diff --git a/src/V3AstNodes.h b/src/V3AstNodes.h index 235fe93b8..479dce113 100644 --- a/src/V3AstNodes.h +++ b/src/V3AstNodes.h @@ -1973,6 +1973,18 @@ struct AstContinue : public AstNodeStmt { virtual bool isSplittable() const { return false; } // SPECIAL: We don't process code after breaks }; +struct AstDisable : public AstNodeStmt { +private: + string m_name; // Name of block +public: + AstDisable(FileLine* fileline, const string& name) + : AstNodeStmt(fileline), m_name(name) {} + ASTNODE_NODE_FUNCS(Disable, DISABLE) + virtual string name() const { return m_name; } // * = Block name + void name(const string& flag) { m_name=flag; } + virtual bool isSplittable() const { return false; } // SPECIAL: We don't process code after breaks +}; + struct AstReturn : public AstNodeStmt { AstReturn(FileLine* fileline, AstNode* lhsp=NULL) : AstNodeStmt (fileline) { diff --git a/src/V3EmitC.cpp b/src/V3EmitC.cpp index 19cee0ea9..96761b907 100644 --- a/src/V3EmitC.cpp +++ b/src/V3EmitC.cpp @@ -127,6 +127,7 @@ public: nodep->lhsp()->iterateAndNext(*this); puts(", "); } else if (nodep->isWide() && nodep->lhsp()->castVarRef() + && !nodep->rhsp()->castCMath() && !nodep->rhsp()->castVarRef() && !nodep->rhsp()->castArraySel()) { // Wide functions assign into the array directly, don't need separate assign statement @@ -1803,6 +1804,11 @@ void EmitCImp::emitImp(AstNodeModule* modp) { // Us puts("#include \""+ symClassName() +".h\"\n"); + if (v3Global.dpi()) { + puts("\n"); + puts("#include \"verilated_dpi.h\"\n"); + } + if (optSystemPerl() && (splitFilenum() || !m_fast)) { puts("\n"); puts("SP_MODULE_CONTINUED("+modClassName(modp)+");\n"); diff --git a/src/V3EmitV.cpp b/src/V3EmitV.cpp index a72422278..e17b563a5 100644 --- a/src/V3EmitV.cpp +++ b/src/V3EmitV.cpp @@ -217,6 +217,9 @@ class EmitVBaseVisitor : public EmitCBaseVisitor { } puts(");\n"); } + virtual void visit(AstDisable* nodep, AstNUser*) { + putbs("disable "+nodep->name()+";\n"); + } virtual void visit(AstDisplay* nodep, AstNUser*) { visitNodeDisplay(nodep, nodep->filep(), nodep->fmtp()->text(), nodep->fmtp()->exprsp()); } diff --git a/src/V3LinkJump.cpp b/src/V3LinkJump.cpp index a12c50b85..4f73b4321 100644 --- a/src/V3LinkJump.cpp +++ b/src/V3LinkJump.cpp @@ -211,6 +211,27 @@ private: } nodep->unlinkFrBack(); pushDeletep(nodep); nodep=NULL; } + virtual void visit(AstDisable* nodep, AstNUser*) { + UINFO(8," DISABLE "<iterateChildren(*this); + AstBegin* beginp = NULL; + for (BeginStack::reverse_iterator it = m_beginStack.rbegin(); it != m_beginStack.rend(); ++it) { + UINFO(9," UNDERBLK "<<*it<name() == nodep->name()) { + beginp = *it; + break; + } + } + //if (debug()>=9) { UINFO(0,"\n"); beginp->dumpTree(cout," labeli: "); } + if (!beginp) { nodep->v3error("disable isn't underneath a begin with name: "<name()); } + else { + // Jump to the end of the named begin + AstJumpLabel* labelp = findAddLabel(beginp, false); + nodep->addNextHere(new AstJumpGo(nodep->fileline(), labelp)); + } + nodep->unlinkFrBack(); pushDeletep(nodep); nodep=NULL; + //if (debug()>=9) { UINFO(0,"\n"); beginp->dumpTree(cout," labelo: "); } + } virtual void visit(AstVarRef* nodep, AstNUser*) { if (m_loopInc && nodep->varp()) nodep->varp()->usedLoopIdx(true); } diff --git a/src/V3Slice.cpp b/src/V3Slice.cpp index d4b5d37d8..074f899f8 100644 --- a/src/V3Slice.cpp +++ b/src/V3Slice.cpp @@ -53,6 +53,7 @@ class SliceCloneVisitor : public AstNVisitor { // Inputs: // AstArraySel::user1p() -> AstVarRef. The VarRef that the final ArraySel points to // AstNodeAssign::user2() -> int. The number of clones needed for this assign + // AstArraySel::user3() -> bool. Error detected // ENUMS enum RedOp { // The type of unary operation to be expanded @@ -221,6 +222,7 @@ class SliceVisitor : public AstNVisitor { // AstNode::user2() -> int. The number of clones needed for this node AstUser1InUse m_inuser1; AstUser2InUse m_inuser2; + AstUser3InUse m_inuser3; // TYPEDEFS typedef pair ArrayDimensions; // Array Dimensions (packed, unpacked) @@ -328,11 +330,11 @@ class SliceVisitor : public AstNVisitor { m_assignp->v3error("Unsupported: Assignment between a constant and an array slice"); m_assignError = true; } - nodep->iterateChildren(*this); } virtual void visit(AstArraySel* nodep, AstNUser*) { if (!m_assignp) return; + if (nodep->user3()) return; // Prevent recursion on just created nodes unsigned dim = explicitDimensions(nodep); AstVarRef* refp = nodep->user1p()->castNode()->castVarRef(); pair arrDim = refp->varp()->dimensions(); @@ -340,16 +342,18 @@ class SliceVisitor : public AstNVisitor { if (implicit > 0) { AstArraySel* newp = insertImplicit(nodep->cloneTree(false), dim+1, implicit); nodep->replaceWith(newp); nodep = newp; + nodep->user3(true); } int clones = countClones(nodep); if (m_assignp->user2() > 0 && m_assignp->user2() != clones) { m_assignp->v3error("Slices of arrays in assignments must have the same unpacked dimensions"); - } else if (m_assignp->user2() == 0 && !m_assignError) { - if (m_extend && clones > 1) { + } else if (!m_assignp->user2()) { + if (m_extend && clones > 1 && !m_assignError) { m_assignp->v3error("Unsupported: Assignment between packed arrays of different dimensions"); m_assignError = true; } - if (clones > 1 && !refp->lvalue() && refp->varp() == m_lhsVarRefp->varp() && !m_assignp->castAssignDly()) { + if (clones > 1 && !refp->lvalue() && refp->varp() == m_lhsVarRefp->varp() + && !m_assignp->castAssignDly() && !m_assignError) { // LHS Var != RHS Var for a non-delayed assignment m_assignp->v3error("Unsupported: Slices in a non-delayed assignment with the same Var on both sides"); m_assignError = true; diff --git a/src/V3Task.cpp b/src/V3Task.cpp index 8b55882d4..f4829f104 100644 --- a/src/V3Task.cpp +++ b/src/V3Task.cpp @@ -587,8 +587,12 @@ private: // Someday we'll have better type support, and this can make variables and casts. // But for now, we'll just text-bash it. if (bitvec) { - // We only support quads, so don't need to sweat longer stuff - stmt += "VL_SET_WQ("+portp->name()+toSuffix+", "+portp->name()+frSuffix+")"; + if (portp->isWide()) { + stmt += ("VL_SET_SVBV_W("+cvtToStr(portp->width()) + +", "+portp->name()+toSuffix+", "+portp->name()+frSuffix+")"); + } else { + stmt += "VL_SET_WQ("+portp->name()+toSuffix+", "+portp->name()+frSuffix+")"; + } } else { if (isPtr) stmt += "*"; // DPI outputs are pointers stmt += portp->name()+toSuffix+" = "; @@ -615,7 +619,8 @@ private: ket += ")"; } if (!cvt - && portp->basicp() && portp->basicp()->isBitLogic() && portp->widthMin() != 1) stmt += "*"; // it's a svBitVecVal + && portp->basicp() && portp->basicp()->isBitLogic() && portp->widthMin() != 1 && !portp->isWide()) + stmt += "*"; // it's a svBitVecVal, which other code won't think is arrayed (as WData aren't), but really is stmt += frName; stmt += ket; // Use a AstCMath, as we want V3Clean to mask off bits that don't make sense. diff --git a/src/config_build.h.in b/src/config_build.h.in index ef306c25d..fc6b345b4 100644 --- a/src/config_build.h.in +++ b/src/config_build.h.in @@ -25,7 +25,7 @@ //********************************************************************** //**** Version and host name -#define DTVERSION "Verilator 3.813 devel" +#define DTVERSION "Verilator 3.814 devel" //********************************************************************** //**** Functions diff --git a/src/verilog.y b/src/verilog.y index c8c24b39c..e284ea022 100644 --- a/src/verilog.y +++ b/src/verilog.y @@ -1886,7 +1886,7 @@ statement_item: // IEEE: statement_item | statementVerilatorPragmas { $$ = $1; } // // // IEEE: disable_statement - //UNSUP yDISABLE idAny/*hierarchical_identifier-task_or_block*/ ';' { UNSUP } + | yDISABLE idAny/*hierarchical_identifier-task_or_block*/ ';' { $$ = new AstDisable($1,*$2); } //UNSUP yDISABLE yFORK ';' { UNSUP } // // IEEE: event_trigger //UNSUP yP_MINUSGT hierarchical_identifier/*event*/ ';' { UNSUP } diff --git a/test_regress/driver.pl b/test_regress/driver.pl index 6fe0c50c9..b85a346ca 100755 --- a/test_regress/driver.pl +++ b/test_regress/driver.pl @@ -304,8 +304,9 @@ sub new { ivrun_flags => [], # VCS vcs => 0, - vcs_flags => [split(/\s+/,"+cli -I +define+VCS+1 -q -sverilog -CFLAGS '-DVCS' ")], + vcs_flags => [split(/\s+/,"+vcs+lic+wait +cli -I +define+VCS+1 -q -sverilog -CFLAGS '-DVCS' ")], vcs_flags2 => [], # Overridden in some sim files + vcsrun_flags => [split(/\s+/,"+vcs+lic_wait")], # NC nc => 0, nc_flags => [split(/\s+/,"+licqueue +nowarn+LIBNOU +define+NC=1 -q +assert +sv -c ")], @@ -603,6 +604,7 @@ sub execute { #$fh->print("quit\n"); $fh->close; $self->_run(logfile=>"$self->{obj_dir}/vcs_sim.log", cmd=>["echo q | ".$run_env."./simv", + @{$param{vcsrun_flags}}, @{$param{all_run_flags}}, ], %param, diff --git a/test_regress/t/t_dpi_export.v b/test_regress/t/t_dpi_export.v index 1601771de..9f02d8f92 100644 --- a/test_regress/t/t_dpi_export.v +++ b/test_regress/t/t_dpi_export.v @@ -38,6 +38,11 @@ module t; function longint dpix_f_longint (longint i); dpix_f_longint = ~i; endfunction function chandle dpix_f_chandle (chandle i); dpix_f_chandle = i; endfunction + export "DPI-C" task dpix_t_bit95; + task dpix_t_bit95(input bit [94:0] i, output bit [94:0] o); o = ~i; endtask + export "DPI-C" task dpix_t_bit96; + task dpix_t_bit96(input bit [95:0] i, output bit [95:0] o); o = ~i; endtask + int lineno; initial begin diff --git a/test_regress/t/t_dpi_export_c.cpp b/test_regress/t/t_dpi_export_c.cpp index c6f8b6eab..b343a8e12 100644 --- a/test_regress/t/t_dpi_export_c.cpp +++ b/test_regress/t/t_dpi_export_c.cpp @@ -136,6 +136,23 @@ int dpix_run_tests() { CHECK_RESULT (unsigned long long, dpix_f_longint(1), 0xfffffffffffffffeULL); CHECK_RESULT (void*, dpix_f_chandle((void*)(12345)), (void*)(12345)); + { + svBitVecVal i_vec95[3] = {0x72912312,0xab782a12,0x8a413bd9}; + svBitVecVal o_vec95[3] = {0,0,0}; + dpix_t_bit95(i_vec95, o_vec95); + CHECK_RESULT(int, o_vec95[0], ~i_vec95[0]); + CHECK_RESULT(int, o_vec95[1], ~i_vec95[1]); + CHECK_RESULT(int, o_vec95[2], (~i_vec95[2])&0x7fffffffUL); + } + { + svBitVecVal i_vec96[3] = {0xf2912312,0xab782a12,0x8a413bd9}; + svBitVecVal o_vec96[3] = {0,0,0}; + dpix_t_bit96(i_vec96, o_vec96); + CHECK_RESULT(int, o_vec96[0], ~i_vec96[0]); + CHECK_RESULT(int, o_vec96[1], ~i_vec96[1]); + CHECK_RESULT(int, o_vec96[2], ~i_vec96[2]); + } + if (int bad=check_sub("top.t.a",1)) return bad; if (int bad=check_sub("top.t.b",2)) return bad; diff --git a/test_regress/t/t_dpi_import.v b/test_regress/t/t_dpi_import.v index 582479c67..6661a3eb3 100644 --- a/test_regress/t/t_dpi_import.v +++ b/test_regress/t/t_dpi_import.v @@ -59,6 +59,8 @@ module t (); `ifndef NO_SHORTREAL import "DPI-C" pure function void dpii_v_shortreal(input shortreal i, output shortreal o); `endif + import "DPI-C" pure function void dpii_v_bit95 (input bit [95-1:0] i, output bit [95-1:0] o); + import "DPI-C" pure function void dpii_v_bit96 (input bit [96-1:0] i, output bit [96-1:0] o); import "DPI-C" pure function int dpii_f_strlen (input string i); @@ -82,6 +84,8 @@ module t (); bit [31:0] i_b32, o_b32; bit [32:0] i_b33, o_b33; bit [63:0] i_b64, o_b64; + bit [94:0] i_b95, o_b95; + bit [95:0] i_b96, o_b96; int i_i, o_i; byte i_y, o_y; @@ -111,6 +115,8 @@ module t (); i_b32 = {1'b1,wide[32-2:0]}; i_b33 = {1'b1,wide[33-2:0]}; i_b64 = {1'b1,wide[64-2:0]}; + i_b95 = {1'b1,wide[95-2:0]}; + i_b96 = {1'b1,wide[96-2:0]}; i_i = {1'b1,wide[32-2:0]}; i_y = {1'b1,wide[8-2:0]}; @@ -159,6 +165,8 @@ module t (); `ifndef NO_SHORTREAL dpii_v_shortreal(i_f,o_f); if (o_f != i_f+1.5) $stop; `endif + dpii_v_bit95 (i_b95,o_b95); if (o_b95 !== ~i_b95) $stop; + dpii_v_bit96 (i_b96,o_b96); if (o_b96 !== ~i_b96) $stop; if (dpii_f_strlen ("")!=0) $stop; if (dpii_f_strlen ("s")!=1) $stop; diff --git a/test_regress/t/t_dpi_import_c.cpp b/test_regress/t/t_dpi_import_c.cpp index 70d95cfa8..c4345ab6c 100644 --- a/test_regress/t/t_dpi_import_c.cpp +++ b/test_regress/t/t_dpi_import_c.cpp @@ -33,13 +33,14 @@ extern "C" { extern unsigned char dpii_f_bit (unsigned char i); - extern svBitVecVal dpii_f_bit8 (const svBitVecVal *i); - extern svBitVecVal dpii_f_bit9 (const svBitVecVal *i); - extern svBitVecVal dpii_f_bit16 (const svBitVecVal *i); - extern svBitVecVal dpii_f_bit17 (const svBitVecVal *i); - extern svBitVecVal dpii_f_bit32 (const svBitVecVal *i); - extern long long dpii_f_bit33 (const svBitVecVal *i); - extern long long dpii_f_bit64 (const svBitVecVal *i); + extern svBitVecVal dpii_f_bit8 (const svBitVecVal* i); + extern svBitVecVal dpii_f_bit9 (const svBitVecVal* i); + extern svBitVecVal dpii_f_bit16 (const svBitVecVal* i); + extern svBitVecVal dpii_f_bit17 (const svBitVecVal* i); + extern svBitVecVal dpii_f_bit32 (const svBitVecVal* i); + extern long long dpii_f_bit33 (const svBitVecVal* i); + extern long long dpii_f_bit64 (const svBitVecVal* i); + extern long long dpii_f_bit95 (const svBitVecVal* i, svBitVecVal* o); extern int dpii_f_int (int i); extern char dpii_f_byte (char i); extern short int dpii_f_shortint(short int i); @@ -49,7 +50,7 @@ extern "C" { extern double dpii_f_real (double i); extern float dpii_f_shortreal(float i); - extern void dpii_v_bit (unsigned char i, unsigned char *o); + extern void dpii_v_bit (unsigned char i, unsigned char* o); extern void dpii_v_int (int i, int *o); extern void dpii_v_byte (char i, char *o); extern void dpii_v_shortint (short int i, short int *o); @@ -100,6 +101,17 @@ void dpii_v_string (const char* i, const char** o) { *o = i; } void dpii_v_real (double i, double* o) { *o = i + 1.5; } void dpii_v_shortreal(float i, float* o) { *o = i + 1.5; } +void dpii_v_bit95(const svBitVecVal* i, svBitVecVal* o) { + o[0] = ~i[0]; + o[1] = ~i[1]; + o[2] = SV_MASK(95-64) & ~i[2]; +} +void dpii_v_bit96(const svBitVecVal* i, svBitVecVal* o) { + o[0] = ~i[0]; + o[1] = ~i[1]; + o[2] = ~i[2]; +} + int dpii_f_strlen (const char* i) { return strlen(i); } //====================================================================== diff --git a/test_regress/t/t_embed1.pl b/test_regress/t/t_embed1.pl new file mode 100755 index 000000000..9abaa2684 --- /dev/null +++ b/test_regress/t/t_embed1.pl @@ -0,0 +1,51 @@ +#!/usr/bin/perl +if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2003 by Wilson Snyder. This program is free software; you can +# redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. + +use File::Spec; + +my $self = $Self; +my $child_dir = "$Self->{obj_dir}_child"; +mkdir $child_dir; + +# Compile the child +{ + my @cmdargs = $Self->compile_vlt_flags + (VM_PREFIX => "$Self->{VM_PREFIX}_child", + top_filename => "$Self->{name}_child.v", + verilator_flags => ["-cc", "-Mdir", "${child_dir}", "--debug-check"], + ); + + $Self->_run(logfile=>"${child_dir}/vlt_compile.log", + cmd=>\@cmdargs); + + $Self->_run(logfile=>"${child_dir}/vlt_gcc.log", + cmd=>["cd ${child_dir} && ", + "make", "-f".getcwd()."/Makefile_obj", + "CPPFLAGS_DRIVER=-D".uc($self->{name}), + ($opt_verbose ? "CPPFLAGS_DRIVER2=-DTEST_VERBOSE=1":""), + "MAKE_MAIN=0", + "VM_PREFIX=$self->{VM_PREFIX}_child", + "V$self->{name}_child__ALL.a", # bypass default rule, make archive + ($param{make_flags}||""), + ]); +} + +# Compile the parent (might be with other than verilator) +compile ( + v_flags2 => [File::Spec->rel2abs("${child_dir}/V$self->{name}_child__ALL.a"), + # TODO would be nice to have this in embedded archive + "t/t_embed1_c.cpp"], + ); + +execute ( + check_finished=>1, + ); + +ok(1); +1; diff --git a/test_regress/t/t_embed1.v b/test_regress/t/t_embed1.v new file mode 100644 index 000000000..d84751fc2 --- /dev/null +++ b/test_regress/t/t_embed1.v @@ -0,0 +1,109 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2011 by Wilson Snyder. + +module t (/*AUTOARG*/ + // Inputs + clk + ); + input clk; + + integer cyc=0; + reg [63:0] crc; + reg [63:0] sum; + + // Take CRC data and apply to testblock inputs + wire bit_in = crc[0]; + wire [30:0] vec_in = crc[31:1]; + wire [123:0] wide_in = {crc[59:0],~crc[63:0]}; + + /*AUTOWIRE*/ + // Beginning of automatic wires (for undeclared instantiated-module outputs) + wire exp_bit_out; // From reference of t_embed1_child.v + wire exp_did_init_out; // From reference of t_embed1_child.v + wire [30:0] exp_vec_out; // From reference of t_embed1_child.v + wire [123:0] exp_wide_out; // From reference of t_embed1_child.v + wire got_bit_out; // From test of t_embed1_wrap.v + wire got_did_init_out; // From test of t_embed1_wrap.v + wire [30:0] got_vec_out; // From test of t_embed1_wrap.v + wire [123:0] got_wide_out; // From test of t_embed1_wrap.v + // End of automatics + + // A non-embedded master + + /* t_embed1_child AUTO_TEMPLATE( + .\(.*_out\) (exp_\1[]), + .is_ref (1'b1)); + */ + t_embed1_child reference + (/*AUTOINST*/ + // Outputs + .bit_out (exp_bit_out), // Templated + .vec_out (exp_vec_out[30:0]), // Templated + .wide_out (exp_wide_out[123:0]), // Templated + .did_init_out (exp_did_init_out), // Templated + // Inputs + .clk (clk), + .bit_in (bit_in), + .vec_in (vec_in[30:0]), + .wide_in (wide_in[123:0]), + .is_ref (1'b1)); // Templated + + // The embeded comparison + + /* t_embed1_wrap AUTO_TEMPLATE( + .\(.*_out\) (got_\1[]), + .is_ref (1'b0)); + */ + + t_embed1_wrap test + (/*AUTOINST*/ + // Outputs + .bit_out (got_bit_out), // Templated + .vec_out (got_vec_out[30:0]), // Templated + .wide_out (got_wide_out[123:0]), // Templated + .did_init_out (got_did_init_out), // Templated + // Inputs + .clk (clk), + .bit_in (bit_in), + .vec_in (vec_in[30:0]), + .wide_in (wide_in[123:0]), + .is_ref (1'b0)); // Templated + + // Aggregate outputs into a single result vector + wire [63:0] result = {60'h0, + got_wide_out !== exp_wide_out, + got_vec_out !== exp_vec_out, + got_bit_out !== exp_bit_out, + got_did_init_out !== exp_did_init_out}; + + // Test loop + always @ (posedge clk) begin +`ifdef TEST_VERBOSE + $write("[%0t] cyc==%0d crc=%x result=%x gv=%x ev=%x\n",$time, cyc, crc, result, + got_vec_out, exp_vec_out); +`endif + cyc <= cyc + 1; + crc <= {crc[62:0], crc[63]^crc[2]^crc[0]}; + if (cyc==0) begin + // Setup + crc <= 64'h5aef0c8d_d70a4497; + end + else if (cyc<10) begin + end + else if (cyc<90) begin + if (result != 64'h0) begin + $display("Bit mismatch, result=%x\n", result); + $stop; + end + end + else if (cyc==99) begin + $write("[%0t] cyc==%0d crc=%x sum=%x\n",$time, cyc, crc, sum); + if (crc !== 64'hc77bb9b3784ea091) $stop; + //Child prints this: $write("*-* All Finished *-*\n"); + $finish; + end + end + +endmodule diff --git a/test_regress/t/t_embed1_c.cpp b/test_regress/t/t_embed1_c.cpp new file mode 100644 index 000000000..54261bb5c --- /dev/null +++ b/test_regress/t/t_embed1_c.cpp @@ -0,0 +1,123 @@ +// -*- C++ -*- +//************************************************************************* +// +// Copyright 2011-2011 by Wilson Snyder. This program is free software; you can +// redistribute it and/or modify it under the terms of either the GNU +// Lesser General Public License Version 3 or the Perl Artistic License. +// Version 2.0. +// +// Verilator is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +//************************************************************************* + +#include +#include "svdpi.h" + +#include "../t_embed1_child/Vt_embed1_child.h" + +//====================================================================== + +#if defined(VERILATOR) +# include "Vt_embed1__Dpi.h" +#elif defined(VCS) +# include "../vc_hdrs.h" +#elif defined(CADENCE) +# define NEED_EXTERNS +#else +# error "Unknown simulator for DPI test" +#endif + +#include "verilated.h" + +#ifdef NEED_EXTERNS +extern "C" { + + extern void t_embed_child_initial(); + extern void t_embed_child_final(); + extern void t_embed_child_eval(); + extern void t_embed_child_io_eval(); // TODO real function params here +} +#endif + +//====================================================================== + +extern int T_Embed_Child_Unique; +int T_Embed_Child_Unique = 0; // Address used for uniqueness + +Vt_embed1_child* __get_modelp() { + svScope scope = svGetScope(); + if (!scope) { + vl_fatal(__FILE__,__LINE__,__FILE__,"svGetScope failed"); + return NULL; + } + + void* __modelp = svGetUserData(scope, &T_Embed_Child_Unique); + if (!__modelp) { + // Create the model + const char* scopenamep = svGetNameFromScope(scope); + if (!scopenamep) vl_fatal(__FILE__,__LINE__,__FILE__,"svGetNameFromScope failed"); + __modelp = new Vt_embed1_child(scopenamep); + if (svPutUserData(scope, &T_Embed_Child_Unique, __modelp)) { + vl_fatal(__FILE__,__LINE__,__FILE__,"svPutUserData failed"); + } + } + return (Vt_embed1_child*)(__modelp); +} + +void t_embed_child_initial() { + VL_DEBUG_IF(VL_PRINTF(" t_embed1_child_initial\n"); ); + Vt_embed1_child* __modelp = __get_modelp(); + __modelp->eval(); +} + +void t_embed_child_final() { + VL_DEBUG_IF(VL_PRINTF(" t_embed1_child_final\n"); ); + Vt_embed1_child* __modelp = __get_modelp(); + __modelp->final(); +} + +void t_embed_child_eval() { + VL_DEBUG_IF(VL_PRINTF(" t_embed1_child_eval\n"); ); + Vt_embed1_child* __modelp = __get_modelp(); + __modelp->eval(); +} + +void t_embed_child_io_eval (unsigned char clk, + unsigned char bit_in, + const svBitVecVal* vec_in, + const svBitVecVal* wide_in, + unsigned char is_ref, + unsigned char* bit_out, + svBitVecVal* vec_out, + svBitVecVal* wide_out, + unsigned char* did_init_out) { + VL_DEBUG_IF(VL_PRINTF(" t_embed1_child_io_eval\n"); ); + Vt_embed1_child* __modelp = __get_modelp(); + VL_DEBUG_IF(VL_PRINTF("[%0ld] in clk=%x b=%x V=%x R=%x\n", + VL_TIME_Q(), clk, bit_in, vec_in[0], is_ref);); + __modelp->clk = clk; + __modelp->bit_in = bit_in; + __modelp->vec_in = vec_in[0]; + __modelp->wide_in[0] = wide_in[0]; + __modelp->wide_in[1] = wide_in[1]; + __modelp->wide_in[2] = wide_in[2]; + __modelp->wide_in[3] = wide_in[3]; + __modelp->is_ref = is_ref; + // + __modelp->eval(); + // TODO maybe we should look at a "change detect" to know if we need to copy + // out the variables; can return this value to the caller verilog code too + // + *bit_out = __modelp->bit_out; + vec_out[0] = __modelp->vec_out; + wide_out[0] = __modelp->wide_out[0]; + wide_out[1] = __modelp->wide_out[1]; + wide_out[2] = __modelp->wide_out[2]; + wide_out[3] = __modelp->wide_out[3]; + *did_init_out = __modelp->did_init_out; + VL_DEBUG_IF(VL_PRINTF("[%0ld] out b=%x V=%x DI=%x\n", + VL_TIME_Q(), *bit_out, *vec_out, *did_init_out);); +} diff --git a/test_regress/t/t_embed1_child.v b/test_regress/t/t_embed1_child.v new file mode 100644 index 000000000..b7b493b21 --- /dev/null +++ b/test_regress/t/t_embed1_child.v @@ -0,0 +1,45 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2011 by Wilson Snyder. + +module t_embed1_child (/*AUTOARG*/ + // Outputs + bit_out, vec_out, wide_out, did_init_out, + // Inputs + clk, bit_in, vec_in, wide_in, is_ref + ); + + input clk; + input bit_in; + output bit_out; + input [30:0] vec_in; + output [30:0] vec_out; + input [123:0] wide_in; + output [123:0] wide_out; + output did_init_out; + + input is_ref; + + reg did_init; initial did_init = 0; + initial begin + did_init = 1; + end + + reg did_final; initial did_final = 0; + final begin + did_final = 1; + if (!is_ref) $write("*-* All Finished *-*\n"); + //$finish is in parent + end + + // Note async use! + wire bit_out = bit_in; + wire did_init_out = did_init; + + always @ (posedge clk) begin + vec_out <= vec_in; + wide_out <= wide_in; + end + +endmodule diff --git a/test_regress/t/t_embed1_wrap.v b/test_regress/t/t_embed1_wrap.v new file mode 100644 index 000000000..9be795fa9 --- /dev/null +++ b/test_regress/t/t_embed1_wrap.v @@ -0,0 +1,90 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2011 by Wilson Snyder. + +module t_embed1_wrap (/*AUTOARG*/ + // Outputs + bit_out, vec_out, wide_out, did_init_out, + // Inputs + clk, bit_in, vec_in, wide_in, is_ref + ); + + /*AUTOINOUTMODULE("t_embed1_child")*/ + // Beginning of automatic in/out/inouts (from specific module) + output bit_out; + output [30:0] vec_out; + output [123:0] wide_out; + output did_init_out; + input clk; + input bit_in; + input [30:0] vec_in; + input [123:0] wide_in; + input is_ref; + // End of automatics + +`ifdef verilator + // Import $t_embed_child__initial etc as a DPI function +`endif + + //TODO would like __'s as in {PREFIX}__initial but presently illegal for users to do this + import "DPI-C" context function void t_embed_child_initial(); + import "DPI-C" context function void t_embed_child_final(); + import "DPI-C" context function void t_embed_child_eval(); + import "DPI-C" context function void t_embed_child_io_eval + ( + //TODO we support bit, but not logic + input bit clk, + input bit bit_in, + input bit [30:0] vec_in, + input bit [123:0] wide_in, + input bit is_ref, + output bit bit_out, + output bit [30:0] vec_out, + output bit [123:0] wide_out, + output bit did_init_out); + + initial begin + // Load all values + t_embed_child_initial(); + end + + // Only if system verilog, and if a "final" block in the code + final begin + t_embed_child_final(); + end + + bit _temp_bit_out; + bit _temp_did_init_out; + bit [30:0] _temp_vec_out; + bit [123:0] _temp_wide_out; + always @* begin + t_embed_child_io_eval( + clk, + bit_in, + vec_in, + wide_in, + is_ref, + _temp_bit_out, + _temp_vec_out, + _temp_wide_out, + _temp_did_init_out + ); + // TODO might eliminate these temporaries + bit_out = _temp_bit_out; + did_init_out = _temp_did_init_out; + end + + + // Send all variables every cycle, + // or have a sensitivity routine for each? + // How to make sure we call eval at end of variable changes? + // #0 (though not verilator compatible!) + + // TODO for now, we know what changes when + always @ (posedge clk) begin + vec_out <= _temp_vec_out; + wide_out <= _temp_wide_out; + end + +endmodule diff --git a/test_regress/t/t_for_break.v b/test_regress/t/t_for_break.v index d7bb3aa27..748be3015 100644 --- a/test_regress/t/t_for_break.v +++ b/test_regress/t/t_for_break.v @@ -92,8 +92,17 @@ module t (/*AUTOARG*/ input [3:0] loop_continue; integer i; - // Placeholder - return Test0(loop_stop,loop_break,loop_continue); + Test1 = 0; + begin : outer_block + for (i=1; i<20; i=i+1) begin : inner_block + Test1 = Test1 + 1; + // continue, IE jump to end-of-inner_block. Must be inside inner_block. + if (i[3:0] == loop_continue) disable inner_block; + // break, IE jump to end-of-outer_block. Must be inside outer_block. + if (i[3:0] == loop_break) disable outer_block; + Test1 = Test1 + i[15:0]; + end : inner_block + end : outer_block endfunction function [15:0] Test2; diff --git a/test_regress/t/t_mem_slice_conc_bad.pl b/test_regress/t/t_mem_slice_conc_bad.pl new file mode 100755 index 000000000..82b51da3d --- /dev/null +++ b/test_regress/t/t_mem_slice_conc_bad.pl @@ -0,0 +1,16 @@ +#!/usr/bin/perl +if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2003 by Wilson Snyder. This program is free software; you can +# redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. + +compile ( + v_flags2 => ["--lint-only"], + fails=>1, + ) if $Self->{v3}; + +ok(1); +1; diff --git a/test_regress/t/t_mem_slice_conc_bad.v b/test_regress/t/t_mem_slice_conc_bad.v new file mode 100644 index 000000000..180ed028d --- /dev/null +++ b/test_regress/t/t_mem_slice_conc_bad.v @@ -0,0 +1,118 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2011 by Wilson Snyder. +// +// bug354 + +typedef logic [5:0] data_t; + +module t (/*AUTOARG*/ + // Inputs + clk + ); + input clk; + + integer cyc=0; + reg [63:0] crc; + reg [63:0] sum; + + // Take CRC data and apply to testblock inputs + wire rst; + data_t iii_in = crc[5:0]; + data_t jjj_in = crc[11:6]; + data_t iii_out; + data_t jjj_out; + logic [1:0] ctl0 = crc[63:62]; + + aaa aaa (.*); + + // Aggregate outputs into a single result vector + wire [63:0] result = {64'h0}; + + // Test loop + always @ (posedge clk) begin +`ifdef TEST_VERBOSE + $write("[%0t] cyc==%0d crc=%x result=%x\n",$time, cyc, crc, result); +`endif + cyc <= cyc + 1; + crc <= {crc[62:0], crc[63]^crc[2]^crc[0]}; + sum <= result ^ {sum[62:0],sum[63]^sum[2]^sum[0]}; + if (cyc==0) begin + // Setup + crc <= 64'h5aef0c8d_d70a4497; + sum <= 64'h0; + rst <= 1'b0; + end + else if (cyc<10) begin + sum <= 64'h0; + rst <= 1'b1; + end + else if (cyc<90) begin + rst <= 1'b0; + end + else if (cyc==99) begin + $write("[%0t] cyc==%0d crc=%x sum=%x\n",$time, cyc, crc, sum); + if (crc !== 64'hc77bb9b3784ea091) $stop; + // What checksum will we end up with (above print should match) +`define EXPECTED_SUM 64'h4afe43fb79d7b71e + if (sum !== `EXPECTED_SUM) $stop; + $write("*-* All Finished *-*\n"); + $finish; + end + end + +endmodule + +module bbb + ( + output data_t ggg_out[1:0], + input data_t ggg_in [1:0], + input [1:0] [1:0] ctl, + + input logic clk, + input logic rst + ); + + genvar i; + + generate + for (i=0; i<2; i++) begin: PPP + always_ff @(posedge clk) begin + if (rst) begin + ggg_out[i] <= 6'b0; + end + else begin + if (ctl[i][0]) begin + if (ctl[i][1]) begin + ggg_out[i] <= ~ggg_in[i]; + end else begin + ggg_out[i] <= ggg_in[i]; + end + end + end + end + end + endgenerate + +endmodule + +module aaa + ( + input data_t iii_in, + input data_t jjj_in, + input [1:0] ctl0, + output data_t iii_out, + output data_t jjj_out, + input logic clk, + input logic rst + ); + + // Below is a bug; {} concat isn't used to make arrays + bbb bbb ( + .ggg_in ({jjj_in, iii_in}), + .ggg_out ({jjj_out, iii_out}), + .ctl ({{1'b1,ctl0[1]}, {1'b0,ctl0[0]}}), + .*); + +endmodule