From 4f98f84da96e065200f26fc7d5d8168ccca08035 Mon Sep 17 00:00:00 2001
From: Wilson Snyder <wsnyder@wsnyder.org>
Date: Fri, 14 Sep 2018 06:56:59 -0400
Subject: [PATCH] Fix duplicate symbol error on generate tri, bug1347.

---
 Changes                       |  2 ++
 src/Verilator.cpp             |  8 ++++----
 test_regress/t/t_gate_fdup.pl | 16 ++++++++++++++++
 test_regress/t/t_gate_fdup.v  | 32 ++++++++++++++++++++++++++++++++
 4 files changed, 54 insertions(+), 4 deletions(-)
 create mode 100755 test_regress/t/t_gate_fdup.pl
 create mode 100644 test_regress/t/t_gate_fdup.v

diff --git a/Changes b/Changes
index f112d1d1b..bdfad57f9 100644
--- a/Changes
+++ b/Changes
@@ -37,6 +37,8 @@ The contributors that suggested a given feature are shown in []. Thanks!
 
 ****  Fix string ?: conditional type resolution, bug1345. [Iztok Jeras]
 
+****  Fix duplicate symbol error on generate tri, bug1347. [Tomas Dzetkulic]
+
 
 * Verilator 3.926 2018-08-22
 
diff --git a/src/Verilator.cpp b/src/Verilator.cpp
index 248f94c81..ef71bc064 100644
--- a/src/Verilator.cpp
+++ b/src/Verilator.cpp
@@ -235,14 +235,14 @@ void process() {
     }
 
     if (!v3Global.opt.xmlOnly()) {
-	// Expand inouts, stage 2
-	// Also simplify pin connections to always be AssignWs in prep for V3Unknown
-	V3Tristate::tristateAll(v3Global.rootp());
-
 	// Task inlining & pushing BEGINs names to variables/cells
 	// Begin processing must be after Param, before module inlining
 	V3Begin::debeginAll(v3Global.rootp());	// Flatten cell names, before inliner
 
+        // Expand inouts, stage 2
+        // Also simplify pin connections to always be AssignWs in prep for V3Unknown
+        V3Tristate::tristateAll(v3Global.rootp());
+
 	// Move assignments from X into MODULE temps.
 	// (Before flattening, so each new X variable is shared between all scopes of that module.)
 	V3Unknown::unknownAll(v3Global.rootp());
diff --git a/test_regress/t/t_gate_fdup.pl b/test_regress/t/t_gate_fdup.pl
new file mode 100755
index 000000000..683765bd3
--- /dev/null
+++ b/test_regress/t/t_gate_fdup.pl
@@ -0,0 +1,16 @@
+#!/usr/bin/perl
+if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2004 by Wilson Snyder. This program is free software; you can
+# redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+
+scenarios(simulator => 1);
+
+compile(
+    );
+
+ok(1);
+1;
diff --git a/test_regress/t/t_gate_fdup.v b/test_regress/t/t_gate_fdup.v
new file mode 100644
index 000000000..eb1778815
--- /dev/null
+++ b/test_regress/t/t_gate_fdup.v
@@ -0,0 +1,32 @@
+// DESCRIPTION: Verilator: Verilog Test module
+//
+// This file ONLY is placed into the Public Domain, for any use,
+// without warranty, 2005 by Thomas Dzetkulic.
+
+module fnor2(f, a, b);
+   parameter W = 1;
+
+   output [W-1:0]f;
+   input [W-1:0] a, b;
+
+   supply0       gnd;
+   supply1       vcc;
+
+   generate
+      genvar     i;
+      for (i = 0; i < W; i = i + 1) begin
+         wire w;
+         pmos(f[i], w, a[i]);
+         pmos(w, vcc, b[i]);
+         nmos(f[i], gnd, a[i]);
+         nmos(f[i], gnd, b[i]);
+      end
+   endgenerate
+endmodule
+
+module t(f, a, b);
+   output [1:0] f;
+   input [1:0]  a, b;
+
+   fnor2 #(2) n(f, a, b);
+endmodule