diff --git a/src/V3LinkDot.cpp b/src/V3LinkDot.cpp
index d67934d68..1b39283f8 100644
--- a/src/V3LinkDot.cpp
+++ b/src/V3LinkDot.cpp
@@ -4471,6 +4471,12 @@ class LinkDotResolveVisitor final : public VNVisitor {
                 nodep->classOrPackagep(cpackagerefp->classOrPackageSkipp());
                 if (!VN_IS(nodep->classOrPackagep(), Class)
                     && !VN_IS(nodep->classOrPackagep(), Package)) {
+                    if (m_statep->forPrimary()) {
+                        // It may be a type that comes from parameter class that is not
+                        // instantioned yet
+                        iterate(cpackagep);
+                        return;
+                    }
                     // Likely impossible, as error thrown earlier
                     cpackagerefp->v3error(  // LCOV_EXCL_LINE
                         "'::' expected to reference a class/package but referenced '"
diff --git a/test_regress/t/t_typedef_param_class.py b/test_regress/t/t_typedef_param_class.py
new file mode 100755
index 000000000..f989a35fb
--- /dev/null
+++ b/test_regress/t/t_typedef_param_class.py
@@ -0,0 +1,18 @@
+#!/usr/bin/env python3
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2025 by Wilson Snyder. This program is free software; you
+# can redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
+
+import vltest_bootstrap
+
+test.scenarios('simulator')
+
+test.compile()
+
+test.execute()
+
+test.passes()
diff --git a/test_regress/t/t_typedef_param_class.v b/test_regress/t/t_typedef_param_class.v
new file mode 100644
index 000000000..7d6fc6ac6
--- /dev/null
+++ b/test_regress/t/t_typedef_param_class.v
@@ -0,0 +1,23 @@
+// DESCRIPTION: Verilator: Verilog Test module
+//
+// This file ONLY is placed under the Creative Commons Public Domain, for
+// any use, without warranty, 2025 by Antmicro.
+// SPDX-License-Identifier: CC0-1.0
+
+class Class1 #(type T);
+  typedef T::Some_type2 Some_type1;
+endclass
+
+class Class2;
+  typedef int Some_type2;
+endclass
+
+module t;
+  initial begin
+    int value0 = 7;
+    Class1#(Class2)::Some_type1 value1 = value0;
+    int value2 = value1;
+    $write("*-* All Finished *-*\n");
+    $finish;
+  end
+endmodule