From 4dde1ede0ec89789c3715955aca28970292cdacd Mon Sep 17 00:00:00 2001 From: Wilson Snyder Date: Thu, 16 Jul 2009 09:19:15 -0400 Subject: [PATCH] Support SystemVerilog "logic", bug101. --- Changes | 4 ++ bin/verilator | 4 +- src/verilog.l | 2 +- src/verilog.y | 2 + test_regress/t/t_var_logic.pl | 18 ++++++++ test_regress/t/t_var_logic.v | 83 +++++++++++++++++++++++++++++++++++ 6 files changed, 110 insertions(+), 3 deletions(-) create mode 100755 test_regress/t/t_var_logic.pl create mode 100644 test_regress/t/t_var_logic.v diff --git a/Changes b/Changes index 9fb2ef658..83bd65f2b 100644 --- a/Changes +++ b/Changes @@ -3,6 +3,10 @@ Revision history for Verilator The contributors that suggested a given feature are shown in []. [by ...] indicates the contributor was also the author of the fix; Thanks! +* Verilator 3.71*** + +*** Support SystemVerilog "logic", bug101. [by Alex Duller] + * Verilator 3.712 2009/07/14 ** Patching SystemC is no longer required to trace sc_bvs. diff --git a/bin/verilator b/bin/verilator index d36925d2f..1abb57bad 100755 --- a/bin/verilator +++ b/bin/verilator @@ -1144,8 +1144,8 @@ including function call-like preprocessor defines. Verilator supports ==? and !=? operators, $bits, $countones, $error, $fatal, $info, $isunknown, $onehot, $onehot0, $warning, always_comb, -always_ff, always_latch, do-while, final, priority case/if, and unique -case/if. +always_ff, always_latch, do-while, final, logic, priority case/if, and +unique case/if. It also supports .name and .* interconnection. diff --git a/src/verilog.l b/src/verilog.l index 99f1f218a..1b4e1622d 100644 --- a/src/verilog.l +++ b/src/verilog.l @@ -358,6 +358,7 @@ escid \\[^ \t\f\r\n]+ "endproperty" { FL; return yENDPROPERTY; } "final" { FL; return yFINAL; } "iff" { FL; return yIFF; } + "logic" { FL; return yLOGIC; } "priority" { FL; return yPRIORITY; } "static" { FL; return ySTATIC; } "timeprecision" { FL; return yTIMEPRECISION; } @@ -407,7 +408,6 @@ escid \\[^ \t\f\r\n]+ "join_any" { yyerrorf("Unsupported: SystemVerilog 2005 reserved word not implemented: %s",yytext); } "join_none" { yyerrorf("Unsupported: SystemVerilog 2005 reserved word not implemented: %s",yytext); } "local" { yyerrorf("Unsupported: SystemVerilog 2005 reserved word not implemented: %s",yytext); } - "logic" { yyerrorf("Unsupported: SystemVerilog 2005 reserved word not implemented: %s",yytext); } "longint" { yyerrorf("Unsupported: SystemVerilog 2005 reserved word not implemented: %s",yytext); } "matches" { yyerrorf("Unsupported: SystemVerilog 2005 reserved word not implemented: %s",yytext); } "modport" { yyerrorf("Unsupported: SystemVerilog 2005 reserved word not implemented: %s",yytext); } diff --git a/src/verilog.y b/src/verilog.y index cc00421e3..cfc60bb37 100644 --- a/src/verilog.y +++ b/src/verilog.y @@ -246,6 +246,7 @@ class AstSenTree; %token yGENVAR "genvar" %token yIF "if" %token yIFF "iff" +%token yLOGIC "logic" %token yINITIAL "initial" %token yINOUT "inout" %token yINPUT "input" @@ -823,6 +824,7 @@ data_type: // ==IEEE: data_type data_typeNoRef: // ==IEEE: data_type, excluding class_type etc references yINTEGER { VARDECL(INTEGER); $$ = new AstRange($1,31,0); $$->isSigned(true); } | yREG signingE rangeListE { VARDECL(REG); $$ = $3; } + | yLOGIC signingE rangeListE { VARDECL(REG); $$ = $3; } //UNSUP: above instead of integer_type // //UNSUP integer_type signingE regArRangeE { UNSUP } diff --git a/test_regress/t/t_var_logic.pl b/test_regress/t/t_var_logic.pl new file mode 100755 index 000000000..7058e622f --- /dev/null +++ b/test_regress/t/t_var_logic.pl @@ -0,0 +1,18 @@ +#!/usr/bin/perl +if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2003 by Wilson Snyder. This program is free software; you can +# redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. + +compile ( + ); + +execute ( + check_finished=>1, + ); + +ok(1); +1; diff --git a/test_regress/t/t_var_logic.v b/test_regress/t/t_var_logic.v new file mode 100644 index 000000000..9405dccd2 --- /dev/null +++ b/test_regress/t/t_var_logic.v @@ -0,0 +1,83 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2009 by Wilson Snyder. + +module t (/*AUTOARG*/ + // Inputs + clk + ); + input clk; + + + integer cyc=0; + // Test that we can actually use the logic keyword without an error popping up + //reg [63:0] crc; + logic [63:0] crc; + reg [63:0] sum; + + + // Take CRC data and apply to testblock inputs + wire [31:0] in = crc[31:0]; + + /*AUTOWIRE*/ + // Beginning of automatic wires (for undeclared instantiated-module outputs) + wire [31:0] out; // From test of Test.v + // End of automatics + + Test test (/*AUTOINST*/ + // Outputs + .out (out[31:0]), + // Inputs + .clk (clk), + .in (in[31:0])); + + // Aggregate outputs into a single result vector + wire [63:0] result = {32'h0, out}; + + // Test loop + always @ (posedge clk) begin +`ifdef TEST_VERBOSE + $write("[%0t] cyc==%0d crc=%x result=%x\n",$time, cyc, crc, result); +`endif + cyc <= cyc + 1; + crc <= {crc[62:0], crc[63]^crc[2]^crc[0]}; + sum <= result ^ {sum[62:0],sum[63]^sum[2]^sum[0]}; + if (cyc==0) begin + // Setup + crc <= 64'h5aef0c8d_d70a4497; + sum <= 64'h0; + end + else if (cyc<10) begin + sum <= 64'h0; + end + else if (cyc<90) begin + end + else if (cyc==99) begin + $write("[%0t] cyc==%0d crc=%x sum=%x\n",$time, cyc, crc, sum); + if (crc !== 64'hc77bb9b3784ea091) $stop; + // What checksum will we end up with (above print should match) +`define EXPECTED_SUM 64'h4afe43fb79d7b71e + if (sum !== `EXPECTED_SUM) $stop; + $write("*-* All Finished *-*\n"); + $finish; + end + end + +endmodule + +module Test (/*AUTOARG*/ + // Outputs + out, + // Inputs + clk, in + ); + + input clk; + input [31:0] in; + output reg [31:0] out; + + always @(posedge clk) begin + out <= in; + end +endmodule