diff --git a/src/verilog.y b/src/verilog.y index 54475e915..d68171115 100644 --- a/src/verilog.y +++ b/src/verilog.y @@ -5541,8 +5541,8 @@ gateDecl: | yNOR driveStrengthE delay_controlE gateNorList ';' { $$ = $4; STRENGTH_LIST($4, $2, AssignW); DELAY_LIST($3, $4); } | yXOR driveStrengthE delay_controlE gateXorList ';' { $$ = $4; STRENGTH_LIST($4, $2, AssignW); DELAY_LIST($3, $4); } | yXNOR driveStrengthE delay_controlE gateXnorList ';' { $$ = $4; STRENGTH_LIST($4, $2, AssignW); DELAY_LIST($3, $4); } - | yPULLUP delay_controlE gatePullupList ';' { $$ = $3; DELAY_LIST($2, $3); } - | yPULLDOWN delay_controlE gatePulldownList ';' { $$ = $3; DELAY_LIST($2, $3); } + | yPULLDOWN pulldown_strengthE delay_controlE gatePulldownList ';' { $$ = $4; DELAY_LIST($3, $4); } + | yPULLUP pullup_strengthE delay_controlE gatePullupList ';' { $$ = $4; DELAY_LIST($3, $4); } | yNMOS delay_controlE gateBufif1List ';' { $$ = $3; DELAY_LIST($2, $3); } | yPMOS delay_controlE gateBufif0List ';' { $$ = $3; DELAY_LIST($2, $3); } // @@ -5759,7 +5759,6 @@ driveStrengthE: | driveStrength { $$ = $1; } ; - driveStrength: yP_PAR__STRENGTH strength0 ',' strength1 ')' { $$ = new AstStrengthSpec{$1, $2, $4}; } | yP_PAR__STRENGTH strength1 ',' strength0 ')' { $$ = new AstStrengthSpec{$1, $4, $2}; } @@ -5769,6 +5768,28 @@ driveStrength: | yP_PAR__STRENGTH yHIGHZ1 ',' strength0 ')' { BBUNSUP($2, "Unsupported: highz strength"); } ; +pulldown_strengthE: // IEEE: [ pulldown_strength ] + /* empty */ { $$ = nullptr; } + | pulldown_strength { $$ = $1; } + ; + +pulldown_strength: // IEEE: pulldown_strength + yP_PAR__STRENGTH strength0 ',' strength1 ')' { BBUNSUP($2, "Unsupported: pulldown strength"); } + | yP_PAR__STRENGTH strength1 ',' strength0 ')' { BBUNSUP($2, "Unsupported: pulldown strength"); } + | yP_PAR__STRENGTH strength0 ')' { BBUNSUP($2, "Unsupported: pulldown strength"); } + ; + +pullup_strengthE: // IEEE: [ pullup_strength ] + /* empty */ { $$ = nullptr; } + | pullup_strength { $$ = $1; } + ; + +pullup_strength: // IEEE: pullup_strength + yP_PAR__STRENGTH strength0 ',' strength1 ')' { BBUNSUP($2, "Unsupported: pullup strength"); } + | yP_PAR__STRENGTH strength1 ',' strength0 ')' { BBUNSUP($2, "Unsupported: pullup strength"); } + | yP_PAR__STRENGTH strength1 ')' { BBUNSUP($2, "Unsupported: pullup strength"); } + ; + //************************************************ // Tables diff --git a/test_regress/t/t_tri_pull_unsup.out b/test_regress/t/t_tri_pull_unsup.out new file mode 100644 index 000000000..1ac22dac5 --- /dev/null +++ b/test_regress/t/t_tri_pull_unsup.out @@ -0,0 +1,38 @@ +%Error-UNSUPPORTED: t/t_tri_pull_unsup.v:15:11: Unsupported: pullup strength + 15 | pullup (supply1) pu1(a); + | ^~~~~~~ + ... For error description see https://verilator.org/warn/UNSUPPORTED?v=latest +%Error-UNSUPPORTED: t/t_tri_pull_unsup.v:16:11: Unsupported: pullup strength + 16 | pullup (strong1) pu2(a); + | ^~~~~~~ +%Error-UNSUPPORTED: t/t_tri_pull_unsup.v:17:11: Unsupported: pullup strength + 17 | pullup (pull1) pu3(a); + | ^~~~~ +%Error-UNSUPPORTED: t/t_tri_pull_unsup.v:18:11: Unsupported: pullup strength + 18 | pullup (weak1) pu4(a); + | ^~~~~ +%Error-UNSUPPORTED: t/t_tri_pull_unsup.v:19:11: Unsupported: pullup strength + 19 | pullup (supply1, supply0) pu5(a); + | ^~~~~~~ +%Error-UNSUPPORTED: t/t_tri_pull_unsup.v:20:11: Unsupported: pullup strength + 20 | pullup (strong0, strong1) pu6(a); + | ^~~~~~~ +%Error-UNSUPPORTED: t/t_tri_pull_unsup.v:29:13: Unsupported: pulldown strength + 29 | pulldown (supply0) pd1(a); + | ^~~~~~~ +%Error-UNSUPPORTED: t/t_tri_pull_unsup.v:30:13: Unsupported: pulldown strength + 30 | pulldown (strong0) pd2(a); + | ^~~~~~~ +%Error-UNSUPPORTED: t/t_tri_pull_unsup.v:31:13: Unsupported: pulldown strength + 31 | pulldown (pull0) pd3(a); + | ^~~~~ +%Error-UNSUPPORTED: t/t_tri_pull_unsup.v:32:13: Unsupported: pulldown strength + 32 | pulldown (weak0) pd4(a); + | ^~~~~ +%Error-UNSUPPORTED: t/t_tri_pull_unsup.v:33:13: Unsupported: pulldown strength + 33 | pulldown (supply0, supply1) pd5(a); + | ^~~~~~~ +%Error-UNSUPPORTED: t/t_tri_pull_unsup.v:34:13: Unsupported: pulldown strength + 34 | pulldown (strong1, strong0) pd6(a); + | ^~~~~~~ +%Error: Exiting due to diff --git a/test_regress/t/t_tri_pull_unsup.py b/test_regress/t/t_tri_pull_unsup.py new file mode 100755 index 000000000..6585af685 --- /dev/null +++ b/test_regress/t/t_tri_pull_unsup.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +test.lint(fails=test.vlt_all, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_tri_pull_unsup.v b/test_regress/t/t_tri_pull_unsup.v new file mode 100644 index 000000000..b20379429 --- /dev/null +++ b/test_regress/t/t_tri_pull_unsup.v @@ -0,0 +1,36 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2025 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 + +module t; + wire u1; + wire u2; + wire u3; + wire u4; + wire u5; + wire u6; + + pullup (supply1) pu1(a); + pullup (strong1) pu2(a); + pullup (pull1) pu3(a); + pullup (weak1) pu4(a); + pullup (supply1, supply0) pu5(a); + pullup (strong0, strong1) pu6(a); + + wire d1; + wire d2; + wire d3; + wire d4; + wire d5; + wire d6; + + pulldown (supply0) pd1(a); + pulldown (strong0) pd2(a); + pulldown (pull0) pd3(a); + pulldown (weak0) pd4(a); + pulldown (supply0, supply1) pd5(a); + pulldown (strong1, strong0) pd6(a); + +endmodule