From 4beaa451994d555c761dbc6cd9cffccb930f54c4 Mon Sep 17 00:00:00 2001 From: Wilson Snyder Date: Tue, 20 Jan 2009 07:24:57 -0500 Subject: [PATCH] Clock_enable is past experimental; bug50. --- bin/verilator | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/bin/verilator b/bin/verilator index fe012d5e9..a0fe43535 100755 --- a/bin/verilator +++ b/bin/verilator @@ -1249,11 +1249,11 @@ The Verilog code returns to the last language mode specified with =item /*verilator clock_enable*/ -Experimental use only. Used after a signal declaration to indicate the -signal is used to gate a clock, and the user takes responsibility for -insuring there are no races related to it. (Typically by adding a latch, -and running static timing analysis.) This will cause the clock gate to be -ignored in the scheduling algorithm, improving performance. +Used after a signal declaration to indicate the signal is used to gate a +clock, and the user takes responsibility for insuring there are no races +related to it. (Typically by adding a latch, and running static timing +analysis.) This will cause the clock gate to be ignored in the scheduling +algorithm, improving performance. =item /*verilator coverage_block_off*/