diff --git a/src/verilog.y b/src/verilog.y
index 250bd3c2a..90bae4f9d 100644
--- a/src/verilog.y
+++ b/src/verilog.y
@@ -1548,7 +1548,7 @@ rangeList<rangep>:		// IEEE: {packed_dimension}
 
 wirerangeE<dtypep>:
 		/* empty */    		               	{ $$ = new AstBasicDType(CRELINE(), LOGIC); }  // not implicit
-	|	anyrange 				{ $$ = GRAMMARP->addRange(new AstBasicDType(CRELINE(), LOGIC),$1); }  // not implicit
+	|	rangeList 				{ $$ = GRAMMARP->addRange(new AstBasicDType(CRELINE(), LOGIC),$1); }  // not implicit
 	//			// Verilator doesn't support 2D wiring yet
 	//UNSUP	rangeListE				{ $$ = $1; }
 	;
diff --git a/test_regress/t/t_mem_packed.v b/test_regress/t/t_mem_packed.v
index 2eb71815d..75ad5f031 100644
--- a/test_regress/t/t_mem_packed.v
+++ b/test_regress/t/t_mem_packed.v
@@ -13,10 +13,13 @@ module t (/*AUTOARG*/
    integer cyc; initial cyc = 0;
 `ifdef iverilog
    reg [7:0] arr [3:0];
+   wire [7:0] arr_w [3:0];
 `else
    reg [3:0] [7:0] arr;
+   wire [3:0] [7:0] arr_w;
 `endif
    reg [7:0] sum;
+   reg [7:0] sum_w;
    integer    i0;
 
    initial begin
@@ -25,18 +28,23 @@ module t (/*AUTOARG*/
       end
    end
 
+   assign arr_w = arr;
+
    always @ (posedge clk) begin
       cyc <= cyc + 1;
       if (cyc==0) begin
 	 // Setup
 	 sum <= 0;
+	 sum_w <= 0;
       end
       else if (cyc >= 10 && cyc < 14) begin
 	 sum <= sum + {4'b0,arr[cyc-10]};
+	 sum_w <= sum_w + {4'b0,arr_w[cyc-10]};
       end
       else if (cyc==99) begin
 	 $write("[%0t] cyc==%0d sum=%x\n",$time, cyc, sum);
 	 if (sum != 8'h0f) $stop;
+	 if (sum != sum_w) $stop;
 	 $write("*-* All Finished *-*\n");
 	 $finish;
       end