From 49fe12963405453629e0f782203876fd73860b1b Mon Sep 17 00:00:00 2001 From: Wilson Snyder Date: Wed, 18 Jun 2025 08:56:32 -0400 Subject: [PATCH] Fix `--lib-create` with double-underscore (#6099). --- Changes | 1 + src/V3ProtectLib.cpp | 22 +++++++++++++--------- test_regress/t/t_lib_prot_comb.v | 12 ++++++------ 3 files changed, 20 insertions(+), 15 deletions(-) diff --git a/Changes b/Changes index 8f7eb7d17..b377e110b 100644 --- a/Changes +++ b/Changes @@ -67,6 +67,7 @@ Verilator 5.037 devel * Fix unpacked to packed parameter assignment (#6081) (#6088). [Todd Strader] * Fix casting reals to large integrals (#6085). [Todd Strader] * Fix nested hier blocks workers error (#6087). [Bartłomiej Chmiel, Antmicro Ltd.] +* Fix `--lib-create` with double-underscore (#6099). Verilator 5.036 2025-04-27 diff --git a/src/V3ProtectLib.cpp b/src/V3ProtectLib.cpp index aec3c1bd4..663c0faaa 100644 --- a/src/V3ProtectLib.cpp +++ b/src/V3ProtectLib.cpp @@ -459,8 +459,9 @@ class ProtectVisitor final : public VNVisitor { handleInput(varp); m_seqPortsp->addNodesp(varp->cloneTree(false)); if (m_hasClk) { - m_seqParamsp->addText(fl, varp->name() + "\n"); - m_clkSensp->addText(fl, "posedge " + varp->name() + " or negedge " + varp->name()); + m_seqParamsp->addText(fl, varp->prettyName() + "\n"); + m_clkSensp->addText(fl, "posedge " + varp->prettyName() + " or negedge " + + varp->prettyName()); } m_cSeqParamsp->addText(fl, varp->dpiArgType(true, false) + "\n"); m_cSeqClksp->addText(fl, cInputConnection(varp)); @@ -470,9 +471,9 @@ class ProtectVisitor final : public VNVisitor { FileLine* const fl = varp->fileline(); handleInput(varp); m_comboPortsp->addNodesp(varp->cloneTree(false)); - m_comboParamsp->addText(fl, varp->name() + "\n"); + m_comboParamsp->addText(fl, varp->prettyName() + "\n"); m_comboIgnorePortsp->addNodesp(varp->cloneTree(false)); - if (m_hasClk) m_comboIgnoreParamsp->addText(fl, varp->name() + "\n"); + if (m_hasClk) m_comboIgnoreParamsp->addText(fl, varp->prettyName() + "\n"); m_cComboParamsp->addText(fl, varp->dpiArgType(true, false) + "\n"); m_cComboInsp->addText(fl, cInputConnection(varp)); m_cIgnoreParamsp->addText(fl, varp->dpiArgType(true, false) + "\n"); @@ -490,10 +491,10 @@ class ProtectVisitor final : public VNVisitor { FileLine* const fl = varp->fileline(); m_modPortsp->addNodesp(varp->cloneTree(false)); m_comboPortsp->addNodesp(varp->cloneTree(false)); - m_comboParamsp->addText(fl, varp->name() + "_combo__V\n"); + m_comboParamsp->addText(fl, varp->prettyName() + "_combo__V\n"); if (m_hasClk) { m_seqPortsp->addNodesp(varp->cloneTree(false)); - m_seqParamsp->addText(fl, varp->name() + "_tmp__V\n"); + m_seqParamsp->addText(fl, varp->prettyName() + "_tmp__V\n"); } addLocalVariable(m_comboDeclsp, varp, "_combo__V"); @@ -502,10 +503,13 @@ class ProtectVisitor final : public VNVisitor { addLocalVariable(m_seqDeclsp, varp, "_seq__V"); addLocalVariable(m_tmpDeclsp, varp, "_tmp__V"); - m_nbAssignsp->addText(fl, varp->name() + "_seq__V <= " + varp->name() + "_tmp__V;\n"); - m_seqAssignsp->addText(fl, varp->name() + " = " + varp->name() + "_seq__V;\n"); + m_nbAssignsp->addText(fl, varp->prettyName() + "_seq__V <= " + varp->prettyName() + + "_tmp__V;\n"); + m_seqAssignsp->addText(fl, + varp->prettyName() + " = " + varp->prettyName() + "_seq__V;\n"); } - m_comboAssignsp->addText(fl, varp->name() + " = " + varp->name() + "_combo__V;\n"); + m_comboAssignsp->addText(fl, + varp->prettyName() + " = " + varp->prettyName() + "_combo__V;\n"); m_cComboParamsp->addText(fl, varp->dpiArgType(true, false) + "\n"); m_cComboOutsp->addText(fl, V3Task::assignInternalToDpi(varp, true, "", "", "handlep__V->")); diff --git a/test_regress/t/t_lib_prot_comb.v b/test_regress/t/t_lib_prot_comb.v index 9b8e9e96d..b4716efa0 100644 --- a/test_regress/t/t_lib_prot_comb.v +++ b/test_regress/t/t_lib_prot_comb.v @@ -4,8 +4,8 @@ // SPDX-License-Identifier: CC0-1.0 `ifdef PROCESS_TOP -`define CHECK if (out0 != (in0 ^ in1) || out1 != (in0 | in1) || out2 != (in0 & in1)) begin \ - $display("Mismatch in0:%b in1:%b out0:%b out1:%b out2:%b", in0, in1, out0, out1, out2); \ +`define CHECK if (out0 != (in0 ^ in1) || out1 != (in0 | in1) || out2__under != (in0 & in1)) begin \ + $display("Mismatch in0:%b in1:%b out0:%b out1:%b out2:%b", in0, in1, out0, out1, out2__under); \ $stop; \ end @@ -17,10 +17,10 @@ module t (/*AUTOARG*/ logic in0, in1; - logic out0, out1, out2; + logic out0, out1, out2__under; logic [31:0] count = 0; // actually XOR and OR and AND - secret i_secret(.in0(in0), .in1(in1), .out0(out0), .out1(out1), .out2(out2)); + secret i_secret(.in0(in0), .in1(in1), .out0(out0), .out1(out1), .out2__under(out2__under)); always @(posedge clk) begin count <= count + 32'd1; @@ -48,9 +48,9 @@ module t (/*AUTOARG*/ endmodule `else -module secret(input in0, input in1, output out0, output out1, output out2); +module secret(input in0, input in1, output out0, output out1, output out2__under); assign out0 = in0 ^ in1; assign out1 = in0 | in1; - assign out2 = in0 & in1; + assign out2__under = in0 & in1; endmodule `endif