diff --git a/Changes b/Changes
index 0a8c09d3c..7b684f71b 100644
--- a/Changes
+++ b/Changes
@@ -13,7 +13,9 @@ Verilator 5.045 devel
 
 **Other:**
 
+* Add IEEE 4-state type lint checks (#3645 partial) (#6895). [Jose Drowne]
 * Add VERILATOR_NUMA_STRATEGY environment variable (#6826) (#6880). [Yangyu Chen]
+* Add parsing of solve-before inside foreach (#6934). [Pawel Kojma, Antmicro Ltd.]
 * Support vpi_put/vpi_get forcing of signals (#5933) (#6704). [Christian Hecken]
 * Support detailed failure info for constraint violations (#6617) (#6883). [Yilou Wang]
 * Support `unique` constraints (on 1D static arrays) (#6810) (#6878). [Srinivasan Venkataramanan]
diff --git a/README.rst b/README.rst
index 2dac2e8bb..7c7274f62 100644
--- a/README.rst
+++ b/README.rst
@@ -60,17 +60,20 @@ performing lint checks, and optionally inserting assertion checks and
 coverage-analysis points. It outputs single- or multithreaded .cpp and .h
 files, the "Verilated" code.
 
-These Verilated C++/SystemC files are then compiled by a C++ compiler
-(gcc/clang/MSVC++), optionally along with a user's own C++/SystemC wrapper
-file, to instantiate the Verilated model. Executing the resulting
-executable performs the design simulation. Verilator also supports linking
-Verilated generated libraries, optionally encrypted, into other simulators.
+Verilator can automatically generate a simulator executable (using
+``--binary``), or users can write their own C++/SystemC wrapper to
+instantiate the model. The resulting Verilated executable performs the
+design simulation. Verilator also supports linking Verilator-generated
+libraries, optionally encrypted, into other simulators.
 
-Verilator may not be the best choice if you are expecting a full-featured
-replacement for a closed-source Verilog simulator, need SDF annotation, or
-mixed-signal simulation. However, if you are looking for a path to migrate
-SystemVerilog to C++/SystemC, or want high-speed simulation of designs,
-Verilator is the tool for you.
+Verilator supports all design constructs, most verification constructs,
+intra-assignment delays (e.g, `#10`), and events. Tristate-bus (`z`) and
+unknowns (`x`) are handled in limited contexts, in a special manor for
+performance. It currently may not be the best choice if you are expecting a
+full-featured replacement for a closed-source Verilog simulator, performing
+SDF annotation, or mixed-signal simulation. However, if you are looking for
+a path to migrate SystemVerilog to C++/SystemC, or want high-speed
+simulation, Verilator is the tool for you.
 
 
 Performance
@@ -131,6 +134,10 @@ organizations; please see `Verilator Commercial Support
 Related Projects
 ================
 
+- `Cocotb <https://www.cocotb.org/>`_ - A coroutine-based cosimulation
+  library for writing testbenches in Python which officially supports
+  Verilator.
+
 - `GTKwave <https://gtkwave.sourceforge.net/>`_ - Waveform viewer for
   Verilator traces.