From 4781a6046aa7417132ade1e4da34e07a5b22d114 Mon Sep 17 00:00:00 2001 From: Wilson Snyder Date: Mon, 2 Dec 2024 07:35:44 -0500 Subject: [PATCH] Update error as misnamed port dtype might be interface --- src/V3LinkDot.cpp | 2 +- src/verilog.y | 2 +- test_regress/t/t_typedef_no_bad.out | 2 +- 3 files changed, 3 insertions(+), 3 deletions(-) diff --git a/src/V3LinkDot.cpp b/src/V3LinkDot.cpp index bde24b439..0cbc5bc79 100644 --- a/src/V3LinkDot.cpp +++ b/src/V3LinkDot.cpp @@ -4137,7 +4137,7 @@ class LinkDotResolveVisitor final : public VNVisitor { if (foundp) { nodep->v3error("Expecting a data type: " << nodep->prettyNameQ()); } else { - nodep->v3error("Can't find typedef: " << nodep->prettyNameQ()); + nodep->v3error("Can't find typedef/interface: " << nodep->prettyNameQ()); } } } diff --git a/src/verilog.y b/src/verilog.y index 9afdbfbdc..0b761d24d 100644 --- a/src/verilog.y +++ b/src/verilog.y @@ -1520,7 +1520,7 @@ port: // ==IEEE: port // // IEEE: interface_port_header port_identifier { unpacked_dimension } // // Expanded interface_port_header // // We use instantCb here because the non-port form looks just like a module instantiation - portDirNetE id/*interface*/ portSig variable_dimensionListE sigAttrListE + portDirNetE id/*interface*/ portSig variable_dimensionListE sigAttrListE { // VAR for now, but V3LinkCells may call setIfcaeRef on it later $$ = $3; VARDECL(VAR); VARIO(NONE); AstNodeDType* const dtp = new AstIfaceRefDType{$2, "", *$2}; diff --git a/test_regress/t/t_typedef_no_bad.out b/test_regress/t/t_typedef_no_bad.out index 1d17e5fc6..e1e4ceaf8 100644 --- a/test_regress/t/t_typedef_no_bad.out +++ b/test_regress/t/t_typedef_no_bad.out @@ -1,4 +1,4 @@ -%Error: t/t_typedef_no_bad.v:10:4: Can't find typedef: 'sometype' +%Error: t/t_typedef_no_bad.v:10:4: Can't find typedef/interface: 'sometype' 10 | sometype p; | ^~~~~~~~ %Error: Exiting due to