From e744c21f562be333f31642b42e2604a9ce600719 Mon Sep 17 00:00:00 2001 From: Wilson Snyder Date: Sat, 12 Mar 2022 13:17:48 -0500 Subject: [PATCH 01/44] devel release --- Changes | 7 +++++++ configure.ac | 2 +- 2 files changed, 8 insertions(+), 1 deletion(-) diff --git a/Changes b/Changes index b817abc5a..ed0c9f570 100644 --- a/Changes +++ b/Changes @@ -8,6 +8,13 @@ The changes in each Verilator version are described below. The contributors that suggested a given feature are shown in []. Thanks! +Verilator 4.221 devel +========================== + +**Minor:** + + + Verilator 4.220 2022-03-12 ========================== diff --git a/configure.ac b/configure.ac index 22e745ffd..0be207f17 100644 --- a/configure.ac +++ b/configure.ac @@ -7,7 +7,7 @@ #AC_INIT([Verilator],[#.### YYYY-MM-DD]) #AC_INIT([Verilator],[#.### devel]) -AC_INIT([Verilator],[4.220 2022-03-12], +AC_INIT([Verilator],[4.221 devel], [https://verilator.org], [verilator],[https://verilator.org]) # When releasing, also update header of Changes file From 47226236f42f73b39d21dc9e22d91b3a59c106ca Mon Sep 17 00:00:00 2001 From: Yutetsu TAKATSUKASA Date: Sun, 13 Mar 2022 18:13:51 +0900 Subject: [PATCH 02/44] Internals: Resolve potential SEGV risk (#3350) --- src/V3AssertPre.cpp | 14 ++++++-------- 1 file changed, 6 insertions(+), 8 deletions(-) diff --git a/src/V3AssertPre.cpp b/src/V3AssertPre.cpp index e091b9855..a0ed59aee 100644 --- a/src/V3AssertPre.cpp +++ b/src/V3AssertPre.cpp @@ -167,16 +167,14 @@ private: nodep->v3warn(E_UNSUPPORTED, "Unsupported: Only one PSL clock allowed per assertion"); // Block is the new expression to evaluate AstNode* blockp = nodep->propp()->unlinkFrBack(); - if (nodep->disablep()) { - m_disablep = nodep->disablep()->cloneTree(false); + if (AstNode* const disablep = nodep->disablep()) { + m_disablep = disablep->cloneTree(false); if (VN_IS(nodep->backp(), Cover)) { - blockp = new AstAnd( - nodep->disablep()->fileline(), - new AstNot(nodep->disablep()->fileline(), nodep->disablep()->unlinkFrBack()), - blockp); + blockp = new AstAnd(disablep->fileline(), + new AstNot(disablep->fileline(), disablep->unlinkFrBack()), + blockp); } else { - blockp = new AstOr(nodep->disablep()->fileline(), - nodep->disablep()->unlinkFrBack(), blockp); + blockp = new AstOr(disablep->fileline(), disablep->unlinkFrBack(), blockp); } } // Unlink and just keep a pointer to it, convert to sentree as needed From c61258c0d0e5cee7be742d1255e05f80bded4eae Mon Sep 17 00:00:00 2001 From: Wilson Snyder Date: Mon, 14 Mar 2022 09:10:03 -0400 Subject: [PATCH 03/44] Commentary (#3351) --- docs/guide/connecting.rst | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/docs/guide/connecting.rst b/docs/guide/connecting.rst index 49fdc4f79..119fa850e 100644 --- a/docs/guide/connecting.rst +++ b/docs/guide/connecting.rst @@ -257,7 +257,9 @@ with respect to that top level module, then the scope could be set with #include "svdpi.h" ... - svSetScope(svGetScopeFromName("TOP.dut")); + const svScope scope = svGetScopeFromName("TOP.dut"); + assert(scope); // Check for nullptr if scope not found + svSetScope(scope); (Remember that Verilator adds a "TOP" to the top of the module hierarchy.) From 14d24213a8b73fe2c22ce623f447762c95837e0e Mon Sep 17 00:00:00 2001 From: Xi Zhang Date: Thu, 17 Mar 2022 21:04:47 +0800 Subject: [PATCH 04/44] Support LoongArch ISA multithreading (#3353) (#3354) --- docs/CONTRIBUTORS | 1 + include/verilatedos.h | 3 +++ 2 files changed, 4 insertions(+) diff --git a/docs/CONTRIBUTORS b/docs/CONTRIBUTORS index 90de66590..7906a039f 100644 --- a/docs/CONTRIBUTORS +++ b/docs/CONTRIBUTORS @@ -111,6 +111,7 @@ Vassilis Papaefstathiou Veripool API Bot Victor Besyakov Wilson Snyder +Xi Zhang Yossi Nivin Yuri Victorovich Yutetsu TAKATSUKASA diff --git a/include/verilatedos.h b/include/verilatedos.h index af7742388..b20f1419f 100644 --- a/include/verilatedos.h +++ b/include/verilatedos.h @@ -475,6 +475,9 @@ using ssize_t = uint32_t; ///< signed size_t; returned from read() # define VL_CPU_RELAX() asm volatile("yield" ::: "memory") # elif defined(__powerpc64__) # define VL_CPU_RELAX() asm volatile("or 1, 1, 1; or 2, 2, 2;" ::: "memory") +# elif defined(__loongarch__) +// LoongArch does not currently have a yield/pause instruction +# define VL_CPU_RELAX() asm volatile("nop" ::: "memory") # else # error "Missing VL_CPU_RELAX() definition. Or, don't use VL_THREADED" # endif From 38b2845e2a41e89e2d3b5c63899e3a964d38bb51 Mon Sep 17 00:00:00 2001 From: Wilson Snyder Date: Sat, 26 Mar 2022 15:41:32 -0400 Subject: [PATCH 05/44] Tests: Fix whitespace test and resulting fallout. --- test_regress/t/t_dist_whitespace.pl | 7 +++++-- test_regress/t/t_dpi_export_scope_bad.v | 2 +- test_regress/t/t_enum_type_bad.v | 2 +- test_regress/t/t_math_signed_calc.v | 4 +--- test_regress/t/t_order_dpi_export_1.v | 1 - test_regress/t/t_order_dpi_export_2.v | 1 - test_regress/t/t_order_dpi_export_3.v | 1 - test_regress/t/t_order_dpi_export_4.v | 1 - test_regress/t/t_order_dpi_export_5.v | 1 - test_regress/t/t_param_in_func.v | 1 - test_regress/t/t_profcfunc.gprof | 5 ++--- test_regress/t/t_split_var_5.pl | 1 - test_regress/t/t_sys_rand_concat.v | 4 ++-- test_regress/t/t_sys_rand_seed.v | 2 +- 14 files changed, 13 insertions(+), 20 deletions(-) diff --git a/test_regress/t/t_dist_whitespace.pl b/test_regress/t/t_dist_whitespace.pl index 451d46e98..1aaf1975f 100755 --- a/test_regress/t/t_dist_whitespace.pl +++ b/test_regress/t/t_dist_whitespace.pl @@ -16,11 +16,12 @@ my $Debug; ### Must trim output before and after our file list my %files = %{get_source_files($root)}; +my $any = 0; foreach my $file (sort keys %files) { my $filename = "$root/$file"; - next if !-f $file; # git file might be deleted but not yet staged + next if !-f $filename; # git file might be deleted but not yet staged my $contents = file_contents($filename); - if ($file =~ /\.out$/) { + if ($file =~ /(\.out|\.dat)$/) { # Ignore golden files next; } elsif ($contents =~ /[\001\002\003\004\005\006]/) { @@ -61,7 +62,9 @@ foreach my $file (sort keys %files) { $warns{$file} = "Trailing newlines at EOF in $file"; } } + ++$any; } +$any > 50 or error("Too few source files found"); if (keys %warns) { # First warning lists everything as that's shown in the driver summary diff --git a/test_regress/t/t_dpi_export_scope_bad.v b/test_regress/t/t_dpi_export_scope_bad.v index ad45d37e6..6a78eaf48 100644 --- a/test_regress/t/t_dpi_export_scope_bad.v +++ b/test_regress/t/t_dpi_export_scope_bad.v @@ -18,4 +18,4 @@ module s; task dpix_task(); $write("Hello in %m\n"); endtask -endmodule +endmodule diff --git a/test_regress/t/t_enum_type_bad.v b/test_regress/t/t_enum_type_bad.v index 84608dbe5..038646ca6 100644 --- a/test_regress/t/t_enum_type_bad.v +++ b/test_regress/t/t_enum_type_bad.v @@ -5,7 +5,7 @@ // SPDX-License-Identifier: CC0-1.0 module t; - + typedef enum {ZERO, ONE, TWO} e_t; typedef enum {THREE=3, FOUR, FIVE} o_t; diff --git a/test_regress/t/t_math_signed_calc.v b/test_regress/t/t_math_signed_calc.v index 90ce5de34..e89562a81 100644 --- a/test_regress/t/t_math_signed_calc.v +++ b/test_regress/t/t_math_signed_calc.v @@ -29,7 +29,7 @@ module t (/*AUTOARG*/ `endif if (out !== 'hfffe) $stop; $write("*-* All Finished *-*\n"); - $finish; + $finish; end endmodule @@ -45,5 +45,3 @@ module Test(in0, in1, out); assign out = $signed({1'b0, in0}) * in1; // this operator should be signed multiplication endmodule - - diff --git a/test_regress/t/t_order_dpi_export_1.v b/test_regress/t/t_order_dpi_export_1.v index e71069e06..293c8a93e 100644 --- a/test_regress/t/t_order_dpi_export_1.v +++ b/test_regress/t/t_order_dpi_export_1.v @@ -33,4 +33,3 @@ module testbench; end endmodule - diff --git a/test_regress/t/t_order_dpi_export_2.v b/test_regress/t/t_order_dpi_export_2.v index a5c1f40a1..0f1e8a577 100644 --- a/test_regress/t/t_order_dpi_export_2.v +++ b/test_regress/t/t_order_dpi_export_2.v @@ -40,4 +40,3 @@ module testbench( end endmodule - diff --git a/test_regress/t/t_order_dpi_export_3.v b/test_regress/t/t_order_dpi_export_3.v index 8083bae97..782d56cb7 100644 --- a/test_regress/t/t_order_dpi_export_3.v +++ b/test_regress/t/t_order_dpi_export_3.v @@ -53,4 +53,3 @@ module testbench( end endmodule - diff --git a/test_regress/t/t_order_dpi_export_4.v b/test_regress/t/t_order_dpi_export_4.v index 73600c1c1..88529466b 100644 --- a/test_regress/t/t_order_dpi_export_4.v +++ b/test_regress/t/t_order_dpi_export_4.v @@ -55,4 +55,3 @@ module testbench( end endmodule - diff --git a/test_regress/t/t_order_dpi_export_5.v b/test_regress/t/t_order_dpi_export_5.v index 744c64ca8..355a606d7 100644 --- a/test_regress/t/t_order_dpi_export_5.v +++ b/test_regress/t/t_order_dpi_export_5.v @@ -43,4 +43,3 @@ module testbench( end endmodule - diff --git a/test_regress/t/t_param_in_func.v b/test_regress/t/t_param_in_func.v index 62e86b395..6d2c82276 100644 --- a/test_regress/t/t_param_in_func.v +++ b/test_regress/t/t_param_in_func.v @@ -127,4 +127,3 @@ function automatic logic [7:0] getType(logic[3:0] d); {"9", "8", "7", "6", "5", "4", "3", "2", "1", "0"}; return digits[d]; endfunction - diff --git a/test_regress/t/t_profcfunc.gprof b/test_regress/t/t_profcfunc.gprof index 91be91407..edb86251b 100644 --- a/test_regress/t/t_profcfunc.gprof +++ b/test_regress/t/t_profcfunc.gprof @@ -2,8 +2,8 @@ Flat profile: Note all numbers below were faked for this test, so might not be consistent. - % cumulative self self total - time seconds seconds calls Ts/call Ts/call name + % cumulative self self total + time seconds seconds calls Ts/call Ts/call name 1.99 1.99 0.99 200578 0.00 0.00 VL_EXTENDS_QQ(int, int, unsigned long) 1.98 0.00 0.98 100000 0.00 0.00 VL_POWSS_QQQ(int, int, int, unsigned long, unsigned long, bool, bool) 1.89 0.00 0.89 1407 0.00 0.00 Verilated::debug() @@ -41,4 +41,3 @@ Flat profile: 1.25 0.00 0.25 3 0.00 0.00 unsigned long const& std::max(unsigned long const&, unsigned long const&) 1.19 0.00 0.19 1 0.00 0.00 vl_finish(char const*, int, char const*) 1.18 0.00 0.18 2 0.00 0.00 vl_time_pow10(int) - diff --git a/test_regress/t/t_split_var_5.pl b/test_regress/t/t_split_var_5.pl index 0fc4cc23a..41ddbc69c 100755 --- a/test_regress/t/t_split_var_5.pl +++ b/test_regress/t/t_split_var_5.pl @@ -23,4 +23,3 @@ file_grep($Self->{stats}, qr/SplitVar,\s+Split packed variables\s+(\d+)/i, 0); file_grep($Self->{stats}, qr/SplitVar,\s+Split unpacked arrays\s+(\d+)/i, 0); ok(1); 1; - diff --git a/test_regress/t/t_sys_rand_concat.v b/test_regress/t/t_sys_rand_concat.v index 820834dc2..acbbf665e 100644 --- a/test_regress/t/t_sys_rand_concat.v +++ b/test_regress/t/t_sys_rand_concat.v @@ -28,7 +28,7 @@ module t; initial begin for (int i = 0; i < `TRIES; ++i) begin // verilator lint_off WIDTH - // Optimize away extracts + // Optimize away extracts b5a = {$random}[4:0]; b5b = {$random}[14:10]; // Optimize away concats @@ -52,7 +52,7 @@ module t; `checkh(max_b7d, 7'h1f); `checkh(max_b60c, ~ 60'h0); `checkh(max_b90c, ~ 90'h0); - + $write("*-* All Finished *-*\n"); $finish; end diff --git a/test_regress/t/t_sys_rand_seed.v b/test_regress/t/t_sys_rand_seed.v index c26867a61..549f5e8c8 100644 --- a/test_regress/t/t_sys_rand_seed.v +++ b/test_regress/t/t_sys_rand_seed.v @@ -29,7 +29,7 @@ module t; valuec = $random(seedc); if (valuea == valueb && valueb == valuec) $stop; // May false fail 1 in 1^64 if (seeda == seedb && seedb == seedc) $stop; // May false fail 1 in 1^64 - + valuea = $urandom(10); valueb = $urandom(10); if (valuea !== valueb) $stop; From 4eaa6fdd06bc0395898e38db086c1fa9ca768150 Mon Sep 17 00:00:00 2001 From: Wilson Snyder Date: Sat, 26 Mar 2022 15:57:52 -0400 Subject: [PATCH 06/44] Internals: Use python pass appropriately. No functional change intended. --- bin/verilator_gantt | 4 ++-- src/astgen | 6 +++--- 2 files changed, 5 insertions(+), 5 deletions(-) diff --git a/bin/verilator_gantt b/bin/verilator_gantt index 5958cc518..f31cfa2b5 100755 --- a/bin/verilator_gantt +++ b/bin/verilator_gantt @@ -83,7 +83,7 @@ def read_data(filename): EvalLoops[start]['start'] = start EvalLoops[start]['end'] = start + elapsed_time elif re.match(r'^VLPROFTHREAD', line): - None # pylint: disable=pointless-statement + pass elif re_arg1.match(line): match = re_arg1.match(line) Global['args'][match.group(1)] = match.group(2) @@ -105,7 +105,7 @@ def read_data(filename): value = re.sub(r'\s+$', '', value) Global['cpuinfo'][cpu][term] = value elif re.match(r'^#', line): - None # pylint: disable=pointless-statement + pass elif Args.debug: print("-Unk: %s" % line) # TODO -- this is parsing text printed by a client. diff --git a/src/astgen b/src/astgen index f27c3b7d2..b6071c06b 100755 --- a/src/astgen +++ b/src/astgen @@ -217,9 +217,9 @@ class Cpt: argtext = func + "\000" # EOF character for tok in argtext: if tok == "\000": - None # pylint: disable=pointless-statement + pass elif re.match(r'\s+', tok): - None # pylint: disable=pointless-statement + pass elif tok == "{": newref = [forming] if not aref: @@ -262,7 +262,7 @@ class Cpt: elif func == "NEVER": out += "nodep->v3fatalSrc(\"Executing transform that was NEVERed\");" elif func == "DONE": - None # pylint: disable=pointless-statement + pass else: self.error("Unknown execution function format: " + func + "\n") return out From bab84627896abd6c0767730eb464f32dd5dc8b73 Mon Sep 17 00:00:00 2001 From: Geza Lore Date: Sat, 26 Mar 2022 21:29:03 +0000 Subject: [PATCH 07/44] Rebuild run-time library if generated makefile changes The generated makefile contains compiler options that are passed when building the run-time library, so re-build if it changes. --- include/verilated.mk.in | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/include/verilated.mk.in b/include/verilated.mk.in index 99fd533c2..4e32df566 100644 --- a/include/verilated.mk.in +++ b/include/verilated.mk.in @@ -193,6 +193,10 @@ VK_USER_OBJS = $(addsuffix .o, $(VM_USER_CLASSES)) # but keeping the distinction for compatibility for now. VK_GLOBAL_OBJS = $(addsuffix .o, $(VM_GLOBAL_FAST) $(VM_GLOBAL_SLOW)) +# Need to re-build if the generated makefile changes, as compiler options might +# have changed. +$(VK_GLOBAL_OBJS): $(VM_PREFIX).mk + ifneq ($(VM_PARALLEL_BUILDS),1) # Fast build for small designs: All .cpp files in one fell swoop. This # saves total compute, but can be slower if only a little changes. It is From c7440b250f2feb76f871a0a568cfc17f41f7158a Mon Sep 17 00:00:00 2001 From: Geza Lore Date: Sat, 26 Mar 2022 22:47:10 +0000 Subject: [PATCH 08/44] Validate integer run-time arguments --- include/verilated.cpp | 71 +++++++++++++++++++++--------- include/verilated_imp.h | 7 ++- test_regress/t/t_runflag_bad.out | 2 - test_regress/t/t_runflag_bad.out-a | 2 + test_regress/t/t_runflag_bad.out-b | 2 + test_regress/t/t_runflag_bad.out-c | 2 + test_regress/t/t_runflag_bad.out-d | 2 + test_regress/t/t_runflag_bad.out-e | 2 + test_regress/t/t_runflag_bad.pl | 28 +++++++++++- 9 files changed, 93 insertions(+), 25 deletions(-) delete mode 100644 test_regress/t/t_runflag_bad.out create mode 100644 test_regress/t/t_runflag_bad.out-a create mode 100644 test_regress/t/t_runflag_bad.out-b create mode 100644 test_regress/t/t_runflag_bad.out-c create mode 100644 test_regress/t/t_runflag_bad.out-d create mode 100644 test_regress/t/t_runflag_bad.out-e diff --git a/include/verilated.cpp b/include/verilated.cpp index 4401ffb45..75eaaefbf 100644 --- a/include/verilated.cpp +++ b/include/verilated.cpp @@ -55,6 +55,7 @@ #include #include #include +#include #include #include // mkdir #include @@ -2506,13 +2507,16 @@ std::pair VerilatedContextImp::argc_argv() VL_MT_SAFE_EXCLUDES(m_ar void VerilatedContextImp::commandArgVl(const std::string& arg) { if (0 == std::strncmp(arg.c_str(), "+verilator+", std::strlen("+verilator+"))) { - std::string value; + std::string str; + uint64_t u64; if (arg == "+verilator+debug") { Verilated::debug(4); - } else if (commandArgVlValue(arg, "+verilator+debugi+", value /*ref*/)) { - Verilated::debug(std::atoi(value.c_str())); - } else if (commandArgVlValue(arg, "+verilator+error+limit+", value /*ref*/)) { - errorLimit(std::atoi(value.c_str())); + } else if (commandArgVlUint64(arg, "+verilator+debugi+", u64, 0, + std::numeric_limits::max())) { + Verilated::debug(static_cast(u64)); + } else if (commandArgVlUint64(arg, "+verilator+error+limit+", u64, 0, + std::numeric_limits::max())) { + errorLimit(static_cast(u64)); } else if (arg == "+verilator+help") { VerilatedImp::versionDump(); VL_PRINTF_MT("For help, please see 'verilator --help'\n"); @@ -2520,18 +2524,19 @@ void VerilatedContextImp::commandArgVl(const std::string& arg) { "Exiting due to command line argument (not an error)"); } else if (arg == "+verilator+noassert") { assertOn(false); - } else if (commandArgVlValue(arg, "+verilator+prof+threads+start+", value /*ref*/)) { - profThreadsStart(std::atoll(value.c_str())); - } else if (commandArgVlValue(arg, "+verilator+prof+threads+window+", value /*ref*/)) { - profThreadsWindow(std::atol(value.c_str())); - } else if (commandArgVlValue(arg, "+verilator+prof+threads+file+", value /*ref*/)) { - profThreadsFilename(value); - } else if (commandArgVlValue(arg, "+verilator+prof+vlt+file+", value /*ref*/)) { - profVltFilename(value); - } else if (commandArgVlValue(arg, "+verilator+rand+reset+", value /*ref*/)) { - randReset(std::atoi(value.c_str())); - } else if (commandArgVlValue(arg, "+verilator+seed+", value /*ref*/)) { - randSeed(std::atoi(value.c_str())); + } else if (commandArgVlUint64(arg, "+verilator+prof+threads+start+", u64)) { + profThreadsStart(u64); + } else if (commandArgVlUint64(arg, "+verilator+prof+threads+window+", u64, 1)) { + profThreadsWindow(u64); + } else if (commandArgVlString(arg, "+verilator+prof+threads+file+", str)) { + profThreadsFilename(str); + } else if (commandArgVlString(arg, "+verilator+prof+vlt+file+", str)) { + profVltFilename(str); + } else if (commandArgVlUint64(arg, "+verilator+rand+reset+", u64, 0, 2)) { + randReset(static_cast(u64)); + } else if (commandArgVlUint64(arg, "+verilator+seed+", u64, 1, + std::numeric_limits::max())) { + randSeed(static_cast(u64)); } else if (arg == "+verilator+V") { VerilatedImp::versionDump(); // Someday more info too VL_FATAL_MT("COMMAND_LINE", 0, "", @@ -2541,12 +2546,14 @@ void VerilatedContextImp::commandArgVl(const std::string& arg) { VL_FATAL_MT("COMMAND_LINE", 0, "", "Exiting due to command line argument (not an error)"); } else { - VL_PRINTF_MT("%%Warning: Unknown +verilator runtime argument: '%s'\n", arg.c_str()); + const std::string msg = "Unknown runtime argument: " + arg; + VL_FATAL_MT("COMMAND_LINE", 0, "", msg.c_str()); } } } -bool VerilatedContextImp::commandArgVlValue(const std::string& arg, const std::string& prefix, - std::string& valuer) { + +bool VerilatedContextImp::commandArgVlString(const std::string& arg, const std::string& prefix, + std::string& valuer) { const size_t len = prefix.length(); if (0 == std::strncmp(prefix.c_str(), arg.c_str(), len)) { valuer = arg.substr(len); @@ -2556,6 +2563,30 @@ bool VerilatedContextImp::commandArgVlValue(const std::string& arg, const std::s } } +bool VerilatedContextImp::commandArgVlUint64(const std::string& arg, const std::string& prefix, + uint64_t& valuer, uint64_t min, uint64_t max) { + std::string str; + if (commandArgVlString(arg, prefix, str)) { + const auto fail = [&](const std::string& extra = "") { + std::stringstream ss; + ss << "Argument '" << prefix << "' must be an unsigned integer"; + if (min != std::numeric_limits::min()) ss << ", greater than " << min - 1; + if (max != std::numeric_limits::max()) ss << ", less than " << max + 1; + if (!extra.empty()) ss << ". " << extra; + const std::string& msg = ss.str(); + VL_FATAL_MT("COMMAND_LINE", 0, "", msg.c_str()); + }; + + if (std::any_of(str.begin(), str.end(), [](int c) { return !std::isdigit(c); })) fail(); + char* end; + valuer = std::strtoull(str.c_str(), &end, 10); + if (errno == ERANGE) fail("Value out of range of uint64_t"); + if (valuer < min || valuer > max) fail(); + return true; + } + return false; +} + //====================================================================== // VerilatedContext:: + VerilatedContextImp:: Methods - random diff --git a/include/verilated_imp.h b/include/verilated_imp.h index 7f07587db..c8b5ba352 100644 --- a/include/verilated_imp.h +++ b/include/verilated_imp.h @@ -34,6 +34,7 @@ #include #include +#include #include #include #include @@ -394,7 +395,11 @@ protected: // METHODS - protected void commandArgsAddGuts(int argc, const char** argv); void commandArgVl(const std::string& arg); - bool commandArgVlValue(const std::string& arg, const std::string& prefix, std::string& valuer); + bool commandArgVlString(const std::string& arg, const std::string& prefix, + std::string& valuer); + bool commandArgVlUint64(const std::string& arg, const std::string& prefix, uint64_t& valuer, + uint64_t min = std::numeric_limits::min(), + uint64_t max = std::numeric_limits::max()); void commandArgDump() const VL_MT_SAFE_EXCLUDES(m_argMutex); }; diff --git a/test_regress/t/t_runflag_bad.out b/test_regress/t/t_runflag_bad.out deleted file mode 100644 index 32330deaf..000000000 --- a/test_regress/t/t_runflag_bad.out +++ /dev/null @@ -1,2 +0,0 @@ -%Warning: Unknown +verilator runtime argument: '+verilator+bad+flag+testing' -*-* All Finished *-* diff --git a/test_regress/t/t_runflag_bad.out-a b/test_regress/t/t_runflag_bad.out-a new file mode 100644 index 000000000..f1fb8cf2c --- /dev/null +++ b/test_regress/t/t_runflag_bad.out-a @@ -0,0 +1,2 @@ +%Error: COMMAND_LINE:0: Unknown runtime argument: +verilator+bad+flag+testing +Aborting... diff --git a/test_regress/t/t_runflag_bad.out-b b/test_regress/t/t_runflag_bad.out-b new file mode 100644 index 000000000..9df23a4e7 --- /dev/null +++ b/test_regress/t/t_runflag_bad.out-b @@ -0,0 +1,2 @@ +%Error: COMMAND_LINE:0: Argument '+verilator+rand+reset+' must be an unsigned integer, less than 3 +Aborting... diff --git a/test_regress/t/t_runflag_bad.out-c b/test_regress/t/t_runflag_bad.out-c new file mode 100644 index 000000000..9df23a4e7 --- /dev/null +++ b/test_regress/t/t_runflag_bad.out-c @@ -0,0 +1,2 @@ +%Error: COMMAND_LINE:0: Argument '+verilator+rand+reset+' must be an unsigned integer, less than 3 +Aborting... diff --git a/test_regress/t/t_runflag_bad.out-d b/test_regress/t/t_runflag_bad.out-d new file mode 100644 index 000000000..f46b3bcaa --- /dev/null +++ b/test_regress/t/t_runflag_bad.out-d @@ -0,0 +1,2 @@ +%Error: COMMAND_LINE:0: Argument '+verilator+prof+threads+window+' must be an unsigned integer, greater than 0 +Aborting... diff --git a/test_regress/t/t_runflag_bad.out-e b/test_regress/t/t_runflag_bad.out-e new file mode 100644 index 000000000..7ad4052fd --- /dev/null +++ b/test_regress/t/t_runflag_bad.out-e @@ -0,0 +1,2 @@ +%Error: COMMAND_LINE:0: Argument '+verilator+prof+threads+window+' must be an unsigned integer, greater than 0. Value out of range of uint64_t +Aborting... diff --git a/test_regress/t/t_runflag_bad.pl b/test_regress/t/t_runflag_bad.pl index 7f6ecf79f..fd3637bc3 100755 --- a/test_regress/t/t_runflag_bad.pl +++ b/test_regress/t/t_runflag_bad.pl @@ -15,8 +15,32 @@ compile( execute( all_run_flags => ["+verilator+bad+flag+testing"], - #fails => 1, # doesn't fail just prints - expect_filename => $Self->{golden_filename}, + fails => 1, + expect_filename => $Self->{golden_filename} . "-a", + ); + +execute( + all_run_flags => ["+verilator+rand+reset+-1"], + fails => 1, + expect_filename => $Self->{golden_filename} . "-b" + ); + +execute( + all_run_flags => ["+verilator+rand+reset+3"], + fails => 1, + expect_filename => $Self->{golden_filename} . "-c" + ); + +execute( + all_run_flags => ["+verilator+prof+threads+window+0"], + fails => 1, + expect_filename => $Self->{golden_filename} . "-d" + ); + +execute( + all_run_flags => ["+verilator+prof+threads+window+1000000000000000000000000"], + fails => 1, + expect_filename => $Self->{golden_filename} . "-e" ); ok(1); From b1b5b5dfe2a473bfb32ed0931482ab9b2734564d Mon Sep 17 00:00:00 2001 From: Geza Lore Date: Fri, 25 Mar 2022 19:46:50 +0000 Subject: [PATCH 09/44] Improve run-time profiling The --prof-threads option has been split into two independent options: 1. --prof-exec, for collecting verilator_gantt and other execution related profiling data, and 2. --prof-pgo, for collecting data needed for PGO The implementation of execution profiling is extricated from VlThreadPool and is now a separate class VlExecutionProfiler. This means --prof-exec can now be used for single-threaded models (though it does not measure a lot of things just yet). For consistency VerilatedProfiler is renamed VlPgoProfiler. Both VlExecutionProfiler and VlPgoProfiler are in verilated_profiler.{h/cpp}, but can be used completely independently. Also re-worked the execution profile format so it now only emits events without holding onto any temporaries. This is in preparation for some future optimizations that would be hindered by the introduction of function locals via AstText. Also removed the Barrier event. Clearing the profile buffers is not notably more expensive as the profiling records are trivially destructible. --- Changes | 1 + bin/verilator | 11 +- bin/verilator_gantt | 304 ++++++++++++----------- docs/guide/deprecations.rst | 11 + docs/guide/exe_sim.rst | 30 ++- docs/guide/exe_verilator.rst | 13 +- docs/guide/exe_verilator_gantt.rst | 2 +- docs/guide/files.rst | 8 +- docs/guide/simulating.rst | 36 +-- docs/guide/verilating.rst | 2 +- docs/internals.rst | 2 +- include/verilated.cpp | 33 +-- include/verilated.h | 20 +- include/verilated_funcs.h | 9 - include/verilated_profiler.cpp | 191 ++++++++++++++ include/verilated_profiler.h | 226 +++++++++++++---- include/verilated_threads.cpp | 147 ++--------- include/verilated_threads.h | 98 +------- include/verilatedos.h | 6 +- src/V3EmitCImp.cpp | 6 +- src/V3EmitCMake.cpp | 3 + src/V3EmitCModel.cpp | 78 +----- src/V3EmitCSyms.cpp | 37 ++- src/V3EmitMk.cpp | 4 + src/V3Options.cpp | 8 +- src/V3Options.h | 7 +- src/V3Partition.cpp | 44 ++-- test_regress/t/t_gantt.pl | 28 ++- test_regress/t/t_gantt_io.dat | 64 +++-- test_regress/t/t_gantt_io.out | 9 +- test_regress/t/t_gantt_io.pl | 2 +- test_regress/t/t_gantt_io.vcd.out | 36 +-- test_regress/t/t_gantt_io_arm.dat | 31 ++- test_regress/t/t_gantt_io_arm.out | 9 +- test_regress/t/t_gantt_io_noproc.dat | 64 +++-- test_regress/t/t_gantt_io_noproc.out | 7 +- test_regress/t/t_gate_tree.pl | 6 +- test_regress/t/t_pgo_threads.pl | 10 +- test_regress/t/t_verilated_all.pl | 5 +- test_regress/t/t_verilated_all_newest.pl | 4 +- 40 files changed, 900 insertions(+), 712 deletions(-) create mode 100644 include/verilated_profiler.cpp diff --git a/Changes b/Changes index ed0c9f570..6bd421472 100644 --- a/Changes +++ b/Changes @@ -13,6 +13,7 @@ Verilator 4.221 devel **Minor:** +* Split --prof-threads into --prof-exec and --prof-pgo (#3365). [Geza Lore, Shunyao CAD] Verilator 4.220 2022-03-12 diff --git a/bin/verilator b/bin/verilator index b216b6f7d..853b94381 100755 --- a/bin/verilator +++ b/bin/verilator @@ -370,7 +370,8 @@ detailed descriptions of these arguments. --prefix Name of top level class --prof-c Compile C++ code with profiling --prof-cfuncs Name functions for profiling - --prof-threads Enable generating gantt chart data for threads + --prof-exec Enable generating execution profile for gantt chart + --prof-pgo Enable generating profiling data for PGO --protect-key Key for symbol protection --protect-ids Hash identifier names for obscurity --protect-lib Create a DPI protected library @@ -445,10 +446,10 @@ description of these arguments. +verilator+error+limit+ Set error limit +verilator+help Display help +verilator+noassert Disable assert checking - +verilator+prof+threads+file+ Set profile filename - +verilator+prof+threads+start+ Set profile starting point - +verilator+prof+threads+window+ Set profile duration - +verilator+prof+vlt+file+ Set profile guided filename + +verilator+prof+exec+file+ Set execution profile filename + +verilator+prof+exec+start+ Set execution profile starting point + +verilator+prof+exec+window+ Set execution profile duration + +verilator+prof+vlt+file+ Set PGO profile filename +verilator+rand+reset+ Set random reset technique +verilator+seed+ Set random seed +verilator+V Verbose version and config diff --git a/bin/verilator_gantt b/bin/verilator_gantt index f31cfa2b5..616af30dc 100755 --- a/bin/verilator_gantt +++ b/bin/verilator_gantt @@ -9,7 +9,7 @@ import re import statistics # from pprint import pprint -Threads = collections.defaultdict(lambda: {}) +Threads = collections.defaultdict(lambda: collections.defaultdict(lambda: {})) Mtasks = collections.defaultdict(lambda: {}) Evals = collections.defaultdict(lambda: {}) EvalLoops = collections.defaultdict(lambda: {}) @@ -30,12 +30,12 @@ def process(filename): def read_data(filename): with open(filename) as fh: - re_prof = re.compile( - r'^VLPROF mtask\s(\d+)\sstart\s(\d+)\selapsed\s(\d+)\spredict_start\s(\d+)\spredict_cost\s(\d+)\scpu\s(\d+)\son thread (\d+)' - ) - re_eval = re.compile(r'^VLPROF eval\sstart\s(\d+)\selapsed\s(\d+)') - re_loop = re.compile( - r'^VLPROF eval_loop\sstart\s(\d+)\selapsed\s(\d+)') + re_thread = re.compile(r'^VLPROFTHREAD (\d+)$') + re_record = re.compile(r'^VLPROFEXEC (\S+) (\d+)(.*)$') + re_payload_mtaskBegin = re.compile( + r'id (\d+) predictStart (\d+) cpu (\d+)') + re_payload_mtaskEnd = re.compile(r'id (\d+) predictCost (\d+)') + re_arg1 = re.compile(r'VLPROF arg\s+(\S+)\+([0-9.]*)\s*') re_arg2 = re.compile(r'VLPROF arg\s+(\S+)\s+([0-9.]*)\s*$') re_stat = re.compile(r'VLPROF stat\s+(\S+)\s+([0-9.]+)') @@ -43,46 +43,59 @@ def read_data(filename): re_proc_cpu = re.compile(r'VLPROFPROC processor\s*:\s*(\d+)\s*$') re_proc_dat = re.compile(r'VLPROFPROC ([a-z_ ]+)\s*:\s*(.*)$') cpu = None + thread = None + + lastEvalBeginTick = None + lastEvalLoopBeginTick = None for line in fh: - if re_prof.match(line): - match = re_prof.match(line) - mtask = int(match.group(1)) - start = int(match.group(2)) - elapsed_time = int(match.group(3)) - end = start + elapsed_time - predict_start = int(match.group(4)) - predict_cost = int(match.group(5)) - cpu = int(match.group(6)) - thread = int(match.group(7)) - if start not in Threads[thread]: - Threads[thread][start] = {} - Threads[thread][start]['mtask'] = mtask - Threads[thread][start]['end'] = end - Threads[thread][start]['cpu'] = cpu - Threads[thread][start]['predict_start'] = predict_start - Threads[thread][start]['predict_cost'] = predict_cost - - if 'elapsed' not in Mtasks[mtask]: - Mtasks[mtask] = {'end': 0, 'elapsed': 0} - Mtasks[mtask]['thread'] = thread - Mtasks[mtask]['elapsed'] += elapsed_time - Mtasks[mtask]['predict_start'] = predict_start - Mtasks[mtask]['predict_cost'] = predict_cost - Mtasks[mtask]['end'] = max(Mtasks[mtask]['end'], end) - elif re_eval.match(line): - match = re_eval.match(line) - start = int(match.group(1)) - elapsed_time = int(match.group(2)) - Evals[start]['start'] = start - Evals[start]['end'] = start + elapsed_time - elif re_loop.match(line): - match = re_loop.match(line) - start = int(match.group(1)) - elapsed_time = int(match.group(2)) - EvalLoops[start]['start'] = start - EvalLoops[start]['end'] = start + elapsed_time - elif re.match(r'^VLPROFTHREAD', line): + recordMatch = re_record.match(line) + if recordMatch: + kind, tick, payload = recordMatch.groups() + tick = int(tick) + payload = payload.strip() + if kind == "EVAL_BEGIN": + Evals[tick]['start'] = tick + lastEvalBeginTick = tick + elif kind == "EVAL_END": + Evals[lastEvalBeginTick]['end'] = tick + lastEvalBeginTick = None + elif kind == "EVAL_LOOP_BEGIN": + EvalLoops[tick]['start'] = tick + lastEvalLoopBeginTick = tick + elif kind == "EVAL_LOOP_END": + EvalLoops[lastEvalLoopBeginTick]['end'] = tick + lastEvalLoopBeginTick = None + elif kind == "MTASK_BEGIN": + mtask, predict_start, ecpu = re_payload_mtaskBegin.match( + payload).groups() + mtask = int(mtask) + predict_start = int(predict_start) + ecpu = int(ecpu) + Threads[thread][tick]['mtask'] = mtask + Threads[thread][tick]['predict_start'] = predict_start + Threads[thread][tick]['cpu'] = ecpu + if 'elapsed' not in Mtasks[mtask]: + Mtasks[mtask] = {'end': 0, 'elapsed': 0} + Mtasks[mtask]['begin'] = tick + Mtasks[mtask]['thread'] = thread + Mtasks[mtask]['predict_start'] = predict_start + elif kind == "MTASK_END": + mtask, predict_cost = re_payload_mtaskEnd.match( + payload).groups() + mtask = int(mtask) + predict_cost = int(predict_cost) + begin = Mtasks[mtask]['begin'] + Threads[thread][begin]['end'] = tick + Threads[thread][begin]['predict_cost'] = predict_cost + Mtasks[mtask]['elapsed'] += tick - begin + Mtasks[mtask]['predict_cost'] = predict_cost + Mtasks[mtask]['end'] = max(Mtasks[mtask]['end'], tick) + elif Args.debug: + print("-Unknown execution trace record: %s" % line) + elif re_thread.match(line): + thread = int(re_thread.match(line).group(1)) + elif re.match(r'^VLPROF(THREAD|VERSION)', line): pass elif re_arg1.match(line): match = re_arg1.match(line) @@ -131,11 +144,12 @@ def report(): plus = "+" if re.match(r'^\+', arg) else " " print(" %s%s%s" % (arg, plus, Global['args'][arg])) - nthreads = len(Threads) + nthreads = int(Global['stats']['threads']) Global['cpus'] = {} for thread in Threads: # Make potentially multiple characters per column for start in Threads[thread]: + if not Threads[thread][start]: continue cpu = Threads[thread][start]['cpu'] elapsed = Threads[thread][start]['end'] - start if cpu not in Global['cpus']: @@ -169,74 +183,79 @@ def report(): print("\nAnalysis:") print(" Total threads = %d" % nthreads) print(" Total mtasks = %d" % len(Mtasks)) - ncpus = len(Global['cpus']) + ncpus = max(len(Global['cpus']), 1) print(" Total cpus used = %d" % ncpus) - print(" Total yields = %d" % int(Global['stats']['yields'])) + print(" Total yields = %d" % + int(Global['stats'].get('yields', 0))) print(" Total evals = %d" % len(Evals)) print(" Total eval loops = %d" % len(EvalLoops)) - print(" Total eval time = %d rdtsc ticks" % - Global['measured_last_end']) - print(" Longest mtask time = %d rdtsc ticks" % long_mtask_time) - print(" All-thread mtask time = %d rdtsc ticks" % - measured_mt_mtask_time) - long_efficiency = long_mtask_time / (Global.get('measured_last_end', 1) - or 1) - print(" Longest-thread efficiency = %0.1f%%" % (long_efficiency * 100.0)) - mt_efficiency = measured_mt_mtask_time / ( - Global.get('measured_last_end', 1) * nthreads or 1) - print(" All-thread efficiency = %0.1f%%" % (mt_efficiency * 100.0)) - print(" All-thread speedup = %0.1f" % (mt_efficiency * nthreads)) - if Global['rdtsc_cycle_time'] > 0: - ut = measured_mt_mtask_time / Global['rdtsc_cycle_time'] - print("tot_mtask_cpu=" + measured_mt_mtask_time + " cyc=" + - Global['rdtsc_cycle_time'] + " ut=" + ut) + if Mtasks: + print(" Total eval time = %d rdtsc ticks" % + Global['measured_last_end']) + print(" Longest mtask time = %d rdtsc ticks" % long_mtask_time) + print(" All-thread mtask time = %d rdtsc ticks" % + measured_mt_mtask_time) + long_efficiency = long_mtask_time / (Global.get( + 'measured_last_end', 1) or 1) + print(" Longest-thread efficiency = %0.1f%%" % + (long_efficiency * 100.0)) + mt_efficiency = measured_mt_mtask_time / ( + Global.get('measured_last_end', 1) * nthreads or 1) + print(" All-thread efficiency = %0.1f%%" % + (mt_efficiency * 100.0)) + print(" All-thread speedup = %0.1f" % + (mt_efficiency * nthreads)) + if Global['rdtsc_cycle_time'] > 0: + ut = measured_mt_mtask_time / Global['rdtsc_cycle_time'] + print("tot_mtask_cpu=" + measured_mt_mtask_time + " cyc=" + + Global['rdtsc_cycle_time'] + " ut=" + ut) - predict_mt_efficiency = predict_mt_mtask_time / ( - Global.get('predict_last_end', 1) * nthreads or 1) - print("\nPrediction (what Verilator used for scheduling):") - print(" All-thread efficiency = %0.1f%%" % - (predict_mt_efficiency * 100.0)) - print(" All-thread speedup = %0.1f" % - (predict_mt_efficiency * nthreads)) + predict_mt_efficiency = predict_mt_mtask_time / ( + Global.get('predict_last_end', 1) * nthreads or 1) + print("\nPrediction (what Verilator used for scheduling):") + print(" All-thread efficiency = %0.1f%%" % + (predict_mt_efficiency * 100.0)) + print(" All-thread speedup = %0.1f" % + (predict_mt_efficiency * nthreads)) - p2e_ratios = [] - min_p2e = 1000000 - min_mtask = None - max_p2e = -1000000 - max_mtask = None + p2e_ratios = [] + min_p2e = 1000000 + min_mtask = None + max_p2e = -1000000 + max_mtask = None - for mtask in sorted(Mtasks.keys()): - if Mtasks[mtask]['elapsed'] > 0: - if Mtasks[mtask]['predict_cost'] == 0: - Mtasks[mtask]['predict_cost'] = 1 # don't log(0) below - p2e_ratio = math.log(Mtasks[mtask]['predict_cost'] / - Mtasks[mtask]['elapsed']) - p2e_ratios.append(p2e_ratio) + for mtask in sorted(Mtasks.keys()): + if Mtasks[mtask]['elapsed'] > 0: + if Mtasks[mtask]['predict_cost'] == 0: + Mtasks[mtask]['predict_cost'] = 1 # don't log(0) below + p2e_ratio = math.log(Mtasks[mtask]['predict_cost'] / + Mtasks[mtask]['elapsed']) + p2e_ratios.append(p2e_ratio) - if p2e_ratio > max_p2e: - max_p2e = p2e_ratio - max_mtask = mtask - if p2e_ratio < min_p2e: - min_p2e = p2e_ratio - min_mtask = mtask + if p2e_ratio > max_p2e: + max_p2e = p2e_ratio + max_mtask = mtask + if p2e_ratio < min_p2e: + min_p2e = p2e_ratio + min_mtask = mtask - print("\nStatistics:") - print(" min log(p2e) = %0.3f" % min_p2e, end="") - print(" from mtask %d (predict %d," % - (min_mtask, Mtasks[min_mtask]['predict_cost']), - end="") - print(" elapsed %d)" % Mtasks[min_mtask]['elapsed']) - print(" max log(p2e) = %0.3f" % max_p2e, end="") - print(" from mtask %d (predict %d," % - (max_mtask, Mtasks[max_mtask]['predict_cost']), - end="") - print(" elapsed %d)" % Mtasks[max_mtask]['elapsed']) + print("\nMTask statistics:") + print(" min log(p2e) = %0.3f" % min_p2e, end="") + print(" from mtask %d (predict %d," % + (min_mtask, Mtasks[min_mtask]['predict_cost']), + end="") + print(" elapsed %d)" % Mtasks[min_mtask]['elapsed']) + print(" max log(p2e) = %0.3f" % max_p2e, end="") + print(" from mtask %d (predict %d," % + (max_mtask, Mtasks[max_mtask]['predict_cost']), + end="") + print(" elapsed %d)" % Mtasks[max_mtask]['elapsed']) - stddev = statistics.pstdev(p2e_ratios) - mean = statistics.mean(p2e_ratios) - print(" mean = %0.3f" % mean) - print(" stddev = %0.3f" % stddev) - print(" e ^ stddev = %0.3f" % math.exp(stddev)) + stddev = statistics.pstdev(p2e_ratios) + mean = statistics.mean(p2e_ratios) + print(" mean = %0.3f" % mean) + print(" stddev = %0.3f" % stddev) + print(" e ^ stddev = %0.3f" % math.exp(stddev)) report_cpus() @@ -375,44 +394,45 @@ def write_vcd(filename): vcd['values'][eval_start][elcode] = n vcd['values'][eval_end][elcode] = None - # Predicted graph - for eval_start in EvalLoops: - eval_end = EvalLoops[eval_start]['end'] - # Compute scale so predicted graph is of same width as eval - measured_scaling = (eval_end - - eval_start) / Global['predict_last_end'] - # Predict mtasks that fill the time the eval occupied - for mtask in Mtasks: - thread = Mtasks[mtask]['thread'] - pred_scaled_start = eval_start + int( - Mtasks[mtask]['predict_start'] * measured_scaling) - pred_scaled_end = eval_start + int( - (Mtasks[mtask]['predict_start'] + - Mtasks[mtask]['predict_cost']) * measured_scaling) - if pred_scaled_start == pred_scaled_end: - continue + if Mtasks: + # Predicted graph + for eval_start in EvalLoops: + eval_end = EvalLoops[eval_start]['end'] + # Compute scale so predicted graph is of same width as eval + measured_scaling = (eval_end - + eval_start) / Global['predict_last_end'] + # Predict mtasks that fill the time the eval occupied + for mtask in Mtasks: + thread = Mtasks[mtask]['thread'] + pred_scaled_start = eval_start + int( + Mtasks[mtask]['predict_start'] * measured_scaling) + pred_scaled_end = eval_start + int( + (Mtasks[mtask]['predict_start'] + + Mtasks[mtask]['predict_cost']) * measured_scaling) + if pred_scaled_start == pred_scaled_end: + continue - sig = "predicted_thread%d_mtask" % thread - if sig not in vcd['sigs']['predicted_threads']: - vcd['sigs']['predicted_threads'][sig] = code - code += 1 - mcode = vcd['sigs']['predicted_threads'][sig] + sig = "predicted_thread%d_mtask" % thread + if sig not in vcd['sigs']['predicted_threads']: + vcd['sigs']['predicted_threads'][sig] = code + code += 1 + mcode = vcd['sigs']['predicted_threads'][sig] - vcd['values'][pred_scaled_start][mcode] = mtask - vcd['values'][pred_scaled_end][mcode] = None + vcd['values'][pred_scaled_start][mcode] = mtask + vcd['values'][pred_scaled_end][mcode] = None - parallelism['predicted'][pred_scaled_start] += 1 - parallelism['predicted'][pred_scaled_end] -= 1 + parallelism['predicted'][pred_scaled_start] += 1 + parallelism['predicted'][pred_scaled_end] -= 1 - # Parallelism graph - for measpred in ('measured', 'predicted'): - vcd['sigs']['Stats']["%s_parallelism" % measpred] = code - pcode = code - code += 1 - value = 0 - for time in sorted(parallelism[measpred].keys()): - value += parallelism[measpred][time] - vcd['values'][time][pcode] = value + # Parallelism graph + for measpred in ('measured', 'predicted'): + vcd['sigs']['Stats']["%s_parallelism" % measpred] = code + pcode = code + code += 1 + value = 0 + for time in sorted(parallelism[measpred].keys()): + value += parallelism[measpred][time] + vcd['values'][time][pcode] = value # Create output file fh.write("$version Generated by verilator_gantt $end\n") @@ -476,10 +496,10 @@ parser.add_argument('--no-vcd', action='store_true') parser.add_argument('--vcd', help='filename for vcd outpue', - default='profile_threads.vcd') + default='profile_exec.vcd') parser.add_argument('filename', - help='input profile_threads.dat filename to process', - default='profile_threads.dat') + help='input profile_exec.dat filename to process', + default='profile_exec.dat') Args = parser.parse_args() diff --git a/docs/guide/deprecations.rst b/docs/guide/deprecations.rst index 87107cca1..33c2ef610 100644 --- a/docs/guide/deprecations.rst +++ b/docs/guide/deprecations.rst @@ -19,3 +19,14 @@ Verilated_heavy.h Option `--cdc` The experimental `--cdc` option is believed to be generally unused and is planned for removal no sooner than January 2023. + +Option `--prof-threads` + The `--prof-threads` option has been superseded by the `--prof-exec` and + `--prof-pgo` options and is planned for removal no sooner than April 2023. + +Verilated model options `+verilator+prof+threads+*` + The `+verilator+prof+threads+start`, `+verilator+prof+threads+window` and + `+verilator+prof+threads+file` options have been superseded by the + `+verilator+prof+exec+start`, `+verilator+prof+exec+window` and + `+verilator+prof+exec+file` options respectively and are planned for removal + no sooner than April 2023. diff --git a/docs/guide/exe_sim.rst b/docs/guide/exe_sim.rst index e8af13bfe..016340cc8 100644 --- a/docs/guide/exe_sim.rst +++ b/docs/guide/exe_sim.rst @@ -38,33 +38,45 @@ Summary: Display help and exit. -.. option:: +verilator+prof+threads+file+ +.. option:: +verilator+prof+exec+file+ - When a model was Verilated using :vlopt:`--prof-threads`, sets the + When a model was Verilated using :vlopt:`--prof-exec`, sets the simulation runtime filename to dump to. Defaults to - :file:`profile_threads.dat`. + :file:`profile_exec.dat`. -.. option:: +verilator+prof+threads+start+ +.. option:: +verilator+prof+exec+start+ - When a model was Verilated using :vlopt:`--prof-threads`, the simulation + When a model was Verilated using :vlopt:`--prof-exec`, the simulation runtime will wait until $time is at this value (expressed in units of the time precision), then start the profiling warmup, then capturing. Generally this should be set to some time that is well within the normal operation of the simulation, i.e. outside of reset. If 0, the dump is disabled. Defaults to 1. -.. option:: +verilator+prof+threads+window+ +.. option:: +verilator+prof+exec+window+ - When a model was Verilated using :vlopt:`--prof-threads`, after $time - reaches :vlopt:`+verilator+prof+threads+start+\`, Verilator will + When a model was Verilated using :vlopt:`--prof-exec`, after $time + reaches :vlopt:`+verilator+prof+exec+start+\`, Verilator will warm up the profiling for this number of eval() calls, then will capture the profiling of this number of eval() calls. Defaults to 2, which makes sense for a single-clock-domain module where it's typical to want to capture one posedge eval() and one negedge eval(). +.. option:: +verilator+prof+threads+file+ + + Deprecated. Alias for :vlopt:`+verilator+prof+exec+file+\` + +.. option:: +verilator+prof+threads+start+ + + Deprecated. Alias for :vlopt:`+verilator+prof+exec+start+\` + +.. option:: +verilator+prof+threads+window+ + + Deprecated. Alias for :vlopt:`+verilator+prof+exec+window+\` + .. option:: +verilator+prof+vlt+file+ - When a model was Verilated using :vlopt:`--prof-threads`, sets the + When a model was Verilated using :vlopt:`--prof-pgo`, sets the profile-guided optimization data runtime filename to dump to. Defaults to :file:`profile.vlt`. diff --git a/docs/guide/exe_verilator.rst b/docs/guide/exe_verilator.rst index 55a356ee4..83b3ad0f5 100644 --- a/docs/guide/exe_verilator.rst +++ b/docs/guide/exe_verilator.rst @@ -845,10 +845,19 @@ Summary: Using :vlopt:`--prof-cfuncs` also enables :vlopt:`--prof-c`. +.. option:: --prof-exec + + Enable collection of execution trace, that can be convered into a gantt + chart with verilator_gantt See :ref:`Execution Profiling`. + +.. option:: --prof-pgo + + Enable collection of profiling data for profile guided verilation. Currently + this is only useful with :vlopt:`--threads`. See :ref:`Thread PGO`. + .. option:: --prof-threads - Enable gantt chart data collection for threaded builds. See :ref:`Thread - Profiling` and :ref:`Thread PGO`. + Deprecated. Same as --prof-exec and --prof-pgo together. .. option:: --protect-key diff --git a/docs/guide/exe_verilator_gantt.rst b/docs/guide/exe_verilator_gantt.rst index 2d0e03cc9..c7054214b 100644 --- a/docs/guide/exe_verilator_gantt.rst +++ b/docs/guide/exe_verilator_gantt.rst @@ -72,7 +72,7 @@ verilator_gantt Arguments .. option:: -The filename to read data from, defaults to "profile_threads.dat". +The filename to read data from, defaults to "profile_exec.dat". .. option:: --help diff --git a/docs/guide/files.rst b/docs/guide/files.rst index c0896f6df..522855ce3 100644 --- a/docs/guide/files.rst +++ b/docs/guide/files.rst @@ -155,13 +155,13 @@ The Verilated executable may produce the following: * - gmon.out - GCC/clang code profiler output, often fed into :command:`verilator_profcfunc` * - profile.vlt - - -profile data file for :ref:`Thread PGO` - * - profile_threads.dat - - -profile-threads data file for :command:`verilator_gantt` + - --prof-pgo data file for :ref:`Thread PGO` + * - profile_exec.dat + - --prof-exec data file for :command:`verilator_gantt` Verilator_gantt may produce the following: .. list-table:: - * - profile_threads.vcd + * - profile_exec.vcd - Gantt report waveform output diff --git a/docs/guide/simulating.rst b/docs/guide/simulating.rst index 064233697..da78bf9dd 100644 --- a/docs/guide/simulating.rst +++ b/docs/guide/simulating.rst @@ -279,26 +279,25 @@ To use profiling: is being spent. -.. _Thread Profiling: +.. _Execution Profiling: -Thread Profiling -================ +Execution Profiling +=================== -When using multithreaded mode (:vlopt:`--threads`), it is useful to see -statistics and visualize how well the multiple CPUs are being utilized. +For performance optimization, it is useful to see statistics and visualize how +execution time is distributed in a verilated model. -With the :vlopt:`--prof-threads` option, Verilator will: +With the :vlopt:`--prof-exec` option, Verilator will: -* Add code to the Verilated model to record the start and end time of each - macro-task across a number of calls to eval. (What is a macro-task? See - the Verilator internals document (:file:`docs/internals.rst` in the - distribution.) +* Add code to the Verilated model to record execution flow. * Add code to save profiling data in non-human-friendly form to the file - specified with :vlopt:`+verilator+prof+threads+file+\`. + specified with :vlopt:`+verilator+prof+exec+file+\`. -* Add code to save profiling data for thread profile-guided - optimization. See :ref:`Thread PGO`. +* In multi-threaded models, add code to record the start and end time of each + macro-task across a number of calls to eval. (What is a macro-task? See the + Verilator internals document (:file:`docs/internals.rst` in the + distribution.) The :command:`verilator_gantt` program may then be run to transform the saved profiling file into a nicer visual format and produce some related @@ -406,8 +405,8 @@ others as they prove beneficial. Thread Profile-Guided Optimization ---------------------------------- -Verilator supports thread profile-guided optimization (Thread PGO) to -improve multithreaded performance. +Verilator supports profile-guided optimization (verilation) of multi-threaded +models (Thread PGO) to improve performance. When using multithreading, Verilator computes how long macro tasks take and tries to balance those across threads. (What is a macro-task? See the @@ -417,13 +416,14 @@ balanced, leading to decreased performance. Thread PGO allows collecting profiling data to replace the estimates and better optimize these decisions. -To use Thread PGO, Verilate the model with the :vlopt:`--prof-threads` -option. +To use Thread PGO, Verilate the model with the :vlopt:`--prof-pgo` option. This +will code to the verilated model to save profiling data for profile-guided +optimization. Run the model executable. When the executable exits, it will create a profile.vlt file. -Rerun Verilator, optionally omitting the :vlopt:`--prof-threads` option, +Rerun Verilator, optionally omitting the :vlopt:`--prof-pgo` option, and adding the profile.vlt generated earlier to the command line. Note there is no Verilator equivalent to GCC's --fprofile-use. Verilator's diff --git a/docs/guide/verilating.rst b/docs/guide/verilating.rst index d58153684..f443ca298 100644 --- a/docs/guide/verilating.rst +++ b/docs/guide/verilating.rst @@ -265,7 +265,7 @@ This will limit memory to socket 0, and threads to cores 0, 1, 2, 3, (presumably on socket 0) optimizing performance. Of course this must be adjusted if you want another simulator using e.g. socket 1, or if you Verilated with a different number of threads. To see what CPUs are -actually used, use :vlopt:`--prof-threads`. +actually used, use :vlopt:`--prof-exec`. Multithreaded Verilog and Library Support diff --git a/docs/internals.rst b/docs/internals.rst index 50cd05905..71fa886a0 100644 --- a/docs/internals.rst +++ b/docs/internals.rst @@ -301,7 +301,7 @@ prerequisites on other threads have finished. The synchronization cost is cheap if the prereqs are done. If they're not, fragmentation (idle CPU cores waiting) is possible. This is the major -source of overhead in this approach. The ``--prof-threads`` switch and the +source of overhead in this approach. The ``--prof-exec`` switch and the ``verilator_gantt`` script can visualize the time lost to such fragmentation. diff --git a/include/verilated.cpp b/include/verilated.cpp index 75eaaefbf..e55da5bf3 100644 --- a/include/verilated.cpp +++ b/include/verilated.cpp @@ -2280,7 +2280,7 @@ VerilatedContext::VerilatedContext() : m_impdatap{new VerilatedContextImpData} { Verilated::lastContextp(this); Verilated::threadContextp(this); - m_ns.m_profThreadsFilename = "profile_threads.dat"; + m_ns.m_profExecFilename = "profile_exec.dat"; m_ns.m_profVltFilename = "profile.vlt"; m_fdps.resize(31); std::fill(m_fdps.begin(), m_fdps.end(), static_cast(nullptr)); @@ -2348,21 +2348,21 @@ void VerilatedContext::gotFinish(bool flag) VL_MT_SAFE { const VerilatedLockGuard lock{m_mutex}; m_s.m_gotFinish = flag; } -void VerilatedContext::profThreadsStart(vluint64_t flag) VL_MT_SAFE { +void VerilatedContext::profExecStart(vluint64_t flag) VL_MT_SAFE { const VerilatedLockGuard lock{m_mutex}; - m_ns.m_profThreadsStart = flag; + m_ns.m_profExecStart = flag; } -void VerilatedContext::profThreadsWindow(vluint64_t flag) VL_MT_SAFE { +void VerilatedContext::profExecWindow(vluint64_t flag) VL_MT_SAFE { const VerilatedLockGuard lock{m_mutex}; - m_ns.m_profThreadsWindow = flag; + m_ns.m_profExecWindow = flag; } -void VerilatedContext::profThreadsFilename(const std::string& flag) VL_MT_SAFE { +void VerilatedContext::profExecFilename(const std::string& flag) VL_MT_SAFE { const VerilatedLockGuard lock{m_mutex}; - m_ns.m_profThreadsFilename = flag; + m_ns.m_profExecFilename = flag; } -std::string VerilatedContext::profThreadsFilename() const VL_MT_SAFE { +std::string VerilatedContext::profExecFilename() const VL_MT_SAFE { const VerilatedLockGuard lock{m_mutex}; - return m_ns.m_profThreadsFilename; + return m_ns.m_profExecFilename; } void VerilatedContext::profVltFilename(const std::string& flag) VL_MT_SAFE { const VerilatedLockGuard lock{m_mutex}; @@ -2524,12 +2524,15 @@ void VerilatedContextImp::commandArgVl(const std::string& arg) { "Exiting due to command line argument (not an error)"); } else if (arg == "+verilator+noassert") { assertOn(false); - } else if (commandArgVlUint64(arg, "+verilator+prof+threads+start+", u64)) { - profThreadsStart(u64); - } else if (commandArgVlUint64(arg, "+verilator+prof+threads+window+", u64, 1)) { - profThreadsWindow(u64); - } else if (commandArgVlString(arg, "+verilator+prof+threads+file+", str)) { - profThreadsFilename(str); + } else if (commandArgVlUint64(arg, "+verilator+prof+exec+start+", u64) + || commandArgVlUint64(arg, "+verilator+prof+threads+start+", u64)) { + profExecStart(u64); + } else if (commandArgVlUint64(arg, "+verilator+prof+exec+window+", u64, 1) + || commandArgVlUint64(arg, "+verilator+prof+threads+window+", u64, 1)) { + profExecWindow(u64); + } else if (commandArgVlString(arg, "+verilator+prof+exec+file+", str) + || commandArgVlString(arg, "+verilator+prof+threads+file+", str)) { + profExecFilename(str); } else if (commandArgVlString(arg, "+verilator+prof+vlt+file+", str)) { profVltFilename(str); } else if (commandArgVlUint64(arg, "+verilator+rand+reset+", u64, 0, 2)) { diff --git a/include/verilated.h b/include/verilated.h index 368be6bcc..15ea667c6 100644 --- a/include/verilated.h +++ b/include/verilated.h @@ -344,10 +344,10 @@ protected: struct NonSerialized { // Non-serialized information // These are reloaded from on command-line settings, so do not need to persist // Fast path - vluint64_t m_profThreadsStart = 1; // +prof+threads starting time - vluint32_t m_profThreadsWindow = 2; // +prof+threads window size + vluint64_t m_profExecStart = 1; // +prof+exec+start time + vluint32_t m_profExecWindow = 2; // +prof+exec+window size // Slow path - std::string m_profThreadsFilename; // +prof+threads filename + std::string m_profExecFilename; // +prof+exec+file filename std::string m_profVltFilename; // +prof+vlt filename } m_ns; @@ -518,13 +518,13 @@ public: // But for internal use only std::string dumpfile() const VL_MT_SAFE_EXCLUDES(m_timeDumpMutex); std::string dumpfileCheck() const VL_MT_SAFE_EXCLUDES(m_timeDumpMutex); - // Internal: --prof-threads related settings - void profThreadsStart(vluint64_t flag) VL_MT_SAFE; - vluint64_t profThreadsStart() const VL_MT_SAFE { return m_ns.m_profThreadsStart; } - void profThreadsWindow(vluint64_t flag) VL_MT_SAFE; - vluint32_t profThreadsWindow() const VL_MT_SAFE { return m_ns.m_profThreadsWindow; } - void profThreadsFilename(const std::string& flag) VL_MT_SAFE; - std::string profThreadsFilename() const VL_MT_SAFE; + // Internal: --prof-exec related settings + void profExecStart(vluint64_t flag) VL_MT_SAFE; + vluint64_t profExecStart() const VL_MT_SAFE { return m_ns.m_profExecStart; } + void profExecWindow(vluint64_t flag) VL_MT_SAFE; + vluint32_t profExecWindow() const VL_MT_SAFE { return m_ns.m_profExecWindow; } + void profExecFilename(const std::string& flag) VL_MT_SAFE; + std::string profExecFilename() const VL_MT_SAFE; void profVltFilename(const std::string& flag) VL_MT_SAFE; std::string profVltFilename() const VL_MT_SAFE; diff --git a/include/verilated_funcs.h b/include/verilated_funcs.h index 988b5d807..481e8980a 100644 --- a/include/verilated_funcs.h +++ b/include/verilated_funcs.h @@ -112,15 +112,6 @@ extern WDataOutP VL_RAND_RESET_W(int obits, WDataOutP outwp); /// Zero reset a signal (slow - else use VL_ZERO_W) extern WDataOutP VL_ZERO_RESET_W(int obits, WDataOutP outwp); -#if VL_THREADED -/// Return high-precision counter for profiling, or 0x0 if not available -inline QData VL_RDTSC_Q() { - vluint64_t val; - VL_RDTSC(val); - return val; -} -#endif - extern void VL_PRINTTIMESCALE(const char* namep, const char* timeunitp, const VerilatedContext* contextp) VL_MT_SAFE; diff --git a/include/verilated_profiler.cpp b/include/verilated_profiler.cpp new file mode 100644 index 000000000..04cc5dfff --- /dev/null +++ b/include/verilated_profiler.cpp @@ -0,0 +1,191 @@ +// -*- mode: C++; c-file-style: "cc-mode" -*- +//============================================================================= +// +// Code available from: https://verilator.org +// +// Copyright 2012-2022 by Wilson Snyder. This program is free software; you can +// redistribute it and/or modify it under the terms of either the GNU +// Lesser General Public License Version 3 or the Perl Artistic License +// Version 2.0. +// SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 +// +//============================================================================= +/// +/// \file +/// \brief Verilated run-time profiling implementation code +/// +//============================================================================= + +#include "verilatedos.h" +#include "verilated_profiler.h" + +#if VL_THREADED +#include "verilated_threads.h" +#endif + +#include +#include + +//============================================================================= +// Globals + +// Internal note: Globals may multi-construct, see verilated.cpp top. + +VL_THREAD_LOCAL VlExecutionProfiler::ExecutionTrace VlExecutionProfiler::t_trace; + +constexpr const char* const VlExecutionRecord::s_ascii[]; + +//============================================================================= +// VlPgoProfiler implementation + +vluint16_t VlExecutionRecord::getcpu() { +#if defined(__linux) + return sched_getcpu(); // TODO: this is a system call. Not exactly cheap. +#elif defined(__APPLE__) && !defined(__arm64__) + vluint32_t info[4]; + __cpuid_count(1, 0, info[0], info[1], info[2], info[3]); + // info[1] is EBX, bits 24-31 are APIC ID + if ((info[3] & (1 << 9)) == 0) { + return -1; // no APIC on chip + } else { + return (unsigned)info[1] >> 24; + } +#elif defined(_WIN32) + return GetCurrentProcessorNumber(); +#else + return 0; +#endif +} + +//============================================================================= +// VlExecutionProfiler implementation + +template size_t roundUptoMultipleOf(size_t value) { + static_assert((N & (N - 1)) == 0, "'N' must be a power of 2"); + size_t mask = N - 1; + return (value + mask) & ~mask; +} + +VlExecutionProfiler::VlExecutionProfiler() { + // Setup profiling on main thread + setupThread(0); +} + +void VlExecutionProfiler::configure(const VerilatedContext& context) { + if (VL_UNLIKELY(m_enabled)) { + --m_windowCount; + if (VL_UNLIKELY(m_windowCount == context.profExecWindow())) { + VL_DEBUG_IF(VL_DBG_MSGF("+ profile start collection\n");); + clear(); // Clear the profile after the cache warm-up cycles. + m_tickBegin = VL_CPU_TICK(); + } else if (VL_UNLIKELY(m_windowCount == 0)) { + const vluint64_t tickEnd = VL_CPU_TICK(); + VL_DEBUG_IF(VL_DBG_MSGF("+ profile end\n");); + const std::string& fileName = context.profExecFilename(); + dump(fileName.c_str(), tickEnd); + m_enabled = false; + } + return; + } + + const vluint64_t startReq = context.profExecStart() + 1; // + 1, so we can start at time 0 + + if (VL_UNLIKELY(m_lastStartReq < startReq && VL_TIME_Q() >= context.profExecStart())) { + VL_DEBUG_IF(VL_DBG_MSGF("+ profile start warmup\n");); + VL_DEBUG_IF(assert(m_windowCount == 0);); + m_enabled = true; + m_windowCount = context.profExecWindow() * 2; + m_lastStartReq = startReq; + } +} + +void VlExecutionProfiler::setupThread(uint32_t threadId) { + // Reserve some space in the thread-local profiling buffer, in order to try to avoid malloc + // while profiling. + t_trace.reserve(RESERVED_TRACE_CAPACITY); + // Register thread-local buffer in list of all buffers + { + const VerilatedLockGuard lock{m_mutex}; + bool exists = !m_traceps.emplace(threadId, &t_trace).second; + assert(!exists); + } +} + +void VlExecutionProfiler::clear() VL_MT_SAFE_EXCLUDES(m_mutex) { + const VerilatedLockGuard lock{m_mutex}; + for (const auto& pair : m_traceps) { + ExecutionTrace* const tracep = pair.second; + const size_t reserve = roundUptoMultipleOf(tracep->size()); + tracep->clear(); + tracep->reserve(reserve); + } +} + +void VlExecutionProfiler::dump(const char* filenamep, vluint64_t tickEnd) + VL_MT_SAFE_EXCLUDES(m_mutex) { + const VerilatedLockGuard lock{m_mutex}; + VL_DEBUG_IF(VL_DBG_MSGF("+prof+exec writing to '%s'\n", filenamep);); + + FILE* const fp = std::fopen(filenamep, "w"); + if (VL_UNLIKELY(!fp)) { VL_FATAL_MT(filenamep, 0, "", "+prof+exec+file file not writable"); } + + // TODO Perhaps merge with verilated_coverage output format, so can + // have a common merging and reporting tool, etc. + fprintf(fp, "VLPROFVERSION 2.0 # Verilator execution profile version 2.0\n"); + fprintf(fp, "VLPROF arg +verilator+prof+exec+start+%" PRIu64 "\n", + Verilated::threadContextp()->profExecStart()); + fprintf(fp, "VLPROF arg +verilator+prof+exec+window+%u\n", + Verilated::threadContextp()->profExecWindow()); + const unsigned threads = static_cast(m_traceps.size()); + fprintf(fp, "VLPROF stat threads %u\n", threads); +#ifdef VL_THREADED + fprintf(fp, "VLPROF stat yields %" PRIu64 "\n", VlMTaskVertex::yields()); +#endif + + // Copy /proc/cpuinfo into this output so verilator_gantt can be run on + // a different machine + { + const std::unique_ptr ifp{new std::ifstream("/proc/cpuinfo")}; + if (!ifp->fail()) { + std::string line; + while (std::getline(*ifp, line)) { fprintf(fp, "VLPROFPROC %s\n", line.c_str()); } + } + } + + for (const auto& pair : m_traceps) { + const uint32_t threadId = pair.first; + ExecutionTrace* const tracep = pair.second; + fprintf(fp, "VLPROFTHREAD %" PRIu32 "\n", threadId); + + for (const VlExecutionRecord& er : *tracep) { + const char* const name = VlExecutionRecord::s_ascii[static_cast(er.m_type)]; + const vluint64_t time = er.m_tick - m_tickBegin; + fprintf(fp, "VLPROFEXEC %s %" PRIu64, name, time); + + switch (er.m_type) { + case VlExecutionRecord::Type::EVAL_BEGIN: + case VlExecutionRecord::Type::EVAL_END: + case VlExecutionRecord::Type::EVAL_LOOP_BEGIN: + case VlExecutionRecord::Type::EVAL_LOOP_END: + // No payload + fprintf(fp, "\n"); + break; + case VlExecutionRecord::Type::MTASK_BEGIN: { + const auto& payload = er.m_payload.mtaskBegin; + fprintf(fp, " id %u predictStart %u cpu %u\n", payload.m_id, + payload.m_predictStart, payload.m_cpu); + break; + } + case VlExecutionRecord::Type::MTASK_END: { + const auto& payload = er.m_payload.mtaskEnd; + fprintf(fp, " id %u predictCost %u\n", payload.m_id, payload.m_predictCost); + break; + } + default: abort(); // LCOV_EXCL_LINE + } + } + } + fprintf(fp, "VLPROF stat ticks %" PRIu64 "\n", tickEnd - m_tickBegin); + + std::fclose(fp); +} diff --git a/include/verilated_profiler.h b/include/verilated_profiler.h index 46df1c249..1f2ecf21b 100644 --- a/include/verilated_profiler.h +++ b/include/verilated_profiler.h @@ -12,7 +12,7 @@ //============================================================================= /// /// \file -/// \brief Verilated general profiling header +/// \brief Verilated run-time profiling header /// /// This file is not part of the Verilated public-facing API. /// It is only for internal use by Verilated library routines. @@ -23,58 +23,204 @@ #define VERILATOR_VERILATED_PROFILER_H_ #include "verilatedos.h" -#include "verilated.h" // for VerilatedMutex and clang annotations -#include +#ifndef VL_PROFILER +#error "verilated_profiler.h/cpp expects VL_PROFILER (from --prof-{exec, pgo}" +#endif + +#include "verilated.h" + +#include +#include +#include #include +#include +#include + +class VlExecutionProfiler; + +//============================================================================= +// Macros to simplify generated code + +#define VL_EXEC_TRACE_ADD_RECORD(vlSymsp) \ + if (VL_UNLIKELY((vlSymsp)->__Vm_executionProfiler.enabled())) \ + (vlSymsp)->__Vm_executionProfiler.addRecord() + +//============================================================================= +// Return high-precision counter for profiling, or 0x0 if not available +VL_ATTR_ALWINLINE +inline QData VL_CPU_TICK() { + vluint64_t val; + VL_GET_CPU_TICK(val); + return val; +} + +//============================================================================= +// Private class used by VlExecutionProfiler + +#define _VL_FOREACH_APPLY(macro, arg) macro(arg, #arg) + +// clang-format off +#define FOREACH_VlExecutionRecord_TYPE(macro) \ + _VL_FOREACH_APPLY(macro, EVAL_BEGIN) \ + _VL_FOREACH_APPLY(macro, EVAL_END) \ + _VL_FOREACH_APPLY(macro, EVAL_LOOP_BEGIN) \ + _VL_FOREACH_APPLY(macro, EVAL_LOOP_END) \ + _VL_FOREACH_APPLY(macro, MTASK_BEGIN) \ + _VL_FOREACH_APPLY(macro, MTASK_END) +// clang-format on + +class VlExecutionRecord final { + friend class VlExecutionProfiler; + + // TYPES + enum class Type : uint8_t { +#define VL_FOREACH_MACRO(id, name) id, + FOREACH_VlExecutionRecord_TYPE(VL_FOREACH_MACRO) +#undef VL_FOREACH_MACRO + }; + + static constexpr const char* const s_ascii[] = { +#define VL_FOREACH_MACRO(id, name) name, + FOREACH_VlExecutionRecord_TYPE(VL_FOREACH_MACRO) +#undef VL_FOREACH_MACRO + }; + + union Payload { + struct { + vluint32_t m_id; // MTask id + vluint32_t m_predictStart; // Time scheduler predicted would start + vluint32_t m_cpu; // Executing CPU id + } mtaskBegin; + struct { + vluint32_t m_id; // MTask id + vluint32_t m_predictCost; // How long scheduler predicted would take + } mtaskEnd; + }; + + // STATE + // Layout below allows efficient packing. + const vluint64_t m_tick = VL_CPU_TICK(); // Tick at construction + Payload m_payload; // The record payload + Type m_type; // The record type + static_assert(alignof(vluint64_t) >= alignof(Payload), "Padding not allowed"); + static_assert(alignof(Payload) >= alignof(Type), "Padding not allowed"); + + static vluint16_t getcpu(); // Return currently executing CPU id -// Profile record, private class used only by this header -class VerilatedProfilerRec final { - const std::string m_name; // Hashed name of mtask/etc - const size_t m_counterNumber = 0; // Which counter has data public: + // CONSTRUCTOR + VlExecutionRecord() = default; + // METHODS - VerilatedProfilerRec(size_t counterNumber, const std::string& name) - : m_name{name} - , m_counterNumber{counterNumber} {} - VerilatedProfilerRec() = default; - size_t counterNumber() const { return m_counterNumber; } - std::string name() const { return m_name; } + void evalBegin() { m_type = Type::EVAL_BEGIN; } + void evalEnd() { m_type = Type::EVAL_END; } + void evalLoopBegin() { m_type = Type::EVAL_LOOP_BEGIN; } + void evalLoopEnd() { m_type = Type::EVAL_LOOP_END; } + void mtaskBegin(vluint32_t id, vluint32_t predictStart) { + m_payload.mtaskBegin.m_id = id; + m_payload.mtaskBegin.m_predictStart = predictStart; + m_payload.mtaskBegin.m_cpu = getcpu(); + m_type = Type::MTASK_BEGIN; + } + void mtaskEnd(vluint32_t id, vluint32_t predictCost) { + m_payload.mtaskEnd.m_id = id; + m_payload.mtaskEnd.m_predictCost = predictCost; + m_type = Type::MTASK_END; + } }; -// Create some number of bucketed profilers -template class VerilatedProfiler final { - // Counters are stored packed, all together, versus in VerilatedProfilerRec to - // reduce cache effects - std::array m_counters{}; // Time spent on this record - std::deque m_records; // Record information +static_assert(std::is_trivially_destructible::value, + "VlExecutionRecord should be trivially destructible for fast buffer clearing"); + +//============================================================================= +// VlExecutionProfiler is for collecting profiling data about model execution + +class VlExecutionProfiler final { + // CONSTANTS + + // In order to try to avoid dynamic memory allocations during the actual profiling phase, + // trace buffers are pre-allocated to be able to hold [a multiple] of this many records. + static constexpr size_t RESERVED_TRACE_CAPACITY = 4096; + + // TYPES + + // Execution traces are recorded into thread local vectors. We can append records of profiling + // events to this vector with very low overhead, and then dump them out later. This prevents + // the overhead of printf/malloc/IO from corrupting the profiling data. It's super cheap to + // append a VlProfileRec struct on the end of a pre-allocated vector; this is the only cost we + // pay in real-time during a profiling cycle. Internal note: Globals may multi-construct, see + // verilated.cpp top. + using ExecutionTrace = std::vector; + + // STATE + static VL_THREAD_LOCAL ExecutionTrace t_trace; // thread-local trace buffers + VerilatedMutex m_mutex; + // Map from thread id to &t_trace of given thread + std::map m_traceps VL_GUARDED_BY(m_mutex); + + bool m_enabled = false; // Is profiling currently enabled + + vluint64_t m_tickBegin = 0; // Sample time (rdtsc() on x86) at beginning of collection + vluint64_t m_lastStartReq = 0; // Last requested profiling start (in simulation time) + vluint32_t m_windowCount = 0; // Track our position in the cache warmup and profile window + +public: + // CONSTRUCTOR + VlExecutionProfiler(); + + // METHODS + + // Is profiling enabled + inline bool enabled() const { return m_enabled; } + // Append a trace record to the trace buffer of the current thread + inline VlExecutionRecord& addRecord() { + t_trace.emplace_back(); + return t_trace.back(); + } + // Configure profiler (called in beginning of 'eval') + void configure(const VerilatedContext&); + // Setup profiling on a particular thread; + void setupThread(uint32_t threadId); + // Clear all profiling data + void clear() VL_MT_SAFE_EXCLUDES(m_mutex); + // Write profiling data into file + void dump(const char* filenamep, vluint64_t tickEnd) VL_MT_SAFE_EXCLUDES(m_mutex); +}; + +//============================================================================= +// VlPgoProfiler is for collecting profiling data for PGO + +template class VlPgoProfiler final { + // TYPES + struct Record final { + const std::string m_name; // Hashed name of mtask/etc + const size_t m_counterNumber = 0; // Which counter has data + }; + + // Counters are stored packed, all together to reduce cache effects + std::array m_counters; // Time spent on this record + std::vector m_records; // Record information public: // METHODS - VerilatedProfiler() = default; - ~VerilatedProfiler() = default; + VlPgoProfiler() = default; + ~VlPgoProfiler() = default; void write(const char* modelp, const std::string& filename) VL_MT_SAFE; void addCounter(size_t counter, const std::string& name) { VL_DEBUG_IF(assert(counter < T_Entries);); - m_records.emplace_back(VerilatedProfilerRec{counter, name}); + m_records.emplace_back(Record{name, counter}); } void startCounter(size_t counter) { - vluint64_t val; - VL_RDTSC(val); - // -= so when we add end time in stopCounter, we already subtracted - // out, without needing to hold another temporary - m_counters[counter] -= val; - } - void stopCounter(size_t counter) { - vluint64_t val; - VL_RDTSC(val); - m_counters[counter] += val; + // -= so when we add end time in stopCounter, the net effect is adding the difference, + // without needing to hold onto a temporary + m_counters[counter] -= VL_CPU_TICK(); } + void stopCounter(size_t counter) { m_counters[counter] += VL_CPU_TICK(); } }; template -void VerilatedProfiler::write(const char* modelp, - const std::string& filename) VL_MT_SAFE { +void VlPgoProfiler::write(const char* modelp, const std::string& filename) VL_MT_SAFE { static VerilatedMutex s_mutex; const VerilatedLockGuard lock{s_mutex}; @@ -88,14 +234,9 @@ void VerilatedProfiler::write(const char* modelp, VL_DEBUG_IF(VL_DBG_MSGF("+prof+vlt+file writing to '%s'\n", filename.c_str());); - FILE* fp = nullptr; - if (!s_firstCall) fp = std::fopen(filename.c_str(), "a"); - if (VL_UNLIKELY(!fp)) - fp = std::fopen(filename.c_str(), "w"); // firstCall, or doesn't exist yet + FILE* const fp = std::fopen(filename.c_str(), s_firstCall ? "w" : "a"); if (VL_UNLIKELY(!fp)) { VL_FATAL_MT(filename.c_str(), 0, "", "+prof+vlt+file file not writable"); - // cppcheck-suppress resourceLeak // bug, doesn't realize fp is nullptr - return; // LCOV_EXCL_LINE } s_firstCall = false; @@ -104,10 +245,9 @@ void VerilatedProfiler::write(const char* modelp, fprintf(fp, "// Verilated model profile-guided optimization data dump file\n"); fprintf(fp, "`verilator_config\n"); - for (const auto& it : m_records) { - const std::string& name = it.name(); + for (const Record& rec : m_records) { fprintf(fp, "profile_data -model \"%s\" -mtask \"%s\" -cost 64'd%" PRIu64 "\n", modelp, - name.c_str(), m_counters[it.counterNumber()]); + rec.m_name.c_str(), m_counters[rec.m_counterNumber]); } std::fclose(fp); diff --git a/include/verilated_threads.cpp b/include/verilated_threads.cpp index 6051b8967..525143244 100644 --- a/include/verilated_threads.cpp +++ b/include/verilated_threads.cpp @@ -24,8 +24,11 @@ #include "verilatedos.h" #include "verilated_threads.h" +#ifdef VL_PROFILER +#include "verilated_profiler.h" +#endif + #include -#include #include #include @@ -36,8 +39,6 @@ std::atomic VlMTaskVertex::s_yields; -VL_THREAD_LOCAL VlThreadPool::ProfileTrace* VlThreadPool::t_profilep = nullptr; - //============================================================================= // VlMTaskVertex @@ -50,12 +51,11 @@ VlMTaskVertex::VlMTaskVertex(vluint32_t upstreamDepCount) //============================================================================= // VlWorkerThread -VlWorkerThread::VlWorkerThread(VlThreadPool* poolp, VerilatedContext* contextp, bool profiling) +VlWorkerThread::VlWorkerThread(uint32_t threadId, VerilatedContext* contextp, + VlExecutionProfiler* profilerp) : m_ready_size{0} - , m_poolp{poolp} - , m_profiling{profiling} // Must init this last -- after setting up fields that it might read: , m_exiting{false} - , m_cthread{startWorker, this} + , m_cthread{startWorker, this, threadId, profilerp} , m_contextp{contextp} {} VlWorkerThread::~VlWorkerThread() { @@ -66,8 +66,6 @@ VlWorkerThread::~VlWorkerThread() { } void VlWorkerThread::workerLoop() { - if (VL_UNLIKELY(m_profiling)) m_poolp->setupProfilingClientThread(); - ExecRec work; work.m_fnp = nullptr; @@ -82,143 +80,42 @@ void VlWorkerThread::workerLoop() { work.m_fnp = nullptr; } } - - if (VL_UNLIKELY(m_profiling)) m_poolp->tearDownProfilingClientThread(); } -void VlWorkerThread::startWorker(VlWorkerThread* workerp) { +void VlWorkerThread::startWorker(VlWorkerThread* workerp, uint32_t threadId, + VlExecutionProfiler* profilerp) { Verilated::threadContextp(workerp->m_contextp); +#ifdef VL_PROFILER + // Note: setupThread is not defined without VL_PROFILER, hence the #ifdef. Still, we might + // not be profiling execution (e.g.: PGO only), so profilerp might still be nullptr. + if (profilerp) profilerp->setupThread(threadId); +#endif workerp->workerLoop(); } //============================================================================= // VlThreadPool -VlThreadPool::VlThreadPool(VerilatedContext* contextp, int nThreads, bool profiling) - : m_profiling{profiling} { +VlThreadPool::VlThreadPool(VerilatedContext* contextp, int nThreads, + VlExecutionProfiler* profiler) { // --threads N passes nThreads=N-1, as the "main" threads counts as 1 + ++nThreads; const unsigned cpus = std::thread::hardware_concurrency(); - if (cpus < nThreads + 1) { + if (cpus < nThreads) { static int warnedOnce = 0; if (!warnedOnce++) { VL_PRINTF_MT("%%Warning: System has %u CPUs but model Verilated with" " --threads %d; may run slow.\n", - cpus, nThreads + 1); + cpus, nThreads); } } - // Create'em - for (int i = 0; i < nThreads; ++i) { - m_workers.push_back(new VlWorkerThread{this, contextp, profiling}); + // Create worker threads + for (uint32_t threadId = 1; threadId < nThreads; ++threadId) { + m_workers.push_back(new VlWorkerThread{threadId, contextp, profiler}); } - // Set up a profile buffer for the current thread too -- on the - // assumption that it's the same thread that calls eval and may be - // donated to run mtasks during the eval. - if (VL_UNLIKELY(m_profiling)) setupProfilingClientThread(); } VlThreadPool::~VlThreadPool() { // Each ~WorkerThread will wait for its thread to exit. for (auto& i : m_workers) delete i; - if (VL_UNLIKELY(m_profiling)) tearDownProfilingClientThread(); -} - -void VlThreadPool::tearDownProfilingClientThread() { - assert(t_profilep); - delete t_profilep; - t_profilep = nullptr; -} - -void VlThreadPool::setupProfilingClientThread() VL_MT_SAFE_EXCLUDES(m_mutex) { - assert(!t_profilep); - t_profilep = new ProfileTrace; - // Reserve some space in the thread-local profiling buffer; - // try not to malloc while collecting profiling. - t_profilep->reserve(4096); - { - const VerilatedLockGuard lock{m_mutex}; - m_allProfiles.insert(t_profilep); - } -} - -void VlThreadPool::profileAppendAll(const VlProfileRec& rec) VL_MT_SAFE_EXCLUDES(m_mutex) { - const VerilatedLockGuard lock{m_mutex}; - for (const auto& profilep : m_allProfiles) { - // Every thread's profile trace gets a copy of rec. - profilep->emplace_back(rec); - } -} - -void VlThreadPool::profileDump(const char* filenamep, vluint64_t tickStart, vluint64_t tickEnd) - VL_MT_SAFE_EXCLUDES(m_mutex) { - const VerilatedLockGuard lock{m_mutex}; - VL_DEBUG_IF(VL_DBG_MSGF("+prof+threads writing to '%s'\n", filenamep);); - - FILE* const fp = std::fopen(filenamep, "w"); - if (VL_UNLIKELY(!fp)) { - VL_FATAL_MT(filenamep, 0, "", "+prof+threads+file file not writable"); - // cppcheck-suppress resourceLeak // bug, doesn't realize fp is nullptr - return; // LCOV_EXCL_LINE - } - - // TODO Perhaps merge with verilated_coverage output format, so can - // have a common merging and reporting tool, etc. - fprintf(fp, "VLPROFTHREAD 1.1 # Verilator thread profile dump version 1.1\n"); - fprintf(fp, "VLPROF arg --threads %" PRIu64 "\n", vluint64_t(m_workers.size() + 1)); - fprintf(fp, "VLPROF arg +verilator+prof+threads+start+%" PRIu64 "\n", - Verilated::threadContextp()->profThreadsStart()); - fprintf(fp, "VLPROF arg +verilator+prof+threads+window+%u\n", - Verilated::threadContextp()->profThreadsWindow()); - fprintf(fp, "VLPROF stat yields %" PRIu64 "\n", VlMTaskVertex::yields()); - - // Copy /proc/cpuinfo into this output so verilator_gantt can be run on - // a different machine - { - const std::unique_ptr ifp{new std::ifstream("/proc/cpuinfo")}; - if (!ifp->fail()) { - std::string line; - while (std::getline(*ifp, line)) { fprintf(fp, "VLPROFPROC %s\n", line.c_str()); } - } - } - - vluint32_t thread_id = 0; - for (const auto& pi : m_allProfiles) { - ++thread_id; - - bool printing = false; // False while in warmup phase - for (const auto& ei : *pi) { - switch (ei.m_type) { - case VlProfileRec::TYPE_BARRIER: // - printing = true; - break; - case VlProfileRec::TYPE_EVAL: - if (!printing) break; - fprintf(fp, - "VLPROF eval start %" PRIu64 " elapsed %" PRIu64 " cpu %u on thread %u\n", - ei.m_startTime - tickStart, (ei.m_endTime - ei.m_startTime), ei.m_cpu, - thread_id); - break; - case VlProfileRec::TYPE_EVAL_LOOP: - if (!printing) break; - fprintf(fp, - "VLPROF eval_loop start %" PRIu64 " elapsed %" PRIu64 - " cpu %u on thread %u\n", - ei.m_startTime - tickStart, (ei.m_endTime - ei.m_startTime), ei.m_cpu, - thread_id); - break; - case VlProfileRec::TYPE_MTASK_RUN: - if (!printing) break; - fprintf(fp, - "VLPROF mtask %d" - " start %" PRIu64 " elapsed %" PRIu64 - " predict_start %u predict_cost %u cpu %u on thread %u\n", - ei.m_mtaskId, ei.m_startTime - tickStart, (ei.m_endTime - ei.m_startTime), - ei.m_predictStart, ei.m_predictCost, ei.m_cpu, thread_id); - break; - default: assert(false); break; // LCOV_EXCL_LINE - } - } - } - fprintf(fp, "VLPROF stat ticks %" PRIu64 "\n", tickEnd - tickStart); - - std::fclose(fp); } diff --git a/include/verilated_threads.h b/include/verilated_threads.h index ffaf02e98..76512ba06 100644 --- a/include/verilated_threads.h +++ b/include/verilated_threads.h @@ -35,8 +35,10 @@ #error "verilated_threads.h/cpp expected VL_THREADED (from verilator --threads)" #endif +#include #include #include +#include #include // clang-format off @@ -127,64 +129,7 @@ public: } }; -// Profiling support -class VlProfileRec final { -protected: - friend class VlThreadPool; - enum VlProfileE { TYPE_MTASK_RUN, TYPE_EVAL, TYPE_EVAL_LOOP, TYPE_BARRIER }; - // Layout below allows efficient packing. - // Leave endTime first, so no math needed to calculate address in endRecord - vluint64_t m_endTime = 0; // Tick at end of execution - vluint64_t m_startTime = 0; // Tick at start of execution - vluint32_t m_mtaskId = 0; // Mtask we're logging - vluint32_t m_predictStart = 0; // Time scheduler predicted would start - vluint32_t m_predictCost = 0; // How long scheduler predicted would take - VlProfileE m_type = TYPE_BARRIER; // Record type - unsigned m_cpu; // Execution CPU number (at start anyways) -public: - class Barrier {}; - VlProfileRec() = default; - explicit VlProfileRec(Barrier) { m_cpu = getcpu(); } - void startEval(vluint64_t time) { - m_type = VlProfileRec::TYPE_EVAL; - m_startTime = time; - m_cpu = getcpu(); - } - void startEvalLoop(vluint64_t time) { - m_type = VlProfileRec::TYPE_EVAL_LOOP; - m_startTime = time; - m_cpu = getcpu(); - } - void startRecord(vluint64_t time, vluint32_t mtask, vluint32_t predictStart, - vluint32_t predictCost) { - m_type = VlProfileRec::TYPE_MTASK_RUN; - m_mtaskId = mtask; - m_predictStart = predictStart; - m_predictCost = predictCost; - m_startTime = time; - m_cpu = getcpu(); - } - void endRecord(vluint64_t time) { m_endTime = time; } - static int getcpu() { // Return current executing CPU -#if defined(__linux) - return sched_getcpu(); -#elif defined(__APPLE__) && !defined(__arm64__) - vluint32_t info[4]; - __cpuid_count(1, 0, info[0], info[1], info[2], info[3]); - // info[1] is EBX, bits 24-31 are APIC ID - if ((info[3] & (1 << 9)) == 0) { - return -1; // no APIC on chip - } else { - return (unsigned)info[1] >> 24; - } -#elif defined(_WIN32) - return GetCurrentProcessorNumber(); -#else - return 0; -#endif - } -}; - +class VlExecutionProfiler; class VlThreadPool; class VlWorkerThread final { @@ -217,9 +162,6 @@ private: // Store the size atomically, so we can spin wait std::atomic m_ready_size; - VlThreadPool* const m_poolp; // Our associated thread pool - - const bool m_profiling; // Is profiling enabled? std::atomic m_exiting; // Worker thread should exit std::thread m_cthread; // Underlying C++ thread record VerilatedContext* const m_contextp; // Context for spawned thread @@ -228,7 +170,8 @@ private: public: // CONSTRUCTORS - explicit VlWorkerThread(VlThreadPool* poolp, VerilatedContext* contextp, bool profiling); + explicit VlWorkerThread(uint32_t threadId, VerilatedContext* contextp, + VlExecutionProfiler* profilerp); ~VlWorkerThread(); // METHODS @@ -265,34 +208,20 @@ public: if (notify) m_cv.notify_one(); } void workerLoop(); - static void startWorker(VlWorkerThread* workerp); + static void startWorker(VlWorkerThread* workerp, uint32_t threadId, + VlExecutionProfiler* profilerp); }; class VlThreadPool final { - // TYPES - using ProfileTrace = std::vector; - // MEMBERS std::vector m_workers; // our workers - const bool m_profiling; // is profiling enabled? - - // Support profiling -- we can append records of profiling events - // to this vector with very low overhead, and then dump them out - // later. This prevents the overhead of printf/malloc/IO from - // corrupting the profiling data. It's super cheap to append - // a VlProfileRec struct on the end of a pre-allocated vector; - // this is the only cost we pay in real-time during a profiling cycle. - // Internal note: Globals may multi-construct, see verilated.cpp top. - static VL_THREAD_LOCAL ProfileTrace* t_profilep; - std::set m_allProfiles VL_GUARDED_BY(m_mutex); - VerilatedMutex m_mutex; public: // CONSTRUCTORS // Construct a thread pool with 'nThreads' dedicated threads. The thread // pool will create these threads and make them available to execute tasks // via this->workerp(index)->addTask(...) - VlThreadPool(VerilatedContext* contextp, int nThreads, bool profiling); + VlThreadPool(VerilatedContext* contextp, int nThreads, VlExecutionProfiler* profilerp); ~VlThreadPool(); // METHODS @@ -302,17 +231,6 @@ public: assert(index < m_workers.size()); return m_workers[index]; } - inline VlProfileRec* profileAppend() { - t_profilep->emplace_back(); - return &(t_profilep->back()); - } - void profileAppendAll(const VlProfileRec& rec) VL_MT_SAFE_EXCLUDES(m_mutex); - void profileDump(const char* filenamep, vluint64_t tickStart, vluint64_t tickEnd) - VL_MT_SAFE_EXCLUDES(m_mutex); - // In profiling mode, each executing thread must call - // this once to setup profiling state: - void setupProfilingClientThread() VL_MT_SAFE_EXCLUDES(m_mutex); - void tearDownProfilingClientThread(); private: VL_UNCOPYABLE(VlThreadPool); diff --git a/include/verilatedos.h b/include/verilatedos.h index b20f1419f..324cc4332 100644 --- a/include/verilatedos.h +++ b/include/verilatedos.h @@ -438,7 +438,7 @@ using ssize_t = uint32_t; ///< signed size_t; returned from read() #if defined(__i386__) || defined(__x86_64__) // The vluint64_t argument is loaded with a high-performance counter for profiling // or 0x0 if not implemented on this platform -#define VL_RDTSC(val) \ +#define VL_GET_CPU_TICK(val) \ { \ vluint32_t hi, lo; \ asm volatile("rdtsc" : "=a"(lo), "=d"(hi)); \ @@ -446,14 +446,14 @@ using ssize_t = uint32_t; ///< signed size_t; returned from read() } #elif defined(__aarch64__) // 1 GHz virtual system timer on SBSA level 5 compliant systems, else often 100 MHz -# define VL_RDTSC(val) \ +# define VL_GET_CPU_TICK(val) \ { \ asm volatile("isb" : : : "memory"); \ asm volatile("mrs %[rt],CNTVCT_EL0" : [rt] "=r"(val)); \ } #else // We just silently ignore unknown OSes, as only leads to missing statistics -# define VL_RDTSC(val) (val) = 0; +# define VL_GET_CPU_TICK(val) (val) = 0; #endif //========================================================================= diff --git a/src/V3EmitCImp.cpp b/src/V3EmitCImp.cpp index 94a314015..e4c48c181 100644 --- a/src/V3EmitCImp.cpp +++ b/src/V3EmitCImp.cpp @@ -63,7 +63,7 @@ class EmitCGatherDependencies final : VNVisitor { UASSERT_OBJ(selfPointer.find("vlSymsp") != string::npos, nodep, "Unknown self pointer: '" << selfPointer << "'"); // Dereferencing vlSymsp, so we need it's definition... - m_dependencies.insert(EmitCBaseVisitor::symClassName()); + addSymsDependency(); } } @@ -117,9 +117,7 @@ class EmitCGatherDependencies final : VNVisitor { iterateChildrenConst(nodep); } virtual void visit(AstNodeSimpleText* nodep) override { - if (nodep->text().find("vlSymsp") != string::npos) { - m_dependencies.insert(EmitCBaseVisitor::symClassName()); - } + if (nodep->text().find("vlSymsp") != string::npos) addSymsDependency(); iterateChildrenConst(nodep); } virtual void visit(AstNode* nodep) override { iterateChildrenConst(nodep); } diff --git a/src/V3EmitCMake.cpp b/src/V3EmitCMake.cpp index b1919bf59..926228c83 100644 --- a/src/V3EmitCMake.cpp +++ b/src/V3EmitCMake.cpp @@ -178,6 +178,9 @@ class CMakeEmitter final { if (v3Global.opt.mtasks()) { global.emplace_back("${VERILATOR_ROOT}/include/verilated_threads.cpp"); } + if (v3Global.opt.usesProfiler()) { + global.emplace_back("${VERILATOR_ROOT}/include/verilated_profiler.cpp"); + } if (!v3Global.opt.libCreate().empty()) { global.emplace_back(v3Global.opt.makeDir() + "/" + v3Global.opt.libCreate() + ".cpp"); } diff --git a/src/V3EmitCModel.cpp b/src/V3EmitCModel.cpp index 84b08d76b..e04c79f7e 100644 --- a/src/V3EmitCModel.cpp +++ b/src/V3EmitCModel.cpp @@ -330,21 +330,14 @@ class EmitCModel final : public EmitCFunc { if (initial) puts(topModNameProtected + "__" + protect("_eval_settle") + "(&(vlSymsp->TOP));\n"); - const string recName = "__Vprfloop"; - if (v3Global.opt.profThreads() && !initial) { - puts("VlProfileRec* " + recName + " = nullptr;\n"); - // Leave this if() here, as don't want to call VL_RDTSC_Q unless profiling - puts("if (VL_UNLIKELY(vlSymsp->__Vm_profile_cycle_start)) {\n"); - // Eval start - puts(/**/ recName + " = vlSymsp->__Vm_threadPoolp->profileAppend();\n"); - puts(/**/ recName + "->startEvalLoop(VL_RDTSC_Q());\n"); - puts("}\n"); + if (v3Global.opt.profExec() && !initial) { + puts("VL_EXEC_TRACE_ADD_RECORD(vlSymsp).evalLoopBegin();\n"); } puts(topModNameProtected + "__" + protect("_eval") + "(&(vlSymsp->TOP));\n"); - if (v3Global.opt.profThreads() && !initial) { - puts("if (VL_UNLIKELY(" + recName + ")) " + recName + "->endRecord(VL_RDTSC_Q());\n"); + if (v3Global.opt.profExec() && !initial) { + puts("VL_EXEC_TRACE_ADD_RECORD(vlSymsp).evalLoopEnd();\n"); } if (v3Global.rootp()->changeRequest()) { @@ -434,61 +427,9 @@ class EmitCModel final : public EmitCFunc { puts("Verilated::mtaskId(" + cvtToStr(mtaskId) + ");\n"); } - if (v3Global.opt.profThreads()) { - puts("if (VL_UNLIKELY((vlSymsp->_vm_contextp__->profThreadsStart() != " - "vlSymsp->__Vm_profile_time_finished)\n"); - puts(" && (VL_TIME_Q() > vlSymsp->_vm_contextp__->profThreadsStart())\n"); - puts(" && (vlSymsp->_vm_contextp__->profThreadsWindow() >= 1))) {\n"); - // Within a profile (either starting, middle, or end) - puts(/**/ "if (vlSymsp->__Vm_profile_window_ct == 0) {\n"); // Opening file? - puts(/**/ "VL_DEBUG_IF(VL_DBG_MSGF(\"+ profile start warmup\\n\"););\n"); - // Start profile on this cycle. We'll capture a window worth, then - // only analyze the next window worth. The idea is that the first window - // capture will hit some cache-cold stuff (eg printf) but it'll be warm - // by the time we hit the second window, we hope. - puts(/****/ "vlSymsp->__Vm_profile_cycle_start = VL_RDTSC_Q();\n"); - // "* 2" as first half is warmup, second half is collection - puts(/****/ "vlSymsp->__Vm_profile_window_ct" - " = vlSymsp->_vm_contextp__->profThreadsWindow()" - " * 2 + 1;\n"); - puts(/**/ "}\n"); - puts(/**/ "--(vlSymsp->__Vm_profile_window_ct);\n"); - puts(/**/ "if (vlSymsp->__Vm_profile_window_ct" - " == vlSymsp->_vm_contextp__->profThreadsWindow()) {\n"); - // This barrier record in every threads' profile demarcates the - // cache-warm-up cycles before the barrier from the actual profile - // cycles afterward. - puts(/****/ "vlSymsp->__Vm_threadPoolp->profileAppendAll("); - puts(/****/ "VlProfileRec{VlProfileRec::Barrier{}});\n"); - puts(/****/ "vlSymsp->__Vm_profile_cycle_start = VL_RDTSC_Q();\n"); - puts(/**/ "}\n"); - // Ending trace file? - puts(/**/ "else if (vlSymsp->__Vm_profile_window_ct == 0) {\n"); - puts(/****/ "vluint64_t tick_end = VL_RDTSC_Q();\n"); - puts(/****/ "VL_DEBUG_IF(VL_DBG_MSGF(\"+ profile end\\n\"););\n"); - puts(/****/ "vlSymsp->__Vm_threadPoolp->profileDump(" - "vlSymsp->_vm_contextp__->profThreadsFilename().c_str(), " - "vlSymsp->__Vm_profile_cycle_start, " - "tick_end);\n"); - // This turns off the test to enter the profiling code, but still - // allows the user to collect another profile by changing - // profThreadsStart - puts(/****/ "vlSymsp->__Vm_profile_time_finished = " - "vlSymsp->_vm_contextp__->profThreadsStart();\n"); - puts(/****/ "vlSymsp->__Vm_profile_cycle_start = 0;\n"); - puts(/**/ "}\n"); - puts("}\n"); - } - - const string recName = "__Vprfeval"; - if (v3Global.opt.profThreads()) { - puts("VlProfileRec* " + recName + " = nullptr;\n"); - // Leave this if() here, as don't want to call VL_RDTSC_Q unless profiling - puts("if (VL_UNLIKELY(vlSymsp->__Vm_profile_cycle_start)) {\n"); - // Eval start - puts(/**/ recName + " = vlSymsp->__Vm_threadPoolp->profileAppend();\n"); - puts(/**/ recName + "->startEval(VL_RDTSC_Q());\n"); - puts("}\n"); + if (v3Global.opt.profExec()) { + puts("vlSymsp->__Vm_executionProfiler.configure(*(vlSymsp->_vm_contextp__));\n"); + puts("VL_EXEC_TRACE_ADD_RECORD(vlSymsp).evalBegin();\n"); } emitSettleLoop(modp, /* initial: */ false); @@ -499,10 +440,7 @@ class EmitCModel final : public EmitCFunc { } if (v3Global.opt.threads()) puts("Verilated::endOfEval(vlSymsp->__Vm_evalMsgQp);\n"); - if (v3Global.opt.profThreads()) { - // End eval record - puts("if (VL_UNLIKELY(" + recName + ")) " + recName + "->endRecord(VL_RDTSC_Q());\n"); - } + if (v3Global.opt.profExec()) puts("VL_EXEC_TRACE_ADD_RECORD(vlSymsp).evalEnd();\n"); puts("}\n"); } diff --git a/src/V3EmitCSyms.cpp b/src/V3EmitCSyms.cpp index 53fa6f628..8857c23d8 100644 --- a/src/V3EmitCSyms.cpp +++ b/src/V3EmitCSyms.cpp @@ -395,7 +395,7 @@ void EmitCSyms::emitSymHdr() { if (v3Global.needTraceDumper()) { puts("#include \"" + v3Global.opt.traceSourceLang() + ".h\"\n"); } - if (v3Global.opt.profThreads()) puts("#include \"verilated_profiler.h\"\n"); + if (v3Global.opt.usesProfiler()) puts("#include \"verilated_profiler.h\"\n"); puts("\n// INCLUDE MODEL CLASS\n"); puts("\n#include \"" + topClassName() + ".h\"\n"); @@ -445,18 +445,15 @@ void EmitCSyms::emitSymHdr() { } puts("bool __Vm_didInit = false;\n"); + if (v3Global.opt.profExec()) { + puts("\n// EXECUTION PROFILING\n"); + puts("VlExecutionProfiler __Vm_executionProfiler;\n"); + } + if (v3Global.opt.mtasks()) { + puts("\n// MULTI-THREADING\n"); puts("VlThreadPool* const __Vm_threadPoolp;\n"); puts("bool __Vm_even_cycle = false;\n"); - - if (v3Global.opt.profThreads()) { - // rdtsc() at current cycle start - puts("vluint64_t __Vm_profile_cycle_start = 0;\n"); - // Time we finished analysis - puts("vluint64_t __Vm_profile_time_finished = 0;\n"); - // Track our position in the cache warmup and actual profile window - puts("vluint32_t __Vm_profile_window_ct = 0;\n"); - } } puts("\n// MODULE INSTANCE STATE\n"); @@ -477,8 +474,8 @@ void EmitCSyms::emitSymHdr() { puts("];\n"); } - if (v3Global.opt.profThreads()) { - puts("\n// PROFILING\n"); + if (v3Global.opt.profPgo()) { + puts("\n// PGO PROFILING\n"); vluint64_t maxProfilerId = 0; if (v3Global.opt.mtasks()) { for (const V3GraphVertex* vxp @@ -490,7 +487,7 @@ void EmitCSyms::emitSymHdr() { } } ++maxProfilerId; // As size must include 0 - puts("VerilatedProfiler<" + cvtToStr(maxProfilerId) + "> _vm_profiler;\n"); + puts("VlPgoProfiler<" + cvtToStr(maxProfilerId) + "> _vm_pgoProfiler;\n"); } if (!m_scopeNames.empty()) { // Scope names @@ -682,8 +679,8 @@ void EmitCSyms::emitSymImp() { puts("if (__Vm_dumping) _traceDumpClose();\n"); puts("#endif // VM_TRACE\n"); } - if (v3Global.opt.profThreads()) { - puts("_vm_profiler.write(\"" + topClassName() + if (v3Global.opt.profPgo()) { + puts("_vm_pgoProfiler.write(\"" + topClassName() + "\", _vm_contextp__->profVltFilename());\n"); } if (v3Global.opt.mtasks()) puts("delete __Vm_threadPoolp;\n"); @@ -719,8 +716,8 @@ void EmitCSyms::emitSymImp() { // that calls eval() becomes the final Nth thread for the // duration of the eval call. puts(" , __Vm_threadPoolp{new VlThreadPool{_vm_contextp__, " - + cvtToStr(v3Global.opt.threads() - 1) + ", " + cvtToStr(v3Global.opt.profThreads()) - + "}}\n"); + + cvtToStr(v3Global.opt.threads() - 1) + ", " + + (v3Global.opt.profExec() ? "&__Vm_executionProfiler" : "nullptr") + "}}\n"); } puts(" // Setup module instances\n"); @@ -741,14 +738,14 @@ void EmitCSyms::emitSymImp() { } puts("{\n"); - if (v3Global.opt.profThreads()) { - puts("// Configure profiling\n"); + if (v3Global.opt.profPgo()) { + puts("// Configure profiling for PGO\n"); if (v3Global.opt.mtasks()) { for (const V3GraphVertex* vxp = v3Global.rootp()->execGraphp()->depGraphp()->verticesBeginp(); vxp; vxp = vxp->verticesNextp()) { ExecMTask* const mtp = dynamic_cast(const_cast(vxp)); - puts("_vm_profiler.addCounter(" + cvtToStr(mtp->profilerId()) + ", \"" + puts("_vm_pgoProfiler.addCounter(" + cvtToStr(mtp->profilerId()) + ", \"" + mtp->hashName() + "\");\n"); } } diff --git a/src/V3EmitMk.cpp b/src/V3EmitMk.cpp index 3f8024f99..e625a74a5 100644 --- a/src/V3EmitMk.cpp +++ b/src/V3EmitMk.cpp @@ -112,6 +112,9 @@ public: } } if (v3Global.opt.mtasks()) putMakeClassEntry(of, "verilated_threads.cpp"); + if (v3Global.opt.usesProfiler()) { + putMakeClassEntry(of, "verilated_profiler.cpp"); + } } else if (support == 2 && slow) { } else { for (AstNodeFile* nodep = v3Global.rootp()->filesp(); nodep; @@ -189,6 +192,7 @@ public: of.puts("# User CFLAGS (from -CFLAGS on Verilator command line)\n"); of.puts("VM_USER_CFLAGS = \\\n"); if (!v3Global.opt.libCreate().empty()) of.puts("\t-fPIC \\\n"); + if (v3Global.opt.usesProfiler()) of.puts("\t-DVL_PROFILER \\\n"); const V3StringList& cFlags = v3Global.opt.cFlags(); for (const string& i : cFlags) of.puts("\t" + i + " \\\n"); of.puts("\n"); diff --git a/src/V3Options.cpp b/src/V3Options.cpp index 57f30b2d0..1b74f1062 100644 --- a/src/V3Options.cpp +++ b/src/V3Options.cpp @@ -1236,7 +1236,13 @@ void V3Options::parseOptsList(FileLine* fl, const string& optdir, int argc, char DECL_OPTION("-prof-cfuncs", CbCall, [this]() { m_profC = m_profCFuncs = true; }); DECL_OPTION("-profile-cfuncs", CbCall, [this]() { m_profC = m_profCFuncs = true; }); // Renamed - DECL_OPTION("-prof-threads", OnOff, &m_profThreads); + DECL_OPTION("-prof-exec", OnOff, &m_profExec); + DECL_OPTION("-prof-pgo", OnOff, &m_profPgo); + DECL_OPTION("-prof-threads", CbOnOff, [this, fl](bool flag) { + fl->v3warn(DEPRECATED, "Option --prof-threads is deprecated. " + "Use --prof-exec and --prof-pgo instead."); + m_profExec = m_profPgo = flag; + }); DECL_OPTION("-protect-ids", OnOff, &m_protectIds); DECL_OPTION("-protect-key", Set, &m_protectKey); DECL_OPTION("-protect-lib", CbVal, [this](const char* valp) { diff --git a/src/V3Options.h b/src/V3Options.h index e5bcc824e..f9cf8f5d5 100644 --- a/src/V3Options.h +++ b/src/V3Options.h @@ -255,7 +255,8 @@ private: bool m_ppComments = false; // main switch: --pp-comments bool m_profC = false; // main switch: --prof-c bool m_profCFuncs = false; // main switch: --prof-cfuncs - bool m_profThreads = false; // main switch: --prof-threads + bool m_profExec = false; // main switch: --prof-exec + bool m_profPgo = false; // main switch: --prof-pgo bool m_protectIds = false; // main switch: --protect-ids bool m_public = false; // main switch: --public bool m_publicFlatRW = false; // main switch: --public-flat-rw @@ -468,7 +469,9 @@ public: bool ppComments() const { return m_ppComments; } bool profC() const { return m_profC; } bool profCFuncs() const { return m_profCFuncs; } - bool profThreads() const { return m_profThreads; } + bool profExec() const { return m_profExec; } + bool profPgo() const { return m_profPgo; } + bool usesProfiler() const { return profExec() || profPgo(); } bool protectIds() const { return m_protectIds; } bool allPublic() const { return m_public; } bool publicFlatRW() const { return m_publicFlatRW; } diff --git a/src/V3Partition.cpp b/src/V3Partition.cpp index d7b23942a..63e264809 100644 --- a/src/V3Partition.cpp +++ b/src/V3Partition.cpp @@ -2918,43 +2918,39 @@ static void addMTaskToFunction(const ThreadSchedule& schedule, const uint32_t th addStrStmt("vlSelf->" + name + +".waitUntilUpstreamDone(even_cycle);\n"); } - string recName; - if (v3Global.opt.profThreads()) { - recName = "__Vprfthr_" + cvtToStr(mtaskp->id()); - addStrStmt("VlProfileRec* " + recName + " = nullptr;\n"); - // Leave this if() here, as don't want to call VL_RDTSC_Q unless profiling - addStrStmt("if (VL_UNLIKELY(vlSymsp->__Vm_profile_cycle_start)) {\n" + // - recName + " = vlSymsp->__Vm_threadPoolp->profileAppend();\n" + // - recName + "->startRecord(VL_RDTSC_Q()," + // - " " + cvtToStr(mtaskp->id()) + "," + // - " " + cvtToStr(mtaskp->predictStart()) + "," + // - " " + cvtToStr(mtaskp->cost()) + ");\n" + // - "}\n"); + if (v3Global.opt.profExec()) { + const string& id = cvtToStr(mtaskp->id()); + const string& predictStart = cvtToStr(mtaskp->predictStart()); + addStrStmt("VL_EXEC_TRACE_ADD_RECORD(vlSymsp).mtaskBegin(" + id + ", " + predictStart + + ");\n"); } - if (v3Global.opt.profThreads()) { + if (v3Global.opt.profPgo()) { // No lock around startCounter, as counter numbers are unique per thread - addStrStmt("vlSymsp->_vm_profiler.startCounter(" + cvtToStr(mtaskp->profilerId()) + addStrStmt("vlSymsp->_vm_pgoProfiler.startCounter(" + cvtToStr(mtaskp->profilerId()) + ");\n"); } // addStrStmt("Verilated::mtaskId(" + cvtToStr(mtaskp->id()) + ");\n"); - // Move the the actual body of calls to leaf functions into this function + // Move the actual body of calls to leaf functions into this function funcp->addStmtsp(mtaskp->bodyp()->unlinkFrBack()); - if (v3Global.opt.profThreads()) { - // No lock around stopCounter, as counter numbers are unique per thread - addStrStmt("vlSymsp->_vm_profiler.stopCounter(" + cvtToStr(mtaskp->profilerId()) + ");\n"); - } - if (v3Global.opt.profThreads()) { - addStrStmt("if (VL_UNLIKELY(" + recName + ")) " // - + recName + "->endRecord(VL_RDTSC_Q());\n"); - } - // Flush message queue addStrStmt("Verilated::endOfThreadMTask(vlSymsp->__Vm_evalMsgQp);\n"); + if (v3Global.opt.profPgo()) { + // No lock around stopCounter, as counter numbers are unique per thread + addStrStmt("vlSymsp->_vm_pgoProfiler.stopCounter(" + cvtToStr(mtaskp->profilerId()) + + ");\n"); + } + if (v3Global.opt.profExec()) { + const string& id = cvtToStr(mtaskp->id()); + const string& predictConst = cvtToStr(mtaskp->cost()); + addStrStmt("VL_EXEC_TRACE_ADD_RECORD(vlSymsp).mtaskEnd(" + id + ", " + predictConst + + ");\n"); + } + // For any dependent mtask that's on another thread, signal one dependency completion. for (V3GraphEdge* edgep = mtaskp->outBeginp(); edgep; edgep = edgep->outNextp()) { const ExecMTask* const nextp = dynamic_cast(edgep->top()); diff --git a/test_regress/t/t_gantt.pl b/test_regress/t/t_gantt.pl index 66b00e554..c757d3fbe 100755 --- a/test_regress/t/t_gantt.pl +++ b/test_regress/t/t_gantt.pl @@ -9,9 +9,8 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); di # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 # Test for bin/verilator_gantt, -# -# Only needed in multithreaded regression. -scenarios(vltmt => 1); + +scenarios(vlt_all => 1); # It doesn't really matter what test # we use, so long as it runs several cycles, @@ -20,13 +19,13 @@ top_filename("t/t_gen_alw.v"); compile( # Checks below care about thread count, so use 2 (minimum reasonable) - v_flags2 => ["--prof-threads --threads 2"] + v_flags2 => ["--prof-exec", ($Self->{vltmt} ? "--threads 2" : "")] ); execute( - all_run_flags => ["+verilator+prof+threads+start+2", - " +verilator+prof+threads+window+2", - " +verilator+prof+threads+file+$Self->{obj_dir}/profile_threads.dat", + all_run_flags => ["+verilator+prof+exec+start+2", + " +verilator+prof+exec+window+2", + " +verilator+prof+exec+file+$Self->{obj_dir}/profile_exec.dat", " +verilator+prof+vlt+file+$Self->{obj_dir}/profile.vlt", ], check_finished => 1, @@ -37,17 +36,22 @@ execute( # The profiling data still goes direct to the runtime's STDOUT # (maybe that should go to a separate file - gantt.dat?) run(cmd => ["$ENV{VERILATOR_ROOT}/bin/verilator_gantt", - "$Self->{obj_dir}/profile_threads.dat", - "--vcd $Self->{obj_dir}/profile_threads.vcd", + "$Self->{obj_dir}/profile_exec.dat", + "--vcd $Self->{obj_dir}/profile_exec.vcd", "| tee $Self->{obj_dir}/gantt.log"], ); -file_grep("$Self->{obj_dir}/gantt.log", qr/Total threads += 2/i); -file_grep("$Self->{obj_dir}/gantt.log", qr/Total mtasks += 7/i); +if ($Self->{vltmt}) { + file_grep("$Self->{obj_dir}/gantt.log", qr/Total threads += 2/i); + file_grep("$Self->{obj_dir}/gantt.log", qr/Total mtasks += 7/i); +} else { + file_grep("$Self->{obj_dir}/gantt.log", qr/Total threads += 1/i); + file_grep("$Self->{obj_dir}/gantt.log", qr/Total mtasks += 0/i); +} file_grep("$Self->{obj_dir}/gantt.log", qr/Total evals += 2/i); # Diff to itself, just to check parsing -vcd_identical("$Self->{obj_dir}/profile_threads.vcd", "$Self->{obj_dir}/profile_threads.vcd"); +vcd_identical("$Self->{obj_dir}/profile_exec.vcd", "$Self->{obj_dir}/profile_exec.vcd"); ok(1); 1; diff --git a/test_regress/t/t_gantt_io.dat b/test_regress/t/t_gantt_io.dat index c20bcd6c9..f31b9f7d5 100644 --- a/test_regress/t/t_gantt_io.dat +++ b/test_regress/t/t_gantt_io.dat @@ -1,8 +1,8 @@ -VLPROFTHREAD 1.1 # Verilator thread profile dump version 1.1 -VLPROF arg --threads 2 -VLPROF arg +verilator+prof+threads+start+2 -VLPROF arg +verilator+prof+threads+window+2 +VLPROFVERSION 2.0 +VLPROF arg +verilator+prof+exec+start+2 +VLPROF arg +verilator+prof+exec+window+2 VLPROF stat yields 0 +VLPROF stat threads 2 VLPROFPROC processor : 0 VLPROFPROC vendor_id : AuthenticTest VLPROFPROC cpu family : 23 @@ -899,22 +899,42 @@ VLPROFPROC cache_alignment : 64 VLPROFPROC address sizes : 43 bits physical, 48 bits virtual VLPROFPROC power management: ts ttp tm hwpstate cpb eff_freq_ro [13] [14] VLPROFPROC -VLPROF eval start 595 elapsed 11655 cpu 19 on thread 1 -VLPROF eval_loop start 945 elapsed 11235 cpu 19 on thread 1 -VLPROF mtask 6 start 2695 elapsed 210 predict_start 0 predict_cost 30 cpu 19 on thread 1 -VLPROF mtask 10 start 9695 elapsed 175 predict_start 196 predict_cost 30 cpu 19 on thread 1 -VLPROF eval start 13720 elapsed 8610 cpu 19 on thread 1 -VLPROF eval_loop start 14000 elapsed 8085 cpu 19 on thread 1 -VLPROF mtask 6 start 15610 elapsed 210 predict_start 0 predict_cost 30 cpu 19 on thread 1 -VLPROF mtask 10 start 21700 elapsed 175 predict_start 196 predict_cost 30 cpu 19 on thread 1 -VLPROF mtask 5 start 5495 elapsed 595 predict_start 0 predict_cost 30 cpu 10 on thread 2 -VLPROF mtask 7 start 6300 elapsed 595 predict_start 30 predict_cost 30 cpu 10 on thread 2 -VLPROF mtask 8 start 7490 elapsed 1050 predict_start 60 predict_cost 107 cpu 10 on thread 2 -VLPROF mtask 9 start 9135 elapsed 595 predict_start 167 predict_cost 30 cpu 10 on thread 2 -VLPROF mtask 11 start 10255 elapsed 805 predict_start 197 predict_cost 30 cpu 10 on thread 2 -VLPROF mtask 5 start 18375 elapsed 595 predict_start 0 predict_cost 30 cpu 10 on thread 2 -VLPROF mtask 7 start 19145 elapsed 175 predict_start 30 predict_cost 30 cpu 10 on thread 2 -VLPROF mtask 8 start 19670 elapsed 140 predict_start 60 predict_cost 107 cpu 10 on thread 2 -VLPROF mtask 9 start 20650 elapsed 70 predict_start 167 predict_cost 30 cpu 10 on thread 2 -VLPROF mtask 11 start 21140 elapsed 105 predict_start 197 predict_cost 30 cpu 10 on thread 2 +VLPROFTHREAD 0 +VLPROFEXEC EVAL_BEGIN 595 +VLPROFEXEC EVAL_LOOP_BEGIN 945 +VLPROFEXEC MTASK_BEGIN 2695 id 6 predictStart 0 cpu 19 +VLPROFEXEC MTASK_END 2905 id 6 predictCost 30 +VLPROFEXEC MTASK_BEGIN 9695 id 10 predictStart 196 cpu 19 +VLPROFEXEC MTASK_END 9870 id 10 predictCost 30 +VLPROFEXEC EVAL_LOOP_END 12180 +VLPROFEXEC EVAL_END 12250 +VLPROFEXEC EVAL_BEGIN 13720 +VLPROFEXEC EVAL_LOOP_BEGIN 14000 +VLPROFEXEC MTASK_BEGIN 15610 id 6 predictStart 0 cpu 19 +VLPROFEXEC MTASK_END 15820 id 6 predictCost 30 +VLPROFEXEC MTASK_BEGIN 21700 id 10 predictStart 196 cpu 19 +VLPROFEXEC MTASK_END 21875 id 10 predictCost 30 +VLPROFEXEC EVAL_LOOP_END 22085 +VLPROFEXEC EVAL_END 22330 +VLPROFTHREAD 1 +VLPROFEXEC MTASK_BEGIN 5495 id 5 predictStart 0 cpu 10 +VLPROFEXEC MTASK_END 6090 id 5 predictCost 30 +VLPROFEXEC MTASK_BEGIN 6300 id 7 predictStart 30 cpu 10 +VLPROFEXEC MTASK_END 6895 id 7 predictCost 30 +VLPROFEXEC MTASK_BEGIN 7490 id 8 predictStart 60 cpu 10 +VLPROFEXEC MTASK_END 8540 id 8 predictCost 107 +VLPROFEXEC MTASK_BEGIN 9135 id 9 predictStart 167 cpu 10 +VLPROFEXEC MTASK_END 9730 id 9 predictCost 30 +VLPROFEXEC MTASK_BEGIN 10255 id 11 predictStart 197 cpu 10 +VLPROFEXEC MTASK_END 11060 id 11 predictCost 30 +VLPROFEXEC MTASK_BEGIN 18375 id 5 predictStart 0 cpu 10 +VLPROFEXEC MTASK_END 18970 id 5 predictCost 30 +VLPROFEXEC MTASK_BEGIN 19145 id 7 predictStart 30 cpu 10 +VLPROFEXEC MTASK_END 19320 id 7 predictCost 30 +VLPROFEXEC MTASK_BEGIN 19670 id 8 predictStart 60 cpu 10 +VLPROFEXEC MTASK_END 19810 id 8 predictCost 107 +VLPROFEXEC MTASK_BEGIN 20650 id 9 predictStart 167 cpu 10 +VLPROFEXEC MTASK_END 20720 id 9 predictCost 30 +VLPROFEXEC MTASK_BEGIN 21140 id 11 predictStart 197 cpu 10 +VLPROFEXEC MTASK_END 21245 id 11 predictCost 30 VLPROF stat ticks 23415 diff --git a/test_regress/t/t_gantt_io.out b/test_regress/t/t_gantt_io.out index f5c1c2b92..55a6f73a5 100644 --- a/test_regress/t/t_gantt_io.out +++ b/test_regress/t/t_gantt_io.out @@ -1,9 +1,8 @@ Verilator Gantt report Argument settings: - +verilator+prof+threads+start+2 - +verilator+prof+threads+window+2 - --threads 2 + +verilator+prof+exec+start+2 + +verilator+prof+exec+window+2 Analysis: Total threads = 2 @@ -23,7 +22,7 @@ Prediction (what Verilator used for scheduling): All-thread efficiency = 63.2% All-thread speedup = 1.3 -Statistics: +MTask statistics: min log(p2e) = -3.681 from mtask 5 (predict 30, elapsed 1190) max log(p2e) = -2.409 from mtask 8 (predict 107, elapsed 1190) mean = -2.992 @@ -34,4 +33,4 @@ CPUs: cpu 10: cpu_time=4725 socket=0 core=10 Test Ryzen 9 3950X 16-Core Processor cpu 19: cpu_time=770 socket=0 core=3 Test Ryzen 9 3950X 16-Core Processor -Writing profile_threads.vcd +Writing profile_exec.vcd diff --git a/test_regress/t/t_gantt_io.pl b/test_regress/t/t_gantt_io.pl index ba111c47f..d3ba7df5c 100755 --- a/test_regress/t/t_gantt_io.pl +++ b/test_regress/t/t_gantt_io.pl @@ -16,7 +16,7 @@ run(cmd => ["cd $Self->{obj_dir} && $ENV{VERILATOR_ROOT}/bin/verilator_gantt" files_identical("$Self->{obj_dir}/gantt.log", $Self->{golden_filename}); -vcd_identical("$Self->{obj_dir}/profile_threads.vcd", "$Self->{t_dir}/$Self->{name}.vcd.out"); +vcd_identical("$Self->{obj_dir}/profile_exec.vcd", "$Self->{t_dir}/$Self->{name}.vcd.out"); ok(1); 1; diff --git a/test_regress/t/t_gantt_io.vcd.out b/test_regress/t/t_gantt_io.vcd.out index 1818f54b7..7fc6ed26c 100644 --- a/test_regress/t/t_gantt_io.vcd.out +++ b/test_regress/t/t_gantt_io.vcd.out @@ -15,8 +15,8 @@ $timescale 1ns $end $var wire 32 vc eval_loop [31:0] $end $upscope $end $scope module measured_threads $end - $var wire 32 v0 thread1_mtask [31:0] $end - $var wire 32 v4 thread2_mtask [31:0] $end + $var wire 32 v0 thread0_mtask [31:0] $end + $var wire 32 v4 thread1_mtask [31:0] $end $upscope $end $scope module mtasks $end $var wire 32 v3 mtask10_cpu [31:0] $end @@ -28,8 +28,8 @@ $timescale 1ns $end $var wire 32 v9 mtask9_cpu [31:0] $end $upscope $end $scope module predicted_threads $end - $var wire 32 vd predicted_thread1_mtask [31:0] $end - $var wire 32 ve predicted_thread2_mtask [31:0] $end + $var wire 32 vd predicted_thread0_mtask [31:0] $end + $var wire 32 ve predicted_thread1_mtask [31:0] $end $upscope $end $upscope $end $enddefinitions $end @@ -65,7 +65,7 @@ b111 ve b1 v10 #2695 b110 v0 -b1 v1 +b0 v1 b10011 v2 b1 vf #2905 @@ -78,7 +78,7 @@ b1000 ve b1 v10 #5495 b101 v4 -b10 v5 +b1 v5 b1010 v6 b1 vf #6090 @@ -88,7 +88,7 @@ bz v6 b0 vf #6300 b111 v4 -b10 v5 +b1 v5 b1010 v7 b1 vf #6895 @@ -98,7 +98,7 @@ bz v7 b0 vf #7490 b1000 v4 -b10 v5 +b1 v5 b1010 v8 b1 vf #8540 @@ -108,7 +108,7 @@ bz v8 b0 vf #9135 b1001 v4 -b10 v5 +b1 v5 b1010 v9 b1 vf #9210 @@ -116,7 +116,7 @@ b1001 ve b1 v10 #9695 b1010 v0 -b1 v1 +b0 v1 b10011 v3 b10 vf #9730 @@ -131,7 +131,7 @@ bz v3 b0 vf #10255 b1011 v4 -b10 v5 +b1 v5 b1010 va b1 vf #10645 @@ -167,7 +167,7 @@ b111 ve b1 v10 #15610 b110 v0 -b1 v1 +b0 v1 b10011 v2 b1 vf #15820 @@ -180,7 +180,7 @@ b1000 ve b1 v10 #18375 b101 v4 -b10 v5 +b1 v5 b1010 v6 b1 vf #18970 @@ -190,7 +190,7 @@ bz v6 b0 vf #19145 b111 v4 -b10 v5 +b1 v5 b1010 v7 b1 vf #19320 @@ -200,7 +200,7 @@ bz v7 b0 vf #19670 b1000 v4 -b10 v5 +b1 v5 b1010 v8 b1 vf #19810 @@ -213,7 +213,7 @@ b1001 ve b1 v10 #20650 b1001 v4 -b10 v5 +b1 v5 b1010 v9 b1 vf #20720 @@ -229,7 +229,7 @@ b1011 ve b10 v10 #21140 b1011 v4 -b10 v5 +b1 v5 b1010 va b1 vf #21245 @@ -239,7 +239,7 @@ bz va b0 vf #21700 b1010 v0 -b1 v1 +b0 v1 b10011 v3 b1 vf #21875 diff --git a/test_regress/t/t_gantt_io_arm.dat b/test_regress/t/t_gantt_io_arm.dat index 33846b417..23d79c253 100644 --- a/test_regress/t/t_gantt_io_arm.dat +++ b/test_regress/t/t_gantt_io_arm.dat @@ -1,7 +1,7 @@ -VLPROFTHREAD 1.1 # Verilator thread profile dump version 1.1 -VLPROF arg --threads 4 -VLPROF arg +verilator+prof+threads+start+1 -VLPROF arg +verilator+prof+threads+window+2 +VLPROFVERSION 2.0 +VLPROF arg +verilator+prof+exec+start+1 +VLPROF arg +verilator+prof+exec+window+2 +VLPROF stat threads 2 VLPROF stat yields 51 VLPROFPROC processor : 0 VLPROFPROC model name : Phytium,FT-2500/128 @@ -43,11 +43,20 @@ VLPROFPROC CPU variant : 0x1 VLPROFPROC CPU part : 0x663 VLPROFPROC CPU revision : 3 VLPROFPROC -VLPROF eval start 57709 elapsed 1745979 cpu 2 on thread 1 -VLPROF eval_loop start 58532 elapsed 1744353 cpu 2 on thread 1 -VLPROF mtask 85 start 90465 elapsed 64569 predict_start 14315 predict_cost 30533 cpu 2 on thread 1 -VLPROF mtask 79 start 156555 elapsed 137754 predict_start 44848 predict_cost 48001 cpu 2 on thread 1 -VLPROF mtask 90 start 77352 elapsed 1159 predict_start 14315 predict_cost 21592 cpu 3 on thread 2 -VLPROF mtask 81 start 79799 elapsed 868 predict_start 35907 predict_cost 29215 cpu 3 on thread 2 -VLPROF mtask 87 start 81746 elapsed 887 predict_start 65147 predict_cost 33809 cpu 3 on thread 2 +VLPROFTHREAD 0 +VLPROFEXEC EVAL_BEGIN 57709 +VLPROFEXEC EVAL_LOOP_BEGIN 58532 +VLPROFEXEC MTASK_BEGIN 90465 id 85 predictStart 14315 cpu 2 +VLPROFEXEC MTASK_END 155034 id 85 predictCost 30533 +VLPROFEXEC MTASK_BEGIN 156555 id 79 predictStart 44848 cpu 2 +VLPROFEXEC MTASK_END 294309 id 79 predictCost 48001 +VLPROFEXEC EVAL_LOOP_END 18028850 +VLPROFEXEC EVAL_END 1803680 +VLPROFTHREAD 1 +VLPROFEXEC MTASK_BEGIN 77352 id 90 predictStart 14315 cpu 3 +VLPROFEXEC MTASK_END 78511 id 90 predictCost 21592 +VLPROFEXEC MTASK_BEGIN 79799 id 81 predictStart 35907 cpu 3 +VLPROFEXEC MTASK_END 80667 id 81 predictCost 29215 +VLPROFEXEC MTASK_BEGIN 81746 id 87 predictStart 65147 cpu 3 +VLPROFEXEC MTASK_END 82633 id 87 predictCost 33809 VLPROF stat ticks 180832 diff --git a/test_regress/t/t_gantt_io_arm.out b/test_regress/t/t_gantt_io_arm.out index d2be5b08e..75c7738ea 100644 --- a/test_regress/t/t_gantt_io_arm.out +++ b/test_regress/t/t_gantt_io_arm.out @@ -1,9 +1,8 @@ Verilator Gantt report Argument settings: - +verilator+prof+threads+start+1 - +verilator+prof+threads+window+2 - --threads 4 + +verilator+prof+exec+start+1 + +verilator+prof+exec+window+2 Analysis: Total threads = 2 @@ -23,7 +22,7 @@ Prediction (what Verilator used for scheduling): All-thread efficiency = 82.4% All-thread speedup = 1.6 -Statistics: +MTask statistics: min log(p2e) = -1.054 from mtask 79 (predict 48001, elapsed 137754) max log(p2e) = 3.641 from mtask 87 (predict 33809, elapsed 887) mean = 1.656 @@ -34,4 +33,4 @@ CPUs: cpu 2: cpu_time=202323 Phytium,FT-2500/128 cpu 3: cpu_time=2914 Phytium,FT-2500/128 -Writing profile_threads.vcd +Writing profile_exec.vcd diff --git a/test_regress/t/t_gantt_io_noproc.dat b/test_regress/t/t_gantt_io_noproc.dat index 423d57a05..a75accf62 100644 --- a/test_regress/t/t_gantt_io_noproc.dat +++ b/test_regress/t/t_gantt_io_noproc.dat @@ -1,24 +1,44 @@ -VLPROFTHREAD 1.1 # Verilator thread profile dump version 1.1 -VLPROF arg --threads 2 -VLPROF arg +verilator+prof+threads+start+2 -VLPROF arg +verilator+prof+threads+window+2 +VLPROFVERSION 2.0 +VLPROF arg +verilator+prof+exec+start+2 +VLPROF arg +verilator+prof+exec+window+2 +VLPROF stat threads 2 VLPROF stat yields 0 -VLPROF eval start 595 elapsed 11655 cpu 19 on thread 1 -VLPROF eval_loop start 945 elapsed 11235 cpu 19 on thread 1 -VLPROF mtask 6 start 2695 elapsed 210 predict_start 0 predict_cost 30 cpu 19 on thread 1 -VLPROF mtask 10 start 9695 elapsed 175 predict_start 196 predict_cost 30 cpu 19 on thread 1 -VLPROF eval start 13720 elapsed 8610 cpu 19 on thread 1 -VLPROF eval_loop start 14000 elapsed 8085 cpu 19 on thread 1 -VLPROF mtask 6 start 15610 elapsed 210 predict_start 0 predict_cost 30 cpu 19 on thread 1 -VLPROF mtask 10 start 21700 elapsed 175 predict_start 196 predict_cost 30 cpu 19 on thread 1 -VLPROF mtask 5 start 5495 elapsed 595 predict_start 0 predict_cost 30 cpu 10 on thread 2 -VLPROF mtask 7 start 6300 elapsed 595 predict_start 30 predict_cost 30 cpu 10 on thread 2 -VLPROF mtask 8 start 7490 elapsed 1050 predict_start 60 predict_cost 107 cpu 10 on thread 2 -VLPROF mtask 9 start 9135 elapsed 595 predict_start 167 predict_cost 30 cpu 10 on thread 2 -VLPROF mtask 11 start 10255 elapsed 805 predict_start 197 predict_cost 30 cpu 10 on thread 2 -VLPROF mtask 5 start 18375 elapsed 595 predict_start 0 predict_cost 30 cpu 10 on thread 2 -VLPROF mtask 7 start 19145 elapsed 175 predict_start 30 predict_cost 30 cpu 10 on thread 2 -VLPROF mtask 8 start 19670 elapsed 140 predict_start 60 predict_cost 107 cpu 10 on thread 2 -VLPROF mtask 9 start 20650 elapsed 70 predict_start 167 predict_cost 30 cpu 10 on thread 2 -VLPROF mtask 11 start 21140 elapsed 105 predict_start 197 predict_cost 30 cpu 10 on thread 2 +VLPROFTHREAD 0 +VLPROFEXEC EVAL_BEGIN 595 +VLPROFEXEC EVAL_LOOP_BEGIN 945 +VLPROFEXEC MTASK_BEGIN 2695 id 6 predictStart 0 cpu 19 +VLPROFEXEC MTASK_END 2905 id 6 predictCost 30 +VLPROFEXEC MTASK_BEGIN 9695 id 10 predictStart 196 cpu 19 +VLPROFEXEC MTASK_END 9870 id 10 predictCost 30 +VLPROFEXEC EVAL_LOOP_END 12180 +VLPROFEXEC EVAL_END 12250 +VLPROFEXEC EVAL_BEGIN 13720 +VLPROFEXEC EVAL_LOOP_BEGIN 14000 +VLPROFEXEC MTASK_BEGIN 15610 id 6 predictStart 0 cpu 19 +VLPROFEXEC MTASK_END 15820 id 6 predictCost 30 +VLPROFEXEC MTASK_BEGIN 21700 id 10 predictStart 196 cpu 19 +VLPROFEXEC MTASK_END 21875 id 10 predictCost 30 +VLPROFEXEC EVAL_LOOP_END 22085 +VLPROFEXEC EVAL_END 22330 +VLPROFTHREAD 1 +VLPROFEXEC MTASK_BEGIN 5495 id 5 predictStart 0 cpu 10 +VLPROFEXEC MTASK_END 6090 id 5 predictCost 30 +VLPROFEXEC MTASK_BEGIN 6300 id 7 predictStart 30 cpu 10 +VLPROFEXEC MTASK_END 6895 id 7 predictCost 30 +VLPROFEXEC MTASK_BEGIN 7490 id 8 predictStart 60 cpu 10 +VLPROFEXEC MTASK_END 8540 id 8 predictCost 107 +VLPROFEXEC MTASK_BEGIN 9135 id 9 predictStart 167 cpu 10 +VLPROFEXEC MTASK_END 9730 id 9 predictCost 30 +VLPROFEXEC MTASK_BEGIN 10255 id 11 predictStart 197 cpu 10 +VLPROFEXEC MTASK_END 11060 id 11 predictCost 30 +VLPROFEXEC MTASK_BEGIN 18375 id 5 predictStart 0 cpu 10 +VLPROFEXEC MTASK_END 18970 id 5 predictCost 30 +VLPROFEXEC MTASK_BEGIN 19145 id 7 predictStart 30 cpu 10 +VLPROFEXEC MTASK_END 19320 id 7 predictCost 30 +VLPROFEXEC MTASK_BEGIN 19670 id 8 predictStart 60 cpu 10 +VLPROFEXEC MTASK_END 19810 id 8 predictCost 107 +VLPROFEXEC MTASK_BEGIN 20650 id 9 predictStart 167 cpu 10 +VLPROFEXEC MTASK_END 20720 id 9 predictCost 30 +VLPROFEXEC MTASK_BEGIN 21140 id 11 predictStart 197 cpu 10 +VLPROFEXEC MTASK_END 21245 id 11 predictCost 30 VLPROF stat ticks 23415 diff --git a/test_regress/t/t_gantt_io_noproc.out b/test_regress/t/t_gantt_io_noproc.out index 87680d43c..4fb6360b3 100644 --- a/test_regress/t/t_gantt_io_noproc.out +++ b/test_regress/t/t_gantt_io_noproc.out @@ -1,9 +1,8 @@ Verilator Gantt report Argument settings: - +verilator+prof+threads+start+2 - +verilator+prof+threads+window+2 - --threads 2 + +verilator+prof+exec+start+2 + +verilator+prof+exec+window+2 Analysis: Total threads = 2 @@ -23,7 +22,7 @@ Prediction (what Verilator used for scheduling): All-thread efficiency = 63.2% All-thread speedup = 1.3 -Statistics: +MTask statistics: min log(p2e) = -3.681 from mtask 5 (predict 30, elapsed 1190) max log(p2e) = -2.409 from mtask 8 (predict 107, elapsed 1190) mean = -2.992 diff --git a/test_regress/t/t_gate_tree.pl b/test_regress/t/t_gate_tree.pl index 67587a1ba..0eb5101e5 100755 --- a/test_regress/t/t_gate_tree.pl +++ b/test_regress/t/t_gate_tree.pl @@ -118,9 +118,9 @@ compile( ); execute( - all_run_flags => ["+verilator+prof+threads+start+100", - " +verilator+prof+threads+window+2", - " +verilator+prof+threads+file+$Self->{obj_dir}/profile_threads.dat", + all_run_flags => ["+verilator+prof+exec+start+100", + " +verilator+prof+exec+window+2", + " +verilator+prof+exec+file+$Self->{obj_dir}/profile_exec.dat", " +verilator+prof+vlt+file+$Self->{obj_dir}/profile.vlt", ], check_finished => 1, diff --git a/test_regress/t/t_pgo_threads.pl b/test_regress/t/t_pgo_threads.pl index 1bcccc905..24e300882 100755 --- a/test_regress/t/t_pgo_threads.pl +++ b/test_regress/t/t_pgo_threads.pl @@ -14,12 +14,12 @@ scenarios(vltmt => 1); top_filename("t/t_gen_alw.v"); compile( - v_flags2 => ["--prof-threads --threads 2"] + v_flags2 => ["--prof-pgo --threads 2"] ); execute( - all_run_flags => ["+verilator+prof+threads+start+0", - " +verilator+prof+threads+file+/dev/null", + all_run_flags => ["+verilator+prof+exec+start+0", + " +verilator+prof+exec+file+/dev/null", " +verilator+prof+vlt+file+$Self->{obj_dir}/profile.vlt", ], check_finished => 1, @@ -28,8 +28,8 @@ execute( file_grep("$Self->{obj_dir}/profile.vlt", qr/profile_data/i); compile( - # Intentinally no --prof-threads here, so we make sure profile data - # can read in without it (that is no prof-thread effect on profile_data hash names) + # Intentinally no --prof-pgo here to make sure profile data can be read in + # without it (that is: --prof-pgo has no effect on profile_data hash names) v_flags2 => ["--threads 2", " $Self->{obj_dir}/profile.vlt"], ); diff --git a/test_regress/t/t_verilated_all.pl b/test_regress/t/t_verilated_all.pl index 14ef03202..1a8bc4469 100755 --- a/test_regress/t/t_verilated_all.pl +++ b/test_regress/t/t_verilated_all.pl @@ -21,13 +21,12 @@ compile( ? "--threads 2 $root/include/verilated_threads.cpp" : ""), ($Self->cfg_with_threaded ? "--trace-threads 1" : ""), - ($Self->cfg_with_threaded - ? "--prof-threads" : ""), + "--prof-exec", "--prof-pgo", "$root/include/verilated_save.cpp"], ); execute( - all_run_flags => [" +verilator+prof+threads+file+/dev/null", + all_run_flags => [" +verilator+prof+exec+file+/dev/null", " +verilator+prof+vlt+file+/dev/null", ], check_finished => 1, diff --git a/test_regress/t/t_verilated_all_newest.pl b/test_regress/t/t_verilated_all_newest.pl index 08b1f3838..221f84ad7 100755 --- a/test_regress/t/t_verilated_all_newest.pl +++ b/test_regress/t/t_verilated_all_newest.pl @@ -16,12 +16,12 @@ my $root = ".."; compile( # Can't use --coverage and --savable together, so cheat and compile inline - verilator_flags2 => ["--cc --coverage-toggle --coverage-line --coverage-user --trace --vpi $root/include/verilated_save.cpp"], + verilator_flags2 => ["--cc --coverage-toggle --coverage-line --coverage-user --trace --prof-exec --prof-pgo --vpi $root/include/verilated_save.cpp"], make_flags => 'DRIVER_STD=newest', ); execute( - all_run_flags => [" +verilator+prof+threads+file+/dev/null", + all_run_flags => [" +verilator+prof+exec+file+/dev/null", " +verilator+prof+vlt+file+/dev/null", ], check_finished => 1, From f9e69984ff44816c56f60f10d4ef8f6c2ef5caa0 Mon Sep 17 00:00:00 2001 From: Geza Lore Date: Sun, 27 Mar 2022 15:05:24 +0100 Subject: [PATCH 10/44] Set vlSymsp in modules at construction time. This ensures it's available from very early on. No functional change. --- src/V3EmitCHeaders.cpp | 7 +++---- src/V3EmitCImp.cpp | 9 ++++----- src/V3EmitCSyms.cpp | 10 ++++++---- 3 files changed, 13 insertions(+), 13 deletions(-) diff --git a/src/V3EmitCHeaders.cpp b/src/V3EmitCHeaders.cpp index bb26512f2..ef53dfa16 100644 --- a/src/V3EmitCHeaders.cpp +++ b/src/V3EmitCHeaders.cpp @@ -118,7 +118,7 @@ class EmitCHeader final : public EmitCConstInit { void emitInternalVarDecls(const AstNodeModule* modp) { if (!VN_IS(modp, Class)) { putsDecoration("\n// INTERNAL VARIABLES\n"); - puts(symClassName() + "* vlSymsp; // Symbol table\n"); + puts(symClassName() + "* const vlSymsp;\n"); } } void emitParamDecls(const AstNodeModule* modp) { @@ -146,7 +146,7 @@ class EmitCHeader final : public EmitCConstInit { if (!VN_IS(modp, Class)) { // Classes use CFuncs with isConstructor/isDestructor const string& name = prefixNameProtect(modp); putsDecoration("\n// CONSTRUCTORS\n"); - puts(name + "(const char* name);\n"); + puts(name + "(" + symClassName() + "* symsp, const char* name);\n"); puts("~" + name + "();\n"); puts("VL_UNCOPYABLE(" + name + ");\n"); } @@ -157,8 +157,7 @@ class EmitCHeader final : public EmitCConstInit { if (!VN_IS(modp, Class)) { decorateFirst(first, section); - puts("void " + protect("__Vconfigure") + "(" + symClassName() - + "* symsp, bool first);\n"); + puts("void " + protect("__Vconfigure") + "(bool first);\n"); } if (v3Global.opt.coverage()) { diff --git a/src/V3EmitCImp.cpp b/src/V3EmitCImp.cpp index e4c48c181..116b2582b 100644 --- a/src/V3EmitCImp.cpp +++ b/src/V3EmitCImp.cpp @@ -234,8 +234,8 @@ class EmitCImp final : EmitCFunc { "(" + modName + "* vlSelf);"); puts("\n"); - puts(modName + "::" + modName + "(const char* _vcname__)\n"); - puts(" : VerilatedModule(_vcname__)\n"); + puts(modName + "::" + modName + "(" + symClassName() + "* symsp, const char* name)\n"); + puts(" : VerilatedModule{name}\n"); ofp()->indentInc(); for (const AstNode* nodep = modp->stmtsp(); nodep; nodep = nodep->nextp()) { @@ -258,6 +258,7 @@ class EmitCImp final : EmitCFunc { } } } + puts(", vlSymsp{symsp}\n"); ofp()->indentDec(); puts(" {\n"); @@ -277,10 +278,8 @@ class EmitCImp final : EmitCFunc { "(" + modName + "* vlSelf, bool first);"); } - puts("\nvoid " + modName + "::" + protect("__Vconfigure") + "(" + symClassName() - + "* _vlSymsp, bool first) {\n"); + puts("\nvoid " + modName + "::" + protect("__Vconfigure") + "(bool first) {\n"); puts("if (false && first) {} // Prevent unused\n"); - puts("this->vlSymsp = _vlSymsp;\n"); // First, as later stuff needs it. if (v3Global.opt.coverage()) { puts(modName + "__" + protect("_configure_coverage") + "(this, first);\n"); } diff --git a/src/V3EmitCSyms.cpp b/src/V3EmitCSyms.cpp index 8857c23d8..07626fbed 100644 --- a/src/V3EmitCSyms.cpp +++ b/src/V3EmitCSyms.cpp @@ -726,14 +726,16 @@ void EmitCSyms::emitSymImp() { const AstNodeModule* const modp = i.second; puts(" , "); puts(protect(scopep->nameDotless())); + puts("{this"); if (modp->isTop()) { - puts("(namep)\n"); + puts(", namep"); } else { // The "." is added by catName - puts("(Verilated::catName(namep, "); + puts(", Verilated::catName(namep, "); putsQuoted(protectWordsIf(scopep->prettyName(), scopep->protect())); - puts("))\n"); + puts(")"); } + puts("}\n"); ++m_numStmts; } puts("{\n"); @@ -793,7 +795,7 @@ void EmitCSyms::emitSymImp() { const bool first = !modp->user1(); modp->user1(true); puts(protectIf(scopep->nameDotless(), scopep->protect()) + "." + protect("__Vconfigure") - + "(this, " + (first ? "true" : "false") + ");\n"); + + "(" + (first ? "true" : "false") + ");\n"); ++m_numStmts; } From 3f7bf3d2dc6bd3e511c724cd8ecd3cc7d3d23065 Mon Sep 17 00:00:00 2001 From: Wilson Snyder Date: Sun, 27 Mar 2022 13:59:18 -0400 Subject: [PATCH 11/44] Fix MSVC localtime_s (#3124). --- Changes | 1 + include/verilatedos.h | 4 +--- src/V3Param.cpp | 1 + 3 files changed, 3 insertions(+), 3 deletions(-) diff --git a/Changes b/Changes index 6bd421472..371bd6d57 100644 --- a/Changes +++ b/Changes @@ -14,6 +14,7 @@ Verilator 4.221 devel **Minor:** * Split --prof-threads into --prof-exec and --prof-pgo (#3365). [Geza Lore, Shunyao CAD] +* Fix MSVC localtime_s (#3124). Verilator 4.220 2022-03-12 diff --git a/include/verilatedos.h b/include/verilatedos.h index 324cc4332..5ba920312 100644 --- a/include/verilatedos.h +++ b/include/verilatedos.h @@ -492,10 +492,8 @@ using ssize_t = uint32_t; ///< signed size_t; returned from read() # define VL_STRCASECMP strcasecmp #endif -#ifdef __MINGW32__ +#if defined(__MINGW32__) || defined(_MSC_VER) # define VL_LOCALTIME_R(timep, tmp) localtime_s((tmp), (timep)) -#elif defined(_MSC_VER) -# define VL_LOCALTIME_R(timep, tmp) localtime_c((tmp), (timep)) #else # define VL_LOCALTIME_R(timep, tmp) localtime_r((timep), (tmp)) #endif diff --git a/src/V3Param.cpp b/src/V3Param.cpp index cdb4ce9a2..02f545516 100644 --- a/src/V3Param.cpp +++ b/src/V3Param.cpp @@ -58,6 +58,7 @@ #include "V3Unroll.h" #include "V3Hasher.h" +#include #include #include #include From 982138105996c4f49252118c0d57721ad0202230 Mon Sep 17 00:00:00 2001 From: Wilson Snyder Date: Sun, 27 Mar 2022 14:42:36 -0400 Subject: [PATCH 12/44] Tests: new t_lint_latch_5 test (#2997). --- test_regress/t/t_lint_latch_5.pl | 17 +++++++++++++++++ test_regress/t/t_lint_latch_5.v | 19 +++++++++++++++++++ 2 files changed, 36 insertions(+) create mode 100755 test_regress/t/t_lint_latch_5.pl create mode 100644 test_regress/t/t_lint_latch_5.v diff --git a/test_regress/t/t_lint_latch_5.pl b/test_regress/t/t_lint_latch_5.pl new file mode 100755 index 000000000..629a44bbb --- /dev/null +++ b/test_regress/t/t_lint_latch_5.pl @@ -0,0 +1,17 @@ +#!/usr/bin/env perl +if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2003-2009 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +scenarios(vlt => 1); + +lint( + ); + +ok(1); +1; diff --git a/test_regress/t/t_lint_latch_5.v b/test_regress/t/t_lint_latch_5.v new file mode 100644 index 000000000..7cf29d05c --- /dev/null +++ b/test_regress/t/t_lint_latch_5.v @@ -0,0 +1,19 @@ +// DESCRIPTION: Verilator: Verilog Test module for Issue#2863 +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2021 by Julien Margetts (Originally provided by Thomas Sailer) + +module test + (input logic [1:0] a, + input logic e, + output logic [1:0] z); + + always_latch + if (e) + z[0] <= a[0]; + + always_latch + if (e) + z[1] <= a[1]; + +endmodule From 31ce1fdfd3c335ed4728cd3034f73ca020b94954 Mon Sep 17 00:00:00 2001 From: Wilson Snyder Date: Sun, 27 Mar 2022 14:50:49 -0400 Subject: [PATCH 13/44] Tests: Check legacy part of (#3255) --- test_regress/t/t_wrapper_legacy.cpp | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/test_regress/t/t_wrapper_legacy.cpp b/test_regress/t/t_wrapper_legacy.cpp index c0dc195d2..6b123aed7 100644 --- a/test_regress/t/t_wrapper_legacy.cpp +++ b/test_regress/t/t_wrapper_legacy.cpp @@ -82,6 +82,15 @@ int main(int argc, char** argv, char** env) { TEST_CHECK_EQ(Verilated::timeunit(), 12); TEST_CHECK_EQ(Verilated::timeprecision(), 12); + TEST_CHECK_EQ(sizeof(vluint8_t), 1); // Intentional use of old typedef + TEST_CHECK_EQ(sizeof(vluint16_t), 2); // Intentional use of old typedef + TEST_CHECK_EQ(sizeof(vluint32_t), 4); // Intentional use of old typedef + TEST_CHECK_EQ(sizeof(vluint64_t), 8); // Intentional use of old typedef + TEST_CHECK_EQ(sizeof(vlsint8_t), 1); // Intentional use of old typedef + TEST_CHECK_EQ(sizeof(vlsint16_t), 2); // Intentional use of old typedef + TEST_CHECK_EQ(sizeof(vlsint32_t), 4); // Intentional use of old typedef + TEST_CHECK_EQ(sizeof(vlsint64_t), 8); // Intentional use of old typedef + VM_PREFIX* topp = new VM_PREFIX(); topp->eval(); From 960d0de3610906d578fde1ecfc960a13f95394ce Mon Sep 17 00:00:00 2001 From: Wilson Snyder Date: Sun, 27 Mar 2022 15:03:25 -0400 Subject: [PATCH 14/44] Tests: Cleanup vluint_t/vlsint_t in tests, part of (#3255) --- test_regress/t/t_clk_inp_init.cpp | 2 +- test_regress/t/t_cover_lib_c.cpp | 6 +++--- test_regress/t/t_dpi_var.cpp | 10 +++++----- test_regress/t/t_extend.v | 2 +- test_regress/t/t_extend_class_c.h | 2 +- test_regress/t/t_func_public.v | 2 +- test_regress/t/t_leak.cpp | 6 +++--- test_regress/t/t_mem_multi_io2.cpp | 12 ++++++------ test_regress/t/t_order_multidriven.cpp | 2 +- test_regress/t/t_scope_map.cpp | 16 ++++++++-------- test_regress/t/t_trace_two_cc.cpp | 4 ++-- test_regress/t/t_vpi_cb_iter.cpp | 2 +- test_regress/t/t_vpi_cbs_called.cpp | 2 +- test_regress/t/t_vpi_get.cpp | 2 +- test_regress/t/t_vpi_memory.cpp | 2 +- test_regress/t/t_vpi_module.cpp | 2 +- test_regress/t/t_vpi_param.cpp | 2 +- test_regress/t/t_vpi_time_cb.cpp | 2 +- test_regress/t/t_vpi_unimpl.cpp | 2 +- test_regress/t/t_vpi_var.cpp | 2 +- test_regress/t/t_vpi_zero_time_cb.cpp | 2 +- 21 files changed, 42 insertions(+), 42 deletions(-) diff --git a/test_regress/t/t_clk_inp_init.cpp b/test_regress/t/t_clk_inp_init.cpp index 4d2e17463..b8a31e3f2 100644 --- a/test_regress/t/t_clk_inp_init.cpp +++ b/test_regress/t/t_clk_inp_init.cpp @@ -9,7 +9,7 @@ #include "verilated.h" void oneTest(int argc, char** argv, int seed) { - vluint64_t sim_time = 1000; + uint64_t sim_time = 1000; #ifdef TEST_VERBOSE VL_PRINTF("== Seed=%d\n", seed); diff --git a/test_regress/t/t_cover_lib_c.cpp b/test_regress/t/t_cover_lib_c.cpp index fc9f38206..ddc94db07 100644 --- a/test_regress/t/t_cover_lib_c.cpp +++ b/test_regress/t/t_cover_lib_c.cpp @@ -30,7 +30,7 @@ int errors = 0; const char* name() { return "main"; } -void hier_insert(VerilatedCovContext* covContextp, vluint64_t* countp, const char* hierp, +void hier_insert(VerilatedCovContext* covContextp, uint64_t* countp, const char* hierp, const char* peri) { // This needs to be a function at one line number so all of the // line numbers for coverage are constant, otherwise instances won't combine. @@ -38,8 +38,8 @@ void hier_insert(VerilatedCovContext* covContextp, vluint64_t* countp, const cha } int main() { - vluint32_t covers[1]; - vluint64_t coverw[6]; + uint32_t covers[1]; + uint64_t coverw[6]; VerilatedCovContext* covContextp = Verilated::defaultContextp()->coveragep(); diff --git a/test_regress/t/t_dpi_var.cpp b/test_regress/t/t_dpi_var.cpp index f62388ccb..0bd8aa1ac 100644 --- a/test_regress/t/t_dpi_var.cpp +++ b/test_regress/t/t_dpi_var.cpp @@ -18,7 +18,7 @@ //====================================================================== struct MyMon { - vluint32_t* sigsp[2]; + uint32_t* sigsp[2]; MyMon() { sigsp[0] = NULL; sigsp[1] = NULL; @@ -31,7 +31,7 @@ void mon_register_a(const char* namep, void* sigp, bool isOut) { #ifdef TEST_VERBOSE VL_PRINTF("- mon_register_a(\"%s\", %p, %d);\n", namep, sigp, isOut); #endif - mons[0].sigsp[isOut] = (vluint32_t*)sigp; + mons[0].sigsp[isOut] = (uint32_t*)sigp; } void mon_do(MyMon* monp) { @@ -80,9 +80,9 @@ void mon_register_b(const char* namep, int isOut) { } else if (varp->vltype() != VLVT_UINT32) { VL_PRINTF("%%Warning: wrong type for signal: \"%s\"\n", namep); } else { - vluint32_t* datap = (vluint32_t*)(varp->datap()); + uint32_t* datap = (uint32_t*)(varp->datap()); VL_PRINTF("- mon_register_b('%s', \"%s\", %p, %d);\n", modp, namep, datap, isOut); - mons[1].sigsp[isOut] = (vluint32_t*)(varp->datap()); + mons[1].sigsp[isOut] = (uint32_t*)(varp->datap()); } } @@ -114,7 +114,7 @@ unsigned int main_time = 0; double sc_time_stamp() { return main_time; } int main(int argc, char** argv, char** env) { - vluint64_t sim_time = 1100; + uint64_t sim_time = 1100; Verilated::commandArgs(argc, argv); Verilated::debug(0); diff --git a/test_regress/t/t_extend.v b/test_regress/t/t_extend.v index f4a8e362c..7a0c372b3 100644 --- a/test_regress/t/t_extend.v +++ b/test_regress/t/t_extend.v @@ -56,7 +56,7 @@ module t (/*AUTOARG*/ #error "`systemc_header didn't work" #endif bool m_did_ctor; - vluint32_t my_function() { + uint32_t my_function() { if (!m_did_ctor) vl_fatal(__FILE__, __LINE__, __FILE__, "`systemc_ctor didn't work"); return 1; } diff --git a/test_regress/t/t_extend_class_c.h b/test_regress/t/t_extend_class_c.h index 4c73f1a2b..87e21d29c 100644 --- a/test_regress/t/t_extend_class_c.h +++ b/test_regress/t/t_extend_class_c.h @@ -13,5 +13,5 @@ public: ~t_extend_class_c() {} // METHODS // This function will be called from a instance created in Verilog - inline vluint32_t my_math(vluint32_t in) { return in + 1; } + inline uint32_t my_math(uint32_t in) { return in + 1; } }; diff --git a/test_regress/t/t_func_public.v b/test_regress/t/t_func_public.v index 00a58e67e..099e52da7 100644 --- a/test_regress/t/t_func_public.v +++ b/test_regress/t/t_func_public.v @@ -108,7 +108,7 @@ module tpub ( if (1'b1 != got_bool) $stop; $c("this->publicGetLong(this->got_long);"); if (24'h11bca != got_long) $stop; - $c("{ vluint64_t qq; this->publicGetQuad(qq); this->got_quad=qq; }"); + $c("{ uint64_t qq; this->publicGetQuad(qq); this->got_quad=qq; }"); if (60'haaaa_bbbb_cccc != got_quad) $stop; $c("{ WData gw[3]; this->publicGetWide(gw); VL_ASSIGN_W(72,this->got_wide,gw); }"); if (72'hac_abca_aaaa_bbbb_1234 != got_wide) $stop; diff --git a/test_regress/t/t_leak.cpp b/test_regress/t/t_leak.cpp index a70ecda6d..a0ad9259b 100644 --- a/test_regress/t/t_leak.cpp +++ b/test_regress/t/t_leak.cpp @@ -29,7 +29,7 @@ long long get_memory_usage() { if (!fp) return 0; int ps_ign; - vluint64_t ps_vsize, ps_rss; + uint64_t ps_vsize, ps_rss; int items = fscanf(fp, ("%d (%*[^) ]) %*1s %d %*d %*d %*d %*d %u" " %u %u %u %u %d %d %d %d" @@ -78,7 +78,7 @@ void make_and_destroy() { } int main(int argc, char* argv[]) { - vluint64_t firstUsage = get_memory_usage(); + uint64_t firstUsage = get_memory_usage(); // Warmup phase for (int i = 0; i < 10; i++) { // @@ -94,7 +94,7 @@ int main(int argc, char* argv[]) { } } - vluint64_t leaked = get_memory_usage() - firstUsage; + uint64_t leaked = get_memory_usage() - firstUsage; if (leaked > 64 * 1024) { // Have to allow some slop for this code. printf("Leaked %" PRId64 " bytes, or ~ %" PRId64 " bytes/construt\n", // leaked, leaked / loops); diff --git a/test_regress/t/t_mem_multi_io2.cpp b/test_regress/t/t_mem_multi_io2.cpp index 7c18d04e3..507ac12b0 100644 --- a/test_regress/t/t_mem_multi_io2.cpp +++ b/test_regress/t/t_mem_multi_io2.cpp @@ -28,12 +28,12 @@ int main() tb = new VM_PREFIX("tb"); #ifdef SYSTEMC_VERSION - sc_signal i3; - sc_signal o3; - sc_signal i34[4]; - sc_signal o34[4]; - sc_signal i345[4][5]; - sc_signal o345[4][5]; + sc_signal i3; + sc_signal o3; + sc_signal i34[4]; + sc_signal o34[4]; + sc_signal i345[4][5]; + sc_signal o345[4][5]; tb->i3(i3); tb->o3(o3); diff --git a/test_regress/t/t_order_multidriven.cpp b/test_regress/t/t_order_multidriven.cpp index 1b9f6ef9a..628fbbc74 100644 --- a/test_regress/t/t_order_multidriven.cpp +++ b/test_regress/t/t_order_multidriven.cpp @@ -12,7 +12,7 @@ double sc_time_stamp() { return 0; } Vt_order_multidriven* vcore; VerilatedVcdC* vcd; -vluint64_t vtime; +uint64_t vtime; #define PHASE_90 diff --git a/test_regress/t/t_scope_map.cpp b/test_regress/t/t_scope_map.cpp index a978627a7..14e7d5812 100644 --- a/test_regress/t/t_scope_map.cpp +++ b/test_regress/t/t_scope_map.cpp @@ -69,13 +69,13 @@ int main(int argc, char** argv, char** env) { int varBits = varLeft + 1; // First expect an incrementing byte pattern - vluint8_t* varData = reinterpret_cast(varp->datap()); + uint8_t* varData = reinterpret_cast(varp->datap()); for (int i = 0; i < varBits / 8; i++) { #ifdef TEST_VERBOSE VL_PRINTF("%02x ", varData[i]); #endif - vluint8_t expected = i % 0xff; + const uint8_t expected = i % 0xff; if (varData[i] != expected) { VL_PRINTF("%%Error: Data mismatch, got 0x%02x, expected 0x%02x\n", varData[i], expected); @@ -85,8 +85,8 @@ int main(int argc, char** argv, char** env) { // Extra bits all set high initially if (varBits % 8 != 0) { - vluint8_t got = varData[varBits / 8]; - vluint8_t expected = ~(0xff << (varBits % 8)); + const uint8_t got = varData[varBits / 8]; + const uint8_t expected = ~(0xff << (varBits % 8)); if (got != expected) { VL_PRINTF("%%Error: Data mismatch, got 0x%02x, expected 0x%02x\n", got, expected); @@ -126,11 +126,11 @@ int main(int argc, char** argv, char** env) { const VerilatedVar* varp = &(varname.second); int varLeft = varp->packed().left(); int varBits = varLeft + 1; - vluint8_t* varData = reinterpret_cast(varp->datap()); + uint8_t* varData = reinterpret_cast(varp->datap()); // Check that all bits are high now for (int i = 0; i < varBits / 8; i++) { - vluint8_t expected = 0xff; + const uint8_t expected = 0xff; if (varData[i] != expected) { VL_PRINTF("%%Error: Data mismatch (%s), got 0x%02x, expected 0x%02x\n", varname.first, varData[i], expected); @@ -139,8 +139,8 @@ int main(int argc, char** argv, char** env) { } if (varBits % 8 != 0) { - vluint8_t got = varData[varBits / 8]; - vluint8_t expected = ~(0xff << (varBits % 8)); + const uint8_t got = varData[varBits / 8]; + const uint8_t expected = ~(0xff << (varBits % 8)); if (got != expected) { VL_PRINTF("%%Error: Data mismatch (%s), got 0x%02x, expected 0x%02x\n", varname.first, got, expected); diff --git a/test_regress/t/t_trace_two_cc.cpp b/test_regress/t/t_trace_two_cc.cpp index 238877e5f..0074d4ecb 100644 --- a/test_regress/t/t_trace_two_cc.cpp +++ b/test_regress/t/t_trace_two_cc.cpp @@ -25,11 +25,11 @@ VM_PREFIX* ap; Vt_trace_two_b* bp; -vluint64_t main_time = 0; +uint64_t main_time = 0; double sc_time_stamp() { return main_time; } int main(int argc, char** argv, char** env) { - vluint64_t sim_time = 1100; + uint64_t sim_time = 1100; Verilated::commandArgs(argc, argv); Verilated::debug(0); Verilated::traceEverOn(true); diff --git a/test_regress/t/t_vpi_cb_iter.cpp b/test_regress/t/t_vpi_cb_iter.cpp index 4fc10ec06..3afbe07e9 100644 --- a/test_regress/t/t_vpi_cb_iter.cpp +++ b/test_regress/t/t_vpi_cb_iter.cpp @@ -143,7 +143,7 @@ static void register_filler_cb() { double sc_time_stamp() { return main_time; } int main(int argc, char** argv, char** env) { - vluint64_t sim_time = 100; + uint64_t sim_time = 100; Verilated::commandArgs(argc, argv); Verilated::debug(0); diff --git a/test_regress/t/t_vpi_cbs_called.cpp b/test_regress/t/t_vpi_cbs_called.cpp index 3b81b1840..c015b38af 100644 --- a/test_regress/t/t_vpi_cbs_called.cpp +++ b/test_regress/t/t_vpi_cbs_called.cpp @@ -248,7 +248,7 @@ static int register_test_callback() { double sc_time_stamp() { return main_time; } int main(int argc, char** argv, char** env) { - vluint64_t sim_time = 100; + uint64_t sim_time = 100; bool cbs_called; Verilated::commandArgs(argc, argv); diff --git a/test_regress/t/t_vpi_get.cpp b/test_regress/t/t_vpi_get.cpp index 3b1d41d07..ab8a9bce5 100644 --- a/test_regress/t/t_vpi_get.cpp +++ b/test_regress/t/t_vpi_get.cpp @@ -242,7 +242,7 @@ void (*vlog_startup_routines[])() = {vpi_compat_bootstrap, 0}; #else double sc_time_stamp() { return main_time; } int main(int argc, char** argv, char** env) { - vluint64_t sim_time = 1100; + uint64_t sim_time = 1100; Verilated::commandArgs(argc, argv); Verilated::debug(0); diff --git a/test_regress/t/t_vpi_memory.cpp b/test_regress/t/t_vpi_memory.cpp index b6b1a83df..490d871e0 100644 --- a/test_regress/t/t_vpi_memory.cpp +++ b/test_regress/t/t_vpi_memory.cpp @@ -252,7 +252,7 @@ void (*vlog_startup_routines[])() = {vpi_compat_bootstrap, 0}; double sc_time_stamp() { return main_time; } int main(int argc, char** argv, char** env) { - vluint64_t sim_time = 1100; + uint64_t sim_time = 1100; Verilated::commandArgs(argc, argv); Verilated::debug(0); // we're going to be checking for these errors do don't crash out diff --git a/test_regress/t/t_vpi_module.cpp b/test_regress/t/t_vpi_module.cpp index 2e9ca88e5..cc3325eca 100644 --- a/test_regress/t/t_vpi_module.cpp +++ b/test_regress/t/t_vpi_module.cpp @@ -174,7 +174,7 @@ void (*vlog_startup_routines[])() = {vpi_compat_bootstrap, 0}; double sc_time_stamp() { return main_time; } int main(int argc, char** argv, char** env) { - vluint64_t sim_time = 1100; + uint64_t sim_time = 1100; Verilated::commandArgs(argc, argv); Verilated::debug(0); // we're going to be checking for these errors do don't crash out diff --git a/test_regress/t/t_vpi_param.cpp b/test_regress/t/t_vpi_param.cpp index cee164fe3..639bb9196 100644 --- a/test_regress/t/t_vpi_param.cpp +++ b/test_regress/t/t_vpi_param.cpp @@ -242,7 +242,7 @@ void (*vlog_startup_routines[])() = {vpi_compat_bootstrap, 0}; double sc_time_stamp() { return main_time; } int main(int argc, char** argv, char** env) { - vluint64_t sim_time = 1100; + uint64_t sim_time = 1100; Verilated::commandArgs(argc, argv); Verilated::debug(0); // we're going to be checking for these errors do don't crash out diff --git a/test_regress/t/t_vpi_time_cb.cpp b/test_regress/t/t_vpi_time_cb.cpp index c6a83d793..70c65cdeb 100644 --- a/test_regress/t/t_vpi_time_cb.cpp +++ b/test_regress/t/t_vpi_time_cb.cpp @@ -29,7 +29,7 @@ unsigned int main_time = 0; double sc_time_stamp() { return main_time; } int main(int argc, char** argv, char** env) { - vluint64_t sim_time = 1100; + uint64_t sim_time = 1100; Verilated::commandArgs(argc, argv); Verilated::debug(0); diff --git a/test_regress/t/t_vpi_unimpl.cpp b/test_regress/t/t_vpi_unimpl.cpp index 816c9eca3..e3763b504 100644 --- a/test_regress/t/t_vpi_unimpl.cpp +++ b/test_regress/t/t_vpi_unimpl.cpp @@ -186,7 +186,7 @@ extern "C" int mon_check() { double sc_time_stamp() { return main_time; } int main(int argc, char** argv, char** env) { - vluint64_t sim_time = 1100; + uint64_t sim_time = 1100; Verilated::commandArgs(argc, argv); Verilated::debug(0); // we're going to be checking for these errors do don't crash out diff --git a/test_regress/t/t_vpi_var.cpp b/test_regress/t/t_vpi_var.cpp index 2861d58b8..648557234 100644 --- a/test_regress/t/t_vpi_var.cpp +++ b/test_regress/t/t_vpi_var.cpp @@ -693,7 +693,7 @@ void (*vlog_startup_routines[])() = {vpi_compat_bootstrap, 0}; double sc_time_stamp() { return main_time; } int main(int argc, char** argv, char** env) { - vluint64_t sim_time = 1100; + uint64_t sim_time = 1100; Verilated::commandArgs(argc, argv); Verilated::debug(0); diff --git a/test_regress/t/t_vpi_zero_time_cb.cpp b/test_regress/t/t_vpi_zero_time_cb.cpp index 9336d60d3..243e97746 100644 --- a/test_regress/t/t_vpi_zero_time_cb.cpp +++ b/test_regress/t/t_vpi_zero_time_cb.cpp @@ -108,7 +108,7 @@ void (*vlog_startup_routines[])() = {vpi_compat_bootstrap, 0}; double sc_time_stamp() { return main_time; } int main(int argc, char** argv, char** env) { - vluint64_t sim_time = 1100; + uint64_t sim_time = 1100; Verilated::commandArgs(argc, argv); Verilated::debug(0); From e02f97854c39448573d06fe56cbf9278778f4f41 Mon Sep 17 00:00:00 2001 From: Wilson Snyder Date: Sun, 27 Mar 2022 15:27:40 -0400 Subject: [PATCH 15/44] Deprecate 'vluint64_t' and similar types (#3255). --- Changes | 1 + bin/verilator | 2 +- docs/guide/connecting.rst | 6 +- docs/guide/exe_verilator.rst | 4 +- docs/guide/extensions.rst | 2 +- docs/guide/faq.rst | 2 +- examples/make_tracing_sc/sc_main.cpp | 8 +- include/verilated.cpp | 121 +++++++++--------- include/verilated.h | 64 +++++----- include/verilated_cov.cpp | 14 +-- include/verilated_cov.h | 6 +- include/verilated_fst_c.cpp | 30 ++--- include/verilated_fst_c.h | 46 +++---- include/verilated_funcs.h | 96 +++++++-------- include/verilated_imp.h | 10 +- include/verilated_profiler.cpp | 12 +- include/verilated_profiler.h | 32 ++--- include/verilated_save.cpp | 10 +- include/verilated_save.h | 50 ++++---- include/verilated_sc.h | 4 +- include/verilated_sym_props.h | 6 +- include/verilated_threads.cpp | 4 +- include/verilated_threads.h | 16 +-- include/verilated_trace.h | 110 ++++++++--------- include/verilated_trace_imp.cpp | 67 +++++----- include/verilated_types.h | 14 +-- include/verilated_vcd_c.cpp | 104 ++++++++-------- include/verilated_vcd_c.h | 155 ++++++++++++------------ include/verilated_vpi.cpp | 136 ++++++++++----------- include/verilated_vpi.h | 2 +- include/verilatedos.h | 14 ++- src/V3Ast.cpp | 6 +- src/V3Ast.h | 16 +-- src/V3AstNodes.cpp | 8 +- src/V3AstNodes.h | 16 +-- src/V3Config.cpp | 10 +- src/V3Config.h | 4 +- src/V3EmitCConstInit.h | 4 +- src/V3EmitCFunc.cpp | 8 +- src/V3EmitCImp.cpp | 6 +- src/V3EmitCSyms.cpp | 2 +- src/V3GraphPathChecker.cpp | 4 +- src/V3GraphPathChecker.h | 2 +- src/V3Life.cpp | 2 +- src/V3List.h | 8 +- src/V3Number.cpp | 89 +++++++------- src/V3Number.h | 10 +- src/V3Order.cpp | 4 +- src/V3Os.cpp | 6 +- src/V3Os.h | 2 +- src/V3Partition.cpp | 60 ++++----- src/V3Partition.h | 6 +- src/V3PartitionGraph.h | 8 +- src/V3SplitVar.cpp | 2 +- src/V3Stats.h | 2 +- src/V3TSP.cpp | 6 +- src/V3Trace.cpp | 14 +-- src/V3Width.cpp | 10 +- src/V3WidthSel.cpp | 16 +-- src/VlcBucket.h | 46 +++---- src/VlcPoint.h | 26 ++-- src/VlcSource.h | 8 +- src/VlcTest.h | 28 ++--- src/VlcTop.cpp | 12 +- test_regress/driver.pl | 2 +- test_regress/t/t_var_pins_sc64.pl | 4 +- test_regress/t/t_var_pins_sc_biguint.pl | 4 +- test_regress/t/t_var_pins_scui.pl | 4 +- 68 files changed, 801 insertions(+), 812 deletions(-) diff --git a/Changes b/Changes index 371bd6d57..16539baa6 100644 --- a/Changes +++ b/Changes @@ -14,6 +14,7 @@ Verilator 4.221 devel **Minor:** * Split --prof-threads into --prof-exec and --prof-pgo (#3365). [Geza Lore, Shunyao CAD] +* Deprecate 'vluint64_t' and similar types (#3255). * Fix MSVC localtime_s (#3124). diff --git a/bin/verilator b/bin/verilator index 853b94381..b1ee97e73 100755 --- a/bin/verilator +++ b/bin/verilator @@ -348,7 +348,7 @@ detailed descriptions of these arguments. --mod-prefix Name to prepend to lower classes --no-clk Prevent marking specified signal as clock --no-decoration Disable comments and symbol decorations - --no-pins64 Don't use vluint64_t's for 33-64 bit sigs + --no-pins64 Don't use uint64_t's for 33-64 bit sigs --no-skip-identical Disable skipping identical output +notimingchecks Ignored -O0 Disable optimizations diff --git a/docs/guide/connecting.rst b/docs/guide/connecting.rst index 119fa850e..8e06f73a0 100644 --- a/docs/guide/connecting.rst +++ b/docs/guide/connecting.rst @@ -96,7 +96,7 @@ model. Here is a simple example: Vtop *top; // Instantiation of model - vluint64_t main_time = 0; // Current simulation time + uint64_t main_time = 0; // Current simulation time // This is a 64-bit integer to reduce wrap over issues and // allow modulus. This is in units of the timeprecision // used in Verilog (or from --timescale-override) @@ -150,7 +150,7 @@ netlist as an instantiation. The SC_MODULE gets the same pinout as the Verilog module, with the following type conversions: Pins of a single bit become bool. Pins 2-32 bits wide become uint32_t's. Pins 33-64 bits wide become sc_bv's or -vluint64_t's depending on the :vlopt:`--no-pins64` option. Wider pins +uint64_t's depending on the :vlopt:`--no-pins64` option. Wider pins become sc_bv's. (Uints simulate the fastest so are used where possible.) Model internals, including lower level sub-modules are not pure SystemC @@ -429,7 +429,7 @@ accesses the above signal "readme" would be: #include "verilated.h" #include "verilated_vpi.h" // Required to get definitions - vluint64_t main_time = 0; // See comments in first example + uint64_t main_time = 0; // See comments in first example double sc_time_stamp() { return main_time; } void read_and_check() { diff --git a/docs/guide/exe_verilator.rst b/docs/guide/exe_verilator.rst index 83b3ad0f5..16a41ba15 100644 --- a/docs/guide/exe_verilator.rst +++ b/docs/guide/exe_verilator.rst @@ -768,7 +768,7 @@ Summary: .. option:: --pins-bv Specifies SystemC inputs/outputs of greater than or equal to - bits wide should use sc_bv's instead of uint32/vluint64_t's. The + bits wide should use sc_bv's instead of uint32/uint64_t's. The default is "--pins-bv 65", and the value must be less than or equal to 65. Versions before Verilator 3.671 defaulted to "--pins-bv 33". The more sc_bv is used, the worse for performance. Use the @@ -1647,7 +1647,7 @@ The grammar of configuration commands is as follows: .. option:: sc_bv -module "" [-function ""] -var "" Sets the port to be of :code:`sc_bv<{width}>` type, instead of bool, - vluint32_t or vluint64_t. Same as :option:`/*verilator&32;sc_bv*/` + uint32_t or uint64_t. Same as :option:`/*verilator&32;sc_bv*/` metacomment. .. option:: sformat [-module ""] [-task ""] -var "" diff --git a/docs/guide/extensions.rst b/docs/guide/extensions.rst index 19951334b..491ff18fc 100644 --- a/docs/guide/extensions.rst +++ b/docs/guide/extensions.rst @@ -445,7 +445,7 @@ or "`ifdef`"'s may break other tools. .. option:: /*verilator&32;sc_bv*/ Used after a port declaration. It sets the port to be of - :code:`sc_bv<{width}>` type, instead of bool, vluint32_t or vluint64_t. + :code:`sc_bv<{width}>` type, instead of bool, uint32_t or uint64_t. This may be useful if the port width is parameterized and the instantiating C++ code wants to always have a sc_bv so it can accept any width. In general you should avoid using this attribute when not diff --git a/docs/guide/faq.rst b/docs/guide/faq.rst index 14f4281ea..e6599dc3c 100644 --- a/docs/guide/faq.rst +++ b/docs/guide/faq.rst @@ -445,7 +445,7 @@ the signal, as you would any other member variable. Signals are the smallest of 8-bit unsigned chars (equivalent to uint8_t), 16-bit unsigned shorts (uint16_t), 32-bit unsigned longs (uint32_t), or 64-bit unsigned long longs (uint64_t) that fits the width of the signal. -Generally, you can use just uint32_t's for 1 to 32 bits, or vluint64_t for +Generally, you can use just uint32_t's for 1 to 32 bits, or uint64_t for 1 to 64 bits, and the compiler will properly up-convert smaller entities. Note even signed ports are declared as unsigned; you must sign extend yourself to the appropriate signal width. diff --git a/examples/make_tracing_sc/sc_main.cpp b/examples/make_tracing_sc/sc_main.cpp index ee42a0aa6..93861ceea 100644 --- a/examples/make_tracing_sc/sc_main.cpp +++ b/examples/make_tracing_sc/sc_main.cpp @@ -58,11 +58,11 @@ int sc_main(int argc, char* argv[]) { // Define interconnect sc_signal reset_l; - sc_signal in_small; - sc_signal in_quad; + sc_signal in_small; + sc_signal in_quad; sc_signal> in_wide; - sc_signal out_small; - sc_signal out_quad; + sc_signal out_small; + sc_signal out_quad; sc_signal> out_wide; // Construct the Verilated model, from inside Vtop.h diff --git a/include/verilated.cpp b/include/verilated.cpp index e55da5bf3..97dbb9263 100644 --- a/include/verilated.cpp +++ b/include/verilated.cpp @@ -74,10 +74,10 @@ constexpr unsigned VL_VALUE_STRING_MAX_WIDTH = 8192; //=========================================================================== // Static sanity checks -static_assert(sizeof(vluint8_t) == 1, "vluint8_t is missized"); -static_assert(sizeof(vluint16_t) == 2, "vluint8_t is missized"); -static_assert(sizeof(vluint32_t) == 4, "vluint8_t is missized"); -static_assert(sizeof(vluint64_t) == 8, "vluint8_t is missized"); +static_assert(sizeof(uint8_t) == 1, "uint8_t is missized"); +static_assert(sizeof(uint16_t) == 2, "uint8_t is missized"); +static_assert(sizeof(uint32_t) == 4, "uint8_t is missized"); +static_assert(sizeof(uint64_t) == 8, "uint8_t is missized"); //=========================================================================== // Global variables @@ -244,21 +244,21 @@ std::string _vl_string_vprintf(const char* formatp, va_list ap) VL_MT_SAFE { return out; } -vluint64_t _vl_dbg_sequence_number() VL_MT_SAFE { +uint64_t _vl_dbg_sequence_number() VL_MT_SAFE { #ifdef VL_THREADED - static std::atomic sequence; + static std::atomic sequence; #else - static vluint64_t sequence = 0; + static uint64_t sequence = 0; #endif return ++sequence; } -vluint32_t VL_THREAD_ID() VL_MT_SAFE { +uint32_t VL_THREAD_ID() VL_MT_SAFE { #ifdef VL_THREADED // Alternative is to use std::this_thread::get_id, but that returns a // hard-to-read number and is very slow - static std::atomic s_nextId(0); - static VL_THREAD_LOCAL vluint32_t t_myId = ++s_nextId; + static std::atomic s_nextId(0); + static VL_THREAD_LOCAL uint32_t t_myId = ++s_nextId; return t_myId; #else return 0; @@ -296,7 +296,7 @@ void VL_PRINTF_MT(const char* formatp, ...) VL_MT_SAFE { //=========================================================================== // Random -- Mostly called at init time, so not inline. -static vluint32_t vl_sys_rand32() VL_MT_UNSAFE { +static uint32_t vl_sys_rand32() VL_MT_UNSAFE { // Return random 32-bits using system library. // Used only to construct seed for Verilator's PNRG. static VerilatedMutex s_mutex; @@ -309,9 +309,9 @@ static vluint32_t vl_sys_rand32() VL_MT_UNSAFE { #endif } -vluint64_t vl_rand64() VL_MT_SAFE { - static VL_THREAD_LOCAL vluint64_t t_state[2]; - static VL_THREAD_LOCAL vluint32_t t_seedEpoch = 0; +uint64_t vl_rand64() VL_MT_SAFE { + static VL_THREAD_LOCAL uint64_t t_state[2]; + static VL_THREAD_LOCAL uint32_t t_seedEpoch = 0; // For speed, we use a thread-local epoch number to know when to reseed // A thread always belongs to a single context, so this works out ok if (VL_UNLIKELY(t_seedEpoch != VerilatedContextImp::randSeedEpoch())) { @@ -325,7 +325,7 @@ vluint64_t vl_rand64() VL_MT_SAFE { if (VL_COUNTONES_I(t_state[1]) < 10) t_state[1] = ~t_state[1]; } // Xoroshiro128+ algorithm - const vluint64_t result = t_state[0] + t_state[1]; + const uint64_t result = t_state[0] + t_state[1]; t_state[1] ^= t_state[0]; t_state[0] = (((t_state[0] << 55) | (t_state[0] >> 9)) ^ t_state[1] ^ (t_state[1] << 14)); t_state[1] = (t_state[1] << 36) | (t_state[1] >> 28); @@ -410,11 +410,11 @@ WDataOutP _vl_moddiv_w(int lbits, WDataOutP owp, const WDataInP lwp, const WData const int vw = VL_WORDS_I(vmsbp1); // aka "n" in the algorithm if (vw == 1) { // Single divisor word breaks rest of algorithm - vluint64_t k = 0; + uint64_t k = 0; for (int j = uw - 1; j >= 0; --j) { - const vluint64_t unw64 = ((k << 32ULL) + static_cast(lwp[j])); - owp[j] = unw64 / static_cast(rwp[0]); - k = unw64 - static_cast(owp[j]) * static_cast(rwp[0]); + const uint64_t unw64 = ((k << 32ULL) + static_cast(lwp[j])); + owp[j] = unw64 / static_cast(rwp[0]); + k = unw64 - static_cast(owp[j]) * static_cast(rwp[0]); } if (is_modulus) { owp[0] = k; @@ -424,8 +424,8 @@ WDataOutP _vl_moddiv_w(int lbits, WDataOutP owp, const WDataInP lwp, const WData } // +1 word as we may shift during normalization - vluint32_t un[VL_MULS_MAX_WORDS + 1]; // Fixed size, as MSVC++ doesn't allow [words] here - vluint32_t vn[VL_MULS_MAX_WORDS + 1]; // v normalized + uint32_t un[VL_MULS_MAX_WORDS + 1]; // Fixed size, as MSVC++ doesn't allow [words] here + uint32_t vn[VL_MULS_MAX_WORDS + 1]; // v normalized // Zero for ease of debugging and to save having to zero for shifts // Note +1 as loop will use extra word @@ -434,7 +434,7 @@ WDataOutP _vl_moddiv_w(int lbits, WDataOutP owp, const WDataInP lwp, const WData // Algorithm requires divisor MSB to be set // Copy and shift to normalize divisor so MSB of vn[vw-1] is set const int s = 31 - VL_BITBIT_I(vmsbp1 - 1); // shift amount (0...31) - const vluint32_t shift_mask = s ? 0xffffffff : 0; // otherwise >> 32 won't mask the value + const uint32_t shift_mask = s ? 0xffffffff : 0; // otherwise >> 32 won't mask the value for (int i = vw - 1; i > 0; --i) { vn[i] = (rwp[i] << s) | (shift_mask & (rwp[i - 1] >> (32 - s))); } @@ -454,10 +454,10 @@ WDataOutP _vl_moddiv_w(int lbits, WDataOutP owp, const WDataInP lwp, const WData // Main loop for (int j = uw - vw; j >= 0; --j) { // Estimate - const vluint64_t unw64 = (static_cast(un[j + vw]) << 32ULL - | static_cast(un[j + vw - 1])); - vluint64_t qhat = unw64 / static_cast(vn[vw - 1]); - vluint64_t rhat = unw64 - qhat * static_cast(vn[vw - 1]); + const uint64_t unw64 + = (static_cast(un[j + vw]) << 32ULL | static_cast(un[j + vw - 1])); + uint64_t qhat = unw64 / static_cast(vn[vw - 1]); + uint64_t rhat = unw64 - qhat * static_cast(vn[vw - 1]); again: if (qhat >= 0x100000000ULL || ((qhat * vn[vw - 2]) > ((rhat << 32ULL) + un[j + vw - 2]))) { @@ -466,10 +466,10 @@ WDataOutP _vl_moddiv_w(int lbits, WDataOutP owp, const WDataInP lwp, const WData if (rhat < 0x100000000ULL) goto again; } - vlsint64_t t = 0; // Must be signed - vluint64_t k = 0; + int64_t t = 0; // Must be signed + uint64_t k = 0; for (int i = 0; i < vw; ++i) { - const vluint64_t p = qhat * vn[i]; // Multiply by estimate + const uint64_t p = qhat * vn[i]; // Multiply by estimate t = un[i + j] - k - (p & 0xFFFFFFFFULL); // Subtract un[i + j] = t; k = (p >> 32ULL) - (t >> 32ULL); @@ -483,7 +483,7 @@ WDataOutP _vl_moddiv_w(int lbits, WDataOutP owp, const WDataInP lwp, const WData owp[j]--; k = 0; for (int i = 0; i < vw; ++i) { - t = static_cast(un[i + j]) + static_cast(vn[i]) + k; + t = static_cast(un[i + j]) + static_cast(vn[i]) + k; un[i + j] = t; k = t >> 32ULL; } @@ -614,7 +614,7 @@ double VL_ITOR_D_W(int lbits, const WDataInP lwp) VL_PURE { } double VL_ISTOR_D_W(int lbits, const WDataInP lwp) VL_PURE { if (!VL_SIGN_W(lbits, lwp)) return VL_ITOR_D_W(lbits, lwp); - vluint32_t pos[VL_MULS_MAX_WORDS + 1]; // Fixed size, as MSVC++ doesn't allow [words] here + uint32_t pos[VL_MULS_MAX_WORDS + 1]; // Fixed size, as MSVC++ doesn't allow [words] here VL_NEGATE_W(VL_WORDS_I(lbits), pos, lwp); _vl_clean_inplace_w(lbits, pos); return -VL_ITOR_D_W(lbits, pos); @@ -688,7 +688,7 @@ std::string _vl_vsformat_time(char* tmp, T ld, int timeunit, bool left, size_t w const WDataInP integer = VL_DIV_WWW(b, tmp0, shifted, fracDigitsPow10); const WDataInP frac = VL_MODDIV_WWW(b, tmp1, shifted, fracDigitsPow10); const WDataInP max64Bit - = VL_EXTEND_WQ(b, 0, tmp2, std::numeric_limits::max()); // breaks shifted + = VL_EXTEND_WQ(b, 0, tmp2, std::numeric_limits::max()); // breaks shifted if (VL_GT_W(w, integer, max64Bit)) { WDataOutP v = VL_ASSIGN_W(b, tmp3, integer); // breaks fracDigitsPow10 VlWide zero, ten; @@ -712,7 +712,7 @@ std::string _vl_vsformat_time(char* tmp, T ld, int timeunit, bool left, size_t w fracDigits, VL_SET_QW(frac), suffix.c_str()); } } else { - const vluint64_t integer64 = VL_SET_QW(integer); + const uint64_t integer64 = VL_SET_QW(integer); if (!fracDigits) { digits = VL_SNPRINTF(tmp, VL_VALUE_STRING_MAX_WIDTH, "%" PRIu64 "%s", integer64, suffix.c_str()); @@ -879,9 +879,9 @@ void _vl_vsformat(std::string& output, const char* formatp, va_list ap) VL_MT_SA int digits = 0; std::string append; if (lbits <= VL_QUADSIZE) { - digits = VL_SNPRINTF( - t_tmp, VL_VALUE_STRING_MAX_WIDTH, "%" PRId64, - static_cast(VL_EXTENDS_QQ(lbits, lbits, ld))); + digits + = VL_SNPRINTF(t_tmp, VL_VALUE_STRING_MAX_WIDTH, "%" PRId64, + static_cast(VL_EXTENDS_QQ(lbits, lbits, ld))); append = t_tmp; } else { if (VL_SIGN_E(lbits, lwp[VL_WORDS_I(lbits) - 1])) { @@ -1184,7 +1184,7 @@ IData _vl_vsscanf(FILE* fp, // If a fscanf _vl_vsss_skipspace(fp, floc, fromp, fstr); _vl_vsss_read_str(fp, floc, fromp, fstr, t_tmp, "0123456789+-xXzZ?_"); if (!t_tmp[0]) goto done; - vlsint64_t ld = 0; + int64_t ld = 0; std::sscanf(t_tmp, "%30" PRId64, &ld); VL_SET_WQ(owp, ld); break; @@ -1198,7 +1198,7 @@ IData _vl_vsscanf(FILE* fp, // If a fscanf // cppcheck-suppress unusedStructMember // It's used union { double r; - vlsint64_t ld; + int64_t ld; } u; u.r = std::strtod(t_tmp, nullptr); VL_SET_WQ(owp, u.ld); @@ -1643,7 +1643,7 @@ IData VL_VALUEPLUSARGS_INW(int rbits, const std::string& ld, WDataOutP rwp) VL_M VL_ZERO_RESET_W(rbits, rwp); switch (std::tolower(fmt)) { case 'd': { - vlsint64_t lld = 0; + int64_t lld = 0; std::sscanf(dp, "%30" PRId64, &lld); VL_SET_WQ(rwp, lld); break; @@ -1768,7 +1768,7 @@ std::string VL_CVT_PACK_STR_NW(int lwords, const WDataInP lwp) VL_MT_SAFE { std::string VL_PUTC_N(const std::string& lhs, IData rhs, CData ths) VL_PURE { std::string lstring = lhs; - const vlsint32_t rhs_s = rhs; // To signed value + const int32_t rhs_s = rhs; // To signed value // 6.16.2:str.putc(i, c) does not change the value when i < 0 || i >= str.len() || c == 0 if (0 <= rhs_s && rhs < lhs.length() && ths != 0) lstring[rhs] = ths; return lstring; @@ -1776,15 +1776,15 @@ std::string VL_PUTC_N(const std::string& lhs, IData rhs, CData ths) VL_PURE { CData VL_GETC_N(const std::string& lhs, IData rhs) VL_PURE { CData v = 0; - const vlsint32_t rhs_s = rhs; // To signed value + const int32_t rhs_s = rhs; // To signed value // 6.16.3:str.getc(i) returns 0 if i < 0 || i >= str.len() if (0 <= rhs_s && rhs < lhs.length()) v = lhs[rhs]; return v; } std::string VL_SUBSTR_N(const std::string& lhs, IData rhs, IData ths) VL_PURE { - const vlsint32_t rhs_s = rhs; // To signed value - const vlsint32_t ths_s = ths; // To signed value + const int32_t rhs_s = rhs; // To signed value + const int32_t ths_s = ths; // To signed value // 6.16.8:str.substr(i, j) returns an empty string when i < 0 || j < i || j >= str.len() if (rhs_s < 0 || ths_s < rhs_s || ths >= lhs.length()) return ""; // Second parameter of std::string::substr(i, n) is length, not position as in SystemVerilog @@ -1823,7 +1823,7 @@ static const char* memhFormat(int nBits) { return t_buf; } -static const char* formatBinary(int nBits, vluint32_t bits) { +static const char* formatBinary(int nBits, uint32_t bits) { assert((nBits >= 1) && (nBits <= 32)); static VL_THREAD_LOCAL char t_buf[64]; @@ -2027,9 +2027,9 @@ void VlWriteMem::print(QData addr, bool addrstamp, const void* valuep) { } } else if (m_bits <= 64) { const QData* const datap = reinterpret_cast(valuep); - const vluint64_t value = VL_MASK_Q(m_bits) & *datap; - const vluint32_t lo = value & 0xffffffff; - const vluint32_t hi = value >> 32; + const uint64_t value = VL_MASK_Q(m_bits) & *datap; + const uint32_t lo = value & 0xffffffff; + const uint32_t hi = value >> 32; if (m_hex) { fprintf(m_fp, memhFormat(m_bits - 32), hi); fprintf(m_fp, "%08x\n", lo); @@ -2235,8 +2235,8 @@ double vl_time_multiplier(int scale) VL_PURE { return pow10[scale]; } } -vluint64_t vl_time_pow10(int n) { - static const vluint64_t pow10[20] = { +uint64_t vl_time_pow10(int n) { + static const uint64_t pow10[20] = { 1ULL, 10ULL, 100ULL, @@ -2348,11 +2348,11 @@ void VerilatedContext::gotFinish(bool flag) VL_MT_SAFE { const VerilatedLockGuard lock{m_mutex}; m_s.m_gotFinish = flag; } -void VerilatedContext::profExecStart(vluint64_t flag) VL_MT_SAFE { +void VerilatedContext::profExecStart(uint64_t flag) VL_MT_SAFE { const VerilatedLockGuard lock{m_mutex}; m_ns.m_profExecStart = flag; } -void VerilatedContext::profExecWindow(vluint64_t flag) VL_MT_SAFE { +void VerilatedContext::profExecWindow(uint64_t flag) VL_MT_SAFE { const VerilatedLockGuard lock{m_mutex}; m_ns.m_profExecWindow = flag; } @@ -2598,20 +2598,19 @@ void VerilatedContext::randSeed(int val) VL_MT_SAFE { // and so the rand seed's mutex must also be static const VerilatedLockGuard lock{VerilatedContextImp::s().s_randMutex}; m_s.m_randSeed = val; - const vluint64_t newEpoch = VerilatedContextImp::s().s_randSeedEpoch + 1; + const uint64_t newEpoch = VerilatedContextImp::s().s_randSeedEpoch + 1; // Obververs must see new epoch AFTER seed updated #ifdef VL_THREADED std::atomic_signal_fence(std::memory_order_release); #endif VerilatedContextImp::s().s_randSeedEpoch = newEpoch; } -vluint64_t VerilatedContextImp::randSeedDefault64() const VL_MT_SAFE { +uint64_t VerilatedContextImp::randSeedDefault64() const VL_MT_SAFE { if (randSeed() != 0) { - return ((static_cast(randSeed()) << 32) - ^ (static_cast(randSeed()))); + return ((static_cast(randSeed()) << 32) ^ (static_cast(randSeed()))); } else { - return ((static_cast(vl_sys_rand32()) << 32) - ^ (static_cast(vl_sys_rand32()))); + return ((static_cast(vl_sys_rand32()) << 32) + ^ (static_cast(vl_sys_rand32()))); } } @@ -2855,8 +2854,8 @@ VerilatedModule::~VerilatedModule() { // VerilatedVar:: Methods // cppcheck-suppress unusedFunction // Used by applications -vluint32_t VerilatedVarProps::entSize() const { - vluint32_t size = 1; +uint32_t VerilatedVarProps::entSize() const { + uint32_t size = 1; switch (vltype()) { case VLVT_PTR: size = sizeof(void*); break; case VLVT_UINT8: size = sizeof(CData); break; @@ -2879,7 +2878,7 @@ void* VerilatedVarProps::datapAdjustIndex(void* datap, int dim, int indx) const if (VL_UNLIKELY(dim <= 0 || dim > udims())) return nullptr; if (VL_UNLIKELY(indx < low(dim) || indx > high(dim))) return nullptr; const int indxAdj = indx - low(dim); - vluint8_t* bytep = reinterpret_cast(datap); + uint8_t* bytep = reinterpret_cast(datap); // If on index 1 of a 2 index array, then each index 1 is index2sz*entsz size_t slicesz = entSize(); for (int d = dim + 1; d <= m_udims; ++d) slicesz *= elements(d); @@ -2900,7 +2899,7 @@ VerilatedScope::~VerilatedScope() { } void VerilatedScope::configure(VerilatedSyms* symsp, const char* prefixp, const char* suffixp, - const char* identifier, vlsint8_t timeunit, + const char* identifier, int8_t timeunit, const Type& type) VL_MT_UNSAFE { // Slowpath - called once/scope at construction // We don't want the space and reference-count access overhead of strings. diff --git a/include/verilated.h b/include/verilated.h index 15ea667c6..889f59c7b 100644 --- a/include/verilated.h +++ b/include/verilated.h @@ -101,11 +101,11 @@ class VerilatedVcdSc; // clang-format off // P // Packed data of bit type (C/S/I/Q/W) -using CData = vluint8_t; ///< Data representing 'bit' of 1-8 packed bits -using SData = vluint16_t; ///< Data representing 'bit' of 9-16 packed bits -using IData = vluint32_t; ///< Data representing 'bit' of 17-32 packed bits -using QData = vluint64_t; ///< Data representing 'bit' of 33-64 packed bits -using EData = vluint32_t; ///< Data representing one element of WData array +using CData = uint8_t; ///< Data representing 'bit' of 1-8 packed bits +using SData = uint16_t; ///< Data representing 'bit' of 9-16 packed bits +using IData = uint32_t; ///< Data representing 'bit' of 17-32 packed bits +using QData = uint64_t; ///< Data representing 'bit' of 33-64 packed bits +using EData = uint32_t; ///< Data representing one element of WData array using WData = EData; ///< Data representing >64 packed bits (used as pointer) // F = float; // No typedef needed; Verilator uses float // D = double; // No typedef needed; Verilator uses double @@ -115,7 +115,7 @@ using WData = EData; ///< Data representing >64 packed bits (used as poin using WDataInP = const WData*; ///< 'bit' of >64 packed bits as array input to a function using WDataOutP = WData*; ///< 'bit' of >64 packed bits as array output from a function -enum VerilatedVarType : vluint8_t { +enum VerilatedVarType : uint8_t { VLVT_UNKNOWN = 0, VLVT_PTR, // Pointer to something VLVT_UINT8, // AKA CData @@ -143,7 +143,7 @@ enum VerilatedVarFlags { // Mutex and threading support // Return current thread ID (or 0), not super fast, cache if needed -extern vluint32_t VL_THREAD_ID() VL_MT_SAFE; +extern uint32_t VL_THREAD_ID() VL_MT_SAFE; #if VL_THREADED @@ -226,7 +226,7 @@ public: class VerilatedAssertOneThread final { // MEMBERS #if defined(VL_THREADED) && defined(VL_DEBUG) - vluint32_t m_threadid; // Thread that is legal + uint32_t m_threadid; // Thread that is legal public: // CONSTRUCTORS // The constructor establishes the thread id for all later calls. @@ -320,10 +320,10 @@ protected: bool m_fatalOnVpiError = true; // Fatal on vpi error/unsupported bool m_gotError = false; // A $finish statement executed bool m_gotFinish = false; // A $finish or $stop statement executed - vluint64_t m_time = 0; // Current $time (unscaled), 0=at zero, or legacy + uint64_t m_time = 0; // Current $time (unscaled), 0=at zero, or legacy // Slow path - vlsint8_t m_timeunit; // Time unit as 0..15 - vlsint8_t m_timeprecision; // Time precision as 0..15 + int8_t m_timeunit; // Time unit as 0..15 + int8_t m_timeprecision; // Time precision as 0..15 int m_errorCount = 0; // Number of errors int m_errorLimit = 1; // Stop on error number int m_randReset = 0; // Random reset: 0=all 0s, 1=all 1s, 2=random @@ -344,8 +344,8 @@ protected: struct NonSerialized { // Non-serialized information // These are reloaded from on command-line settings, so do not need to persist // Fast path - vluint64_t m_profExecStart = 1; // +prof+exec+start time - vluint32_t m_profExecWindow = 2; // +prof+exec+window size + uint64_t m_profExecStart = 1; // +prof+exec+start time + uint32_t m_profExecWindow = 2; // +prof+exec+window size // Slow path std::string m_profExecFilename; // +prof+exec+file filename std::string m_profVltFilename; // +prof+vlt filename @@ -468,16 +468,16 @@ public: /// timeInc, operating on the thread's context. /// /// * Else, if VL_TIME_STAMP64 is defined, time comes from the legacy - /// 'vluint64_t vl_time_stamp64()' which must a function be defined by + /// 'uint64_t vl_time_stamp64()' which must a function be defined by /// the user's wrapper. /// /// * Else, time comes from the legacy 'double sc_time_stamp()' which /// must be a function defined by the user's wrapper. - vluint64_t time() const VL_MT_SAFE; + uint64_t time() const VL_MT_SAFE; /// Set current simulation time. See time() for side effect details - void time(vluint64_t value) VL_MT_SAFE { m_s.m_time = value; } + void time(uint64_t value) VL_MT_SAFE { m_s.m_time = value; } /// Advance current simulation time. See time() for side effect details - void timeInc(vluint64_t add) VL_MT_UNSAFE { m_s.m_time += add; } + void timeInc(uint64_t add) VL_MT_UNSAFE { m_s.m_time += add; } /// Return time units as power-of-ten int timeunit() const VL_MT_SAFE { return -m_s.m_timeunit; } /// Set time units as power-of-ten @@ -519,10 +519,10 @@ public: // But for internal use only std::string dumpfileCheck() const VL_MT_SAFE_EXCLUDES(m_timeDumpMutex); // Internal: --prof-exec related settings - void profExecStart(vluint64_t flag) VL_MT_SAFE; - vluint64_t profExecStart() const VL_MT_SAFE { return m_ns.m_profExecStart; } - void profExecWindow(vluint64_t flag) VL_MT_SAFE; - vluint32_t profExecWindow() const VL_MT_SAFE { return m_ns.m_profExecWindow; } + void profExecStart(uint64_t flag) VL_MT_SAFE; + uint64_t profExecStart() const VL_MT_SAFE { return m_ns.m_profExecStart; } + void profExecWindow(uint64_t flag) VL_MT_SAFE; + uint32_t profExecWindow() const VL_MT_SAFE { return m_ns.m_profExecWindow; } void profExecFilename(const std::string& flag) VL_MT_SAFE; std::string profExecFilename() const VL_MT_SAFE; void profVltFilename(const std::string& flag) VL_MT_SAFE; @@ -559,7 +559,7 @@ public: // But for internal use only class VerilatedScope final { public: - enum Type : vluint8_t { + enum Type : uint8_t { SCOPE_MODULE, SCOPE_OTHER }; // Type of a scope, currently module is only interesting @@ -572,21 +572,21 @@ private: VerilatedVarNameMap* m_varsp = nullptr; // Variable map const char* m_namep = nullptr; // Scope name (Slowpath) const char* m_identifierp = nullptr; // Identifier of scope (with escapes removed) - vlsint8_t m_timeunit = 0; // Timeunit in negative power-of-10 + int8_t m_timeunit = 0; // Timeunit in negative power-of-10 Type m_type = SCOPE_OTHER; // Type of the scope public: // But internals only - called from VerilatedModule's VerilatedScope() = default; ~VerilatedScope(); void configure(VerilatedSyms* symsp, const char* prefixp, const char* suffixp, - const char* identifier, vlsint8_t timeunit, const Type& type) VL_MT_UNSAFE; + const char* identifier, int8_t timeunit, const Type& type) VL_MT_UNSAFE; void exportInsert(int finalize, const char* namep, void* cb) VL_MT_UNSAFE; void varInsert(int finalize, const char* namep, void* datap, bool isParam, VerilatedVarType vltype, int vlflags, int dims, ...) VL_MT_UNSAFE; // ACCESSORS const char* name() const { return m_namep; } const char* identifier() const { return m_identifierp; } - vlsint8_t timeunit() const { return m_timeunit; } + int8_t timeunit() const { return m_timeunit; } inline VerilatedSyms* symsp() const { return m_symsp; } VerilatedVar* varFind(const char* namep) const VL_MT_SAFE_POSTINIT; VerilatedVarNameMap* varsp() const VL_MT_SAFE_POSTINIT { return m_varsp; } @@ -636,9 +636,9 @@ class Verilated final { // Fast path VerilatedContext* t_contextp = nullptr; // Thread's context #ifdef VL_THREADED - vluint32_t t_mtaskId = 0; // mtask# executing on this thread + uint32_t t_mtaskId = 0; // mtask# executing on this thread // Messages maybe pending on thread, needs end-of-eval calls - vluint32_t t_endOfEvalReqd = 0; + uint32_t t_endOfEvalReqd = 0; #endif const VerilatedScope* t_dpiScopep = nullptr; // DPI context scope const char* t_dpiFilename = nullptr; // DPI context filename @@ -760,11 +760,11 @@ public: /// Return VerilatedContext::randSeed using current thread's VerilatedContext static int randSeed() VL_MT_SAFE { return Verilated::threadContextp()->randSeed(); } /// Call VerilatedContext::time using current thread's VerilatedContext - static void time(vluint64_t val) VL_MT_SAFE { Verilated::threadContextp()->time(val); } + static void time(uint64_t val) VL_MT_SAFE { Verilated::threadContextp()->time(val); } /// Return VerilatedContext::time using current thread's VerilatedContext - static vluint64_t time() VL_MT_SAFE { return Verilated::threadContextp()->time(); } + static uint64_t time() VL_MT_SAFE { return Verilated::threadContextp()->time(); } /// Call VerilatedContext::timeInc using current thread's VerilatedContext - static void timeInc(vluint64_t add) VL_MT_UNSAFE { Verilated::threadContextp()->timeInc(add); } + static void timeInc(uint64_t add) VL_MT_UNSAFE { Verilated::threadContextp()->timeInc(add); } // Deprecated static int timeunit() VL_MT_SAFE { return Verilated::threadContextp()->timeunit(); } static int timeprecision() VL_MT_SAFE { return Verilated::threadContextp()->timeprecision(); } @@ -850,8 +850,8 @@ public: #ifdef VL_THREADED // Internal: Set the mtaskId, called when an mtask starts // Per thread, so no need to be in VerilatedContext - static void mtaskId(vluint32_t id) VL_MT_SAFE { t_s.t_mtaskId = id; } - static vluint32_t mtaskId() VL_MT_SAFE { return t_s.t_mtaskId; } + static void mtaskId(uint32_t id) VL_MT_SAFE { t_s.t_mtaskId = id; } + static uint32_t mtaskId() VL_MT_SAFE { return t_s.t_mtaskId; } static void endOfEvalReqdInc() VL_MT_SAFE { ++t_s.t_endOfEvalReqd; } static void endOfEvalReqdDec() VL_MT_SAFE { --t_s.t_endOfEvalReqd; } diff --git a/include/verilated_cov.cpp b/include/verilated_cov.cpp index 6a1fcf69a..dd559427a 100644 --- a/include/verilated_cov.cpp +++ b/include/verilated_cov.cpp @@ -59,7 +59,7 @@ public: // But only local to this file } } virtual ~VerilatedCovImpItem() = default; - virtual vluint64_t count() const = 0; + virtual uint64_t count() const = 0; virtual void zero() const = 0; }; @@ -76,7 +76,7 @@ private: public: // METHODS // cppcheck-suppress truncLongCastReturn - virtual vluint64_t count() const override { return *m_countp; } + virtual uint64_t count() const override { return *m_countp; } virtual void zero() const override { *m_countp = 0; } // CONSTRUCTORS // cppcheck-suppress noExplicitConstructor @@ -372,7 +372,7 @@ public: os << "# SystemC::Coverage-3\n"; // Build list of events; totalize if collapsing hierarchy - std::map> eventCounts; + std::map> eventCounts; for (const auto& itemp : m_items) { std::string name; std::string hier; @@ -439,11 +439,11 @@ void VerilatedCovContext::clearNonMatch(const char* matchp) VL_MT_SAFE { } void VerilatedCovContext::zero() VL_MT_SAFE { impp()->zero(); } void VerilatedCovContext::write(const char* filenamep) VL_MT_SAFE { impp()->write(filenamep); } -void VerilatedCovContext::_inserti(vluint32_t* itemp) VL_MT_SAFE { - impp()->inserti(new VerilatedCoverItemSpec{itemp}); +void VerilatedCovContext::_inserti(uint32_t* itemp) VL_MT_SAFE { + impp()->inserti(new VerilatedCoverItemSpec{itemp}); } -void VerilatedCovContext::_inserti(vluint64_t* itemp) VL_MT_SAFE { - impp()->inserti(new VerilatedCoverItemSpec{itemp}); +void VerilatedCovContext::_inserti(uint64_t* itemp) VL_MT_SAFE { + impp()->inserti(new VerilatedCoverItemSpec{itemp}); } void VerilatedCovContext::_insertf(const char* filename, int lineno) VL_MT_SAFE { impp()->insertf(filename, lineno); diff --git a/include/verilated_cov.h b/include/verilated_cov.h index 30ca063c6..d7bc1b993 100644 --- a/include/verilated_cov.h +++ b/include/verilated_cov.h @@ -72,7 +72,7 @@ class VerilatedCovImp; /// /// Example: /// -/// vluint32_t m_cases[10]; // Storage for coverage data +/// uint32_t m_cases[10]; // Storage for coverage data /// constructor() { /// // Initialize /// for (int i = 0; i < 10; ++i) m_cases[i] = 0; @@ -126,8 +126,8 @@ public: // But Internal use only // Call _insert1, followed by _insert2 and _insert3 // Do not call directly; use VL_COVER_INSERT or higher level macros instead // _insert1: Remember item pointer with count. (Not const, as may add zeroing function) - void _inserti(vluint32_t* itemp) VL_MT_SAFE; - void _inserti(vluint64_t* itemp) VL_MT_SAFE; + void _inserti(uint32_t* itemp) VL_MT_SAFE; + void _inserti(uint64_t* itemp) VL_MT_SAFE; // _insert2: Set default filename and line number void _insertf(const char* filename, int lineno) VL_MT_SAFE; // _insert3: Set parameters diff --git a/include/verilated_fst_c.cpp b/include/verilated_fst_c.cpp index 365834b88..68431db71 100644 --- a/include/verilated_fst_c.cpp +++ b/include/verilated_fst_c.cpp @@ -144,12 +144,12 @@ void VerilatedFst::flush() VL_MT_SAFE_EXCLUDES(m_mutex) { fstWriterFlushContext(m_fst); } -void VerilatedFst::emitTimeChange(vluint64_t timeui) { fstWriterEmitTimeChange(m_fst, timeui); } +void VerilatedFst::emitTimeChange(uint64_t timeui) { fstWriterEmitTimeChange(m_fst, timeui); } //============================================================================= // Decl -void VerilatedFst::declDTypeEnum(int dtypenum, const char* name, vluint32_t elements, +void VerilatedFst::declDTypeEnum(int dtypenum, const char* name, uint32_t elements, unsigned int minValbits, const char** itemNamesp, const char** itemValuesp) { const fstEnumHandle enumNum @@ -157,7 +157,7 @@ void VerilatedFst::declDTypeEnum(int dtypenum, const char* name, vluint32_t elem m_local2fstdtype[dtypenum] = enumNum; } -void VerilatedFst::declare(vluint32_t code, const char* name, int dtypenum, fstVarDir vardir, +void VerilatedFst::declare(uint32_t code, const char* name, int dtypenum, fstVarDir vardir, fstVarType vartype, bool array, int arraynum, bool bussed, int msb, int lsb) { const int bits = ((msb > lsb) ? (msb - lsb) : (lsb - msb)) + 1; @@ -224,23 +224,23 @@ void VerilatedFst::declare(vluint32_t code, const char* name, int dtypenum, fstV } } -void VerilatedFst::declBit(vluint32_t code, const char* name, int dtypenum, fstVarDir vardir, +void VerilatedFst::declBit(uint32_t code, const char* name, int dtypenum, fstVarDir vardir, fstVarType vartype, bool array, int arraynum) { declare(code, name, dtypenum, vardir, vartype, array, arraynum, false, 0, 0); } -void VerilatedFst::declBus(vluint32_t code, const char* name, int dtypenum, fstVarDir vardir, +void VerilatedFst::declBus(uint32_t code, const char* name, int dtypenum, fstVarDir vardir, fstVarType vartype, bool array, int arraynum, int msb, int lsb) { declare(code, name, dtypenum, vardir, vartype, array, arraynum, true, msb, lsb); } -void VerilatedFst::declQuad(vluint32_t code, const char* name, int dtypenum, fstVarDir vardir, +void VerilatedFst::declQuad(uint32_t code, const char* name, int dtypenum, fstVarDir vardir, fstVarType vartype, bool array, int arraynum, int msb, int lsb) { declare(code, name, dtypenum, vardir, vartype, array, arraynum, true, msb, lsb); } -void VerilatedFst::declArray(vluint32_t code, const char* name, int dtypenum, fstVarDir vardir, +void VerilatedFst::declArray(uint32_t code, const char* name, int dtypenum, fstVarDir vardir, fstVarType vartype, bool array, int arraynum, int msb, int lsb) { declare(code, name, dtypenum, vardir, vartype, array, arraynum, true, msb, lsb); } -void VerilatedFst::declDouble(vluint32_t code, const char* name, int dtypenum, fstVarDir vardir, +void VerilatedFst::declDouble(uint32_t code, const char* name, int dtypenum, fstVarDir vardir, fstVarType vartype, bool array, int arraynum) { declare(code, name, dtypenum, vardir, vartype, array, arraynum, false, 63, 0); } @@ -250,13 +250,13 @@ void VerilatedFst::declDouble(vluint32_t code, const char* name, int dtypenum, f // so always inline them. VL_ATTR_ALWINLINE -void VerilatedFst::emitBit(vluint32_t code, CData newval) { +void VerilatedFst::emitBit(uint32_t code, CData newval) { VL_DEBUG_IFDEF(assert(m_symbolp[code]);); fstWriterEmitValueChange(m_fst, m_symbolp[code], newval ? "1" : "0"); } VL_ATTR_ALWINLINE -void VerilatedFst::emitCData(vluint32_t code, CData newval, int bits) { +void VerilatedFst::emitCData(uint32_t code, CData newval, int bits) { char buf[VL_BYTESIZE]; VL_DEBUG_IFDEF(assert(m_symbolp[code]);); cvtCDataToStr(buf, newval << (VL_BYTESIZE - bits)); @@ -264,7 +264,7 @@ void VerilatedFst::emitCData(vluint32_t code, CData newval, int bits) { } VL_ATTR_ALWINLINE -void VerilatedFst::emitSData(vluint32_t code, SData newval, int bits) { +void VerilatedFst::emitSData(uint32_t code, SData newval, int bits) { char buf[VL_SHORTSIZE]; VL_DEBUG_IFDEF(assert(m_symbolp[code]);); cvtSDataToStr(buf, newval << (VL_SHORTSIZE - bits)); @@ -272,7 +272,7 @@ void VerilatedFst::emitSData(vluint32_t code, SData newval, int bits) { } VL_ATTR_ALWINLINE -void VerilatedFst::emitIData(vluint32_t code, IData newval, int bits) { +void VerilatedFst::emitIData(uint32_t code, IData newval, int bits) { char buf[VL_IDATASIZE]; VL_DEBUG_IFDEF(assert(m_symbolp[code]);); cvtIDataToStr(buf, newval << (VL_IDATASIZE - bits)); @@ -280,7 +280,7 @@ void VerilatedFst::emitIData(vluint32_t code, IData newval, int bits) { } VL_ATTR_ALWINLINE -void VerilatedFst::emitQData(vluint32_t code, QData newval, int bits) { +void VerilatedFst::emitQData(uint32_t code, QData newval, int bits) { char buf[VL_QUADSIZE]; VL_DEBUG_IFDEF(assert(m_symbolp[code]);); cvtQDataToStr(buf, newval << (VL_QUADSIZE - bits)); @@ -288,7 +288,7 @@ void VerilatedFst::emitQData(vluint32_t code, QData newval, int bits) { } VL_ATTR_ALWINLINE -void VerilatedFst::emitWData(vluint32_t code, const WData* newvalp, int bits) { +void VerilatedFst::emitWData(uint32_t code, const WData* newvalp, int bits) { int words = VL_WORDS_I(bits); char* wp = m_strbuf; // Convert the most significant word @@ -304,6 +304,6 @@ void VerilatedFst::emitWData(vluint32_t code, const WData* newvalp, int bits) { } VL_ATTR_ALWINLINE -void VerilatedFst::emitDouble(vluint32_t code, double newval) { +void VerilatedFst::emitDouble(uint32_t code, double newval) { fstWriterEmitValueChange(m_fst, m_symbolp[code], &newval); } diff --git a/include/verilated_fst_c.h b/include/verilated_fst_c.h index 3e48daf92..b622a1894 100644 --- a/include/verilated_fst_c.h +++ b/include/verilated_fst_c.h @@ -45,7 +45,7 @@ private: // FST specific internals void* m_fst; - std::map m_code2symbol; + std::map m_code2symbol; std::map m_local2fstdtype; std::list m_curScope; fstHandle* m_symbolp = nullptr; // same as m_code2symbol, but as an array @@ -53,7 +53,7 @@ private: // CONSTRUCTORS VL_UNCOPYABLE(VerilatedFst); - void declare(vluint32_t code, const char* name, int dtypenum, fstVarDir vardir, + void declare(uint32_t code, const char* name, int dtypenum, fstVarDir vardir, fstVarType vartype, bool array, int arraynum, bool bussed, int msb, int lsb); protected: @@ -61,7 +61,7 @@ protected: // Implementation of VerilatedTrace interface // Implementations of protected virtual methods for VerilatedTrace - virtual void emitTimeChange(vluint64_t timeui) override; + virtual void emitTimeChange(uint64_t timeui) override; // Hooks called from VerilatedTrace virtual bool preFullDump() override { return isOpen(); } @@ -69,13 +69,13 @@ protected: // Implementations of duck-typed methods for VerilatedTrace. These are // called from only one place (namely full*) so always inline them. - inline void emitBit(vluint32_t code, CData newval); - inline void emitCData(vluint32_t code, CData newval, int bits); - inline void emitSData(vluint32_t code, SData newval, int bits); - inline void emitIData(vluint32_t code, IData newval, int bits); - inline void emitQData(vluint32_t code, QData newval, int bits); - inline void emitWData(vluint32_t code, const WData* newvalp, int bits); - inline void emitDouble(vluint32_t code, double newval); + inline void emitBit(uint32_t code, CData newval); + inline void emitCData(uint32_t code, CData newval, int bits); + inline void emitSData(uint32_t code, SData newval, int bits); + inline void emitIData(uint32_t code, IData newval, int bits); + inline void emitQData(uint32_t code, QData newval, int bits); + inline void emitWData(uint32_t code, const WData* newvalp, int bits); + inline void emitDouble(uint32_t code, double newval); public: //========================================================================= @@ -98,25 +98,25 @@ public: // Internal interface to Verilator generated code // Inside dumping routines, declare a data type - void declDTypeEnum(int dtypenum, const char* name, vluint32_t elements, - unsigned int minValbits, const char** itemNamesp, const char** itemValuesp); + void declDTypeEnum(int dtypenum, const char* name, uint32_t elements, unsigned int minValbits, + const char** itemNamesp, const char** itemValuesp); // Inside dumping routines, declare a signal - void declBit(vluint32_t code, const char* name, int dtypenum, fstVarDir vardir, + void declBit(uint32_t code, const char* name, int dtypenum, fstVarDir vardir, fstVarType vartype, bool array, int arraynum); - void declBus(vluint32_t code, const char* name, int dtypenum, fstVarDir vardir, + void declBus(uint32_t code, const char* name, int dtypenum, fstVarDir vardir, fstVarType vartype, bool array, int arraynum, int msb, int lsb); - void declQuad(vluint32_t code, const char* name, int dtypenum, fstVarDir vardir, + void declQuad(uint32_t code, const char* name, int dtypenum, fstVarDir vardir, fstVarType vartype, bool array, int arraynum, int msb, int lsb); - void declArray(vluint32_t code, const char* name, int dtypenum, fstVarDir vardir, + void declArray(uint32_t code, const char* name, int dtypenum, fstVarDir vardir, fstVarType vartype, bool array, int arraynum, int msb, int lsb); - void declDouble(vluint32_t code, const char* name, int dtypenum, fstVarDir vardir, + void declDouble(uint32_t code, const char* name, int dtypenum, fstVarDir vardir, fstVarType vartype, bool array, int arraynum); }; #ifndef DOXYGEN // Declare specialization here as it's used in VerilatedFstC just below -template <> void VerilatedTrace::dump(vluint64_t timeui); +template <> void VerilatedTrace::dump(uint64_t timeui); template <> void VerilatedTrace::set_time_unit(const char* unitp); template <> void VerilatedTrace::set_time_unit(const std::string& unit); template <> void VerilatedTrace::set_time_resolution(const char* unitp); @@ -155,12 +155,12 @@ public: /// Write one cycle of dump data /// Call with the current context's time just after eval'ed, /// e.g. ->dump(contextp->time()) - void dump(vluint64_t timeui) { m_sptrace.dump(timeui); } + void dump(uint64_t timeui) { m_sptrace.dump(timeui); } /// Write one cycle of dump data - backward compatible and to reduce - /// conversion warnings. It's better to use a vluint64_t time instead. - void dump(double timestamp) { dump(static_cast(timestamp)); } - void dump(vluint32_t timestamp) { dump(static_cast(timestamp)); } - void dump(int timestamp) { dump(static_cast(timestamp)); } + /// conversion warnings. It's better to use a uint64_t time instead. + void dump(double timestamp) { dump(static_cast(timestamp)); } + void dump(uint32_t timestamp) { dump(static_cast(timestamp)); } + void dump(int timestamp) { dump(static_cast(timestamp)); } // METHODS - Internal/backward compatible // \protectedsection diff --git a/include/verilated_funcs.h b/include/verilated_funcs.h index 481e8980a..ab71839b5 100644 --- a/include/verilated_funcs.h +++ b/include/verilated_funcs.h @@ -90,7 +90,7 @@ extern WDataOutP VL_RANDOM_W(int obits, WDataOutP outwp); extern IData VL_RANDOM_SEEDED_II(IData& seedr) VL_MT_SAFE; extern IData VL_URANDOM_SEEDED_II(IData seed) VL_MT_SAFE; inline IData VL_URANDOM_RANGE_I(IData hi, IData lo) { - const vluint64_t rnd = vl_rand64(); + const uint64_t rnd = vl_rand64(); if (VL_LIKELY(hi > lo)) { // (hi - lo + 1) can be zero when hi is UINT_MAX and lo is zero if (VL_UNLIKELY(hi - lo + 1 == 0)) return rnd; @@ -210,29 +210,27 @@ static inline QData VL_CVT_Q_D(double lhs) VL_PURE { // Return double from lhs (numeric) unsigned double VL_ITOR_D_W(int lbits, WDataInP const lwp) VL_PURE; static inline double VL_ITOR_D_I(int, IData lhs) VL_PURE { - return static_cast(static_cast(lhs)); + return static_cast(static_cast(lhs)); } static inline double VL_ITOR_D_Q(int, QData lhs) VL_PURE { - return static_cast(static_cast(lhs)); + return static_cast(static_cast(lhs)); } // Return double from lhs (numeric) signed double VL_ISTOR_D_W(int lbits, WDataInP const lwp) VL_PURE; static inline double VL_ISTOR_D_I(int lbits, IData lhs) VL_PURE { - if (lbits == 32) return static_cast(static_cast(lhs)); + if (lbits == 32) return static_cast(static_cast(lhs)); VlWide lwp; VL_SET_WI(lwp, lhs); return VL_ISTOR_D_W(lbits, lwp); } static inline double VL_ISTOR_D_Q(int lbits, QData lhs) VL_PURE { - if (lbits == 64) return static_cast(static_cast(lhs)); + if (lbits == 64) return static_cast(static_cast(lhs)); VlWide lwp; VL_SET_WQ(lwp, lhs); return VL_ISTOR_D_W(lbits, lwp); } // Return QData from double (numeric) -static inline IData VL_RTOI_I_D(double lhs) VL_PURE { - return static_cast(VL_TRUNC(lhs)); -} +static inline IData VL_RTOI_I_D(double lhs) VL_PURE { return static_cast(VL_TRUNC(lhs)); } // Sign extend such that if MSB set, we get ffff_ffff, else 0s // (Requires clean input) @@ -281,28 +279,28 @@ extern int VL_TIME_STR_CONVERT(const char* strp) VL_PURE; #if defined(SYSTEMC_VERSION) /// Return current simulation time // Already defined: extern sc_time sc_time_stamp(); -inline vluint64_t vl_time_stamp64() { return sc_time_stamp().value(); } +inline uint64_t vl_time_stamp64() { return sc_time_stamp().value(); } #else // Non-SystemC # if !defined(VL_TIME_CONTEXT) && !defined(VL_NO_LEGACY) # ifdef VL_TIME_STAMP64 // vl_time_stamp64() may be optionally defined by the user to return time. // On MSVC++ weak symbols are not supported so must be declared, or define // VL_TIME_CONTEXT. -extern vluint64_t vl_time_stamp64() VL_ATTR_WEAK; +extern uint64_t vl_time_stamp64() VL_ATTR_WEAK; # else // sc_time_stamp() may be optionally defined by the user to return time. // On MSVC++ weak symbols are not supported so must be declared, or define // VL_TIME_CONTEXT. extern double sc_time_stamp() VL_ATTR_WEAK; // Verilator 4.032 and newer -inline vluint64_t vl_time_stamp64() { +inline uint64_t vl_time_stamp64() { // clang9.0.1 requires & although we really do want the weak symbol value - return VL_LIKELY(&sc_time_stamp) ? static_cast(sc_time_stamp()) : 0; + return VL_LIKELY(&sc_time_stamp) ? static_cast(sc_time_stamp()) : 0; } # endif # endif #endif -inline vluint64_t VerilatedContext::time() const VL_MT_SAFE { +inline uint64_t VerilatedContext::time() const VL_MT_SAFE { // When using non-default context, fastest path is return time if (VL_LIKELY(m_s.m_time)) return m_s.m_time; #if defined(SYSTEMC_VERSION) || (!defined(VL_TIME_CONTEXT) && !defined(VL_NO_LEGACY)) @@ -327,7 +325,7 @@ inline vluint64_t VerilatedContext::time() const VL_MT_SAFE { // Return time precision as multiplier of time units double vl_time_multiplier(int scale) VL_PURE; // Return power of 10. e.g. returns 100 if n==2 -vluint64_t vl_time_pow10(int n) VL_PURE; +uint64_t vl_time_pow10(int n) VL_PURE; #ifdef VL_DEBUG /// Evaluate statement if VL_DEBUG defined @@ -873,46 +871,46 @@ static inline int _vl_cmp_w(int words, WDataInP const lwp, WDataInP const rwp) V static inline IData VL_GTS_III(int lbits, IData lhs, IData rhs) VL_PURE { // For lbits==32, this becomes just a single instruction, otherwise ~5. // GCC 3.3.4 sign extension bugs on AMD64 architecture force us to use quad logic - const vlsint64_t lhs_signed = VL_EXTENDS_QQ(64, lbits, lhs); // Q for gcc - const vlsint64_t rhs_signed = VL_EXTENDS_QQ(64, lbits, rhs); // Q for gcc + const int64_t lhs_signed = VL_EXTENDS_QQ(64, lbits, lhs); // Q for gcc + const int64_t rhs_signed = VL_EXTENDS_QQ(64, lbits, rhs); // Q for gcc return lhs_signed > rhs_signed; } static inline IData VL_GTS_IQQ(int lbits, QData lhs, QData rhs) VL_PURE { - const vlsint64_t lhs_signed = VL_EXTENDS_QQ(64, lbits, lhs); - const vlsint64_t rhs_signed = VL_EXTENDS_QQ(64, lbits, rhs); + const int64_t lhs_signed = VL_EXTENDS_QQ(64, lbits, lhs); + const int64_t rhs_signed = VL_EXTENDS_QQ(64, lbits, rhs); return lhs_signed > rhs_signed; } static inline IData VL_GTES_III(int lbits, IData lhs, IData rhs) VL_PURE { - const vlsint64_t lhs_signed = VL_EXTENDS_QQ(64, lbits, lhs); // Q for gcc - const vlsint64_t rhs_signed = VL_EXTENDS_QQ(64, lbits, rhs); // Q for gcc + const int64_t lhs_signed = VL_EXTENDS_QQ(64, lbits, lhs); // Q for gcc + const int64_t rhs_signed = VL_EXTENDS_QQ(64, lbits, rhs); // Q for gcc return lhs_signed >= rhs_signed; } static inline IData VL_GTES_IQQ(int lbits, QData lhs, QData rhs) VL_PURE { - const vlsint64_t lhs_signed = VL_EXTENDS_QQ(64, lbits, lhs); - const vlsint64_t rhs_signed = VL_EXTENDS_QQ(64, lbits, rhs); + const int64_t lhs_signed = VL_EXTENDS_QQ(64, lbits, lhs); + const int64_t rhs_signed = VL_EXTENDS_QQ(64, lbits, rhs); return lhs_signed >= rhs_signed; } static inline IData VL_LTS_III(int lbits, IData lhs, IData rhs) VL_PURE { - const vlsint64_t lhs_signed = VL_EXTENDS_QQ(64, lbits, lhs); // Q for gcc - const vlsint64_t rhs_signed = VL_EXTENDS_QQ(64, lbits, rhs); // Q for gcc + const int64_t lhs_signed = VL_EXTENDS_QQ(64, lbits, lhs); // Q for gcc + const int64_t rhs_signed = VL_EXTENDS_QQ(64, lbits, rhs); // Q for gcc return lhs_signed < rhs_signed; } static inline IData VL_LTS_IQQ(int lbits, QData lhs, QData rhs) VL_PURE { - const vlsint64_t lhs_signed = VL_EXTENDS_QQ(64, lbits, lhs); - const vlsint64_t rhs_signed = VL_EXTENDS_QQ(64, lbits, rhs); + const int64_t lhs_signed = VL_EXTENDS_QQ(64, lbits, lhs); + const int64_t rhs_signed = VL_EXTENDS_QQ(64, lbits, rhs); return lhs_signed < rhs_signed; } static inline IData VL_LTES_III(int lbits, IData lhs, IData rhs) VL_PURE { - const vlsint64_t lhs_signed = VL_EXTENDS_QQ(64, lbits, lhs); // Q for gcc - const vlsint64_t rhs_signed = VL_EXTENDS_QQ(64, lbits, rhs); // Q for gcc + const int64_t lhs_signed = VL_EXTENDS_QQ(64, lbits, lhs); // Q for gcc + const int64_t rhs_signed = VL_EXTENDS_QQ(64, lbits, rhs); // Q for gcc return lhs_signed <= rhs_signed; } static inline IData VL_LTES_IQQ(int lbits, QData lhs, QData rhs) VL_PURE { - const vlsint64_t lhs_signed = VL_EXTENDS_QQ(64, lbits, lhs); - const vlsint64_t rhs_signed = VL_EXTENDS_QQ(64, lbits, rhs); + const int64_t lhs_signed = VL_EXTENDS_QQ(64, lbits, lhs); + const int64_t rhs_signed = VL_EXTENDS_QQ(64, lbits, rhs); return lhs_signed <= rhs_signed; } @@ -1006,13 +1004,13 @@ static inline WDataOutP VL_MUL_W(int words, WDataOutP owp, WDataInP const lwp, } static inline IData VL_MULS_III(int lbits, IData lhs, IData rhs) VL_PURE { - const vlsint32_t lhs_signed = VL_EXTENDS_II(32, lbits, lhs); - const vlsint32_t rhs_signed = VL_EXTENDS_II(32, lbits, rhs); + const int32_t lhs_signed = VL_EXTENDS_II(32, lbits, lhs); + const int32_t rhs_signed = VL_EXTENDS_II(32, lbits, rhs); return lhs_signed * rhs_signed; } static inline QData VL_MULS_QQQ(int lbits, QData lhs, QData rhs) VL_PURE { - const vlsint64_t lhs_signed = VL_EXTENDS_QQ(64, lbits, lhs); - const vlsint64_t rhs_signed = VL_EXTENDS_QQ(64, lbits, rhs); + const int64_t lhs_signed = VL_EXTENDS_QQ(64, lbits, lhs); + const int64_t rhs_signed = VL_EXTENDS_QQ(64, lbits, rhs); return lhs_signed * rhs_signed; } @@ -1058,30 +1056,30 @@ static inline IData VL_DIVS_III(int lbits, IData lhs, IData rhs) VL_PURE { if (VL_UNLIKELY(rhs == 0)) return 0; // -MAX / -1 cannot be represented in twos complement, and will cause SIGFPE if (VL_UNLIKELY(lhs == 0x80000000 && rhs == 0xffffffff)) return 0; - const vlsint32_t lhs_signed = VL_EXTENDS_II(VL_IDATASIZE, lbits, lhs); - const vlsint32_t rhs_signed = VL_EXTENDS_II(VL_IDATASIZE, lbits, rhs); + const int32_t lhs_signed = VL_EXTENDS_II(VL_IDATASIZE, lbits, lhs); + const int32_t rhs_signed = VL_EXTENDS_II(VL_IDATASIZE, lbits, rhs); return lhs_signed / rhs_signed; } static inline QData VL_DIVS_QQQ(int lbits, QData lhs, QData rhs) VL_PURE { if (VL_UNLIKELY(rhs == 0)) return 0; // -MAX / -1 cannot be represented in twos complement, and will cause SIGFPE if (VL_UNLIKELY(lhs == 0x8000000000000000ULL && rhs == 0xffffffffffffffffULL)) return 0; - const vlsint64_t lhs_signed = VL_EXTENDS_QQ(VL_QUADSIZE, lbits, lhs); - const vlsint64_t rhs_signed = VL_EXTENDS_QQ(VL_QUADSIZE, lbits, rhs); + const int64_t lhs_signed = VL_EXTENDS_QQ(VL_QUADSIZE, lbits, lhs); + const int64_t rhs_signed = VL_EXTENDS_QQ(VL_QUADSIZE, lbits, rhs); return lhs_signed / rhs_signed; } static inline IData VL_MODDIVS_III(int lbits, IData lhs, IData rhs) VL_PURE { if (VL_UNLIKELY(rhs == 0)) return 0; if (VL_UNLIKELY(lhs == 0x80000000 && rhs == 0xffffffff)) return 0; - const vlsint32_t lhs_signed = VL_EXTENDS_II(VL_IDATASIZE, lbits, lhs); - const vlsint32_t rhs_signed = VL_EXTENDS_II(VL_IDATASIZE, lbits, rhs); + const int32_t lhs_signed = VL_EXTENDS_II(VL_IDATASIZE, lbits, lhs); + const int32_t rhs_signed = VL_EXTENDS_II(VL_IDATASIZE, lbits, rhs); return lhs_signed % rhs_signed; } static inline QData VL_MODDIVS_QQQ(int lbits, QData lhs, QData rhs) VL_PURE { if (VL_UNLIKELY(rhs == 0)) return 0; if (VL_UNLIKELY(lhs == 0x8000000000000000ULL && rhs == 0xffffffffffffffffULL)) return 0; - const vlsint64_t lhs_signed = VL_EXTENDS_QQ(VL_QUADSIZE, lbits, lhs); - const vlsint64_t rhs_signed = VL_EXTENDS_QQ(VL_QUADSIZE, lbits, rhs); + const int64_t lhs_signed = VL_EXTENDS_QQ(VL_QUADSIZE, lbits, lhs); + const int64_t rhs_signed = VL_EXTENDS_QQ(VL_QUADSIZE, lbits, rhs); return lhs_signed % rhs_signed; } @@ -1412,8 +1410,8 @@ static inline IData VL_STREAML_FAST_III(int lbits, IData ld, IData rd_log2) VL_P // ret = 10324--- IData ret = ld; if (rd_log2) { - const vluint32_t lbitsFloor = lbits & ~VL_MASK_I(rd_log2); // max multiple of rd <= lbits - const vluint32_t lbitsRem = lbits - lbitsFloor; // number of bits in most-sig slice (MSS) + const uint32_t lbitsFloor = lbits & ~VL_MASK_I(rd_log2); // max multiple of rd <= lbits + const uint32_t lbitsRem = lbits - lbitsFloor; // number of bits in most-sig slice (MSS) const IData msbMask = VL_MASK_I(lbitsRem) << lbitsFloor; // mask to sel only bits in MSS ret = (ret & ~msbMask) | ((ret & msbMask) << ((VL_UL(1) << rd_log2) - lbitsRem)); } @@ -1432,8 +1430,8 @@ static inline QData VL_STREAML_FAST_QQI(int lbits, QData ld, IData rd_log2) VL_P // Pre-shift bits in most-significant slice (see comment in VL_STREAML_FAST_III) QData ret = ld; if (rd_log2) { - const vluint32_t lbitsFloor = lbits & ~VL_MASK_I(rd_log2); - const vluint32_t lbitsRem = lbits - lbitsFloor; + const uint32_t lbitsFloor = lbits & ~VL_MASK_I(rd_log2); + const uint32_t lbitsRem = lbits - lbitsFloor; const QData msbMask = lbitsFloor == 64 ? 0ULL : VL_MASK_Q(lbitsRem) << lbitsFloor; ret = (ret & ~msbMask) | ((ret & msbMask) << ((1ULL << rd_log2) - lbitsRem)); } @@ -1931,8 +1929,8 @@ static inline QData VL_RTOIROUND_Q_D(double lhs) VL_PURE { if (lhs == 0.0) return 0; const QData q = VL_CVT_Q_D(lhs); const int lsb = static_cast((q >> 52ULL) & VL_MASK_Q(11)) - 1023 - 52; - const vluint64_t mantissa = (q & VL_MASK_Q(52)) | (1ULL << 52); - vluint64_t out = 0; + const uint64_t mantissa = (q & VL_MASK_Q(52)) | (1ULL << 52); + uint64_t out = 0; if (lsb < 0) { out = mantissa >> -lsb; } else if (lsb < 64) { @@ -1952,7 +1950,7 @@ static inline WDataOutP VL_RTOIROUND_W_D(int obits, WDataOutP owp, double lhs) V if (lhs == 0.0) return owp; const QData q = VL_CVT_Q_D(lhs); const int lsb = static_cast((q >> 52ULL) & VL_MASK_Q(11)) - 1023 - 52; - const vluint64_t mantissa = (q & VL_MASK_Q(52)) | (1ULL << 52); + const uint64_t mantissa = (q & VL_MASK_Q(52)) | (1ULL << 52); if (lsb < 0) { VL_SET_WQ(owp, mantissa >> -lsb); } else if (lsb < obits) { diff --git a/include/verilated_imp.h b/include/verilated_imp.h index c8b5ba352..078722183 100644 --- a/include/verilated_imp.h +++ b/include/verilated_imp.h @@ -65,7 +65,7 @@ public: private: // MEMBERS - vluint32_t m_mtaskId; // MTask that did enqueue + uint32_t m_mtaskId; // MTask that did enqueue std::function m_cb; // Lambda to execute when message received public: // CONSTRUCTORS @@ -78,7 +78,7 @@ public: VerilatedMsg& operator=(const VerilatedMsg&) = default; VerilatedMsg& operator=(VerilatedMsg&&) = default; // METHODS - vluint32_t mtaskId() const { return m_mtaskId; } + uint32_t mtaskId() const { return m_mtaskId; } // Execute the lambda function void run() const { m_cb(); } }; @@ -89,7 +89,7 @@ public: class VerilatedEvalMsgQueue final { using VerilatedThreadQueue = std::multiset; - std::atomic m_depth; // Current depth of queue (see comments below) + std::atomic m_depth; // Current depth of queue (see comments below) VerilatedMutex m_mutex; // Mutex protecting queue VerilatedThreadQueue m_queue VL_GUARDED_BY(m_mutex); // Message queue @@ -245,8 +245,8 @@ public: // But only for verilated*.cpp // METHODS - extending into VerilatedContext, call via impp()-> // Random seed handling - vluint64_t randSeedDefault64() const VL_MT_SAFE; - static vluint32_t randSeedEpoch() VL_MT_SAFE { return s().s_randSeedEpoch; } + uint64_t randSeedDefault64() const VL_MT_SAFE; + static uint32_t randSeedEpoch() VL_MT_SAFE { return s().s_randSeedEpoch; } // METHODS - timeformat int timeFormatUnits() const VL_MT_SAFE { diff --git a/include/verilated_profiler.cpp b/include/verilated_profiler.cpp index 04cc5dfff..1a5f16a36 100644 --- a/include/verilated_profiler.cpp +++ b/include/verilated_profiler.cpp @@ -38,11 +38,11 @@ constexpr const char* const VlExecutionRecord::s_ascii[]; //============================================================================= // VlPgoProfiler implementation -vluint16_t VlExecutionRecord::getcpu() { +uint16_t VlExecutionRecord::getcpu() { #if defined(__linux) return sched_getcpu(); // TODO: this is a system call. Not exactly cheap. #elif defined(__APPLE__) && !defined(__arm64__) - vluint32_t info[4]; + uint32_t info[4]; __cpuid_count(1, 0, info[0], info[1], info[2], info[3]); // info[1] is EBX, bits 24-31 are APIC ID if ((info[3] & (1 << 9)) == 0) { @@ -79,7 +79,7 @@ void VlExecutionProfiler::configure(const VerilatedContext& context) { clear(); // Clear the profile after the cache warm-up cycles. m_tickBegin = VL_CPU_TICK(); } else if (VL_UNLIKELY(m_windowCount == 0)) { - const vluint64_t tickEnd = VL_CPU_TICK(); + const uint64_t tickEnd = VL_CPU_TICK(); VL_DEBUG_IF(VL_DBG_MSGF("+ profile end\n");); const std::string& fileName = context.profExecFilename(); dump(fileName.c_str(), tickEnd); @@ -88,7 +88,7 @@ void VlExecutionProfiler::configure(const VerilatedContext& context) { return; } - const vluint64_t startReq = context.profExecStart() + 1; // + 1, so we can start at time 0 + const uint64_t startReq = context.profExecStart() + 1; // + 1, so we can start at time 0 if (VL_UNLIKELY(m_lastStartReq < startReq && VL_TIME_Q() >= context.profExecStart())) { VL_DEBUG_IF(VL_DBG_MSGF("+ profile start warmup\n");); @@ -121,7 +121,7 @@ void VlExecutionProfiler::clear() VL_MT_SAFE_EXCLUDES(m_mutex) { } } -void VlExecutionProfiler::dump(const char* filenamep, vluint64_t tickEnd) +void VlExecutionProfiler::dump(const char* filenamep, uint64_t tickEnd) VL_MT_SAFE_EXCLUDES(m_mutex) { const VerilatedLockGuard lock{m_mutex}; VL_DEBUG_IF(VL_DBG_MSGF("+prof+exec writing to '%s'\n", filenamep);); @@ -159,7 +159,7 @@ void VlExecutionProfiler::dump(const char* filenamep, vluint64_t tickEnd) for (const VlExecutionRecord& er : *tracep) { const char* const name = VlExecutionRecord::s_ascii[static_cast(er.m_type)]; - const vluint64_t time = er.m_tick - m_tickBegin; + const uint64_t time = er.m_tick - m_tickBegin; fprintf(fp, "VLPROFEXEC %s %" PRIu64, name, time); switch (er.m_type) { diff --git a/include/verilated_profiler.h b/include/verilated_profiler.h index 1f2ecf21b..86bfd3d13 100644 --- a/include/verilated_profiler.h +++ b/include/verilated_profiler.h @@ -50,7 +50,7 @@ class VlExecutionProfiler; // Return high-precision counter for profiling, or 0x0 if not available VL_ATTR_ALWINLINE inline QData VL_CPU_TICK() { - vluint64_t val; + uint64_t val; VL_GET_CPU_TICK(val); return val; } @@ -88,25 +88,25 @@ class VlExecutionRecord final { union Payload { struct { - vluint32_t m_id; // MTask id - vluint32_t m_predictStart; // Time scheduler predicted would start - vluint32_t m_cpu; // Executing CPU id + uint32_t m_id; // MTask id + uint32_t m_predictStart; // Time scheduler predicted would start + uint32_t m_cpu; // Executing CPU id } mtaskBegin; struct { - vluint32_t m_id; // MTask id - vluint32_t m_predictCost; // How long scheduler predicted would take + uint32_t m_id; // MTask id + uint32_t m_predictCost; // How long scheduler predicted would take } mtaskEnd; }; // STATE // Layout below allows efficient packing. - const vluint64_t m_tick = VL_CPU_TICK(); // Tick at construction + const uint64_t m_tick = VL_CPU_TICK(); // Tick at construction Payload m_payload; // The record payload Type m_type; // The record type - static_assert(alignof(vluint64_t) >= alignof(Payload), "Padding not allowed"); + static_assert(alignof(uint64_t) >= alignof(Payload), "Padding not allowed"); static_assert(alignof(Payload) >= alignof(Type), "Padding not allowed"); - static vluint16_t getcpu(); // Return currently executing CPU id + static uint16_t getcpu(); // Return currently executing CPU id public: // CONSTRUCTOR @@ -117,13 +117,13 @@ public: void evalEnd() { m_type = Type::EVAL_END; } void evalLoopBegin() { m_type = Type::EVAL_LOOP_BEGIN; } void evalLoopEnd() { m_type = Type::EVAL_LOOP_END; } - void mtaskBegin(vluint32_t id, vluint32_t predictStart) { + void mtaskBegin(uint32_t id, uint32_t predictStart) { m_payload.mtaskBegin.m_id = id; m_payload.mtaskBegin.m_predictStart = predictStart; m_payload.mtaskBegin.m_cpu = getcpu(); m_type = Type::MTASK_BEGIN; } - void mtaskEnd(vluint32_t id, vluint32_t predictCost) { + void mtaskEnd(uint32_t id, uint32_t predictCost) { m_payload.mtaskEnd.m_id = id; m_payload.mtaskEnd.m_predictCost = predictCost; m_type = Type::MTASK_END; @@ -161,9 +161,9 @@ class VlExecutionProfiler final { bool m_enabled = false; // Is profiling currently enabled - vluint64_t m_tickBegin = 0; // Sample time (rdtsc() on x86) at beginning of collection - vluint64_t m_lastStartReq = 0; // Last requested profiling start (in simulation time) - vluint32_t m_windowCount = 0; // Track our position in the cache warmup and profile window + uint64_t m_tickBegin = 0; // Sample time (rdtsc() on x86) at beginning of collection + uint64_t m_lastStartReq = 0; // Last requested profiling start (in simulation time) + uint32_t m_windowCount = 0; // Track our position in the cache warmup and profile window public: // CONSTRUCTOR @@ -185,7 +185,7 @@ public: // Clear all profiling data void clear() VL_MT_SAFE_EXCLUDES(m_mutex); // Write profiling data into file - void dump(const char* filenamep, vluint64_t tickEnd) VL_MT_SAFE_EXCLUDES(m_mutex); + void dump(const char* filenamep, uint64_t tickEnd) VL_MT_SAFE_EXCLUDES(m_mutex); }; //============================================================================= @@ -199,7 +199,7 @@ template class VlPgoProfiler final { }; // Counters are stored packed, all together to reduce cache effects - std::array m_counters; // Time spent on this record + std::array m_counters; // Time spent on this record std::vector m_records; // Record information public: diff --git a/include/verilated_save.cpp b/include/verilated_save.cpp index e63bc0d28..777feccb0 100644 --- a/include/verilated_save.cpp +++ b/include/verilated_save.cpp @@ -63,8 +63,8 @@ static const char* const VLTSAVE_TRAILER_STR = "vltsaved"; bool VerilatedDeserialize::readDiffers(const void* __restrict datap, size_t size) VL_MT_UNSAFE_ONE { bufferCheck(); - const vluint8_t* __restrict dp = static_cast(datap); - vluint8_t miss = 0; + const uint8_t* __restrict dp = static_cast(datap); + uint8_t miss = 0; while (size--) miss |= (*dp++ ^ *m_cp++); return (miss != 0); } @@ -192,7 +192,7 @@ void VerilatedRestore::close() VL_MT_UNSAFE_ONE { void VerilatedSave::flush() VL_MT_UNSAFE_ONE { m_assertOne.check(); if (VL_UNLIKELY(!isOpen())) return; - const vluint8_t* wp = m_bufp; + const uint8_t* wp = m_bufp; while (true) { const ssize_t remaining = (m_cp - wp); if (remaining == 0) break; @@ -219,8 +219,8 @@ void VerilatedRestore::fill() VL_MT_UNSAFE_ONE { m_assertOne.check(); if (VL_UNLIKELY(!isOpen())) return; // Move remaining characters down to start of buffer. (No memcpy, overlaps allowed) - vluint8_t* rp = m_bufp; - for (vluint8_t* sp = m_cp; sp < m_endp; *rp++ = *sp++) {} // Overlaps + uint8_t* rp = m_bufp; + for (uint8_t* sp = m_cp; sp < m_endp; *rp++ = *sp++) {} // Overlaps m_endp = m_bufp + (m_endp - m_cp); m_cp = m_bufp; // Reset buffer // Read into buffer starting at m_endp diff --git a/include/verilated_save.h b/include/verilated_save.h index f78da143a..c7230e74e 100644 --- a/include/verilated_save.h +++ b/include/verilated_save.h @@ -40,8 +40,8 @@ class VerilatedSerialize VL_NOT_FINAL { protected: // MEMBERS // For speed, keep m_cp as the first member of this structure - vluint8_t* m_cp; // Current pointer into m_bufp buffer - vluint8_t* m_bufp; // Output buffer + uint8_t* m_cp; // Current pointer into m_bufp buffer + uint8_t* m_bufp; // Output buffer bool m_isOpen = false; // True indicates open file/stream std::string m_filename; // Filename, for error messages VerilatedAssertOneThread m_assertOne; // Assert only called from single thread @@ -58,7 +58,7 @@ protected: public: /// Construct VerilatedSerialize() { - m_bufp = new vluint8_t[bufferSize()]; + m_bufp = new uint8_t[bufferSize()]; m_cp = m_bufp; } /// Flish, close, and destruct @@ -77,12 +77,12 @@ public: virtual void flush() VL_MT_UNSAFE_ONE {} /// Write data to stream VerilatedSerialize& write(const void* __restrict datap, size_t size) VL_MT_UNSAFE_ONE { - const vluint8_t* __restrict dp = (const vluint8_t* __restrict)datap; + const uint8_t* __restrict dp = (const uint8_t* __restrict)datap; while (size) { bufferCheck(); size_t blk = size; if (blk > bufferInsertSize()) blk = bufferInsertSize(); - const vluint8_t* __restrict maxp = dp + blk; + const uint8_t* __restrict maxp = dp + blk; for (; dp < maxp; *m_cp++ = *dp++) {} size -= blk; } @@ -111,9 +111,9 @@ class VerilatedDeserialize VL_NOT_FINAL { protected: // MEMBERS // For speed, keep m_cp as the first member of this structure - vluint8_t* m_cp; // Current pointer into m_bufp buffer - vluint8_t* m_bufp; // Output buffer - vluint8_t* m_endp = nullptr; // Last valid byte in m_bufp buffer + uint8_t* m_cp; // Current pointer into m_bufp buffer + uint8_t* m_bufp; // Output buffer + uint8_t* m_endp = nullptr; // Last valid byte in m_bufp buffer bool m_isOpen = false; // True indicates open file/stream std::string m_filename; // Filename, for error messages VerilatedAssertOneThread m_assertOne; // Assert only called from single thread @@ -131,7 +131,7 @@ protected: public: /// Construct VerilatedDeserialize() { - m_bufp = new vluint8_t[bufferSize()]; + m_bufp = new uint8_t[bufferSize()]; m_cp = m_bufp; } /// Destruct @@ -150,12 +150,12 @@ public: virtual void flush() VL_MT_UNSAFE_ONE {} /// Read data from stream VerilatedDeserialize& read(void* __restrict datap, size_t size) VL_MT_UNSAFE_ONE { - vluint8_t* __restrict dp = static_cast(datap); + uint8_t* __restrict dp = static_cast(datap); while (size) { bufferCheck(); size_t blk = size; if (blk > bufferInsertSize()) blk = bufferInsertSize(); - const vluint8_t* __restrict maxp = dp + blk; + const uint8_t* __restrict maxp = dp + blk; for (; dp < maxp; *dp++ = *m_cp++) {} size -= blk; } @@ -165,7 +165,7 @@ public: // Internal use: // Read a datum and compare with expected value VerilatedDeserialize& readAssert(const void* __restrict datap, size_t size) VL_MT_UNSAFE_ONE; - VerilatedDeserialize& readAssert(vluint64_t data) VL_MT_UNSAFE_ONE { + VerilatedDeserialize& readAssert(uint64_t data) VL_MT_UNSAFE_ONE { return readAssert(&data, sizeof(data)); } @@ -236,28 +236,28 @@ public: //============================================================================= -inline VerilatedSerialize& operator<<(VerilatedSerialize& os, const vluint64_t& rhs) { +inline VerilatedSerialize& operator<<(VerilatedSerialize& os, const uint64_t& rhs) { return os.write(&rhs, sizeof(rhs)); } -inline VerilatedDeserialize& operator>>(VerilatedDeserialize& os, vluint64_t& rhs) { +inline VerilatedDeserialize& operator>>(VerilatedDeserialize& os, uint64_t& rhs) { return os.read(&rhs, sizeof(rhs)); } -inline VerilatedSerialize& operator<<(VerilatedSerialize& os, const vluint32_t& rhs) { +inline VerilatedSerialize& operator<<(VerilatedSerialize& os, const uint32_t& rhs) { return os.write(&rhs, sizeof(rhs)); } -inline VerilatedDeserialize& operator>>(VerilatedDeserialize& os, vluint32_t& rhs) { +inline VerilatedDeserialize& operator>>(VerilatedDeserialize& os, uint32_t& rhs) { return os.read(&rhs, sizeof(rhs)); } -inline VerilatedSerialize& operator<<(VerilatedSerialize& os, const vluint16_t& rhs) { +inline VerilatedSerialize& operator<<(VerilatedSerialize& os, const uint16_t& rhs) { return os.write(&rhs, sizeof(rhs)); } -inline VerilatedDeserialize& operator>>(VerilatedDeserialize& os, vluint16_t& rhs) { +inline VerilatedDeserialize& operator>>(VerilatedDeserialize& os, uint16_t& rhs) { return os.read(&rhs, sizeof(rhs)); } -inline VerilatedSerialize& operator<<(VerilatedSerialize& os, const vluint8_t& rhs) { +inline VerilatedSerialize& operator<<(VerilatedSerialize& os, const uint8_t& rhs) { return os.write(&rhs, sizeof(rhs)); } -inline VerilatedDeserialize& operator>>(VerilatedDeserialize& os, vluint8_t& rhs) { +inline VerilatedDeserialize& operator>>(VerilatedDeserialize& os, uint8_t& rhs) { return os.read(&rhs, sizeof(rhs)); } inline VerilatedSerialize& operator<<(VerilatedSerialize& os, const bool& rhs) { @@ -279,12 +279,12 @@ inline VerilatedDeserialize& operator>>(VerilatedDeserialize& os, float& rhs) { return os.read(&rhs, sizeof(rhs)); } inline VerilatedSerialize& operator<<(VerilatedSerialize& os, const std::string& rhs) { - const vluint32_t len = rhs.length(); + const uint32_t len = rhs.length(); os << len; return os.write(rhs.data(), len); } inline VerilatedDeserialize& operator>>(VerilatedDeserialize& os, std::string& rhs) { - vluint32_t len = 0; + uint32_t len = 0; os >> len; rhs.resize(len); return os.read((void*)rhs.data(), len); @@ -295,7 +295,7 @@ VerilatedDeserialize& operator>>(VerilatedDeserialize& os, VerilatedContext* rhs template VerilatedSerialize& operator<<(VerilatedSerialize& os, VlAssocArray& rhs) { os << rhs.atDefault(); - const vluint32_t len = rhs.size(); + const uint32_t len = rhs.size(); os << len; for (const auto& i : rhs) { const T_Key index = i.first; // Copy to get around const_iterator @@ -307,10 +307,10 @@ VerilatedSerialize& operator<<(VerilatedSerialize& os, VlAssocArray VerilatedDeserialize& operator>>(VerilatedDeserialize& os, VlAssocArray& rhs) { os >> rhs.atDefault(); - vluint32_t len = 0; + uint32_t len = 0; os >> len; rhs.clear(); - for (vluint32_t i = 0; i < len; ++i) { + for (uint32_t i = 0; i < len; ++i) { T_Key index; T_Value value; os >> index; diff --git a/include/verilated_sc.h b/include/verilated_sc.h index aadccedf8..614382dd1 100644 --- a/include/verilated_sc.h +++ b/include/verilated_sc.h @@ -39,10 +39,10 @@ // This class is thread safe (though most of SystemC is not). class VlScBvExposer final : public sc_bv_base { public: - static const vluint32_t* sp_datap(const sc_bv_base& base) VL_MT_SAFE { + static const uint32_t* sp_datap(const sc_bv_base& base) VL_MT_SAFE { return static_cast(&base)->sp_datatp(); } - const vluint32_t* sp_datatp() const { return reinterpret_cast(m_data); } + const uint32_t* sp_datatp() const { return reinterpret_cast(m_data); } // Above reads this protected element in sc_bv_base: // sc_digit* m_data; // data array }; diff --git a/include/verilated_sym_props.h b/include/verilated_sym_props.h index 362afdfaf..0f3fb4eeb 100644 --- a/include/verilated_sym_props.h +++ b/include/verilated_sym_props.h @@ -69,9 +69,9 @@ public: class VerilatedVarProps VL_NOT_FINAL { // TYPES - static constexpr vluint32_t MAGIC = 0xddc4f829UL; + static constexpr uint32_t MAGIC = 0xddc4f829UL; // MEMBERS - const vluint32_t m_magic; // Magic number + const uint32_t m_magic; // Magic number const VerilatedVarType m_vltype; // Data type const VerilatedVarFlags m_vlflags; // Direction const int m_pdims; // Packed dimensions, 0 = none @@ -142,7 +142,7 @@ public: VerilatedVarFlags vldir() const { return static_cast(static_cast(m_vlflags) & VLVF_MASK_DIR); } - vluint32_t entSize() const; + uint32_t entSize() const; bool isPublicRW() const { return ((m_vlflags & VLVF_PUB_RW) != 0); } // DPI compatible C standard layout bool isDpiCLayout() const { return ((m_vlflags & VLVF_DPI_CLAY) != 0); } diff --git a/include/verilated_threads.cpp b/include/verilated_threads.cpp index 525143244..12a579026 100644 --- a/include/verilated_threads.cpp +++ b/include/verilated_threads.cpp @@ -37,12 +37,12 @@ // Internal note: Globals may multi-construct, see verilated.cpp top. -std::atomic VlMTaskVertex::s_yields; +std::atomic VlMTaskVertex::s_yields; //============================================================================= // VlMTaskVertex -VlMTaskVertex::VlMTaskVertex(vluint32_t upstreamDepCount) +VlMTaskVertex::VlMTaskVertex(uint32_t upstreamDepCount) : m_upstreamDepsDone{0} , m_upstreamDepCount{upstreamDepCount} { assert(atomic_is_lock_free(&m_upstreamDepsDone)); diff --git a/include/verilated_threads.h b/include/verilated_threads.h index 76512ba06..e69ac8929 100644 --- a/include/verilated_threads.h +++ b/include/verilated_threads.h @@ -60,7 +60,7 @@ using VlExecFnp = void (*)(VlSelfP, bool); // Track dependencies for a single MTask. class VlMTaskVertex final { // MEMBERS - static std::atomic s_yields; // Statistics + static std::atomic s_yields; // Statistics // On even cycles, _upstreamDepsDone increases as upstream // dependencies complete. When it reaches _upstreamDepCount, @@ -78,8 +78,8 @@ class VlMTaskVertex final { // during done-notification. Nobody's quantified that cost though. // If we were really serious about shrinking this class, we could // use 16-bit types here...) - std::atomic m_upstreamDepsDone; - const vluint32_t m_upstreamDepCount; + std::atomic m_upstreamDepsDone; + const uint32_t m_upstreamDepCount; public: // CONSTRUCTORS @@ -87,10 +87,10 @@ public: // 'upstreamDepCount' is the number of upstream MTaskVertex's // that must notify this MTaskVertex before it will become ready // to run. - explicit VlMTaskVertex(vluint32_t upstreamDepCount); + explicit VlMTaskVertex(uint32_t upstreamDepCount); ~VlMTaskVertex() = default; - static vluint64_t yields() { return s_yields; } + static uint64_t yields() { return s_yields; } static void yieldThread() { ++s_yields; // Statistics std::this_thread::yield(); @@ -101,19 +101,19 @@ public: // false while it's still waiting on more dependencies. inline bool signalUpstreamDone(bool evenCycle) { if (evenCycle) { - const vluint32_t upstreamDepsDone + const uint32_t upstreamDepsDone = 1 + m_upstreamDepsDone.fetch_add(1, std::memory_order_release); assert(upstreamDepsDone <= m_upstreamDepCount); return (upstreamDepsDone == m_upstreamDepCount); } else { - const vluint32_t upstreamDepsDone_prev + const uint32_t upstreamDepsDone_prev = m_upstreamDepsDone.fetch_sub(1, std::memory_order_release); assert(upstreamDepsDone_prev > 0); return (upstreamDepsDone_prev == 1); } } inline bool areUpstreamDepsDone(bool evenCycle) const { - const vluint32_t target = evenCycle ? m_upstreamDepCount : 0; + const uint32_t target = evenCycle ? m_upstreamDepCount : 0; return m_upstreamDepsDone.load(std::memory_order_acquire) == target; } inline void waitUntilUpstreamDone(bool evenCycle) const { diff --git a/include/verilated_trace.h b/include/verilated_trace.h index 6caeb5d03..8069174ee 100644 --- a/include/verilated_trace.h +++ b/include/verilated_trace.h @@ -92,7 +92,7 @@ class VerilatedTraceCommand final { public: // These must all fit in 4 bit at the moment, as the tracing routines // pack parameters in the top bits. - enum : vluint8_t { + enum : uint8_t { CHG_BIT_0 = 0x0, CHG_BIT_1 = 0x1, CHG_CDATA = 0x2, @@ -120,7 +120,7 @@ public: //========================================================================= // Generic tracing internals - using initCb_t = void (*)(void*, T_Derived*, vluint32_t); // Type of init callbacks + using initCb_t = void (*)(void*, T_Derived*, uint32_t); // Type of init callbacks using dumpCb_t = void (*)(void*, T_Derived*); // Type of all but init callbacks private: @@ -142,18 +142,18 @@ private: , m_userp{userp} {} }; - vluint32_t* m_sigs_oldvalp; // Old value store + uint32_t* m_sigs_oldvalp; // Old value store EData* m_sigs_enabledp; // Bit vector of enabled codes (nullptr = all on) - vluint64_t m_timeLastDump; // Last time we did a dump + uint64_t m_timeLastDump; // Last time we did a dump std::vector m_sigs_enabledVec; // Staging for m_sigs_enabledp std::vector m_initCbs; // Routines to initialize traciong std::vector m_fullCbs; // Routines to perform full dump std::vector m_chgCbs; // Routines to perform incremental dump std::vector m_cleanupCbs; // Routines to call at the end of dump bool m_fullDump; // Whether a full dump is required on the next call to 'dump' - vluint32_t m_nextCode; // Next code number to assign - vluint32_t m_numSignals; // Number of distinct signals - vluint32_t m_maxBits; // Number of bits in the widest signal + uint32_t m_nextCode; // Next code number to assign + uint32_t m_numSignals; // Number of distinct signals + uint32_t m_maxBits; // Number of bits in the widest signal std::vector m_namePrefixStack{""}; // Path prefixes to add to signal names std::vector> m_dumpvars; // dumpvar() entries char m_scopeEscape; @@ -174,28 +174,28 @@ private: #ifdef VL_TRACE_THREADED // Number of total trace buffers that have been allocated - vluint32_t m_numTraceBuffers; + uint32_t m_numTraceBuffers; // Size of trace buffers size_t m_traceBufferSize; // Buffers handed to worker for processing - VerilatedThreadQueue m_buffersToWorker; + VerilatedThreadQueue m_buffersToWorker; // Buffers returned from worker after processing - VerilatedThreadQueue m_buffersFromWorker; + VerilatedThreadQueue m_buffersFromWorker; // Write pointer into current buffer - vluint32_t* m_traceBufferWritep; + uint32_t* m_traceBufferWritep; // End of trace buffer - vluint32_t* m_traceBufferEndp; + uint32_t* m_traceBufferEndp; // The worker thread itself std::unique_ptr m_workerThread; // Get a new trace buffer that can be populated. May block if none available - vluint32_t* getTraceBuffer(); + uint32_t* getTraceBuffer(); // The function executed by the worker thread void workerThreadMain(); // Wait until given buffer is placed in m_buffersFromWorker - void waitForBuffer(const vluint32_t* bufferp); + void waitForBuffer(const uint32_t* bufferp); // Shut down and join worker, if it's running, otherwise do nothing void shutdownWorker(); @@ -210,11 +210,11 @@ protected: VerilatedMutex m_mutex; // Ensure dump() etc only called from single thread - vluint32_t nextCode() const { return m_nextCode; } - vluint32_t numSignals() const { return m_numSignals; } - vluint32_t maxBits() const { return m_maxBits; } + uint32_t nextCode() const { return m_nextCode; } + uint32_t numSignals() const { return m_numSignals; } + uint32_t maxBits() const { return m_maxBits; } void fullDump(bool value) { m_fullDump = value; } - vluint64_t timeLastDump() { return m_timeLastDump; } + uint64_t timeLastDump() { return m_timeLastDump; } double timeRes() const { return m_timeRes; } double timeUnit() const { return m_timeUnit; } @@ -223,7 +223,7 @@ protected: void traceInit() VL_MT_UNSAFE; // Declare new signal and return true if enabled - bool declCode(vluint32_t code, const char* namep, vluint32_t bits, bool tri); + bool declCode(uint32_t code, const char* namep, uint32_t bits, bool tri); // Is this an escape? bool isScopeEscape(char c) { return std::isspace(c) || c == m_scopeEscape; } @@ -239,7 +239,7 @@ protected: // Virtual functions to be provided by the format specific implementation // Called when the trace moves forward to a new time point - virtual void emitTimeChange(vluint64_t timeui) = 0; + virtual void emitTimeChange(uint64_t timeui) = 0; // These hooks are called before a full or change based dump is produced. // The return value indicates whether to proceed with the dump. @@ -264,7 +264,7 @@ public: void dumpvars(int level, const std::string& hier) VL_MT_SAFE; // Call - void dump(vluint64_t timeui) VL_MT_SAFE_EXCLUDES(m_mutex); + void dump(uint64_t timeui) VL_MT_SAFE_EXCLUDES(m_mutex); //========================================================================= // Non-hot path internal interface to Verilator generated code @@ -288,69 +288,69 @@ public: // these here, but we cannot afford dynamic dispatch for calling these as // this is very hot code during tracing. - // duck-typed void emitBit(vluint32_t code, CData newval) = 0; - // duck-typed void emitCData(vluint32_t code, CData newval, int bits) = 0; - // duck-typed void emitSData(vluint32_t code, SData newval, int bits) = 0; - // duck-typed void emitIData(vluint32_t code, IData newval, int bits) = 0; - // duck-typed void emitQData(vluint32_t code, QData newval, int bits) = 0; - // duck-typed void emitWData(vluint32_t code, const WData* newvalp, int bits) = 0; - // duck-typed void emitDouble(vluint32_t code, double newval) = 0; + // duck-typed void emitBit(uint32_t code, CData newval) = 0; + // duck-typed void emitCData(uint32_t code, CData newval, int bits) = 0; + // duck-typed void emitSData(uint32_t code, SData newval, int bits) = 0; + // duck-typed void emitIData(uint32_t code, IData newval, int bits) = 0; + // duck-typed void emitQData(uint32_t code, QData newval, int bits) = 0; + // duck-typed void emitWData(uint32_t code, const WData* newvalp, int bits) = 0; + // duck-typed void emitDouble(uint32_t code, double newval) = 0; - vluint32_t* oldp(vluint32_t code) { return m_sigs_oldvalp + code; } + uint32_t* oldp(uint32_t code) { return m_sigs_oldvalp + code; } // Write to previous value buffer value and emit trace entry. - void fullBit(vluint32_t* oldp, CData newval); - void fullCData(vluint32_t* oldp, CData newval, int bits); - void fullSData(vluint32_t* oldp, SData newval, int bits); - void fullIData(vluint32_t* oldp, IData newval, int bits); - void fullQData(vluint32_t* oldp, QData newval, int bits); - void fullWData(vluint32_t* oldp, const WData* newvalp, int bits); - void fullDouble(vluint32_t* oldp, double newval); + void fullBit(uint32_t* oldp, CData newval); + void fullCData(uint32_t* oldp, CData newval, int bits); + void fullSData(uint32_t* oldp, SData newval, int bits); + void fullIData(uint32_t* oldp, IData newval, int bits); + void fullQData(uint32_t* oldp, QData newval, int bits); + void fullWData(uint32_t* oldp, const WData* newvalp, int bits); + void fullDouble(uint32_t* oldp, double newval); #ifdef VL_TRACE_THREADED // Threaded tracing. Just dump everything in the trace buffer - inline void chgBit(vluint32_t code, CData newval) { + inline void chgBit(uint32_t code, CData newval) { m_traceBufferWritep[0] = VerilatedTraceCommand::CHG_BIT_0 | newval; m_traceBufferWritep[1] = code; m_traceBufferWritep += 2; VL_DEBUG_IF(assert(m_traceBufferWritep <= m_traceBufferEndp);); } - inline void chgCData(vluint32_t code, CData newval, int bits) { + inline void chgCData(uint32_t code, CData newval, int bits) { m_traceBufferWritep[0] = (bits << 4) | VerilatedTraceCommand::CHG_CDATA; m_traceBufferWritep[1] = code; m_traceBufferWritep[2] = newval; m_traceBufferWritep += 3; VL_DEBUG_IF(assert(m_traceBufferWritep <= m_traceBufferEndp);); } - inline void chgSData(vluint32_t code, SData newval, int bits) { + inline void chgSData(uint32_t code, SData newval, int bits) { m_traceBufferWritep[0] = (bits << 4) | VerilatedTraceCommand::CHG_SDATA; m_traceBufferWritep[1] = code; m_traceBufferWritep[2] = newval; m_traceBufferWritep += 3; VL_DEBUG_IF(assert(m_traceBufferWritep <= m_traceBufferEndp);); } - inline void chgIData(vluint32_t code, IData newval, int bits) { + inline void chgIData(uint32_t code, IData newval, int bits) { m_traceBufferWritep[0] = (bits << 4) | VerilatedTraceCommand::CHG_IDATA; m_traceBufferWritep[1] = code; m_traceBufferWritep[2] = newval; m_traceBufferWritep += 3; VL_DEBUG_IF(assert(m_traceBufferWritep <= m_traceBufferEndp);); } - inline void chgQData(vluint32_t code, QData newval, int bits) { + inline void chgQData(uint32_t code, QData newval, int bits) { m_traceBufferWritep[0] = (bits << 4) | VerilatedTraceCommand::CHG_QDATA; m_traceBufferWritep[1] = code; *reinterpret_cast(m_traceBufferWritep + 2) = newval; m_traceBufferWritep += 4; VL_DEBUG_IF(assert(m_traceBufferWritep <= m_traceBufferEndp);); } - inline void chgWData(vluint32_t code, const WData* newvalp, int bits) { + inline void chgWData(uint32_t code, const WData* newvalp, int bits) { m_traceBufferWritep[0] = (bits << 4) | VerilatedTraceCommand::CHG_WDATA; m_traceBufferWritep[1] = code; m_traceBufferWritep += 2; for (int i = 0; i < (bits + 31) / 32; ++i) { *m_traceBufferWritep++ = newvalp[i]; } VL_DEBUG_IF(assert(m_traceBufferWritep <= m_traceBufferEndp);); } - inline void chgDouble(vluint32_t code, double newval) { + inline void chgDouble(uint32_t code, double newval) { m_traceBufferWritep[0] = VerilatedTraceCommand::CHG_DOUBLE; m_traceBufferWritep[1] = code; // cppcheck-suppress invalidPointerCast @@ -369,27 +369,27 @@ public: // thread and are called chg*Impl // Check previous dumped value of signal. If changed, then emit trace entry - inline void CHG(Bit)(vluint32_t* oldp, CData newval) { - const vluint32_t diff = *oldp ^ newval; + inline void CHG(Bit)(uint32_t* oldp, CData newval) { + const uint32_t diff = *oldp ^ newval; if (VL_UNLIKELY(diff)) fullBit(oldp, newval); } - inline void CHG(CData)(vluint32_t* oldp, CData newval, int bits) { - const vluint32_t diff = *oldp ^ newval; + inline void CHG(CData)(uint32_t* oldp, CData newval, int bits) { + const uint32_t diff = *oldp ^ newval; if (VL_UNLIKELY(diff)) fullCData(oldp, newval, bits); } - inline void CHG(SData)(vluint32_t* oldp, SData newval, int bits) { - const vluint32_t diff = *oldp ^ newval; + inline void CHG(SData)(uint32_t* oldp, SData newval, int bits) { + const uint32_t diff = *oldp ^ newval; if (VL_UNLIKELY(diff)) fullSData(oldp, newval, bits); } - inline void CHG(IData)(vluint32_t* oldp, IData newval, int bits) { - const vluint32_t diff = *oldp ^ newval; + inline void CHG(IData)(uint32_t* oldp, IData newval, int bits) { + const uint32_t diff = *oldp ^ newval; if (VL_UNLIKELY(diff)) fullIData(oldp, newval, bits); } - inline void CHG(QData)(vluint32_t* oldp, QData newval, int bits) { - const vluint64_t diff = *reinterpret_cast(oldp) ^ newval; + inline void CHG(QData)(uint32_t* oldp, QData newval, int bits) { + const uint64_t diff = *reinterpret_cast(oldp) ^ newval; if (VL_UNLIKELY(diff)) fullQData(oldp, newval, bits); } - inline void CHG(WData)(vluint32_t* oldp, const WData* newvalp, int bits) { + inline void CHG(WData)(uint32_t* oldp, const WData* newvalp, int bits) { for (int i = 0; i < (bits + 31) / 32; ++i) { if (VL_UNLIKELY(oldp[i] ^ newvalp[i])) { fullWData(oldp, newvalp, bits); @@ -397,7 +397,7 @@ public: } } } - inline void CHG(Double)(vluint32_t* oldp, double newval) { + inline void CHG(Double)(uint32_t* oldp, double newval) { // cppcheck-suppress invalidPointerCast if (VL_UNLIKELY(*reinterpret_cast(oldp) != newval)) fullDouble(oldp, newval); } diff --git a/include/verilated_trace_imp.cpp b/include/verilated_trace_imp.cpp index 26e0bf63a..e5dd41fcd 100644 --- a/include/verilated_trace_imp.cpp +++ b/include/verilated_trace_imp.cpp @@ -82,8 +82,8 @@ static std::string doubleToTimescale(double value) { //========================================================================= // Buffer management -template <> vluint32_t* VerilatedTrace::getTraceBuffer() { - vluint32_t* bufferp; +template <> uint32_t* VerilatedTrace::getTraceBuffer() { + uint32_t* bufferp; // Some jitter is expected, so some number of alternative trace buffers are // required, but don't allocate more than 8 buffers. if (m_numTraceBuffers < 8) { @@ -92,7 +92,7 @@ template <> vluint32_t* VerilatedTrace::getTraceBuffer() { ++m_numTraceBuffers; // Note: over allocate a bit so pointer comparison is well defined // if we overflow only by a small amount - bufferp = new vluint32_t[m_traceBufferSize + 16]; + bufferp = new uint32_t[m_traceBufferSize + 16]; } } else { // Block until a buffer becomes available @@ -101,10 +101,10 @@ template <> vluint32_t* VerilatedTrace::getTraceBuffer() { return bufferp; } -template <> void VerilatedTrace::waitForBuffer(const vluint32_t* buffp) { +template <> void VerilatedTrace::waitForBuffer(const uint32_t* buffp) { // Slow path code only called on flush/shutdown, so use a simple algorithm. // Collect buffers from worker and stash them until we get the one we want. - std::deque stash; + std::deque stash; do { stash.push_back(m_buffersFromWorker.get()); } while (stash.back() != buffp); // Now put them back in the queue, in the original order. while (!stash.empty()) { @@ -120,18 +120,18 @@ template <> void VerilatedTrace::workerThreadMain() { bool shutdown = false; do { - vluint32_t* const bufferp = m_buffersToWorker.get(); + uint32_t* const bufferp = m_buffersToWorker.get(); VL_TRACE_THREAD_DEBUG(""); VL_TRACE_THREAD_DEBUG("Got buffer: " << bufferp); - const vluint32_t* readp = bufferp; + const uint32_t* readp = bufferp; while (true) { - const vluint32_t cmd = readp[0]; - const vluint32_t top = cmd >> 4; + const uint32_t cmd = readp[0]; + const uint32_t top = cmd >> 4; // Always set this up, as it is almost always needed - vluint32_t* const oldp = m_sigs_oldvalp + readp[1]; + uint32_t* const oldp = m_sigs_oldvalp + readp[1]; // Note this increment needs to be undone on commands which do not // actually contain a code, but those are the rare cases. readp += 2; @@ -187,7 +187,7 @@ template <> void VerilatedTrace::workerThreadMain() { case VerilatedTraceCommand::TIME_CHANGE: VL_TRACE_THREAD_DEBUG("Command TIME_CHANGE " << top); readp -= 1; // No code in this command, undo increment - emitTimeChange(*reinterpret_cast(readp)); + emitTimeChange(*reinterpret_cast(readp)); readp += 2; continue; @@ -226,7 +226,7 @@ template <> void VerilatedTrace::shutdownWorker() { if (!m_workerThread) return; // Hand an buffer with a shutdown command to the worker thread - vluint32_t* const bufferp = getTraceBuffer(); + uint32_t* const bufferp = getTraceBuffer(); bufferp[0] = VerilatedTraceCommand::SHUTDOWN; m_buffersToWorker.put(bufferp); // Wait for it to return @@ -254,7 +254,7 @@ template <> void VerilatedTrace::closeBase() { template <> void VerilatedTrace::flushBase() { #ifdef VL_TRACE_THREADED // Hand an empty buffer to the worker thread - vluint32_t* const bufferp = getTraceBuffer(); + uint32_t* const bufferp = getTraceBuffer(); *bufferp = VerilatedTraceCommand::END; m_buffersToWorker.put(bufferp); // Wait for it to be returned. As the processing is in-order, @@ -318,7 +318,7 @@ template <> void VerilatedTrace::traceInit() VL_MT_UNSAFE { // Note: It is possible to re-open a trace file (VCD in particular), // so we must reset the next code here, but it must have the same number // of codes on re-open - const vluint32_t expectedCodes = nextCode(); + const uint32_t expectedCodes = nextCode(); m_nextCode = 1; m_numSignals = 0; m_maxBits = 0; @@ -327,7 +327,7 @@ template <> void VerilatedTrace::traceInit() VL_MT_UNSAFE { // Call all initialize callbacks, which will: // - Call decl* for each signal (these eventually call ::declCode) // - Store the base code - for (vluint32_t i = 0; i < m_initCbs.size(); ++i) { + for (uint32_t i = 0; i < m_initCbs.size(); ++i) { const CallbackRecord& cbr = m_initCbs[i]; cbr.m_initCb(cbr.m_userp, self(), nextCode()); } @@ -339,7 +339,7 @@ template <> void VerilatedTrace::traceInit() VL_MT_UNSAFE { // Now that we know the number of codes, allocate space for the buffer // holding previous signal values. - if (!m_sigs_oldvalp) m_sigs_oldvalp = new vluint32_t[nextCode()]; + if (!m_sigs_oldvalp) m_sigs_oldvalp = new uint32_t[nextCode()]; // Apply enables if (m_sigs_enabledp) VL_DO_CLEAR(delete[] m_sigs_enabledp, m_sigs_enabledp = nullptr); @@ -348,7 +348,7 @@ template <> void VerilatedTrace::traceInit() VL_MT_UNSAFE { // But it isn't, so alloc one bit for each code to indicate enablement // We don't want to still use m_signs_enabledVec as std::vector is not // guarenteed to be fast - m_sigs_enabledp = new vluint32_t[1 + VL_WORDS_I(nextCode())]{0}; + m_sigs_enabledp = new uint32_t[1 + VL_WORDS_I(nextCode())]{0}; m_sigs_enabledVec.reserve(nextCode()); for (size_t code = 0; code < nextCode(); ++code) { if (m_sigs_enabledVec[code]) { @@ -376,7 +376,7 @@ template <> void VerilatedTrace::traceInit() VL_MT_UNSAFE { } template <> -bool VerilatedTrace::declCode(vluint32_t code, const char* namep, vluint32_t bits, +bool VerilatedTrace::declCode(uint32_t code, const char* namep, uint32_t bits, bool tri) { if (VL_UNCOVERABLE(!code)) { VL_FATAL_MT(__FILE__, __LINE__, "", "Internal: internal trace problem, code 0 is illegal"); @@ -455,8 +455,7 @@ void VerilatedTrace::dumpvars(int level, const std::string& hier) } } -template <> -void VerilatedTrace::dump(vluint64_t timeui) VL_MT_SAFE_EXCLUDES(m_mutex) { +template <> void VerilatedTrace::dump(uint64_t timeui) VL_MT_SAFE_EXCLUDES(m_mutex) { // Not really VL_MT_SAFE but more VL_MT_UNSAFE_ONE. // This does get the mutex, but if multiple threads are trying to dump // chances are the data being dumped will have other problems @@ -480,7 +479,7 @@ void VerilatedTrace::dump(vluint64_t timeui) VL_MT_SAFE_EXCLUDES(m #ifdef VL_TRACE_THREADED // Currently only incremental dumps run on the worker thread - vluint32_t* bufferp = nullptr; + uint32_t* bufferp = nullptr; if (VL_LIKELY(!m_fullDump)) { // Get the trace buffer we are about to fill bufferp = getTraceBuffer(); @@ -489,7 +488,7 @@ void VerilatedTrace::dump(vluint64_t timeui) VL_MT_SAFE_EXCLUDES(m // Tell worker to update time point m_traceBufferWritep[0] = VerilatedTraceCommand::TIME_CHANGE; - *reinterpret_cast(m_traceBufferWritep + 1) = timeui; + *reinterpret_cast(m_traceBufferWritep + 1) = timeui; m_traceBufferWritep += 3; } else { // Update time point @@ -504,18 +503,18 @@ void VerilatedTrace::dump(vluint64_t timeui) VL_MT_SAFE_EXCLUDES(m // Run the callbacks if (VL_UNLIKELY(m_fullDump)) { m_fullDump = false; // No more need for next dump to be full - for (vluint32_t i = 0; i < m_fullCbs.size(); ++i) { + for (uint32_t i = 0; i < m_fullCbs.size(); ++i) { const CallbackRecord& cbr = m_fullCbs[i]; cbr.m_dumpCb(cbr.m_userp, self()); } } else { - for (vluint32_t i = 0; i < m_chgCbs.size(); ++i) { + for (uint32_t i = 0; i < m_chgCbs.size(); ++i) { const CallbackRecord& cbr = m_chgCbs[i]; cbr.m_dumpCb(cbr.m_userp, self()); } } - for (vluint32_t i = 0; i < m_cleanupCbs.size(); ++i) { + for (uint32_t i = 0; i < m_cleanupCbs.size(); ++i) { const CallbackRecord& cbr = m_cleanupCbs[i]; cbr.m_dumpCb(cbr.m_userp, self()); } @@ -584,39 +583,35 @@ template <> void VerilatedTrace::popNamePrefix(unsigned count) { // that this file must be included in the format specific implementation, so // the emit* functions can be inlined for performance. -template <> void VerilatedTrace::fullBit(vluint32_t* oldp, CData newval) { +template <> void VerilatedTrace::fullBit(uint32_t* oldp, CData newval) { const uint32_t code = oldp - m_sigs_oldvalp; *oldp = newval; // Still copy even if not tracing so chg doesn't call full if (VL_UNLIKELY(m_sigs_enabledp && !(VL_BITISSET_W(m_sigs_enabledp, code)))) return; self()->emitBit(code, newval); } -template <> -void VerilatedTrace::fullCData(vluint32_t* oldp, CData newval, int bits) { +template <> void VerilatedTrace::fullCData(uint32_t* oldp, CData newval, int bits) { const uint32_t code = oldp - m_sigs_oldvalp; *oldp = newval; // Still copy even if not tracing so chg doesn't call full if (VL_UNLIKELY(m_sigs_enabledp && !(VL_BITISSET_W(m_sigs_enabledp, code)))) return; self()->emitCData(code, newval, bits); } -template <> -void VerilatedTrace::fullSData(vluint32_t* oldp, SData newval, int bits) { +template <> void VerilatedTrace::fullSData(uint32_t* oldp, SData newval, int bits) { const uint32_t code = oldp - m_sigs_oldvalp; *oldp = newval; // Still copy even if not tracing so chg doesn't call full if (VL_UNLIKELY(m_sigs_enabledp && !(VL_BITISSET_W(m_sigs_enabledp, code)))) return; self()->emitSData(code, newval, bits); } -template <> -void VerilatedTrace::fullIData(vluint32_t* oldp, IData newval, int bits) { +template <> void VerilatedTrace::fullIData(uint32_t* oldp, IData newval, int bits) { const uint32_t code = oldp - m_sigs_oldvalp; *oldp = newval; // Still copy even if not tracing so chg doesn't call full if (VL_UNLIKELY(m_sigs_enabledp && !(VL_BITISSET_W(m_sigs_enabledp, code)))) return; self()->emitIData(code, newval, bits); } -template <> -void VerilatedTrace::fullQData(vluint32_t* oldp, QData newval, int bits) { +template <> void VerilatedTrace::fullQData(uint32_t* oldp, QData newval, int bits) { const uint32_t code = oldp - m_sigs_oldvalp; *reinterpret_cast(oldp) = newval; if (VL_UNLIKELY(m_sigs_enabledp && !(VL_BITISSET_W(m_sigs_enabledp, code)))) return; @@ -624,14 +619,14 @@ void VerilatedTrace::fullQData(vluint32_t* oldp, QData newval, int } template <> -void VerilatedTrace::fullWData(vluint32_t* oldp, const WData* newvalp, int bits) { +void VerilatedTrace::fullWData(uint32_t* oldp, const WData* newvalp, int bits) { const uint32_t code = oldp - m_sigs_oldvalp; for (int i = 0; i < VL_WORDS_I(bits); ++i) oldp[i] = newvalp[i]; if (VL_UNLIKELY(m_sigs_enabledp && !(VL_BITISSET_W(m_sigs_enabledp, code)))) return; self()->emitWData(code, newvalp, bits); } -template <> void VerilatedTrace::fullDouble(vluint32_t* oldp, double newval) { +template <> void VerilatedTrace::fullDouble(uint32_t* oldp, double newval) { const uint32_t code = oldp - m_sigs_oldvalp; *reinterpret_cast(oldp) = newval; if (VL_UNLIKELY(m_sigs_enabledp && !(VL_BITISSET_W(m_sigs_enabledp, code)))) return; diff --git a/include/verilated_types.h b/include/verilated_types.h index 39592db96..43bad0b4b 100644 --- a/include/verilated_types.h +++ b/include/verilated_types.h @@ -73,7 +73,7 @@ extern std::string VL_TO_STRING_W(int words, const WDataInP obj); //=================================================================== // Shuffle RNG -extern vluint64_t vl_rand64() VL_MT_SAFE; +extern uint64_t vl_rand64() VL_MT_SAFE; class VlURNG final { public: @@ -241,7 +241,7 @@ public: int size() const { return m_deque.size(); } // Clear array. Verilog: function void delete([input index]) void clear() { m_deque.clear(); } - void erase(vlsint32_t index) { + void erase(int32_t index) { if (VL_LIKELY(index >= 0 && index < m_deque.size())) m_deque.erase(m_deque.begin() + index); } @@ -288,7 +288,7 @@ public: // Setting. Verilog: assoc[index] = v // Can't just overload operator[] or provide a "at" reference to set, // because we need to be able to insert only when the value is set - T_Value& at(vlsint32_t index) { + T_Value& at(int32_t index) { static T_Value s_throwAway; // Needs to work for dynamic arrays, so does not use T_MaxSize if (VL_UNLIKELY(index < 0 || index >= m_deque.size())) { @@ -299,7 +299,7 @@ public: } } // Accessing. Verilog: v = assoc[index] - const T_Value& at(vlsint32_t index) const { + const T_Value& at(int32_t index) const { static T_Value s_throwAway; // Needs to work for dynamic arrays, so does not use T_MaxSize if (VL_UNLIKELY(index < 0 || index >= m_deque.size())) { @@ -309,18 +309,18 @@ public: } } // function void q.insert(index, value); - void insert(vlsint32_t index, const T_Value& value) { + void insert(int32_t index, const T_Value& value) { if (VL_UNLIKELY(index < 0 || index >= m_deque.size())) return; m_deque.insert(m_deque.begin() + index, value); } // Return slice q[lsb:msb] - VlQueue slice(vlsint32_t lsb, vlsint32_t msb) const { + VlQueue slice(int32_t lsb, int32_t msb) const { VlQueue out; if (VL_UNLIKELY(lsb < 0)) lsb = 0; if (VL_UNLIKELY(lsb >= m_deque.size())) lsb = m_deque.size() - 1; if (VL_UNLIKELY(msb >= m_deque.size())) msb = m_deque.size() - 1; - for (vlsint32_t i = lsb; i <= msb; ++i) out.push_back(m_deque[i]); + for (int32_t i = lsb; i <= msb; ++i) out.push_back(m_deque[i]); return out; } diff --git a/include/verilated_vcd_c.cpp b/include/verilated_vcd_c.cpp index cba693d3b..855f51634 100644 --- a/include/verilated_vcd_c.cpp +++ b/include/verilated_vcd_c.cpp @@ -172,7 +172,7 @@ bool VerilatedVcd::preChangeDump() { return isOpen(); } -void VerilatedVcd::emitTimeChange(vluint64_t timeui) { +void VerilatedVcd::emitTimeChange(uint64_t timeui) { printStr("#"); printQuad(timeui); printStr("\n"); @@ -270,14 +270,14 @@ void VerilatedVcd::printStr(const char* str) { } } -void VerilatedVcd::printQuad(vluint64_t n) { +void VerilatedVcd::printQuad(uint64_t n) { constexpr size_t LEN_STR_QUAD = 40; char buf[LEN_STR_QUAD]; VL_SNPRINTF(buf, LEN_STR_QUAD, "%" PRIu64, n); printStr(buf); } -void VerilatedVcd::bufferResize(vluint64_t minsize) { +void VerilatedVcd::bufferResize(uint64_t minsize) { // minsize is size of largest write. We buffer at least 8 times as much data, // writing when we are 3/4 full (with thus 2*minsize remaining free) if (VL_UNLIKELY(minsize > m_wrChunkSize)) { @@ -328,7 +328,7 @@ void VerilatedVcd::bufferFlush() VL_MT_UNSAFE_ONE { //============================================================================= // VCD string code -char* VerilatedVcd::writeCode(char* writep, vluint32_t code) { +char* VerilatedVcd::writeCode(char* writep, uint32_t code) { *writep++ = static_cast('!' + code % 94); code /= 94; while (code) { @@ -459,7 +459,7 @@ void VerilatedVcd::dumpHeader() { deleteNameMap(); } -void VerilatedVcd::declare(vluint32_t code, const char* name, const char* wirep, bool array, +void VerilatedVcd::declare(uint32_t code, const char* name, const char* wirep, bool array, int arraynum, bool tri, bool bussed, int msb, int lsb) { const int bits = ((msb > lsb) ? (msb - lsb) : (lsb - msb)) + 1; @@ -544,38 +544,38 @@ void VerilatedVcd::declare(vluint32_t code, const char* name, const char* wirep, m_namemapp->emplace(hiername, decl); } -void VerilatedVcd::declBit(vluint32_t code, const char* name, bool array, int arraynum) { +void VerilatedVcd::declBit(uint32_t code, const char* name, bool array, int arraynum) { declare(code, name, "wire", array, arraynum, false, false, 0, 0); } -void VerilatedVcd::declBus(vluint32_t code, const char* name, bool array, int arraynum, int msb, +void VerilatedVcd::declBus(uint32_t code, const char* name, bool array, int arraynum, int msb, int lsb) { declare(code, name, "wire", array, arraynum, false, true, msb, lsb); } -void VerilatedVcd::declQuad(vluint32_t code, const char* name, bool array, int arraynum, int msb, +void VerilatedVcd::declQuad(uint32_t code, const char* name, bool array, int arraynum, int msb, int lsb) { declare(code, name, "wire", array, arraynum, false, true, msb, lsb); } -void VerilatedVcd::declArray(vluint32_t code, const char* name, bool array, int arraynum, int msb, +void VerilatedVcd::declArray(uint32_t code, const char* name, bool array, int arraynum, int msb, int lsb) { declare(code, name, "wire", array, arraynum, false, true, msb, lsb); } -void VerilatedVcd::declDouble(vluint32_t code, const char* name, bool array, int arraynum) { +void VerilatedVcd::declDouble(uint32_t code, const char* name, bool array, int arraynum) { declare(code, name, "real", array, arraynum, false, false, 63, 0); } #ifdef VL_TRACE_VCD_OLD_API -void VerilatedVcd::declTriBit(vluint32_t code, const char* name, bool array, int arraynum) { +void VerilatedVcd::declTriBit(uint32_t code, const char* name, bool array, int arraynum) { declare(code, name, "wire", array, arraynum, true, false, 0, 0); } -void VerilatedVcd::declTriBus(vluint32_t code, const char* name, bool array, int arraynum, int msb, +void VerilatedVcd::declTriBus(uint32_t code, const char* name, bool array, int arraynum, int msb, int lsb) { declare(code, name, "wire", array, arraynum, true, true, msb, lsb); } -void VerilatedVcd::declTriQuad(vluint32_t code, const char* name, bool array, int arraynum, - int msb, int lsb) { +void VerilatedVcd::declTriQuad(uint32_t code, const char* name, bool array, int arraynum, int msb, + int lsb) { declare(code, name, "wire", array, arraynum, true, true, msb, lsb); } -void VerilatedVcd::declTriArray(vluint32_t code, const char* name, bool array, int arraynum, - int msb, int lsb) { +void VerilatedVcd::declTriArray(uint32_t code, const char* name, bool array, int arraynum, int msb, + int lsb) { declare(code, name, "wire", array, arraynum, true, true, msb, lsb); } #endif // VL_TRACE_VCD_OLD_API @@ -593,7 +593,7 @@ static inline void VerilatedVcdCCopyAndAppendNewLine(char* writep, const char* s #ifdef VL_X86_64 // Copy the whole 8 bytes in one go, this works on little-endian machines // supporting unaligned stores. - *reinterpret_cast(writep) = *reinterpret_cast(suffixp); + *reinterpret_cast(writep) = *reinterpret_cast(suffixp); #else // Portable variant writep[0] = suffixp[0]; @@ -606,7 +606,7 @@ static inline void VerilatedVcdCCopyAndAppendNewLine(char* writep, const char* s #endif } -void VerilatedVcd::finishLine(vluint32_t code, char* writep) { +void VerilatedVcd::finishLine(uint32_t code, char* writep) { const char* const suffixp = m_suffixes.data() + code * VL_TRACE_SUFFIX_ENTRY_SIZE; VL_DEBUG_IFDEF(assert(suffixp[0]);); VerilatedVcdCCopyAndAppendNewLine(writep, suffixp); @@ -625,7 +625,7 @@ void VerilatedVcd::finishLine(vluint32_t code, char* writep) { // so always inline them. VL_ATTR_ALWINLINE -void VerilatedVcd::emitBit(vluint32_t code, CData newval) { +void VerilatedVcd::emitBit(uint32_t code, CData newval) { // Don't prefetch suffix as it's a bit too late; char* wp = m_writep; *wp++ = '0' | static_cast(newval); @@ -633,7 +633,7 @@ void VerilatedVcd::emitBit(vluint32_t code, CData newval) { } VL_ATTR_ALWINLINE -void VerilatedVcd::emitCData(vluint32_t code, CData newval, int bits) { +void VerilatedVcd::emitCData(uint32_t code, CData newval, int bits) { char* wp = m_writep; *wp++ = 'b'; cvtCDataToStr(wp, newval << (VL_BYTESIZE - bits)); @@ -641,7 +641,7 @@ void VerilatedVcd::emitCData(vluint32_t code, CData newval, int bits) { } VL_ATTR_ALWINLINE -void VerilatedVcd::emitSData(vluint32_t code, SData newval, int bits) { +void VerilatedVcd::emitSData(uint32_t code, SData newval, int bits) { char* wp = m_writep; *wp++ = 'b'; cvtSDataToStr(wp, newval << (VL_SHORTSIZE - bits)); @@ -649,7 +649,7 @@ void VerilatedVcd::emitSData(vluint32_t code, SData newval, int bits) { } VL_ATTR_ALWINLINE -void VerilatedVcd::emitIData(vluint32_t code, IData newval, int bits) { +void VerilatedVcd::emitIData(uint32_t code, IData newval, int bits) { char* wp = m_writep; *wp++ = 'b'; cvtIDataToStr(wp, newval << (VL_IDATASIZE - bits)); @@ -657,7 +657,7 @@ void VerilatedVcd::emitIData(vluint32_t code, IData newval, int bits) { } VL_ATTR_ALWINLINE -void VerilatedVcd::emitQData(vluint32_t code, QData newval, int bits) { +void VerilatedVcd::emitQData(uint32_t code, QData newval, int bits) { char* wp = m_writep; *wp++ = 'b'; cvtQDataToStr(wp, newval << (VL_QUADSIZE - bits)); @@ -665,7 +665,7 @@ void VerilatedVcd::emitQData(vluint32_t code, QData newval, int bits) { } VL_ATTR_ALWINLINE -void VerilatedVcd::emitWData(vluint32_t code, const WData* newvalp, int bits) { +void VerilatedVcd::emitWData(uint32_t code, const WData* newvalp, int bits) { int words = VL_WORDS_I(bits); char* wp = m_writep; *wp++ = 'b'; @@ -682,7 +682,7 @@ void VerilatedVcd::emitWData(vluint32_t code, const WData* newvalp, int bits) { } VL_ATTR_ALWINLINE -void VerilatedVcd::emitDouble(vluint32_t code, double newval) { +void VerilatedVcd::emitDouble(uint32_t code, double newval) { char* wp = m_writep; // Buffer can't overflow before VL_SNPRINTF; we sized during declaration VL_SNPRINTF(wp, m_wrChunkSize, "r%.16g", newval); @@ -692,7 +692,7 @@ void VerilatedVcd::emitDouble(vluint32_t code, double newval) { #ifdef VL_TRACE_VCD_OLD_API -void VerilatedVcd::fullBit(vluint32_t code, const vluint32_t newval) { +void VerilatedVcd::fullBit(uint32_t code, const uint32_t newval) { // Note the &1, so we don't require clean input -- makes more common no change case faster *oldp(code) = newval; *m_writep++ = ('0' + static_cast(newval & 1)); @@ -700,7 +700,7 @@ void VerilatedVcd::fullBit(vluint32_t code, const vluint32_t newval) { *m_writep++ = '\n'; bufferCheck(); } -void VerilatedVcd::fullBus(vluint32_t code, const vluint32_t newval, int bits) { +void VerilatedVcd::fullBus(uint32_t code, const uint32_t newval, int bits) { *oldp(code) = newval; *m_writep++ = 'b'; for (int bit = bits - 1; bit >= 0; --bit) { @@ -711,8 +711,8 @@ void VerilatedVcd::fullBus(vluint32_t code, const vluint32_t newval, int bits) { *m_writep++ = '\n'; bufferCheck(); } -void VerilatedVcd::fullQuad(vluint32_t code, const vluint64_t newval, int bits) { - (*(reinterpret_cast(oldp(code)))) = newval; +void VerilatedVcd::fullQuad(uint32_t code, const uint64_t newval, int bits) { + (*(reinterpret_cast(oldp(code)))) = newval; *m_writep++ = 'b'; for (int bit = bits - 1; bit >= 0; --bit) { *m_writep++ = ((newval & (1ULL << bit)) ? '1' : '0'); @@ -722,7 +722,7 @@ void VerilatedVcd::fullQuad(vluint32_t code, const vluint64_t newval, int bits) *m_writep++ = '\n'; bufferCheck(); } -void VerilatedVcd::fullArray(vluint32_t code, const vluint32_t* newval, int bits) { +void VerilatedVcd::fullArray(uint32_t code, const uint32_t* newval, int bits) { for (int word = 0; word < (((bits - 1) / 32) + 1); ++word) { oldp(code)[word] = newval[word]; } *m_writep++ = 'b'; for (int bit = bits - 1; bit >= 0; --bit) { @@ -733,7 +733,7 @@ void VerilatedVcd::fullArray(vluint32_t code, const vluint32_t* newval, int bits *m_writep++ = '\n'; bufferCheck(); } -void VerilatedVcd::fullArray(vluint32_t code, const vluint64_t* newval, int bits) { +void VerilatedVcd::fullArray(uint32_t code, const uint64_t* newval, int bits) { for (int word = 0; word < (((bits - 1) / 64) + 1); ++word) { oldp(code)[word] = newval[word]; } *m_writep++ = 'b'; for (int bit = bits - 1; bit >= 0; --bit) { @@ -744,7 +744,7 @@ void VerilatedVcd::fullArray(vluint32_t code, const vluint64_t* newval, int bits *m_writep++ = '\n'; bufferCheck(); } -void VerilatedVcd::fullTriBit(vluint32_t code, const vluint32_t newval, const vluint32_t newtri) { +void VerilatedVcd::fullTriBit(uint32_t code, const uint32_t newval, const uint32_t newtri) { oldp(code)[0] = newval; oldp(code)[1] = newtri; *m_writep++ = "01zz"[newval | (newtri << 1)]; @@ -752,7 +752,7 @@ void VerilatedVcd::fullTriBit(vluint32_t code, const vluint32_t newval, const vl *m_writep++ = '\n'; bufferCheck(); } -void VerilatedVcd::fullTriBus(vluint32_t code, const vluint32_t newval, const vluint32_t newtri, +void VerilatedVcd::fullTriBus(uint32_t code, const uint32_t newval, const uint32_t newtri, int bits) { oldp(code)[0] = newval; oldp(code)[1] = newtri; @@ -765,10 +765,10 @@ void VerilatedVcd::fullTriBus(vluint32_t code, const vluint32_t newval, const vl *m_writep++ = '\n'; bufferCheck(); } -void VerilatedVcd::fullTriQuad(vluint32_t code, const vluint64_t newval, const vluint64_t newtri, +void VerilatedVcd::fullTriQuad(uint32_t code, const uint64_t newval, const uint64_t newtri, int bits) { - (*(reinterpret_cast(oldp(code)))) = newval; - (*(reinterpret_cast(oldp(code + 1)))) = newtri; + (*(reinterpret_cast(oldp(code)))) = newval; + (*(reinterpret_cast(oldp(code + 1)))) = newtri; *m_writep++ = 'b'; for (int bit = bits - 1; bit >= 0; --bit) { *m_writep++ = "01zz"[((newval >> bit) & 1ULL) | (((newtri >> bit) & 1ULL) << 1ULL)]; @@ -778,16 +778,16 @@ void VerilatedVcd::fullTriQuad(vluint32_t code, const vluint64_t newval, const v *m_writep++ = '\n'; bufferCheck(); } -void VerilatedVcd::fullTriArray(vluint32_t code, const vluint32_t* newvalp, - const vluint32_t* newtrip, int bits) { +void VerilatedVcd::fullTriArray(uint32_t code, const uint32_t* newvalp, const uint32_t* newtrip, + int bits) { for (int word = 0; word < (((bits - 1) / 32) + 1); ++word) { oldp(code)[word * 2] = newvalp[word]; oldp(code)[word * 2 + 1] = newtrip[word]; } *m_writep++ = 'b'; for (int bit = bits - 1; bit >= 0; --bit) { - vluint32_t valbit = (newvalp[(bit / 32)] >> (bit & 0x1f)) & 1; - vluint32_t tribit = (newtrip[(bit / 32)] >> (bit & 0x1f)) & 1; + uint32_t valbit = (newvalp[(bit / 32)] >> (bit & 0x1f)) & 1; + uint32_t tribit = (newtrip[(bit / 32)] >> (bit & 0x1f)) & 1; *m_writep++ = "01zz"[valbit | (tribit << 1)]; } *m_writep++ = ' '; @@ -795,7 +795,7 @@ void VerilatedVcd::fullTriArray(vluint32_t code, const vluint32_t* newvalp, *m_writep++ = '\n'; bufferCheck(); } -void VerilatedVcd::fullDouble(vluint32_t code, const double newval) { +void VerilatedVcd::fullDouble(uint32_t code, const double newval) { // cppcheck-suppress invalidPointerCast (*(reinterpret_cast(oldp(code)))) = newval; // Buffer can't overflow before VL_SNPRINTF; we sized during declaration @@ -818,18 +818,18 @@ void VerilatedVcd::fullDouble(vluint32_t code, const double newval) { extern void verilated_trace_imp_selftest(); -vluint32_t v1, v2, s1, s2[3]; -vluint32_t tri96[3]; -vluint32_t tri96__tri[3]; -vluint64_t quad96[2]; -vluint64_t tquad; -vluint64_t tquad__tri; -vluint8_t ch; -vluint64_t timestamp = 1; +uint32_t v1, v2, s1, s2[3]; +uint32_t tri96[3]; +uint32_t tri96__tri[3]; +uint64_t quad96[2]; +uint64_t tquad; +uint64_t tquad__tri; +uint8_t ch; +uint64_t timestamp = 1; double doub = 0.0; float flo = 0.0f; -void vcdInit(void*, VerilatedVcd* vcdp, vluint32_t) { +void vcdInit(void*, VerilatedVcd* vcdp, uint32_t) { vcdp->scopeEscape('.'); vcdp->pushNamePrefix("top."); /**/ vcdp->declBus(0x2, "v1", -1, 0, 5, 1); @@ -933,8 +933,8 @@ void vcdTestMain(const char* filenamep) { vcdp->dump(++timestamp); vcdp->dump(++timestamp); # ifdef VERILATED_VCD_TEST_64BIT - const vluint64_t bytesPerDump = 15ULL; - for (vluint64_t i = 0; i < ((1ULL << 32) / bytesPerDump); i++) { + const uint64_t bytesPerDump = 15ULL; + for (uint64_t i = 0; i < ((1ULL << 32) / bytesPerDump); i++) { v1 = i; vcdp->dump(++timestamp); } diff --git a/include/verilated_vcd_c.h b/include/verilated_vcd_c.h index 8595baba3..5fbb6022c 100644 --- a/include/verilated_vcd_c.h +++ b/include/verilated_vcd_c.h @@ -70,21 +70,21 @@ private: bool m_isOpen = false; // True indicates open file bool m_evcd = false; // True for evcd format std::string m_filename; // Filename we're writing to (if open) - vluint64_t m_rolloverMB = 0; // MB of file size to rollover at + uint64_t m_rolloverMB = 0; // MB of file size to rollover at int m_modDepth = 0; // Depth of module hierarchy char* m_wrBufp; // Output buffer const char* m_wrFlushp; // Output buffer flush trigger location char* m_writep; // Write pointer into output buffer - vluint64_t m_wrChunkSize; // Output buffer size - vluint64_t m_wroteBytes = 0; // Number of bytes written to this file + uint64_t m_wrChunkSize; // Output buffer size + uint64_t m_wroteBytes = 0; // Number of bytes written to this file std::vector m_suffixes; // VCD line end string codes + metadata using NameMap = std::map; NameMap* m_namemapp = nullptr; // List of names for the header - void bufferResize(vluint64_t minsize); + void bufferResize(uint64_t minsize); void bufferFlush() VL_MT_UNSAFE_ONE; inline void bufferCheck() { // Flush the write buffer if there's not enough space left for new information @@ -98,16 +98,16 @@ private: void deleteNameMap(); void printIndent(int level_change); void printStr(const char* str); - void printQuad(vluint64_t n); - void printTime(vluint64_t timeui); - void declare(vluint32_t code, const char* name, const char* wirep, bool array, int arraynum, + void printQuad(uint64_t n); + void printTime(uint64_t timeui); + void declare(uint32_t code, const char* name, const char* wirep, bool array, int arraynum, bool tri, bool bussed, int msb, int lsb); void dumpHeader(); - static char* writeCode(char* writep, vluint32_t code); + static char* writeCode(char* writep, uint32_t code); - void finishLine(vluint32_t code, char* writep); + void finishLine(uint32_t code, char* writep); // CONSTRUCTORS VL_UNCOPYABLE(VerilatedVcd); @@ -117,7 +117,7 @@ protected: // Implementation of VerilatedTrace interface // Implementations of protected virtual methods for VerilatedTrace - virtual void emitTimeChange(vluint64_t timeui) override; + virtual void emitTimeChange(uint64_t timeui) override; // Hooks called from VerilatedTrace virtual bool preFullDump() override { return isOpen(); } @@ -125,13 +125,13 @@ protected: // Implementations of duck-typed methods for VerilatedTrace. These are // called from only one place (namely full*) so always inline them. - inline void emitBit(vluint32_t code, CData newval); - inline void emitCData(vluint32_t code, CData newval, int bits); - inline void emitSData(vluint32_t code, SData newval, int bits); - inline void emitIData(vluint32_t code, IData newval, int bits); - inline void emitQData(vluint32_t code, QData newval, int bits); - inline void emitWData(vluint32_t code, const WData* newvalp, int bits); - inline void emitDouble(vluint32_t code, double newval); + inline void emitBit(uint32_t code, CData newval); + inline void emitCData(uint32_t code, CData newval, int bits); + inline void emitSData(uint32_t code, SData newval, int bits); + inline void emitIData(uint32_t code, IData newval, int bits); + inline void emitQData(uint32_t code, QData newval, int bits); + inline void emitWData(uint32_t code, const WData* newvalp, int bits); + inline void emitDouble(uint32_t code, double newval); public: //========================================================================= @@ -142,7 +142,7 @@ public: // ACCESSORS // Set size in megabytes after which new file should be created - void rolloverMB(vluint64_t rolloverMB) { m_rolloverMB = rolloverMB; } + void rolloverMB(uint64_t rolloverMB) { m_rolloverMB = rolloverMB; } // METHODS // Open the file; call isOpen() to see if errors @@ -159,11 +159,11 @@ public: //========================================================================= // Internal interface to Verilator generated code - void declBit(vluint32_t code, const char* name, bool array, int arraynum); - void declBus(vluint32_t code, const char* name, bool array, int arraynum, int msb, int lsb); - void declQuad(vluint32_t code, const char* name, bool array, int arraynum, int msb, int lsb); - void declArray(vluint32_t code, const char* name, bool array, int arraynum, int msb, int lsb); - void declDouble(vluint32_t code, const char* name, bool array, int arraynum); + void declBit(uint32_t code, const char* name, bool array, int arraynum); + void declBus(uint32_t code, const char* name, bool array, int arraynum, int msb, int lsb); + void declQuad(uint32_t code, const char* name, bool array, int arraynum, int msb, int lsb); + void declArray(uint32_t code, const char* name, bool array, int arraynum, int msb, int lsb); + void declDouble(uint32_t code, const char* name, bool array, int arraynum); #ifdef VL_TRACE_VCD_OLD_API //========================================================================= @@ -171,88 +171,85 @@ public: // code and is not used by Verilator. Do not use these as there is no // guarantee of functionality. - void declTriBit(vluint32_t code, const char* name, bool array, int arraynum); - void declTriBus(vluint32_t code, const char* name, bool array, int arraynum, int msb, int lsb); - void declTriQuad(vluint32_t code, const char* name, bool array, int arraynum, int msb, - int lsb); - void declTriArray(vluint32_t code, const char* name, bool array, int arraynum, int msb, - int lsb); + void declTriBit(uint32_t code, const char* name, bool array, int arraynum); + void declTriBus(uint32_t code, const char* name, bool array, int arraynum, int msb, int lsb); + void declTriQuad(uint32_t code, const char* name, bool array, int arraynum, int msb, int lsb); + void declTriArray(uint32_t code, const char* name, bool array, int arraynum, int msb, int lsb); - void fullBit(vluint32_t* oldp, CData newval) { fullBit(oldp - this->oldp(0), newval); } - void fullCData(vluint32_t* oldp, CData newval, int bits) { + void fullBit(uint32_t* oldp, CData newval) { fullBit(oldp - this->oldp(0), newval); } + void fullCData(uint32_t* oldp, CData newval, int bits) { fullBus(oldp - this->oldp(0), newval, bits); } - void fullSData(vluint32_t* oldp, SData newval, int bits) { + void fullSData(uint32_t* oldp, SData newval, int bits) { fullBus(oldp - this->oldp(0), newval, bits); } - void fullIData(vluint32_t* oldp, IData newval, int bits) { + void fullIData(uint32_t* oldp, IData newval, int bits) { fullBus(oldp - this->oldp(0), newval, bits); } - void fullQData(vluint32_t* oldp, QData newval, int bits) { + void fullQData(uint32_t* oldp, QData newval, int bits) { fullQuad(oldp - this->oldp(0), newval, bits); } - void fullWData(vluint32_t* oldp, const WData* newvalp, int bits) { + void fullWData(uint32_t* oldp, const WData* newvalp, int bits) { fullArray(oldp - this->oldp(0), newvalp, bits); } - void fullDouble(vluint32_t* oldp, double newval) { fullDouble(oldp - this->oldp(0), newval); } + void fullDouble(uint32_t* oldp, double newval) { fullDouble(oldp - this->oldp(0), newval); } - inline void chgBit(vluint32_t* oldp, CData newval) { chgBit(oldp - this->oldp(0), newval); } - inline void chgCData(vluint32_t* oldp, CData newval, int bits) { + inline void chgBit(uint32_t* oldp, CData newval) { chgBit(oldp - this->oldp(0), newval); } + inline void chgCData(uint32_t* oldp, CData newval, int bits) { chgBus(oldp - this->oldp(0), newval, bits); } - inline void chgSData(vluint32_t* oldp, SData newval, int bits) { + inline void chgSData(uint32_t* oldp, SData newval, int bits) { chgBus(oldp - this->oldp(0), newval, bits); } - inline void chgIData(vluint32_t* oldp, IData newval, int bits) { + inline void chgIData(uint32_t* oldp, IData newval, int bits) { chgBus(oldp - this->oldp(0), newval, bits); } - inline void chgQData(vluint32_t* oldp, QData newval, int bits) { + inline void chgQData(uint32_t* oldp, QData newval, int bits) { chgQuad(oldp - this->oldp(0), newval, bits); } - inline void chgWData(vluint32_t* oldp, const WData* newvalp, int bits) { + inline void chgWData(uint32_t* oldp, const WData* newvalp, int bits) { chgArray(oldp - this->oldp(0), newvalp, bits); } - inline void chgDouble(vluint32_t* oldp, double newval) { + inline void chgDouble(uint32_t* oldp, double newval) { chgDouble(oldp - this->oldp(0), newval); } // Inside dumping routines, dump one signal, faster when not inlined // due to code size reduction. - void fullBit(vluint32_t code, const vluint32_t newval); - void fullBus(vluint32_t code, const vluint32_t newval, int bits); - void fullQuad(vluint32_t code, const vluint64_t newval, int bits); - void fullArray(vluint32_t code, const vluint32_t* newvalp, int bits); - void fullArray(vluint32_t code, const vluint64_t* newvalp, int bits); - void fullTriBit(vluint32_t code, const vluint32_t newval, const vluint32_t newtri); - void fullTriBus(vluint32_t code, const vluint32_t newval, const vluint32_t newtri, int bits); - void fullTriQuad(vluint32_t code, const vluint64_t newval, const vluint64_t newtri, int bits); - void fullTriArray(vluint32_t code, const vluint32_t* newvalp, const vluint32_t* newtrip, - int bits); - void fullDouble(vluint32_t code, const double newval); + void fullBit(uint32_t code, const uint32_t newval); + void fullBus(uint32_t code, const uint32_t newval, int bits); + void fullQuad(uint32_t code, const uint64_t newval, int bits); + void fullArray(uint32_t code, const uint32_t* newvalp, int bits); + void fullArray(uint32_t code, const uint64_t* newvalp, int bits); + void fullTriBit(uint32_t code, const uint32_t newval, const uint32_t newtri); + void fullTriBus(uint32_t code, const uint32_t newval, const uint32_t newtri, int bits); + void fullTriQuad(uint32_t code, const uint64_t newval, const uint64_t newtri, int bits); + void fullTriArray(uint32_t code, const uint32_t* newvalp, const uint32_t* newtrip, int bits); + void fullDouble(uint32_t code, const double newval); // Inside dumping routines, dump one signal if it has changed. // We do want to inline these to avoid calls when the value did not change. - inline void chgBit(vluint32_t code, const vluint32_t newval) { - const vluint32_t diff = oldp(code)[0] ^ newval; + inline void chgBit(uint32_t code, const uint32_t newval) { + const uint32_t diff = oldp(code)[0] ^ newval; if (VL_UNLIKELY(diff)) fullBit(code, newval); } - inline void chgBus(vluint32_t code, const vluint32_t newval, int bits) { - const vluint32_t diff = oldp(code)[0] ^ newval; + inline void chgBus(uint32_t code, const uint32_t newval, int bits) { + const uint32_t diff = oldp(code)[0] ^ newval; if (VL_UNLIKELY(diff)) { if (VL_UNLIKELY(bits == 32 || (diff & ((1U << bits) - 1)))) { fullBus(code, newval, bits); } } } - inline void chgQuad(vluint32_t code, const vluint64_t newval, int bits) { - const vluint64_t diff = (*(reinterpret_cast(oldp(code)))) ^ newval; + inline void chgQuad(uint32_t code, const uint64_t newval, int bits) { + const uint64_t diff = (*(reinterpret_cast(oldp(code)))) ^ newval; if (VL_UNLIKELY(diff)) { if (VL_UNLIKELY(bits == 64 || (diff & ((1ULL << bits) - 1)))) { fullQuad(code, newval, bits); } } } - inline void chgArray(vluint32_t code, const vluint32_t* newvalp, int bits) { + inline void chgArray(uint32_t code, const uint32_t* newvalp, int bits) { for (int word = 0; word < (((bits - 1) / 32) + 1); ++word) { if (VL_UNLIKELY(oldp(code)[word] ^ newvalp[word])) { fullArray(code, newvalp, bits); @@ -260,17 +257,17 @@ public: } } } - inline void chgArray(vluint32_t code, const vluint64_t* newvalp, int bits) { + inline void chgArray(uint32_t code, const uint64_t* newvalp, int bits) { for (int word = 0; word < (((bits - 1) / 64) + 1); ++word) { - if (VL_UNLIKELY(*(reinterpret_cast(oldp(code + 2 * word))) + if (VL_UNLIKELY(*(reinterpret_cast(oldp(code + 2 * word))) ^ newvalp[word])) { fullArray(code, newvalp, bits); return; } } } - inline void chgTriBit(vluint32_t code, const vluint32_t newval, const vluint32_t newtri) { - const vluint32_t diff = ((oldp(code)[0] ^ newval) | (oldp(code)[1] ^ newtri)); + inline void chgTriBit(uint32_t code, const uint32_t newval, const uint32_t newtri) { + const uint32_t diff = ((oldp(code)[0] ^ newval) | (oldp(code)[1] ^ newtri)); if (VL_UNLIKELY(diff)) { // Verilator 3.510 and newer provide clean input, so the below // is only for back compatibility @@ -279,26 +276,24 @@ public: } } } - inline void chgTriBus(vluint32_t code, const vluint32_t newval, const vluint32_t newtri, - int bits) { - const vluint32_t diff = ((oldp(code)[0] ^ newval) | (oldp(code)[1] ^ newtri)); + inline void chgTriBus(uint32_t code, const uint32_t newval, const uint32_t newtri, int bits) { + const uint32_t diff = ((oldp(code)[0] ^ newval) | (oldp(code)[1] ^ newtri)); if (VL_UNLIKELY(diff)) { if (VL_UNLIKELY(bits == 32 || (diff & ((1U << bits) - 1)))) { fullTriBus(code, newval, newtri, bits); } } } - inline void chgTriQuad(vluint32_t code, const vluint64_t newval, const vluint64_t newtri, - int bits) { - const vluint64_t diff = (((*(reinterpret_cast(oldp(code)))) ^ newval) - | ((*(reinterpret_cast(oldp(code + 1)))) ^ newtri)); + inline void chgTriQuad(uint32_t code, const uint64_t newval, const uint64_t newtri, int bits) { + const uint64_t diff = (((*(reinterpret_cast(oldp(code)))) ^ newval) + | ((*(reinterpret_cast(oldp(code + 1)))) ^ newtri)); if (VL_UNLIKELY(diff)) { if (VL_UNLIKELY(bits == 64 || (diff & ((1ULL << bits) - 1)))) { fullTriQuad(code, newval, newtri, bits); } } } - inline void chgTriArray(vluint32_t code, const vluint32_t* newvalp, const vluint32_t* newtrip, + inline void chgTriArray(uint32_t code, const uint32_t* newvalp, const uint32_t* newtrip, int bits) { for (int word = 0; word < (((bits - 1) / 32) + 1); ++word) { if (VL_UNLIKELY((oldp(code)[word * 2] ^ newvalp[word]) @@ -308,7 +303,7 @@ public: } } } - inline void chgDouble(vluint32_t code, const double newval) { + inline void chgDouble(uint32_t code, const double newval) { // cppcheck-suppress invalidPointerCast if (VL_UNLIKELY((*(reinterpret_cast(oldp(code)))) != newval)) { fullDouble(code, newval); @@ -323,7 +318,7 @@ public: #ifndef DOXYGEN // Declare specializations here they are used in VerilatedVcdC just below -template <> void VerilatedTrace::dump(vluint64_t timeui); +template <> void VerilatedTrace::dump(uint64_t timeui); template <> void VerilatedTrace::set_time_unit(const char* unitp); template <> void VerilatedTrace::set_time_unit(const std::string& unit); template <> void VerilatedTrace::set_time_resolution(const char* unitp); @@ -371,12 +366,12 @@ public: /// Write one cycle of dump data /// Call with the current context's time just after eval'ed, /// e.g. ->dump(contextp->time()) - void dump(vluint64_t timeui) VL_MT_SAFE { m_sptrace.dump(timeui); } + void dump(uint64_t timeui) VL_MT_SAFE { m_sptrace.dump(timeui); } /// Write one cycle of dump data - backward compatible and to reduce - /// conversion warnings. It's better to use a vluint64_t time instead. - void dump(double timestamp) { dump(static_cast(timestamp)); } - void dump(vluint32_t timestamp) { dump(static_cast(timestamp)); } - void dump(int timestamp) { dump(static_cast(timestamp)); } + /// conversion warnings. It's better to use a uint64_t time instead. + void dump(double timestamp) { dump(static_cast(timestamp)); } + void dump(uint32_t timestamp) { dump(static_cast(timestamp)); } + void dump(int timestamp) { dump(static_cast(timestamp)); } // METHODS - Internal/backward compatible // \protectedsection diff --git a/include/verilated_vpi.cpp b/include/verilated_vpi.cpp index 365d0e520..479a9cb59 100644 --- a/include/verilated_vpi.cpp +++ b/include/verilated_vpi.cpp @@ -66,11 +66,11 @@ class VerilatedVpio VL_NOT_FINAL { // CONSTANTS // Magic value stored in front of object to detect double free etc // Must be odd, as aligned pointer can never be odd - static constexpr vluint32_t activeMagic() { return 0xfeed100f; } + static constexpr uint32_t activeMagic() { return 0xfeed100f; } // MEM MANGLEMENT // Internal note: Globals may multi-construct, see verilated.cpp top. - static VL_THREAD_LOCAL vluint8_t* t_freeHead; + static VL_THREAD_LOCAL uint8_t* t_freeHead; public: // CONSTRUCTORS @@ -84,19 +84,19 @@ public: static const size_t chunk = 96; if (VL_UNCOVERABLE(size > chunk)) VL_FATAL_MT(__FILE__, __LINE__, "", "increase chunk"); if (VL_LIKELY(t_freeHead)) { - vluint8_t* const newp = t_freeHead; - t_freeHead = *(reinterpret_cast(newp)); - *(reinterpret_cast(newp)) = activeMagic(); + uint8_t* const newp = t_freeHead; + t_freeHead = *(reinterpret_cast(newp)); + *(reinterpret_cast(newp)) = activeMagic(); return newp + 8; } // +8: 8 bytes for next - vluint8_t* newp = reinterpret_cast(::operator new(chunk + 8)); - *(reinterpret_cast(newp)) = activeMagic(); + uint8_t* newp = reinterpret_cast(::operator new(chunk + 8)); + *(reinterpret_cast(newp)) = activeMagic(); return newp + 8; } static void operator delete(void* obj, size_t /*size*/)VL_MT_SAFE { - vluint8_t* const oldp = (static_cast(obj)) - 8; - if (VL_UNLIKELY(*(reinterpret_cast(oldp)) != activeMagic())) { + uint8_t* const oldp = (static_cast(obj)) - 8; + if (VL_UNLIKELY(*(reinterpret_cast(oldp)) != activeMagic())) { VL_FATAL_MT(__FILE__, __LINE__, "", "vpi_release_handle() called on same object twice, or on non-Verilator " "VPI object"); @@ -117,8 +117,8 @@ public: virtual const char* name() const { return ""; } virtual const char* fullname() const { return ""; } virtual const char* defname() const { return ""; } - virtual vluint32_t type() const { return 0; } - virtual vluint32_t size() const { return 0; } + virtual uint32_t type() const { return 0; } + virtual uint32_t size() const { return 0; } virtual const VerilatedRange* rangep() const { return nullptr; } virtual vpiHandle dovpi_scan() { return nullptr; } virtual PLI_INT32 dovpi_remove_cb() { return 0; } @@ -127,52 +127,52 @@ public: class VerilatedVpioTimedCb final : public VerilatedVpio { // A handle to a timed callback created with vpi_register_cb // User can call vpi_remove_cb or vpi_release_handle on it - const vluint64_t m_id; // Unique id/sequence number to find schedule's event + const uint64_t m_id; // Unique id/sequence number to find schedule's event const QData m_time; public: - VerilatedVpioTimedCb(vluint64_t id, QData time) + VerilatedVpioTimedCb(uint64_t id, QData time) : m_id{id} , m_time{time} {} virtual ~VerilatedVpioTimedCb() override = default; static VerilatedVpioTimedCb* castp(vpiHandle h) { return dynamic_cast(reinterpret_cast(h)); } - virtual vluint32_t type() const override { return vpiCallback; } + virtual uint32_t type() const override { return vpiCallback; } virtual PLI_INT32 dovpi_remove_cb() override; }; class VerilatedVpioReasonCb final : public VerilatedVpio { // A handle to a non-timed callback created with vpi_register_cb // User can call vpi_remove_cb or vpi_release_handle on it - const vluint64_t m_id; // Unique id/sequence number to find schedule's event + const uint64_t m_id; // Unique id/sequence number to find schedule's event const PLI_INT32 m_reason; // VPI callback reason code public: // cppcheck-suppress uninitVar // m_value - VerilatedVpioReasonCb(vluint64_t id, PLI_INT32 reason) + VerilatedVpioReasonCb(uint64_t id, PLI_INT32 reason) : m_id{id} , m_reason{reason} {} virtual ~VerilatedVpioReasonCb() override = default; static VerilatedVpioReasonCb* castp(vpiHandle h) { return dynamic_cast(reinterpret_cast(h)); } - virtual vluint32_t type() const override { return vpiCallback; } + virtual uint32_t type() const override { return vpiCallback; } virtual PLI_INT32 dovpi_remove_cb() override; }; class VerilatedVpioConst final : public VerilatedVpio { - const vlsint32_t m_num; + const int32_t m_num; public: - explicit VerilatedVpioConst(vlsint32_t num) + explicit VerilatedVpioConst(int32_t num) : m_num{num} {} virtual ~VerilatedVpioConst() override = default; static VerilatedVpioConst* castp(vpiHandle h) { return dynamic_cast(reinterpret_cast(h)); } - virtual vluint32_t type() const override { return vpiConstant; } - vlsint32_t num() const { return m_num; } + virtual uint32_t type() const override { return vpiConstant; } + int32_t num() const { return m_num; } }; class VerilatedVpioVarBase VL_NOT_FINAL : public VerilatedVpio { @@ -199,7 +199,7 @@ public: } const VerilatedVar* varp() const { return m_varp; } const VerilatedScope* scopep() const { return m_scopep; } - virtual vluint32_t size() const override { return get_range().elements(); } + virtual uint32_t size() const override { return get_range().elements(); } virtual const VerilatedRange* rangep() const override { return &get_range(); } virtual const char* name() const override { return m_varp->name(); } virtual const char* fullname() const override { @@ -218,7 +218,7 @@ public: static VerilatedVpioParam* castp(vpiHandle h) { return dynamic_cast(reinterpret_cast(h)); } - virtual vluint32_t type() const override { return vpiParameter; } + virtual uint32_t type() const override { return vpiParameter; } void* varDatap() const { return m_varp->datap(); } }; @@ -232,8 +232,8 @@ public: static VerilatedVpioRange* castp(vpiHandle h) { return dynamic_cast(reinterpret_cast(h)); } - virtual vluint32_t type() const override { return vpiRange; } - virtual vluint32_t size() const override { return m_range->elements(); } + virtual uint32_t type() const override { return vpiRange; } + virtual uint32_t size() const override { return m_range->elements(); } virtual const VerilatedRange* rangep() const override { return m_range; } }; @@ -249,7 +249,7 @@ public: static VerilatedVpioRangeIter* castp(vpiHandle h) { return dynamic_cast(reinterpret_cast(h)); } - virtual vluint32_t type() const override { return vpiIterator; } + virtual uint32_t type() const override { return vpiIterator; } virtual vpiHandle dovpi_scan() override { if (VL_UNLIKELY(m_done)) { delete this; // IEEE 37.2.2 vpi_scan at end does a vpi_release_handle @@ -271,22 +271,22 @@ public: static VerilatedVpioScope* castp(vpiHandle h) { return dynamic_cast(reinterpret_cast(h)); } - virtual vluint32_t type() const override { return vpiScope; } + virtual uint32_t type() const override { return vpiScope; } const VerilatedScope* scopep() const { return m_scopep; } virtual const char* name() const override { return m_scopep->name(); } virtual const char* fullname() const override { return m_scopep->name(); } }; class VerilatedVpioVar VL_NOT_FINAL : public VerilatedVpioVarBase { - vluint8_t* m_prevDatap = nullptr; // Previous value of data, for cbValueChange + uint8_t* m_prevDatap = nullptr; // Previous value of data, for cbValueChange union { - vluint8_t u8[4]; - vluint32_t u32; + uint8_t u8[4]; + uint32_t u32; } m_mask; // memoized variable mask - vluint32_t m_entSize = 0; // memoized variable size + uint32_t m_entSize = 0; // memoized variable size protected: void* m_varDatap = nullptr; // varp()->datap() adjusted for array entries - vlsint32_t m_index = 0; + int32_t m_index = 0; public: VerilatedVpioVar(const VerilatedVar* varp, const VerilatedScope* scopep) @@ -313,18 +313,18 @@ public: static VerilatedVpioVar* castp(vpiHandle h) { return dynamic_cast(reinterpret_cast(h)); } - vluint32_t mask() const { return m_mask.u32; } - vluint8_t mask_byte(int idx) const { return m_mask.u8[idx & 3]; } - vluint32_t entSize() const { return m_entSize; } - vluint32_t index() const { return m_index; } - virtual vluint32_t type() const override { + uint32_t mask() const { return m_mask.u32; } + uint8_t mask_byte(int idx) const { return m_mask.u8[idx & 3]; } + uint32_t entSize() const { return m_entSize; } + uint32_t index() const { return m_index; } + virtual uint32_t type() const override { return (varp()->dims() > 1) ? vpiMemory : vpiReg; // but might be wire, logic } void* prevDatap() const { return m_prevDatap; } void* varDatap() const { return m_varDatap; } void createPrevDatap() { if (VL_UNLIKELY(!m_prevDatap)) { - m_prevDatap = new vluint8_t[entSize()]; + m_prevDatap = new uint8_t[entSize()]; std::memcpy(prevDatap(), varp()->datap(), entSize()); } } @@ -332,18 +332,18 @@ public: class VerilatedVpioMemoryWord final : public VerilatedVpioVar { public: - VerilatedVpioMemoryWord(const VerilatedVar* varp, const VerilatedScope* scopep, - vlsint32_t index, int offset) + VerilatedVpioMemoryWord(const VerilatedVar* varp, const VerilatedScope* scopep, int32_t index, + int offset) : VerilatedVpioVar{varp, scopep} { m_index = index; - m_varDatap = (static_cast(varp->datap())) + entSize() * offset; + m_varDatap = (static_cast(varp->datap())) + entSize() * offset; } virtual ~VerilatedVpioMemoryWord() override = default; static VerilatedVpioMemoryWord* castp(vpiHandle h) { return dynamic_cast(reinterpret_cast(h)); } - virtual vluint32_t type() const override { return vpiMemoryWord; } - virtual vluint32_t size() const override { return varp()->packed().elements(); } + virtual uint32_t type() const override { return vpiMemoryWord; } + virtual uint32_t size() const override { return varp()->packed().elements(); } virtual const VerilatedRange* rangep() const override { return &(varp()->packed()); } virtual const char* fullname() const override { static VL_THREAD_LOCAL std::string t_out; @@ -367,7 +367,7 @@ public: static VerilatedVpioVarIter* castp(vpiHandle h) { return dynamic_cast(reinterpret_cast(h)); } - virtual vluint32_t type() const override { return vpiIterator; } + virtual uint32_t type() const override { return vpiIterator; } virtual vpiHandle dovpi_scan() override { if (VL_LIKELY(m_scopep->varsp())) { const VerilatedVarNameMap* const varsp = m_scopep->varsp(); @@ -394,8 +394,8 @@ public: class VerilatedVpioMemoryWordIter final : public VerilatedVpio { const vpiHandle m_handle; const VerilatedVar* const m_varp; - vlsint32_t m_iteration; - const vlsint32_t m_direction; + int32_t m_iteration; + const int32_t m_direction; bool m_done = false; public: @@ -408,7 +408,7 @@ public: static VerilatedVpioMemoryWordIter* castp(vpiHandle h) { return dynamic_cast(reinterpret_cast(h)); } - virtual vluint32_t type() const override { return vpiIterator; } + virtual uint32_t type() const override { return vpiIterator; } void iterationInc() { if (!(m_done = (m_iteration == m_varp->unpacked().left()))) m_iteration += m_direction; } @@ -437,7 +437,7 @@ public: static VerilatedVpioModule* castp(vpiHandle h) { return dynamic_cast(reinterpret_cast(h)); } - virtual vluint32_t type() const override { return vpiModule; } + virtual uint32_t type() const override { return vpiModule; } virtual const char* name() const override { return m_name; } virtual const char* fullname() const override { return m_fullname; } }; @@ -455,7 +455,7 @@ public: static VerilatedVpioModuleIter* castp(vpiHandle h) { return dynamic_cast(reinterpret_cast(h)); } - virtual vluint32_t type() const override { return vpiIterator; } + virtual uint32_t type() const override { return vpiIterator; } virtual vpiHandle dovpi_scan() override { if (m_it == m_vec->end()) { delete this; // IEEE 37.2.2 vpi_scan at end does a vpi_release_handle @@ -472,14 +472,14 @@ using VerilatedPliCb = PLI_INT32 (*)(struct t_cb_data*); class VerilatedVpiCbHolder final { // Holds information needed to call a callback - vluint64_t m_id; + uint64_t m_id; s_cb_data m_cbData; s_vpi_value m_value; VerilatedVpioVar m_varo; // If a cbValueChange callback, the object we will return public: // cppcheck-suppress uninitVar // m_value - VerilatedVpiCbHolder(vluint64_t id, const s_cb_data* cbDatap, const VerilatedVpioVar* varop) + VerilatedVpiCbHolder(uint64_t id, const s_cb_data* cbDatap, const VerilatedVpioVar* varop) : m_id{id} , m_cbData{*cbDatap} , m_varo{varop} { @@ -495,15 +495,15 @@ public: ~VerilatedVpiCbHolder() = default; VerilatedPliCb cb_rtnp() const { return m_cbData.cb_rtn; } s_cb_data* cb_datap() { return &m_cbData; } - vluint64_t id() const { return m_id; } + uint64_t id() const { return m_id; } bool invalid() const { return !m_id; } void invalidate() { m_id = 0; } }; struct VerilatedVpiTimedCbsCmp { // Ordering sets keyed by time, then callback unique id - bool operator()(const std::pair& a, - const std::pair& b) const { + bool operator()(const std::pair& a, + const std::pair& b) const { if (a.first < b.first) return true; if (a.first > b.first) return false; return a.second < b.second; @@ -515,14 +515,14 @@ class VerilatedVpiError; class VerilatedVpiImp final { enum { CB_ENUM_MAX_VALUE = cbAtEndOfSimTime + 1 }; // Maxium callback reason using VpioCbList = std::list; - using VpioTimedCbs = std::map, VerilatedVpiCbHolder>; + using VpioTimedCbs = std::map, VerilatedVpiCbHolder>; // All only medium-speed, so use singleton function VpioCbList m_cbObjLists[CB_ENUM_MAX_VALUE]; // Callbacks for each supported reason VpioTimedCbs m_timedCbs; // Time based callbacks VerilatedVpiError* m_errorInfop = nullptr; // Container for vpi error info VerilatedAssertOneThread m_assertOne; // Assert only called from single thread - vluint64_t m_nextCallbackId = 1; // Id to identify callback + uint64_t m_nextCallbackId = 1; // Id to identify callback static VerilatedVpiImp& s() { // Singleton static VerilatedVpiImp s_s; @@ -531,9 +531,9 @@ class VerilatedVpiImp final { public: static void assertOneCheck() { s().m_assertOne.check(); } - static vluint64_t nextCallbackId() { return ++s().m_nextCallbackId; } + static uint64_t nextCallbackId() { return ++s().m_nextCallbackId; } - static void cbReasonAdd(vluint64_t id, const s_cb_data* cb_data_p) { + static void cbReasonAdd(uint64_t id, const s_cb_data* cb_data_p) { // The passed cb_data_p was property of the user, so need to recreate if (VL_UNCOVERABLE(cb_data_p->reason >= CB_ENUM_MAX_VALUE)) { VL_FATAL_MT(__FILE__, __LINE__, "", "vpi bb reason too large"); @@ -544,7 +544,7 @@ public: if (cb_data_p->reason == cbValueChange) varop = VerilatedVpioVar::castp(cb_data_p->obj); s().m_cbObjLists[cb_data_p->reason].emplace_back(id, cb_data_p, varop); } - static void cbTimedAdd(vluint64_t id, const s_cb_data* cb_data_p, QData time) { + static void cbTimedAdd(uint64_t id, const s_cb_data* cb_data_p, QData time) { // The passed cb_data_p was property of the user, so need to recreate VL_DEBUG_IF_PLI(VL_DBG_MSGF("- vpi: vpi_register_cb reason=%d id=%" PRId64 " delay=%" PRIu64 "\n", @@ -553,7 +553,7 @@ public: std::forward_as_tuple(std::make_pair(time, id)), std::forward_as_tuple(id, cb_data_p, nullptr)); } - static void cbReasonRemove(vluint64_t id, vluint32_t reason) { + static void cbReasonRemove(uint64_t id, uint32_t reason) { // Id might no longer exist, if already removed due to call after event, or teardown VpioCbList& cbObjList = s().m_cbObjLists[reason]; // We do not remove it now as we may be iterating the list, @@ -562,7 +562,7 @@ public: if (ir.id() == id) ir.invalidate(); } } - static void cbTimedRemove(vluint64_t id, QData time) { + static void cbTimedRemove(uint64_t id, QData time) { // Id might no longer exist, if already removed due to call after event, or teardown const auto it = s().m_timedCbs.find(std::make_pair(time, id)); if (VL_LIKELY(it != s().m_timedCbs.end())) it->second.invalidate(); @@ -592,7 +592,7 @@ public: if (VL_LIKELY(it != s().m_timedCbs.cend())) return it->first.first; return ~0ULL; // maxquad } - static bool callCbs(const vluint32_t reason) VL_MT_UNSAFE_ONE { + static bool callCbs(const uint32_t reason) VL_MT_UNSAFE_ONE { VpioCbList& cbObjList = s().m_cbObjLists[reason]; bool called = false; if (cbObjList.empty()) return called; @@ -664,7 +664,7 @@ public: // Statics // Internal note: Globals may multi-construct, see verilated.cpp top. -VL_THREAD_LOCAL vluint8_t* VerilatedVpio::t_freeHead = nullptr; +VL_THREAD_LOCAL uint8_t* VerilatedVpio::t_freeHead = nullptr; //====================================================================== // VerilatedVpiError @@ -744,7 +744,7 @@ void VerilatedVpi::callTimedCbs() VL_MT_UNSAFE_ONE { VerilatedVpiImp::callTimedC bool VerilatedVpi::callValueCbs() VL_MT_UNSAFE_ONE { return VerilatedVpiImp::callValueCbs(); } -bool VerilatedVpi::callCbs(vluint32_t reason) VL_MT_UNSAFE_ONE { +bool VerilatedVpi::callCbs(uint32_t reason) VL_MT_UNSAFE_ONE { return VerilatedVpiImp::callCbs(reason); } @@ -1309,7 +1309,7 @@ vpiHandle vpi_register_cb(p_cb_data cb_data_p) { QData time = 0; if (cb_data_p->time) time = VL_SET_QII(cb_data_p->time->high, cb_data_p->time->low); const QData abstime = VL_TIME_Q() + time; - const vluint64_t id = VerilatedVpiImp::nextCallbackId(); + const uint64_t id = VerilatedVpiImp::nextCallbackId(); VerilatedVpioTimedCb* const vop = new VerilatedVpioTimedCb{id, abstime}; VerilatedVpiImp::cbTimedAdd(id, cb_data_p, abstime); return vop->castVpiHandle(); @@ -1324,7 +1324,7 @@ vpiHandle vpi_register_cb(p_cb_data cb_data_p) { case cbEnterInteractive: // FALLTHRU // NOP, but need to return handle, so make object case cbExitInteractive: // FALLTHRU // NOP, but need to return handle, so make object case cbInteractiveScopeChange: { // FALLTHRU // NOP, but need to return handle, so make object - const vluint64_t id = VerilatedVpiImp::nextCallbackId(); + const uint64_t id = VerilatedVpiImp::nextCallbackId(); VerilatedVpioReasonCb* const vop = new VerilatedVpioReasonCb{id, cb_data_p->reason}; VerilatedVpiImp::cbReasonAdd(id, cb_data_p); return vop->castVpiHandle(); @@ -1474,7 +1474,7 @@ vpiHandle vpi_handle(PLI_INT32 type, vpiHandle object) { case vpiIndex: { const VerilatedVpioVar* const vop = VerilatedVpioVar::castp(object); if (VL_UNLIKELY(!vop)) return nullptr; - const vlsint32_t val = vop->index(); + const int32_t val = vop->index(); return (new VerilatedVpioConst{val})->castVpiHandle(); } case vpiScope: { @@ -1996,7 +1996,7 @@ vpiHandle vpi_put_value(vpiHandle object, p_vpi_value valuep, p_vpi_time /*time_ for (int i = 0; i < chars; ++i) { union { char byte[2]; - vluint16_t half; + uint16_t half; } val; idx = div(i * 3, 8); if (i < len) { diff --git a/include/verilated_vpi.h b/include/verilated_vpi.h index 74bff7abf..93555cf6d 100644 --- a/include/verilated_vpi.h +++ b/include/verilated_vpi.h @@ -47,7 +47,7 @@ public: static bool callValueCbs() VL_MT_UNSAFE_ONE; /// Call callbacks of arbitrary types. /// User wrapper code should call this from their main loops. - static bool callCbs(const vluint32_t reason) VL_MT_UNSAFE_ONE; + static bool callCbs(const uint32_t reason) VL_MT_UNSAFE_ONE; /// Returns time of the next registered VPI callback, or /// ~(0ULL) if none are registered static QData cbNextDeadline() VL_MT_UNSAFE_ONE; diff --git a/include/verilatedos.h b/include/verilatedos.h index 5ba920312..797ffab99 100644 --- a/include/verilatedos.h +++ b/include/verilatedos.h @@ -282,6 +282,7 @@ void __gcov_flush(); // gcc sources gcc/gcov-io.h has the prototype #include #include +#ifndef VL_NO_LEGACY using vluint8_t = uint8_t; ///< 8-bit unsigned type (backward compatibility) using vluint16_t = uint16_t; ///< 16-bit unsigned type (backward compatibility) using vluint32_t = uint32_t; ///< 32-bit unsigned type (backward compatibility) @@ -290,6 +291,7 @@ using vlsint8_t = int8_t; ///< 8-bit signed type (backward compatibility) using vlsint16_t = int16_t; ///< 16-bit signed type (backward compatibility) using vlsint32_t = int32_t; ///< 32-bit signed type (backward compatibility) using vlsint64_t = int64_t; ///< 64-bit signed type (backward compatibility) +#endif #if defined(__CYGWIN__) @@ -320,12 +322,12 @@ using ssize_t = uint32_t; ///< signed size_t; returned from read() // Deprecated, favor C++11's PRIx64, etc, instead #ifndef VL_NO_LEGACY # ifdef _MSC_VER -# define VL_PRI64 "I64" ///< print a vluint64_t (backward compatibility) +# define VL_PRI64 "I64" ///< print a uint64_t (backward compatibility) # else // use standard C99 format specifiers # if defined(__WORDSIZE) && (__WORDSIZE == 64) -# define VL_PRI64 "l" ///< print a vluint64_t (backward compatibility) +# define VL_PRI64 "l" ///< print a uint64_t (backward compatibility) # else -# define VL_PRI64 "ll" ///< print a vluint64_t (backward compatibility) +# define VL_PRI64 "ll" ///< print a uint64_t (backward compatibility) # endif # endif #endif @@ -436,13 +438,13 @@ using ssize_t = uint32_t; ///< signed size_t; returned from read() // Performance counters #if defined(__i386__) || defined(__x86_64__) -// The vluint64_t argument is loaded with a high-performance counter for profiling +// The uint64_t argument is loaded with a high-performance counter for profiling // or 0x0 if not implemented on this platform #define VL_GET_CPU_TICK(val) \ { \ - vluint32_t hi, lo; \ + uint32_t hi, lo; \ asm volatile("rdtsc" : "=a"(lo), "=d"(hi)); \ - (val) = ((vluint64_t)lo) | (((vluint64_t)hi) << 32); \ + (val) = ((uint64_t)lo) | (((uint64_t)hi) << 32); \ } #elif defined(__aarch64__) // 1 GHz virtual system timer on SBSA level 5 compliant systems, else often 100 MHz diff --git a/src/V3Ast.cpp b/src/V3Ast.cpp index a711e9a27..5a18c98ee 100644 --- a/src/V3Ast.cpp +++ b/src/V3Ast.cpp @@ -30,8 +30,8 @@ //====================================================================== // Statics -vluint64_t AstNode::s_editCntLast = 0; -vluint64_t AstNode::s_editCntGbl = 0; // Hot cache line +uint64_t AstNode::s_editCntLast = 0; +uint64_t AstNode::s_editCntGbl = 0; // Hot cache line // To allow for fast clearing of all user pointers, we keep a "timestamp" // along with each userp, and thus by bumping this count we can make it look @@ -114,7 +114,7 @@ string AstNode::encodeName(const string& namein) { return vname.hashedName(); } -string AstNode::encodeNumber(vlsint64_t num) { +string AstNode::encodeNumber(int64_t num) { if (num < 0) { return "__02D" + cvtToStr(-num); // 2D=- } else { diff --git a/src/V3Ast.h b/src/V3Ast.h index 5667b5db2..902bb37ae 100644 --- a/src/V3Ast.h +++ b/src/V3Ast.h @@ -83,7 +83,7 @@ using MTaskIdSet = std::set; // Set of mtaskIds for Var sorting #define VN_AS(nodep, nodetypename) (AstNode::privateAs(nodep)) // (V)erilator (N)ode deleted: Pointer to deleted AstNode (for assertions only) -#define VN_DELETED(nodep) VL_UNLIKELY((vluint64_t)(nodep) == 0x1) +#define VN_DELETED(nodep) VL_UNLIKELY((uint64_t)(nodep) == 0x1) //###################################################################### @@ -1398,10 +1398,10 @@ class AstNode VL_NOT_FINAL { AstNodeDType* m_dtypep = nullptr; // Data type of output or assignment (etc) AstNode* m_headtailp; // When at begin/end of list, the opposite end of the list FileLine* m_fileline; // Where it was declared - vluint64_t m_editCount; // When it was last edited - static vluint64_t s_editCntGbl; // Global edit counter + uint64_t m_editCount; // When it was last edited + static uint64_t s_editCntGbl; // Global edit counter // Global edit counter, last value for printing * near node #s - static vluint64_t s_editCntLast; + static uint64_t s_editCntLast; AstNode* m_clonep = nullptr; // Pointer to clone of/ source of this module (for *LAST* cloneTree() ONLY) @@ -1559,7 +1559,7 @@ public: } static string encodeName(const string& namein); // Encode user name into internal C representation - static string encodeNumber(vlsint64_t num); // Encode number into internal C representation + static string encodeNumber(int64_t num); // Encode number into internal C representation static string vcdName(const string& namein); // Name for printing out to vcd files string prettyName() const { return prettyName(name()); } string prettyNameQ() const { return prettyNameQ(name()); } @@ -1666,12 +1666,12 @@ public: static void user5ClearTree() { VNUser5InUse::clear(); } // Clear userp()'s across the entire tree // clang-format on - vluint64_t editCount() const { return m_editCount; } + uint64_t editCount() const { return m_editCount; } void editCountInc() { m_editCount = ++s_editCntGbl; // Preincrement, so can "watch AstNode::s_editCntGbl=##" } - static vluint64_t editCountLast() { return s_editCntLast; } - static vluint64_t editCountGbl() { return s_editCntGbl; } + static uint64_t editCountLast() { return s_editCntLast; } + static uint64_t editCountGbl() { return s_editCntGbl; } static void editCountSetLast() { s_editCntLast = editCountGbl(); } // ACCESSORS for specific types diff --git a/src/V3AstNodes.cpp b/src/V3AstNodes.cpp index 4b90ed159..14b15428a 100644 --- a/src/V3AstNodes.cpp +++ b/src/V3AstNodes.cpp @@ -463,7 +463,7 @@ string AstVar::cPubArgType(bool named, bool forReturn) const { } else if (widthMin() <= VL_IDATASIZE) { arg += "uint32_t"; } else if (widthMin() <= VL_QUADSIZE) { - arg += "vluint64_t"; + arg += "uint64_t"; } else { arg += "uint32_t"; // []'s added later } @@ -600,7 +600,7 @@ string AstVar::scType() const { return "uint32_t"; } } else { - return "vluint64_t"; + return "uint64_t"; } } @@ -1071,8 +1071,8 @@ static bool sameInit(const AstInitArray* ap, const AstInitArray* bp) { if (!aDTypep->rangep()->sameTree(bDTypep->rangep())) return false; // Compare initializer arrays by value. Note this is only called when they hash the same, // so they likely run at most once per call to 'AstConstPool::findTable'. - const vluint64_t size = aDTypep->elementsConst(); - for (vluint64_t n = 0; n < size; ++n) { + const uint64_t size = aDTypep->elementsConst(); + for (uint64_t n = 0; n < size; ++n) { const AstNode* const valAp = ap->getIndexDefaultedValuep(n); const AstNode* const valBp = bp->getIndexDefaultedValuep(n); if (!valAp->sameTree(valBp)) return false; diff --git a/src/V3AstNodes.h b/src/V3AstNodes.h index 984fcb112..49cb900d8 100644 --- a/src/V3AstNodes.h +++ b/src/V3AstNodes.h @@ -115,14 +115,14 @@ public: dtypeSetLogicUnsized(32, m_num.widthMin(), VSigning::SIGNED); } class Unsized64 {}; // for creator type-overload selection - AstConst(FileLine* fl, Unsized64, vluint64_t num) + AstConst(FileLine* fl, Unsized64, uint64_t num) : ASTGEN_SUPER_Const(fl) , m_num(this, 64, 0) { m_num.setQuad(num); dtypeSetLogicSized(64, VSigning::UNSIGNED); } class SizedEData {}; // for creator type-overload selection - AstConst(FileLine* fl, SizedEData, vluint64_t num) + AstConst(FileLine* fl, SizedEData, uint64_t num) : ASTGEN_SUPER_Const(fl) , m_num(this, VL_EDATASIZE, 0) { m_num.setQuad(num); @@ -166,8 +166,8 @@ public: const V3Number& num() const { return m_num; } // * = Value V3Number& num() { return m_num; } // * = Value uint32_t toUInt() const { return num().toUInt(); } - vlsint32_t toSInt() const { return num().toSInt(); } - vluint64_t toUQuad() const { return num().toUQuad(); } + int32_t toSInt() const { return num().toSInt(); } + uint64_t toUQuad() const { return num().toUQuad(); } virtual string emitVerilog() override { V3ERROR_NA_RETURN(""); } virtual string emitC() override { V3ERROR_NA_RETURN(""); } virtual bool cleanOut() const override { return true; } @@ -5019,7 +5019,7 @@ class AstInitArray final : public AstNode { // Parents: ASTVAR::init() // Children: AstInitItem public: - using KeyItemMap = std::map; + using KeyItemMap = std::map; private: KeyItemMap m_map; // Node value for each array index @@ -5054,7 +5054,7 @@ public: AstNode* initsp() const { return op2p(); } // op2 = Initial value expressions void addValuep(AstNode* newp) { addIndexValuep(m_map.size(), newp); } const KeyItemMap& map() const { return m_map; } - AstNode* addIndexValuep(vluint64_t index, AstNode* newp) { + AstNode* addIndexValuep(uint64_t index, AstNode* newp) { // Returns old value, caller must garbage collect AstNode* oldp = nullptr; const auto it = m_map.find(index); @@ -5068,7 +5068,7 @@ public: } return oldp; } - AstNode* getIndexValuep(vluint64_t index) const { + AstNode* getIndexValuep(uint64_t index) const { const auto it = m_map.find(index); if (it == m_map.end()) { return nullptr; @@ -5076,7 +5076,7 @@ public: return it->second->valuep(); } } - AstNode* getIndexDefaultedValuep(vluint64_t index) const { + AstNode* getIndexDefaultedValuep(uint64_t index) const { AstNode* valuep = getIndexValuep(index); if (!valuep) valuep = defaultp(); return valuep; diff --git a/src/V3Config.cpp b/src/V3Config.cpp index 166297344..b8128eaa9 100644 --- a/src/V3Config.cpp +++ b/src/V3Config.cpp @@ -350,7 +350,7 @@ using V3ConfigFileResolver = V3ConfigWildcardResolver; class V3ConfigResolver final { V3ConfigModuleResolver m_modules; // Access to module names (with wildcards) V3ConfigFileResolver m_files; // Access to file names (with wildcards) - std::unordered_map> + std::unordered_map> m_profileData; // Access to profile_data records FileLine* m_profileFileLine = nullptr; @@ -364,12 +364,12 @@ public: V3ConfigModuleResolver& modules() { return m_modules; } V3ConfigFileResolver& files() { return m_files; } - void addProfileData(FileLine* fl, const string& model, const string& key, vluint64_t cost) { + void addProfileData(FileLine* fl, const string& model, const string& key, uint64_t cost) { if (!m_profileFileLine) m_profileFileLine = fl; if (cost == 0) cost = 1; // Cost 0 means delete (or no data) m_profileData[model][key] += cost; } - vluint64_t getProfileData(const string& model, const string& key) const { + uint64_t getProfileData(const string& model, const string& key) const { const auto mit = m_profileData.find(model); if (mit == m_profileData.cend()) return 0; const auto it = mit->second.find(key); @@ -430,7 +430,7 @@ void V3Config::addModulePragma(const string& module, VPragmaType pragma) { } void V3Config::addProfileData(FileLine* fl, const string& model, const string& key, - vluint64_t cost) { + uint64_t cost) { V3ConfigResolver::s().addProfileData(fl, model, key, cost); } @@ -534,7 +534,7 @@ void V3Config::applyVarAttr(AstNodeModule* modulep, AstNodeFTask* ftaskp, AstVar if (vp) vp->apply(varp); } -vluint64_t V3Config::getProfileData(const string& model, const string& key) { +uint64_t V3Config::getProfileData(const string& model, const string& key) { return V3ConfigResolver::s().getProfileData(model, key); } FileLine* V3Config::getProfileDataFileLine() { diff --git a/src/V3Config.h b/src/V3Config.h index c966074f1..750d152fd 100644 --- a/src/V3Config.h +++ b/src/V3Config.h @@ -36,7 +36,7 @@ public: static void addInline(FileLine* fl, const string& module, const string& ftask, bool on); static void addModulePragma(const string& module, VPragmaType pragma); static void addProfileData(FileLine* fl, const string& model, const string& key, - vluint64_t cost); + uint64_t cost); static void addWaiver(V3ErrorCode code, const string& filename, const string& message); static void addVarAttr(FileLine* fl, const string& module, const string& ftask, const string& signal, VAttrType type, AstSenTree* nodep); @@ -48,7 +48,7 @@ public: static void applyFTask(AstNodeModule* modulep, AstNodeFTask* ftaskp); static void applyVarAttr(AstNodeModule* modulep, AstNodeFTask* ftaskp, AstVar* varp); - static vluint64_t getProfileData(const string& model, const string& key); + static uint64_t getProfileData(const string& model, const string& key); static FileLine* getProfileDataFileLine(); static bool waive(FileLine* filelinep, V3ErrorCode code, const string& message); }; diff --git a/src/V3EmitCConstInit.h b/src/V3EmitCConstInit.h index 2728fd629..6c02bf099 100644 --- a/src/V3EmitCConstInit.h +++ b/src/V3EmitCConstInit.h @@ -73,7 +73,7 @@ protected: ofp()->putsNoTracking("}"); } else if (const AstUnpackArrayDType* const dtypep = VN_CAST(nodep->dtypep()->skipRefp(), UnpackArrayDType)) { - const vluint64_t size = dtypep->elementsConst(); + const uint64_t size = dtypep->elementsConst(); const uint32_t tabMod = tabModulus(dtypep->subDTypep()); // Note the double {{ initializer. The first { starts the initializer of the // VlUnpacked, and the second starts the initializer of m_storage within the @@ -81,7 +81,7 @@ protected: puts("{"); ofp()->putsNoTracking("{"); puts("\n"); - for (vluint64_t n = 0; n < size; ++n) { + for (uint64_t n = 0; n < size; ++n) { m_unpackedWord = n; if (n) puts((n % tabMod) ? ", " : ",\n"); iterate(nodep->getIndexDefaultedValuep(n)); diff --git a/src/V3EmitCFunc.cpp b/src/V3EmitCFunc.cpp index 5c3808332..786b8368c 100644 --- a/src/V3EmitCFunc.cpp +++ b/src/V3EmitCFunc.cpp @@ -543,7 +543,7 @@ void EmitCFunc::emitConstant(AstConst* nodep, AstVarRef* assigntop, const string } for (int word = VL_WORDS_I(upWidth) - 1; word >= 0; word--) { // Only 32 bits - llx + long long here just to appease CPP format warning - ofp()->printf(",0x%08" PRIx64, static_cast(nodep->num().edataWord( + ofp()->printf(",0x%08" PRIx64, static_cast(nodep->num().edataWord( word + chunks * EMITC_NUM_CONSTW))); } puts(")"); @@ -565,7 +565,7 @@ void EmitCFunc::emitConstant(AstConst* nodep, AstVarRef* assigntop, const string } for (int word = EMITC_NUM_CONSTW - 1; word >= 0; word--) { // Only 32 bits - llx + long long here just to appease CPP format warning - ofp()->printf(",0x%08" PRIx64, static_cast(nodep->num().edataWord( + ofp()->printf(",0x%08" PRIx64, static_cast(nodep->num().edataWord( word + chunks * EMITC_NUM_CONSTW))); } puts(")"); @@ -580,7 +580,7 @@ void EmitCFunc::emitConstant(AstConst* nodep, AstVarRef* assigntop, const string ofp()->printf("%.17e", nodep->num().toDouble()); } } else if (nodep->isQuad()) { - const vluint64_t num = nodep->toUQuad(); + const uint64_t num = nodep->toUQuad(); if (num < 10) { ofp()->printf("%" PRIu64 "ULL", num); } else { @@ -592,7 +592,7 @@ void EmitCFunc::emitConstant(AstConst* nodep, AstVarRef* assigntop, const string if (num < 10) { puts(cvtToStr(num)); } else { - ofp()->printf("0x%" PRIx64, static_cast(num)); + ofp()->printf("0x%" PRIx64, static_cast(num)); } // If signed, we'll do our own functions // But must be here, or <= comparisons etc may end up signed diff --git a/src/V3EmitCImp.cpp b/src/V3EmitCImp.cpp index 116b2582b..f5da29d61 100644 --- a/src/V3EmitCImp.cpp +++ b/src/V3EmitCImp.cpp @@ -350,8 +350,8 @@ class EmitCImp final : EmitCFunc { hash.insert(varp->dtypep()->width()); } } - ofp()->printf("vluint64_t __Vcheckval = 0x%" PRIx64 "ULL;\n", - static_cast(hash.digestUInt64())); + ofp()->printf("uint64_t __Vcheckval = 0x%" PRIx64 "ULL;\n", + static_cast(hash.digestUInt64())); if (de) { puts("os.readAssert(__Vcheckval);\n"); } else { @@ -783,7 +783,7 @@ class EmitCTrace final : EmitCFunc { AstVar* const varp = varrefp->varp(); puts("("); if (emitTraceIsScBigUint(nodep)) { - puts("(vluint32_t*)"); + puts("(uint32_t*)"); } else if (emitTraceIsScBv(nodep)) { puts("VL_SC_BV_DATAP("); } diff --git a/src/V3EmitCSyms.cpp b/src/V3EmitCSyms.cpp index 07626fbed..131d3a304 100644 --- a/src/V3EmitCSyms.cpp +++ b/src/V3EmitCSyms.cpp @@ -476,7 +476,7 @@ void EmitCSyms::emitSymHdr() { if (v3Global.opt.profPgo()) { puts("\n// PGO PROFILING\n"); - vluint64_t maxProfilerId = 0; + uint64_t maxProfilerId = 0; if (v3Global.opt.mtasks()) { for (const V3GraphVertex* vxp = v3Global.rootp()->execGraphp()->depGraphp()->verticesBeginp(); diff --git a/src/V3GraphPathChecker.cpp b/src/V3GraphPathChecker.cpp index 135e1562d..a88ab6221 100644 --- a/src/V3GraphPathChecker.cpp +++ b/src/V3GraphPathChecker.cpp @@ -32,13 +32,13 @@ struct GraphPCNode { // // Unlike the LogicMTasks's, we have no cost info for the generic graph // accepted by GraphPathChecker, so assume each node has unit cost. - std::array m_cp; + std::array m_cp; // Detect if we've seen this node before in a given recursive // operation. We'll use this in pathExistsInternal() to avoid checking // the same node twice, and again in updateHalfCriticalPath() to assert // there are no cycles. - vluint64_t m_seenAtGeneration = 0; + uint64_t m_seenAtGeneration = 0; // CONSTRUCTORS GraphPCNode() { diff --git a/src/V3GraphPathChecker.h b/src/V3GraphPathChecker.h index 99414e679..06be17d4f 100644 --- a/src/V3GraphPathChecker.h +++ b/src/V3GraphPathChecker.h @@ -34,7 +34,7 @@ class GraphPathChecker final : GraphAlg { // the graph. Each node is marked with the last generation that scanned // it, to enable asserting there are no cycles, and to avoid recursing // through the same node twice while searching for a path. - vluint64_t m_generation = 0; + uint64_t m_generation = 0; public: // CONSTRUCTORS diff --git a/src/V3Life.cpp b/src/V3Life.cpp index da104adaf..691e490b9 100644 --- a/src/V3Life.cpp +++ b/src/V3Life.cpp @@ -302,7 +302,7 @@ private: virtual void visit(AstNodeAssign* nodep) override { // Collect any used variables first, as lhs may also be on rhs // Similar code in V3Dead - const vluint64_t lastEdit = AstNode::editCountGbl(); // When it was last edited + const uint64_t lastEdit = AstNode::editCountGbl(); // When it was last edited m_sideEffect = false; iterateAndNextNull(nodep->rhsp()); if (lastEdit != AstNode::editCountGbl()) { diff --git a/src/V3List.h b/src/V3List.h index c5cb321cb..7871cd282 100644 --- a/src/V3List.h +++ b/src/V3List.h @@ -61,7 +61,7 @@ private: // "this" must be a element inside of *basep // Use that to determine a structure offset, then apply to the new base // to get our new pointer information - return (V3ListEnt*)(((vluint8_t*)newbasep) + offset); + return (V3ListEnt*)(((uint8_t*)newbasep) + offset); } public: @@ -78,7 +78,7 @@ public: void pushBack(V3List& listr, T newp) { // "this" must be a element inside of *newp // cppcheck-suppress thisSubtraction - const size_t offset = (size_t)(vluint8_t*)(this) - (size_t)(vluint8_t*)(newp); + const size_t offset = (size_t)(uint8_t*)(this) - (size_t)(uint8_t*)(newp); m_nextp = nullptr; if (!listr.m_headp) listr.m_headp = newp; m_prevp = listr.m_tailp; @@ -88,7 +88,7 @@ public: void pushFront(V3List& listr, T newp) { // "this" must be a element inside of *newp // cppcheck-suppress thisSubtraction - const size_t offset = (size_t)(vluint8_t*)(this) - (size_t)(vluint8_t*)(newp); + const size_t offset = (size_t)(uint8_t*)(this) - (size_t)(uint8_t*)(newp); m_nextp = listr.m_headp; if (m_nextp) baseToListEnt(m_nextp, offset)->m_prevp = newp; listr.m_headp = newp; @@ -99,7 +99,7 @@ public: void unlink(V3List& listr, T oldp) { // "this" must be a element inside of *oldp // cppcheck-suppress thisSubtraction - const size_t offset = (size_t)(vluint8_t*)(this) - (size_t)(vluint8_t*)(oldp); + const size_t offset = (size_t)(uint8_t*)(this) - (size_t)(uint8_t*)(oldp); if (m_nextp) { baseToListEnt(m_nextp, offset)->m_prevp = m_prevp; } else { diff --git a/src/V3Number.cpp b/src/V3Number.cpp index 5c7493d69..df4622a95 100644 --- a/src/V3Number.cpp +++ b/src/V3Number.cpp @@ -375,7 +375,7 @@ V3Number& V3Number::setZero() { for (int i = 0; i < words(); i++) m_value[i] = {0, 0}; return *this; } -V3Number& V3Number::setQuad(vluint64_t value) { +V3Number& V3Number::setQuad(uint64_t value) { for (int i = 0; i < words(); i++) m_value[i] = {0, 0}; m_value[0].m_value = value & 0xffffffffULL; if (width() > 32) m_value[1].m_value = (value >> 32ULL) & 0xffffffffULL; @@ -388,11 +388,11 @@ V3Number& V3Number::setLong(uint32_t value) { opCleanThis(); return *this; } -V3Number& V3Number::setLongS(vlsint32_t value) { +V3Number& V3Number::setLongS(int32_t value) { for (int i = 0; i < words(); i++) m_value[i] = {0, 0}; union { uint32_t u; - vlsint32_t s; + int32_t s; } u; u.s = value; if (u.s) {} @@ -878,40 +878,40 @@ double V3Number::toDouble() const { return u.d; } -vlsint32_t V3Number::toSInt() const { +int32_t V3Number::toSInt() const { if (isSigned()) { const uint32_t v = toUInt(); const uint32_t signExtend = (-(v & (1UL << (width() - 1)))); const uint32_t extended = v | signExtend; - return static_cast(extended); + return static_cast(extended); } else { // Where we use this (widths, etc) and care about signedness, // we can reasonably assume the MSB isn't set on unsigned numbers. - return static_cast(toUInt()); + return static_cast(toUInt()); } } -vluint64_t V3Number::toUQuad() const { +uint64_t V3Number::toUQuad() const { UASSERT(!isFourState(), "toUQuad with 4-state " << *this); // We allow wide numbers that represent values <= 64 bits - if (isDouble()) return static_cast(toDouble()); + if (isDouble()) return static_cast(toDouble()); for (int i = 2; i < words(); ++i) { if (m_value[i].m_value) { v3error("Value too wide for 64-bits expected in this context " << *this); break; } } - if (width() <= 32) return (static_cast(toUInt())); - return ((static_cast(m_value[1].m_value) << 32ULL) - | (static_cast(m_value[0].m_value))); + if (width() <= 32) return (static_cast(toUInt())); + return ((static_cast(m_value[1].m_value) << 32ULL) + | (static_cast(m_value[0].m_value))); } -vlsint64_t V3Number::toSQuad() const { - if (isDouble()) return static_cast(toDouble()); - const vluint64_t v = toUQuad(); - const vluint64_t signExtend = (-(v & (1ULL << (width() - 1)))); - const vluint64_t extended = v | signExtend; - return static_cast(extended); +int64_t V3Number::toSQuad() const { + if (isDouble()) return static_cast(toDouble()); + const uint64_t v = toUQuad(); + const uint64_t signExtend = (-(v & (1ULL << (width() - 1)))); + const uint64_t extended = v | signExtend; + return static_cast(extended); } string V3Number::toString() const { @@ -1499,15 +1499,15 @@ V3Number& V3Number::opAtoN(const V3Number& lhs, int base) { errno = 0; auto v = std::strtol(str.c_str(), nullptr, base); if (errno != 0) v = 0; - return setLongS(static_cast(v)); + return setLongS(static_cast(v)); } V3Number& V3Number::opPutcN(const V3Number& lhs, const V3Number& rhs, const V3Number& ths) { NUM_ASSERT_OP_ARGS3(lhs, rhs, ths); NUM_ASSERT_STRING_ARGS1(lhs); string lstring = lhs.toString(); - const vlsint32_t i = rhs.toSInt(); - const vlsint32_t c = ths.toSInt() & 0xFF; + const int32_t i = rhs.toSInt(); + const int32_t c = ths.toSInt() & 0xFF; // 6.16.2:str.putc(i, c) does not change the value when i < 0 || i >= str.len() || c == 0 // when evaluating the second condition, i must be positive. if (0 <= i && static_cast(i) < lstring.length() && c != 0) lstring[i] = c; @@ -1518,8 +1518,8 @@ V3Number& V3Number::opGetcN(const V3Number& lhs, const V3Number& rhs) { NUM_ASSERT_OP_ARGS2(lhs, rhs); NUM_ASSERT_STRING_ARGS1(lhs); const string lstring = lhs.toString(); - const vlsint32_t i = rhs.toSInt(); - vlsint32_t v = 0; + const int32_t i = rhs.toSInt(); + int32_t v = 0; // 6.16.3:str.getc(i) returns 0 if i < 0 || i >= str.len() // when evaluating the second condition, i must be positive. if (0 <= i && static_cast(i) < lstring.length()) v = lstring[i]; @@ -1530,8 +1530,8 @@ V3Number& V3Number::opSubstrN(const V3Number& lhs, const V3Number& rhs, const V3 NUM_ASSERT_OP_ARGS3(lhs, rhs, ths); NUM_ASSERT_STRING_ARGS1(lhs); const string lstring = lhs.toString(); - const vlsint32_t i = rhs.toSInt(); - const vlsint32_t j = ths.toSInt(); + const int32_t i = rhs.toSInt(); + const int32_t j = ths.toSInt(); // 6.16.8:str.substr(i, j) returns an empty string when i < 0 || j < i || j >= str.len() // when evaluating the third condition, j must be positive because 0 <= i <= j is guaranteed by // the former two conditions. @@ -1837,14 +1837,14 @@ V3Number& V3Number::opMul(const V3Number& lhs, const V3Number& rhs) { opCleanThis(); // Mult produces extra bits in result } else { for (int lword = 0; lword < lhs.words(); lword++) { - const vluint64_t lwordval = static_cast(lhs.m_value[lword].m_value); + const uint64_t lwordval = static_cast(lhs.m_value[lword].m_value); if (lwordval == 0) continue; for (int rword = 0; rword < rhs.words(); rword++) { - const vluint64_t rwordval = static_cast(rhs.m_value[rword].m_value); + const uint64_t rwordval = static_cast(rhs.m_value[rword].m_value); if (rwordval == 0) continue; - vluint64_t mul = lwordval * rwordval; + uint64_t mul = lwordval * rwordval; for (int qword = lword + rword; qword < this->words(); qword++) { - mul += static_cast(m_value[qword].m_value); + mul += static_cast(m_value[qword].m_value); m_value[qword].m_value = (mul & 0xffffffffULL); mul = (mul >> 32ULL) & 0xffffffffULL; if (mul == 0) break; @@ -1960,14 +1960,13 @@ V3Number& V3Number::opModDivGuts(const V3Number& lhs, const V3Number& rhs, bool const int vw = (vmsbp1 + 31) / 32; // aka "n" in the algorithm if (vw == 1) { // Single divisor word breaks rest of algorithm - vluint64_t k = 0; + uint64_t k = 0; for (int j = uw - 1; j >= 0; j--) { - const vluint64_t unw64 - = ((k << 32ULL) + static_cast(lhs.m_value[j].m_value)); - m_value[j].m_value = unw64 / static_cast(rhs.m_value[0].m_value); + const uint64_t unw64 = ((k << 32ULL) + static_cast(lhs.m_value[j].m_value)); + m_value[j].m_value = unw64 / static_cast(rhs.m_value[0].m_value); k = unw64 - - (static_cast(m_value[j].m_value) - * static_cast(rhs.m_value[0].m_value)); + - (static_cast(m_value[j].m_value) + * static_cast(rhs.m_value[0].m_value)); } UINFO(9, " opmoddiv-1w " << lhs << " " << rhs << " q=" << *this << " rem=0x" << std::hex << k << std::dec << endl); @@ -2016,10 +2015,10 @@ V3Number& V3Number::opModDivGuts(const V3Number& lhs, const V3Number& rhs, bool // Main loop for (int j = uw - vw; j >= 0; j--) { // Estimate - const vluint64_t unw64 = (static_cast(un[j + vw]) << 32ULL - | static_cast(un[j + vw - 1])); - vluint64_t qhat = unw64 / static_cast(vn[vw - 1]); - vluint64_t rhat = unw64 - qhat * static_cast(vn[vw - 1]); + const uint64_t unw64 + = (static_cast(un[j + vw]) << 32ULL | static_cast(un[j + vw - 1])); + uint64_t qhat = unw64 / static_cast(vn[vw - 1]); + uint64_t rhat = unw64 - qhat * static_cast(vn[vw - 1]); again: if (qhat >= 0x100000000ULL || ((qhat * vn[vw - 2]) > ((rhat << 32ULL) + un[j + vw - 2]))) { @@ -2028,10 +2027,10 @@ V3Number& V3Number::opModDivGuts(const V3Number& lhs, const V3Number& rhs, bool if (rhat < 0x100000000ULL) goto again; } - vlsint64_t t = 0; // Must be signed - vluint64_t k = 0; + int64_t t = 0; // Must be signed + uint64_t k = 0; for (int i = 0; i < vw; i++) { - const vluint64_t p = qhat * vn[i]; // Multiply by estimate + const uint64_t p = qhat * vn[i]; // Multiply by estimate t = un[i + j] - k - (p & 0xFFFFFFFFULL); // Subtract un[i + j] = t; k = (p >> 32ULL) - (t >> 32ULL); @@ -2045,7 +2044,7 @@ V3Number& V3Number::opModDivGuts(const V3Number& lhs, const V3Number& rhs, bool this->m_value[j].m_value--; k = 0; for (int i = 0; i < vw; i++) { - t = static_cast(un[i + j]) + static_cast(vn[i]) + k; + t = static_cast(un[i + j]) + static_cast(vn[i]) + k; un[i + j] = t; k = t >> 32ULL; } @@ -2265,7 +2264,7 @@ V3Number& V3Number::opRToIS(const V3Number& lhs) { NUM_ASSERT_OP_ARGS1(lhs); NUM_ASSERT_DOUBLE_ARGS1(lhs); const double v = VL_TRUNC(lhs.toDouble()); - const vlsint32_t i = static_cast(v); // C converts from double to vlsint32 + const int32_t i = static_cast(v); // C converts from double to int32_t return setLongS(i); } V3Number& V3Number::opRToIRoundS(const V3Number& lhs) { @@ -2275,14 +2274,14 @@ V3Number& V3Number::opRToIRoundS(const V3Number& lhs) { setZero(); union { double d; - vluint64_t q; + uint64_t q; } u; u.d = v; if (u.d == 0.0) {} const int exp = static_cast((u.q >> 52ULL) & VL_MASK_Q(11)) - 1023; const int lsb = exp - 52; - const vluint64_t mantissa = (u.q & VL_MASK_Q(52)) | (1ULL << 52); + const uint64_t mantissa = (u.q & VL_MASK_Q(52)) | (1ULL << 52); if (v != 0) { // IEEE format: [63]=sign [62:52]=exp+1023 [51:0]=mantissa // This does not need to support subnormals as they are sub-integral diff --git a/src/V3Number.h b/src/V3Number.h index 67cdab14e..a574bb191 100644 --- a/src/V3Number.h +++ b/src/V3Number.h @@ -111,9 +111,9 @@ public: void nodep(AstNode* nodep) { setNames(nodep); } FileLine* fileline() const { return m_fileline; } V3Number& setZero(); - V3Number& setQuad(vluint64_t value); + V3Number& setQuad(uint64_t value); V3Number& setLong(uint32_t value); - V3Number& setLongS(vlsint32_t value); + V3Number& setLongS(int32_t value); V3Number& setDouble(double value); void setBit(int bit, char value) { // Note must be pre-zeroed! if (bit >= m_width) return; @@ -339,9 +339,9 @@ public: bool isAnyZ() const; bool isMsbXZ() const { return bitIsXZ(m_width); } uint32_t toUInt() const; - vlsint32_t toSInt() const; - vluint64_t toUQuad() const; - vlsint64_t toSQuad() const; + int32_t toSInt() const; + uint64_t toUQuad() const; + int64_t toSQuad() const; string toString() const; string toDecimalS() const; // return ASCII signed decimal number string toDecimalU() const; // return ASCII unsigned decimal number diff --git a/src/V3Order.cpp b/src/V3Order.cpp index 433082e68..529680624 100644 --- a/src/V3Order.cpp +++ b/src/V3Order.cpp @@ -1025,8 +1025,8 @@ public: virtual bool operator()(const V3GraphVertex* lhsp, const V3GraphVertex* rhsp) const { const MTaskMoveVertex* const l_vxp = dynamic_cast(lhsp); const MTaskMoveVertex* const r_vxp = dynamic_cast(rhsp); - vluint64_t l_id = m_ids.findId(l_vxp->domainp()); - vluint64_t r_id = m_ids.findId(r_vxp->domainp()); + uint64_t l_id = m_ids.findId(l_vxp->domainp()); + uint64_t r_id = m_ids.findId(r_vxp->domainp()); if (l_id < r_id) return true; if (l_id > r_id) return false; l_id = m_ids.findId(l_vxp->scopep()); diff --git a/src/V3Os.cpp b/src/V3Os.cpp index 33d8e2a5b..c88ff65ae 100644 --- a/src/V3Os.cpp +++ b/src/V3Os.cpp @@ -254,9 +254,9 @@ void V3Os::unlinkRegexp(const string& dir, const string& regexp) { //###################################################################### // METHODS (random) -vluint64_t V3Os::rand64(std::array& stater) { +uint64_t V3Os::rand64(std::array& stater) { // Xoroshiro128+ algorithm - const vluint64_t result = stater[0] + stater[1]; + const uint64_t result = stater[0] + stater[1]; stater[1] ^= stater[0]; stater[0] = (((stater[0] << 55) | (stater[0] >> 9)) ^ stater[1] ^ (stater[1] << 14)); stater[1] = (stater[1] << 36) | (stater[1] >> 28); @@ -319,7 +319,7 @@ uint64_t V3Os::memUsageBytes() { const char* const statmFilename = "/proc/self/statm"; FILE* fp = fopen(statmFilename, "r"); if (!fp) return 0; - vluint64_t size, resident, share, text, lib, data, dt; // All in pages + uint64_t size, resident, share, text, lib, data, dt; // All in pages const int items = fscanf( fp, "%" SCNu64 " %" SCNu64 " %" SCNu64 " %" SCNu64 " %" SCNu64 " %" SCNu64 " %" SCNu64, &size, &resident, &share, &text, &lib, &data, &dt); diff --git a/src/V3Os.h b/src/V3Os.h index b1143587d..7daf580e6 100644 --- a/src/V3Os.h +++ b/src/V3Os.h @@ -57,7 +57,7 @@ public: static void unlinkRegexp(const string& dir, const string& regexp); // METHODS (random) - static vluint64_t rand64(std::array& stater); + static uint64_t rand64(std::array& stater); static string trueRandom(size_t size); // METHODS (time & performance) diff --git a/src/V3Partition.cpp b/src/V3Partition.cpp index 63e264809..4c16c0aa3 100644 --- a/src/V3Partition.cpp +++ b/src/V3Partition.cpp @@ -307,7 +307,7 @@ private: } void go() { // Generate a pseudo-random graph - std::array rngState + std::array rngState = {{0x12345678ULL, 0x9abcdef0ULL}}; // GCC 3.8.0 wants {{}} // Create 50 vertices for (auto& i : m_vx) i = new V3GraphVertex(&m_graph); @@ -435,7 +435,7 @@ private: // graph. We'll mark each node with the last generation that scanned // it. We can use this to avoid recursing through the same node twice // while searching for a path. - vluint64_t m_generation = 0; + uint64_t m_generation = 0; // Redundant with the V3GraphEdge's, store a map of relatives so we can // quickly check if we have a given parent or child. @@ -471,8 +471,8 @@ public: m_cost += otherp->m_cost; } virtual const VxList* vertexListp() const override { return &m_vertices; } - static vluint64_t incGeneration() { - static vluint64_t s_generation = 0; + static uint64_t incGeneration() { + static uint64_t s_generation = 0; ++s_generation; return s_generation; } @@ -569,7 +569,7 @@ public: private: static bool pathExistsFromInternal(LogicMTask* fromp, LogicMTask* top, - const V3GraphEdge* excludedEdgep, vluint64_t generation) { + const V3GraphEdge* excludedEdgep, uint64_t generation) { // Q) Why does this take LogicMTask instead of generic V3GraphVertex? // A) We'll use the critical paths known to LogicMTask to prune the // recursion for speed. Also store 'generation' in @@ -718,16 +718,16 @@ private: // using another bit of the id to denote the actual subtype. // By using the bottom bits for flags, we can still use < to compare IDs without masking. - vluint64_t m_id; // <63:2> Serial number for ordering, <1> subtype (SiblingMC), <0> removed - static constexpr vluint64_t REMOVED_MASK = 1ULL << 0; - static constexpr vluint64_t IS_SIBLING_MASK = 1ULL << 1; - static constexpr vluint64_t ID_INCREMENT = 1ULL << 2; + uint64_t m_id; // <63:2> Serial number for ordering, <1> subtype (SiblingMC), <0> removed + static constexpr uint64_t REMOVED_MASK = 1ULL << 0; + static constexpr uint64_t IS_SIBLING_MASK = 1ULL << 1; + static constexpr uint64_t ID_INCREMENT = 1ULL << 2; bool isSiblingMC() const { return m_id & IS_SIBLING_MASK; } // CONSTRUCTORS explicit MergeCandidate(bool isSiblingMC) { - static vluint64_t serial = 0; + static uint64_t serial = 0; serial += ID_INCREMENT; // +ID_INCREMENT so doesn't set the special bottom bits m_id = serial | (isSiblingMC * IS_SIBLING_MASK); } @@ -746,7 +746,7 @@ public: bool operator<(const MergeCandidate& other) const { return m_id < other.m_id; } }; -static_assert(sizeof(MergeCandidate) == sizeof(vluint64_t), "Should not have a vtable"); +static_assert(sizeof(MergeCandidate) == sizeof(uint64_t), "Should not have a vtable"); // A pair of associated LogicMTask's that are merge candidates for sibling // contraction @@ -865,8 +865,8 @@ class OrderByPtrId final { public: virtual bool operator()(const OrderVarStdVertex* lhsp, const OrderVarStdVertex* rhsp) const { - const vluint64_t l_id = m_ids.findId(lhsp); - const vluint64_t r_id = m_ids.findId(rhsp); + const uint64_t l_id = m_ids.findId(lhsp); + const uint64_t r_id = m_ids.findId(rhsp); return l_id < r_id; } }; @@ -1580,8 +1580,8 @@ private: // runtime should be N*log(N) for a chain-shaped graph. // static void selfTestChain() { - const vluint64_t usecsSmall = partitionChainUsecs(5); - const vluint64_t usecsLarge = partitionChainUsecs(500); + const uint64_t usecsSmall = partitionChainUsecs(5); + const uint64_t usecsLarge = partitionChainUsecs(500); // Large input is 50x bigger than small input. // Its runtime should be about 10x longer -- not about 2500x longer // or worse which would suggest N^2 scaling or worse. @@ -1590,9 +1590,9 @@ private: << usecsSmall << ", large input runtime = " << usecsLarge); } - static vluint64_t partitionChainUsecs(unsigned chain_len) { + static uint64_t partitionChainUsecs(unsigned chain_len) { // NOTE: To get a dot file run with --debugi-V3Partition 4 or more. - const vluint64_t startUsecs = V3Os::timeUsecs(); + const uint64_t startUsecs = V3Os::timeUsecs(); V3Graph mtasks; LogicMTask* lastp = nullptr; for (unsigned i = 0; i < chain_len; ++i) { @@ -1614,8 +1614,8 @@ private: PartParallelismEst check(&mtasks); check.traverse(); - const vluint64_t endUsecs = V3Os::timeUsecs(); - const vluint64_t elapsedUsecs = endUsecs - startUsecs; + const uint64_t endUsecs = V3Os::timeUsecs(); + const uint64_t elapsedUsecs = endUsecs - startUsecs; if (debug() >= 6) { UINFO(0, "Chain self test stats:\n"); @@ -1927,7 +1927,7 @@ private: public: void go() { - vluint64_t startUsecs = 0; + uint64_t startUsecs = 0; if (debug() >= 3) startUsecs = V3Os::timeUsecs(); // Build an OLV->mtask map and a set of OVVs @@ -2682,21 +2682,21 @@ void V3Partition::go(V3Graph* mtasksp) { } } -void add(std::unordered_map& cmap, int id, vluint64_t cost) { cmap[id] += cost; } +void add(std::unordered_map& cmap, int id, uint64_t cost) { cmap[id] += cost; } -using EstimateAndProfiled = std::pair; // cost est, cost profiled +using EstimateAndProfiled = std::pair; // cost est, cost profiled using Costs = std::unordered_map; static void normalizeCosts(Costs& costs) { - const auto scaleCost = [](vluint64_t value, double multiplier) { + const auto scaleCost = [](uint64_t value, double multiplier) { double scaled = static_cast(value) * multiplier; if (value && scaled < 1) scaled = 1; return static_cast(scaled); }; // For all costs with a profile, compute sum - vluint64_t sumCostProfiled = 0; // For data with estimate and profile - vluint64_t sumCostEstimate = 0; // For data with estimate and profile + uint64_t sumCostProfiled = 0; // For data with estimate and profile + uint64_t sumCostEstimate = 0; // For data with estimate and profile for (const auto& est : costs) { if (est.second.second) { sumCostEstimate += est.second.first; @@ -2720,7 +2720,7 @@ static void normalizeCosts(Costs& costs) { } // COSTS can overflow a uint32. Using maximum value of costs, scale all down - vluint64_t maxCost = 0; + uint64_t maxCost = 0; for (auto& est : costs) { const uint64_t& costEstimate = est.second.first; const uint64_t& costProfiled = est.second.second; @@ -2729,7 +2729,7 @@ static void normalizeCosts(Costs& costs) { UINFO(9, "Post uint scale: ce = " << est.second.first << " cp=" << est.second.second << endl); } - const vluint64_t scaleDownTo = 10000000; // Extra room for future algorithms to add costs + const uint64_t scaleDownTo = 10000000; // Extra room for future algorithms to add costs if (maxCost > scaleDownTo) { const double scaleup = static_cast(scaleDownTo) / static_cast(maxCost); UINFO(5, "Scaling data to within 32-bits by multiply by=" << scaleup << ", maxCost=" @@ -2783,8 +2783,8 @@ static void fillinCosts(V3Graph* execMTaskGraphp) { mtp->hashName(m_uniqueNames.get(mtp->bodyp())); // This estimate is 64 bits, but the final mtask graph algorithm needs 32 bits - const vluint64_t costEstimate = V3InstrCount::count(mtp->bodyp(), false); - const vluint64_t costProfiled + const uint64_t costEstimate = V3InstrCount::count(mtp->bodyp(), false); + const uint64_t costProfiled = V3Config::getProfileData(v3Global.opt.prefix(), mtp->hashName()); if (costProfiled) { UINFO(5, "Profile data for mtask " << mtp->id() << " " << mtp->hashName() @@ -2868,7 +2868,7 @@ static void finalizeCosts(V3Graph* execMTaskGraphp) { } // Assign profiler IDs - vluint64_t profilerId = 0; + uint64_t profilerId = 0; for (const V3GraphVertex* vxp = execMTaskGraphp->verticesBeginp(); vxp; vxp = vxp->verticesNextp()) { ExecMTask* const mtp = dynamic_cast(const_cast(vxp)); diff --git a/src/V3Partition.h b/src/V3Partition.h index d6155a852..4ba4cc29e 100644 --- a/src/V3Partition.h +++ b/src/V3Partition.h @@ -78,14 +78,14 @@ class PartPtrIdMap final { private: // TYPES // MEMBERS - mutable vluint64_t m_nextId = 0; - mutable std::unordered_map m_id; + mutable uint64_t m_nextId = 0; + mutable std::unordered_map m_id; public: // CONSTRUCTORS PartPtrIdMap() = default; // METHODS - vluint64_t findId(const void* ptrp) const { + uint64_t findId(const void* ptrp) const { const auto it = m_id.find(ptrp); if (it != m_id.end()) return it->second; m_id[ptrp] = m_nextId; diff --git a/src/V3PartitionGraph.h b/src/V3PartitionGraph.h index e32a759e2..2fba23172 100644 --- a/src/V3PartitionGraph.h +++ b/src/V3PartitionGraph.h @@ -77,10 +77,10 @@ public: void priority(uint32_t pri) { m_priority = pri; } virtual uint32_t cost() const override { return m_cost; } void cost(uint32_t cost) { m_cost = cost; } - void predictStart(vluint64_t time) { m_predictStart = time; } - vluint64_t predictStart() const { return m_predictStart; } - void profilerId(vluint64_t id) { m_profilerId = id; } - vluint64_t profilerId() const { return m_profilerId; } + void predictStart(uint64_t time) { m_predictStart = time; } + uint64_t predictStart() const { return m_predictStart; } + void profilerId(uint64_t id) { m_profilerId = id; } + uint64_t profilerId() const { return m_profilerId; } string cFuncName() const { // If this MTask maps to a C function, this should be the name return string("__Vmtask") + "__" + cvtToStr(m_id); diff --git a/src/V3SplitVar.cpp b/src/V3SplitVar.cpp index a4197d74d..549d6ecbc 100644 --- a/src/V3SplitVar.cpp +++ b/src/V3SplitVar.cpp @@ -697,7 +697,7 @@ class SplitUnpackedVarVisitor final : public VNVisitor, public SplitVarImpl { const bool needNext = VN_IS(subTypep, UnpackArrayDType); // Still unpacked array. std::vector vars; // Add the split variables - for (vlsint32_t i = 0; i < dtypep->elementsConst(); ++i) { + for (int32_t i = 0; i < dtypep->elementsConst(); ++i) { // Unpacked array is traced as var(idx), not var[idx]. const std::string name = varp->name() + AstNode::encodeName('(' + cvtToStr(i + dtypep->lo()) + ')'); diff --git a/src/V3Stats.h b/src/V3Stats.h index f8bfb6231..7fb43db33 100644 --- a/src/V3Stats.h +++ b/src/V3Stats.h @@ -35,7 +35,7 @@ public: ~VDouble0() = default; // Implicit conversion operators: - explicit VDouble0(const vluint64_t v) + explicit VDouble0(const uint64_t v) : m_d{static_cast(v)} {} operator double() const { return m_d; } diff --git a/src/V3TSP.cpp b/src/V3TSP.cpp index 4032a0622..ec9f491aa 100644 --- a/src/V3TSP.cpp +++ b/src/V3TSP.cpp @@ -338,7 +338,7 @@ public: // Look for an arbitrary edge we've not yet marked for (V3GraphEdge* edgep = cur_vertexp->outBeginp(); edgep; edgep = edgep->outNextp()) { - const vluint32_t edgeId = getEdgeId(edgep); + const uint32_t edgeId = getEdgeId(edgep); if (markedEdgesp->end() == markedEdgesp->find(edgeId)) { // This edge is not yet marked, so follow it. markedEdgesp->insert(edgeId); @@ -362,7 +362,7 @@ public: recursed = false; // Look for an arbitrary edge at vxp we've not yet marked for (V3GraphEdge* edgep = vxp->outBeginp(); edgep; edgep = edgep->outNextp()) { - const vluint32_t edgeId = getEdgeId(edgep); + const uint32_t edgeId = getEdgeId(edgep); if (markedEdgesp->end() == markedEdgesp->find(edgeId)) { UINFO(6, "Recursing.\n"); findEulerTourRecurse(markedEdgesp, vxp, sortedOutp); @@ -414,7 +414,7 @@ public: std::vector result; for (V3GraphVertex* vxp = verticesBeginp(); vxp; vxp = vxp->verticesNextp()) { const Vertex* const tspvp = castVertexp(vxp); - vluint32_t degree = 0; + uint32_t degree = 0; for (V3GraphEdge* edgep = vxp->outBeginp(); edgep; edgep = edgep->outNextp()) { degree++; } diff --git a/src/V3Trace.cpp b/src/V3Trace.cpp index 477d97d2e..82d688252 100644 --- a/src/V3Trace.cpp +++ b/src/V3Trace.cpp @@ -54,7 +54,7 @@ class TraceActivityVertex final : public V3GraphVertex { AstNode* const m_insertp; - vlsint32_t m_activityCode; + int32_t m_activityCode; bool m_slow; // If always slow, we can use the same code public: enum { ACTIVITY_NEVER = ((1UL << 31) - 1) }; @@ -66,7 +66,7 @@ public: m_activityCode = 0; m_slow = slow; } - TraceActivityVertex(V3Graph* graphp, vlsint32_t code) + TraceActivityVertex(V3Graph* graphp, int32_t code) : V3GraphVertex{graphp} , m_insertp{nullptr} { m_activityCode = code; @@ -86,10 +86,10 @@ public: } } virtual string dotColor() const override { return slow() ? "yellowGreen" : "green"; } - vlsint32_t activityCode() const { return m_activityCode; } + int32_t activityCode() const { return m_activityCode; } bool activityAlways() const { return activityCode() == ACTIVITY_ALWAYS; } bool activitySlow() const { return activityCode() == ACTIVITY_SLOW; } - void activityCode(vlsint32_t code) { m_activityCode = code; } + void activityCode(int32_t code) { m_activityCode = code; } bool slow() const { return m_slow; } void slow(bool flag) { if (!flag) m_slow = false; @@ -516,17 +516,17 @@ private: // sub function, hence the VL_ATTR_UNUSED attributes. if (full) { // Full dump sub function - addInitStr("vluint32_t* const oldp VL_ATTR_UNUSED = " + addInitStr("uint32_t* const oldp VL_ATTR_UNUSED = " "tracep->oldp(vlSymsp->__Vm_baseCode);\n"); } else { // Change dump sub function if (v3Global.opt.trueTraceThreads()) { - addInitStr("const vluint32_t base VL_ATTR_UNUSED = " + addInitStr("const uint32_t base VL_ATTR_UNUSED = " "vlSymsp->__Vm_baseCode + " + cvtToStr(baseCode) + ";\n"); addInitStr("if (false && tracep) {} // Prevent unused\n"); } else { - addInitStr("vluint32_t* const oldp VL_ATTR_UNUSED = " + addInitStr("uint32_t* const oldp VL_ATTR_UNUSED = " "tracep->oldp(vlSymsp->__Vm_baseCode + " + cvtToStr(baseCode) + ");\n"); } diff --git a/src/V3Width.cpp b/src/V3Width.cpp index 743f641a4..e968decd3 100644 --- a/src/V3Width.cpp +++ b/src/V3Width.cpp @@ -5766,12 +5766,12 @@ private: VNRelinker linker; nodep->unlinkFrBack(&linker); if (const AstConst* const constp = VN_CAST(nodep, Const)) { - // We convert to/from vlsint32 rather than use floor() as want to make sure is + // We convert to/from int32_t rather than use floor() as want to make sure is // representable in integer's number of bits if (constp->isDouble() && v3EpsilonEqual( constp->num().toDouble(), - static_cast(static_cast(constp->num().toDouble())))) { + static_cast(static_cast(constp->num().toDouble())))) { warnOn = false; } } @@ -6168,7 +6168,7 @@ private: // Find valid values and populate UASSERT_OBJ(nodep->itemsp(), nodep, "enum without items"); - std::map values; + std::map values; { AstEnumItem* const firstp = nodep->itemsp(); const AstEnumItem* prevp = firstp; // Prev must start with last item @@ -6177,7 +6177,7 @@ private: AstEnumItem* const nextp = VN_AS(itemp->nextp(), EnumItem); const AstConst* const vconstp = VN_AS(itemp->valuep(), Const); UASSERT_OBJ(vconstp, nodep, "Enum item without constified value"); - const vluint64_t i = vconstp->toUQuad(); + const uint64_t i = vconstp->toUQuad(); if (attrType == VAttrType::ENUM_NAME) { values[i] = new AstConst(nodep->fileline(), AstConst::String(), itemp->name()); } else if (attrType == VAttrType::ENUM_NEXT) { @@ -6197,7 +6197,7 @@ private: if (assoc) { for (const auto& itr : values) initp->addIndexValuep(itr.first, itr.second); } else { - for (vluint64_t i = 0; i < (msbdim + 1); ++i) { + for (uint64_t i = 0; i < (msbdim + 1); ++i) { if (values[i]) initp->addIndexValuep(i, values[i]); } } diff --git a/src/V3WidthSel.cpp b/src/V3WidthSel.cpp index a437c472d..793b98aec 100644 --- a/src/V3WidthSel.cpp +++ b/src/V3WidthSel.cpp @@ -114,7 +114,7 @@ private: return FromData(errp, ddtypep, fromRange); } - AstNode* newSubNeg(AstNode* lhsp, vlsint32_t rhs) { + AstNode* newSubNeg(AstNode* lhsp, int32_t rhs) { // Return lhs-rhs, but if rhs is negative use an add, so we won't // have to deal with signed math and related 32bit sign extension problems if (rhs == 0) { @@ -142,7 +142,7 @@ private: return newp; } } - AstNode* newSubNeg(vlsint32_t lhs, AstNode* rhsp) { + AstNode* newSubNeg(int32_t lhs, AstNode* rhsp) { // Return lhs-rhs // We must make sure sub gets sign of original value AstNode* const newp = new AstSub( @@ -337,9 +337,9 @@ private: AstNode* const fromp = nodep->fromp()->unlinkFrBack(); AstNode* const msbp = nodep->rhsp()->unlinkFrBack(); AstNode* const lsbp = nodep->thsp()->unlinkFrBack(); - vlsint32_t msb = VN_AS(msbp, Const)->toSInt(); - vlsint32_t lsb = VN_AS(lsbp, Const)->toSInt(); - const vlsint32_t elem = (msb > lsb) ? (msb - lsb + 1) : (lsb - msb + 1); + int32_t msb = VN_AS(msbp, Const)->toSInt(); + int32_t lsb = VN_AS(lsbp, Const)->toSInt(); + const int32_t elem = (msb > lsb) ? (msb - lsb + 1) : (lsb - msb + 1); const FromData fromdata = fromDataForArray(nodep, fromp); AstNodeDType* const ddtypep = fromdata.m_dtypep; const VNumRange fromRange = fromdata.m_fromRange; @@ -507,13 +507,13 @@ private: nodep->replaceWith(newp); VL_DO_DANGLING(pushDeletep(nodep), nodep); } else if (VN_IS(rhsp, Const)) { // Slice - const vlsint32_t rhs = VN_AS(rhsp, Const)->toSInt(); + const int32_t rhs = VN_AS(rhsp, Const)->toSInt(); // down array: lsb/lo +: width // down array: msb/hi -: width // up array: msb/lo +: width // up array: lsb/hi -: width - const vlsint32_t msb = VN_IS(nodep, SelPlus) ? rhs + width - 1 : rhs; - const vlsint32_t lsb = VN_IS(nodep, SelPlus) ? rhs : rhs - width + 1; + const int32_t msb = VN_IS(nodep, SelPlus) ? rhs + width - 1 : rhs; + const int32_t lsb = VN_IS(nodep, SelPlus) ? rhs : rhs - width + 1; AstSliceSel* const newp = new AstSliceSel( nodep->fileline(), fromp, VNumRange(msb, lsb, fromRange.littleEndian())); nodep->replaceWith(newp); diff --git a/src/VlcBucket.h b/src/VlcBucket.h index 5bc39d946..ef5fdcdc7 100644 --- a/src/VlcBucket.h +++ b/src/VlcBucket.h @@ -31,25 +31,25 @@ class VlcBuckets final { private: // MEMBERS - vluint64_t* m_datap = nullptr; ///< Pointer to first bucket (dynamically allocated) - vluint64_t m_dataSize = 0; ///< Current entries in m_datap - vluint64_t m_bucketsCovered = 0; ///< Num buckets with sufficient coverage + uint64_t* m_datap = nullptr; ///< Pointer to first bucket (dynamically allocated) + uint64_t m_dataSize = 0; ///< Current entries in m_datap + uint64_t m_bucketsCovered = 0; ///< Num buckets with sufficient coverage - static vluint64_t covBit(vluint64_t point) { return 1ULL << (point & 63); } - vluint64_t allocSize() const { return sizeof(vluint64_t) * m_dataSize / 64; } - void allocate(vluint64_t point) { - const vluint64_t oldsize = m_dataSize; + static uint64_t covBit(uint64_t point) { return 1ULL << (point & 63); } + uint64_t allocSize() const { return sizeof(uint64_t) * m_dataSize / 64; } + void allocate(uint64_t point) { + const uint64_t oldsize = m_dataSize; if (m_dataSize < point) m_dataSize = (point + 64) & ~63ULL; // Keep power of two m_dataSize *= 2; // UINFO(9, "Realloc "<(std::realloc(m_datap, allocSize())); + uint64_t* const newp = static_cast(std::realloc(m_datap, allocSize())); if (VL_UNCOVERABLE(!newp)) { // cppcheck-suppress doubleFree // cppcheck 1.90 bug - realloc doesn't free on fail free(m_datap); // LCOV_EXCL_LINE v3fatal("Out of memory increasing buckets"); // LCOV_EXCL_LINE } m_datap = newp; - for (vluint64_t i = oldsize; i < m_dataSize; i += 64) m_datap[i / 64] = 0; + for (uint64_t i = oldsize; i < m_dataSize; i += 64) m_datap[i / 64] = 0; } public: @@ -61,11 +61,11 @@ public: } // ACCESSORS - static vluint64_t sufficient() { return 1; } - vluint64_t bucketsCovered() const { return m_bucketsCovered; } + static uint64_t sufficient() { return 1; } + uint64_t bucketsCovered() const { return m_bucketsCovered; } // METHODS - void addData(vluint64_t point, vluint64_t hits) { + void addData(uint64_t point, uint64_t hits) { if (hits >= sufficient()) { // UINFO(9," addData "<; // Sorted by name (ordered) + using NameMap = std::map; // Sorted by name (ordered) NameMap m_nameMap; //< Name to point-number std::vector m_points; //< List of all points - vluint64_t m_numPoints = 0; //< Total unique points + uint64_t m_numPoints = 0; //< Total unique points public: // ITERATORS @@ -121,9 +121,9 @@ public: point.dump(); } } - VlcPoint& pointNumber(vluint64_t num) { return m_points[num]; } - vluint64_t findAddPoint(const string& name, vluint64_t count) { - vluint64_t pointnum; + VlcPoint& pointNumber(uint64_t num) { return m_points[num]; } + uint64_t findAddPoint(const string& name, uint64_t count) { + uint64_t pointnum; const auto iter = m_nameMap.find(name); if (iter != m_nameMap.end()) { pointnum = iter->second; diff --git a/src/VlcSource.h b/src/VlcSource.h index f8dece1a8..b1ec313f2 100644 --- a/src/VlcSource.h +++ b/src/VlcSource.h @@ -32,7 +32,7 @@ private: // MEMBERS int m_lineno; ///< Line number int m_column; ///< Column number - vluint64_t m_count = 0; ///< Count + uint64_t m_count = 0; ///< Count bool m_ok = false; ///< Coverage is above threshold public: @@ -45,11 +45,11 @@ public: // ACCESSORS int lineno() const { return m_lineno; } int column() const { return m_column; } - vluint64_t count() const { return m_count; } + uint64_t count() const { return m_count; } bool ok() const { return m_ok; } // METHODS - void incCount(vluint64_t count, bool ok) { + void incCount(uint64_t count, bool ok) { m_count += count; if (ok) m_ok = true; } @@ -83,7 +83,7 @@ public: LinenoMap& lines() { return m_lines; } // METHODS - void incCount(int lineno, int column, vluint64_t count, bool ok) { + void incCount(int lineno, int column, uint64_t count, bool ok) { LinenoMap::iterator lit = m_lines.find(lineno); if (lit == m_lines.end()) lit = m_lines.insert(std::make_pair(lineno, ColumnMap())).first; ColumnMap& cmap = lit->second; diff --git a/src/VlcTest.h b/src/VlcTest.h index 1596bcb66..d4717d16c 100644 --- a/src/VlcTest.h +++ b/src/VlcTest.h @@ -34,15 +34,15 @@ private: // MEMBERS string m_name; //< Name of the test double m_computrons; //< Runtime for the test - vluint64_t m_testrun; //< Test run number, for database use - vluint64_t m_rank = 0; //< Execution rank suggestion - vluint64_t m_rankPoints = 0; //< Ranked additional points - vluint64_t m_user = 0; //< User data for algorithms (not persisted in .dat file) + uint64_t m_testrun; //< Test run number, for database use + uint64_t m_rank = 0; //< Execution rank suggestion + uint64_t m_rankPoints = 0; //< Ranked additional points + uint64_t m_user = 0; //< User data for algorithms (not persisted in .dat file) VlcBuckets m_buckets; //< Coverage data for each coverage point public: // CONSTRUCTORS - VlcTest(const string& name, vluint64_t testrun, double comp) + VlcTest(const string& name, uint64_t testrun, double comp) : m_name{name} , m_computrons{comp} , m_testrun{testrun} {} @@ -51,15 +51,15 @@ public: // ACCESSORS const string& name() const { return m_name; } double computrons() const { return m_computrons; } - vluint64_t testrun() const { return m_testrun; } + uint64_t testrun() const { return m_testrun; } VlcBuckets& buckets() { return m_buckets; } - vluint64_t bucketsCovered() const { return m_buckets.bucketsCovered(); } - vluint64_t rank() const { return m_rank; } - void rank(vluint64_t flag) { m_rank = flag; } - vluint64_t rankPoints() const { return m_rankPoints; } - void rankPoints(vluint64_t flag) { m_rankPoints = flag; } - vluint64_t user() const { return m_user; } - void user(vluint64_t flag) { m_user = flag; } + uint64_t bucketsCovered() const { return m_buckets.bucketsCovered(); } + uint64_t rank() const { return m_rank; } + void rank(uint64_t flag) { m_rank = flag; } + uint64_t rankPoints() const { return m_rankPoints; } + void rankPoints(uint64_t flag) { m_rankPoints = flag; } + uint64_t user() const { return m_user; } + void user(uint64_t flag) { m_user = flag; } // METHODS static void dumpHeader() { @@ -111,7 +111,7 @@ public: VlcTest::dumpHeader(); for (const auto& testp : m_tests) testp->dump(bucketsToo); } - VlcTest* newTest(const string& name, vluint64_t testrun, double comp) { + VlcTest* newTest(const string& name, uint64_t testrun, double comp) { VlcTest* const testp = new VlcTest{name, testrun, comp}; m_tests.push_back(testp); return testp; diff --git a/src/VlcTop.cpp b/src/VlcTop.cpp index 1d57c23ce..ba08eb6d0 100644 --- a/src/VlcTop.cpp +++ b/src/VlcTop.cpp @@ -47,10 +47,10 @@ void VlcTop::readCoverage(const string& filename, bool nonfatal) { if (line[secspace] == '\'' && line[secspace + 1] == ' ') break; } const string point = line.substr(3, secspace - 3); - vluint64_t hits = std::atoll(line.c_str() + secspace + 1); + uint64_t hits = std::atoll(line.c_str() + secspace + 1); // UINFO(9," point '"<= VlcBuckets::sufficient()) { @@ -117,7 +117,7 @@ void VlcTop::writeInfo(const string& filename) { const int lineno = li.first; VlcSource::ColumnMap& cmap = li.second; bool first = true; - vluint64_t min_count = 0; // Minimum across all columns on line + uint64_t min_count = 0; // Minimum across all columns on line for (auto& ci : cmap) { VlcSourceCount& col = ci.second; if (first) { @@ -146,7 +146,7 @@ struct CmpComputrons { void VlcTop::rank() { UINFO(2, "rank...\n"); - vluint64_t nextrank = 1; + uint64_t nextrank = 1; // Sort by computrons, so fast tests get selected first std::vector bytime; @@ -174,10 +174,10 @@ void VlcTop::rank() { remaining.dump(); // LCOV_EXCL_LINE } VlcTest* bestTestp = nullptr; - vluint64_t bestRemain = 0; + uint64_t bestRemain = 0; for (const auto& testp : bytime) { if (!testp->rank()) { - vluint64_t remain = testp->buckets().dataPopCount(remaining); + uint64_t remain = testp->buckets().dataPopCount(remaining); if (remain > bestRemain) { bestTestp = testp; bestRemain = remain; diff --git a/test_regress/driver.pl b/test_regress/driver.pl index 48b6d9539..3f4db9538 100755 --- a/test_regress/driver.pl +++ b/test_regress/driver.pl @@ -1808,7 +1808,7 @@ sub _make_main { print $fh " sc_time sim_time($self->{sim_time}, $Self->{sc_time_resolution});\n"; } else { print $fh "int main(int argc, char** argv, char** env) {\n"; - print $fh " vluint64_t sim_time = $self->{sim_time};\n"; + print $fh " uint64_t sim_time = $self->{sim_time};\n"; } print $fh " const std::unique_ptr contextp{new VerilatedContext};\n"; diff --git a/test_regress/t/t_var_pins_sc64.pl b/test_regress/t/t_var_pins_sc64.pl index ec4a48b94..9414d82d4 100755 --- a/test_regress/t/t_var_pins_sc64.pl +++ b/test_regress/t/t_var_pins_sc64.pl @@ -22,7 +22,7 @@ if ($Self->{vlt_all}) { file_grep("$Self->{obj_dir}/$Self->{VM_PREFIX}.h", qr/sc_in \s+ &i8;/x); file_grep("$Self->{obj_dir}/$Self->{VM_PREFIX}.h", qr/sc_in \s+ &i16;/x); file_grep("$Self->{obj_dir}/$Self->{VM_PREFIX}.h", qr/sc_in \s+ &i32;/x); - file_grep("$Self->{obj_dir}/$Self->{VM_PREFIX}.h", qr/sc_in \s+ &i64;/x); + file_grep("$Self->{obj_dir}/$Self->{VM_PREFIX}.h", qr/sc_in \s+ &i64;/x); file_grep("$Self->{obj_dir}/$Self->{VM_PREFIX}.h", qr/sc_in\s> \s+ &i65;/x); file_grep("$Self->{obj_dir}/$Self->{VM_PREFIX}.h", qr/sc_in\s> \s+ &ibv1;/x); file_grep("$Self->{obj_dir}/$Self->{VM_PREFIX}.h", qr/sc_in\s> \s+ &ibv16;/x); @@ -33,7 +33,7 @@ if ($Self->{vlt_all}) { file_grep("$Self->{obj_dir}/$Self->{VM_PREFIX}.h", qr/sc_out \s+ &o8;/x); file_grep("$Self->{obj_dir}/$Self->{VM_PREFIX}.h", qr/sc_out \s+ &o16;/x); file_grep("$Self->{obj_dir}/$Self->{VM_PREFIX}.h", qr/sc_out \s+ &o32;/x); - file_grep("$Self->{obj_dir}/$Self->{VM_PREFIX}.h", qr/sc_out \s+ &o64;/x); + file_grep("$Self->{obj_dir}/$Self->{VM_PREFIX}.h", qr/sc_out \s+ &o64;/x); file_grep("$Self->{obj_dir}/$Self->{VM_PREFIX}.h", qr/sc_out\s> \s+ &o65;/x); file_grep("$Self->{obj_dir}/$Self->{VM_PREFIX}.h", qr/sc_out\s> \s+ &obv1;/x); file_grep("$Self->{obj_dir}/$Self->{VM_PREFIX}.h", qr/sc_out\s> \s+ &obv16;/x); diff --git a/test_regress/t/t_var_pins_sc_biguint.pl b/test_regress/t/t_var_pins_sc_biguint.pl index bb64269ce..05ac18ba4 100755 --- a/test_regress/t/t_var_pins_sc_biguint.pl +++ b/test_regress/t/t_var_pins_sc_biguint.pl @@ -22,7 +22,7 @@ if ($Self->{vlt_all}) { file_grep("$Self->{obj_dir}/$Self->{VM_PREFIX}.h", qr/sc_in \s+ &i8;/x); file_grep("$Self->{obj_dir}/$Self->{VM_PREFIX}.h", qr/sc_in \s+ &i16;/x); file_grep("$Self->{obj_dir}/$Self->{VM_PREFIX}.h", qr/sc_in \s+ &i32;/x); - file_grep("$Self->{obj_dir}/$Self->{VM_PREFIX}.h", qr/sc_in \s+ &i64;/x); + file_grep("$Self->{obj_dir}/$Self->{VM_PREFIX}.h", qr/sc_in \s+ &i64;/x); file_grep("$Self->{obj_dir}/$Self->{VM_PREFIX}.h", qr/sc_in\s> \s+ &i65;/x); file_grep("$Self->{obj_dir}/$Self->{VM_PREFIX}.h", qr/sc_in\s> \s+ &i128;/x); file_grep("$Self->{obj_dir}/$Self->{VM_PREFIX}.h", qr/sc_in\s> \s+ &i513;/x); @@ -33,7 +33,7 @@ if ($Self->{vlt_all}) { file_grep("$Self->{obj_dir}/$Self->{VM_PREFIX}.h", qr/sc_out \s+ &o8;/x); file_grep("$Self->{obj_dir}/$Self->{VM_PREFIX}.h", qr/sc_out \s+ &o16;/x); file_grep("$Self->{obj_dir}/$Self->{VM_PREFIX}.h", qr/sc_out \s+ &o32;/x); - file_grep("$Self->{obj_dir}/$Self->{VM_PREFIX}.h", qr/sc_out \s+ &o64;/x); + file_grep("$Self->{obj_dir}/$Self->{VM_PREFIX}.h", qr/sc_out \s+ &o64;/x); file_grep("$Self->{obj_dir}/$Self->{VM_PREFIX}.h", qr/sc_out\s> \s+ &o65;/x); file_grep("$Self->{obj_dir}/$Self->{VM_PREFIX}.h", qr/sc_out\s> \s+ &o128;/x); file_grep("$Self->{obj_dir}/$Self->{VM_PREFIX}.h", qr/sc_out\s> \s+ &o513;/x); diff --git a/test_regress/t/t_var_pins_scui.pl b/test_regress/t/t_var_pins_scui.pl index a28789078..a0d81d189 100755 --- a/test_regress/t/t_var_pins_scui.pl +++ b/test_regress/t/t_var_pins_scui.pl @@ -22,7 +22,7 @@ if ($Self->{vlt_all}) { file_grep("$Self->{obj_dir}/$Self->{VM_PREFIX}.h", qr/sc_in \s+ &i8;/x); file_grep("$Self->{obj_dir}/$Self->{VM_PREFIX}.h", qr/sc_in \s+ &i16;/x); file_grep("$Self->{obj_dir}/$Self->{VM_PREFIX}.h", qr/sc_in \s+ &i32;/x); - file_grep("$Self->{obj_dir}/$Self->{VM_PREFIX}.h", qr/sc_in \s+ &i64;/x); + file_grep("$Self->{obj_dir}/$Self->{VM_PREFIX}.h", qr/sc_in \s+ &i64;/x); file_grep("$Self->{obj_dir}/$Self->{VM_PREFIX}.h", qr/sc_in\s> \s+ &i65;/x); file_grep("$Self->{obj_dir}/$Self->{VM_PREFIX}.h", qr/sc_in\s> \s+ &ibv1;/x); file_grep("$Self->{obj_dir}/$Self->{VM_PREFIX}.h", qr/sc_in\s> \s+ &ibv16;/x); @@ -31,7 +31,7 @@ if ($Self->{vlt_all}) { file_grep("$Self->{obj_dir}/$Self->{VM_PREFIX}.h", qr/sc_out \s+ &o8;/x); file_grep("$Self->{obj_dir}/$Self->{VM_PREFIX}.h", qr/sc_out \s+ &o16;/x); file_grep("$Self->{obj_dir}/$Self->{VM_PREFIX}.h", qr/sc_out \s+ &o32;/x); - file_grep("$Self->{obj_dir}/$Self->{VM_PREFIX}.h", qr/sc_out \s+ &o64;/x); + file_grep("$Self->{obj_dir}/$Self->{VM_PREFIX}.h", qr/sc_out \s+ &o64;/x); file_grep("$Self->{obj_dir}/$Self->{VM_PREFIX}.h", qr/sc_out\s> \s+ &o65;/x); file_grep("$Self->{obj_dir}/$Self->{VM_PREFIX}.h", qr/sc_out\s> \s+ &obv1;/x); file_grep("$Self->{obj_dir}/$Self->{VM_PREFIX}.h", qr/sc_out\s> \s+ &obv16;/x); From 33105f017c994ccdb67480cfae29371a609e7ca2 Mon Sep 17 00:00:00 2001 From: Wilson Snyder Date: Wed, 30 Mar 2022 20:17:59 -0400 Subject: [PATCH 16/44] Commentary --- README.rst | 2 +- docs/guide/connecting.rst | 4 ++-- docs/guide/exe_verilator.rst | 8 ++++---- docs/guide/faq.rst | 6 +++--- docs/guide/languages.rst | 8 ++++---- docs/guide/simulating.rst | 4 ++-- docs/guide/warnings.rst | 14 +++++++------- docs/internals.rst | 14 +++++++------- examples/make_tracing_c/sim_main.cpp | 2 +- include/verilated.cpp | 2 +- include/verilated_dpi.cpp | 2 +- include/verilated_imp.h | 2 +- nodist/fastcov.py | 2 +- src/V3Assert.cpp | 2 +- src/V3Ast.h | 2 +- src/V3AstNodes.h | 4 ++-- src/V3AstUserAllocator.h | 2 +- src/V3Case.cpp | 2 +- src/V3Const.cpp | 2 +- src/V3Descope.cpp | 2 +- src/V3EmitCFunc.h | 2 +- src/V3Life.cpp | 2 +- src/V3LinkDot.cpp | 2 +- src/V3MergeCond.cpp | 2 +- src/V3Number.cpp | 2 +- src/V3Scope.cpp | 2 +- src/V3Simulate.h | 2 +- src/V3TSP.cpp | 2 +- src/V3Task.cpp | 4 ++-- src/V3WidthCommit.h | 2 +- src/verilog.y | 4 ++-- test_regress/t/t_dpi_accessors.cpp | 4 ++-- test_regress/t/t_order_dpi_export_1.v | 2 +- test_regress/t/t_preproc_dos.pl | 2 +- 34 files changed, 60 insertions(+), 60 deletions(-) diff --git a/README.rst b/README.rst index aab9e30af..caf5678b9 100644 --- a/README.rst +++ b/README.rst @@ -73,7 +73,7 @@ for you. Performance =========== -Verilator does not simply convert Verilog HDL to C++ or SystemC. Rather, +Verilator does not directly translate Verilog HDL to C++ or SystemC. Rather, Verilator compiles your code into a much faster optimized and optionally thread-partitioned model, which is in turn wrapped inside a C++/SystemC module. The results are a compiled Verilog model that executes even on a diff --git a/docs/guide/connecting.rst b/docs/guide/connecting.rst index 8e06f73a0..8259447b3 100644 --- a/docs/guide/connecting.rst +++ b/docs/guide/connecting.rst @@ -200,7 +200,7 @@ DPI System Task/Functions ------------------------- Verilator extends the DPI format to allow using the same scheme to -efficiently add system functions. Simply use a dollar-sign prefixed system +efficiently add system functions. Use a dollar-sign prefixed system function name for the import, but note it must be escaped. .. code-block:: sv @@ -508,7 +508,7 @@ structure. If a ``VerilatedContext`` is not created prior to creating a model, a default global one is created automatically. The ``Verilated::`` methods, including the ``Verilated::commandArgs`` call -shown above, simply call VerilatedContext methods using the default global +shown above, call VerilatedContext methods using the default global VerilatedContext. (Technically they operate on the last one used by a given thread.) If you are using multiple simulation contexts you should not use the Verilated:: methods, and instead always use VerilatedContext diff --git a/docs/guide/exe_verilator.rst b/docs/guide/exe_verilator.rst index 16a41ba15..d129c4a55 100644 --- a/docs/guide/exe_verilator.rst +++ b/docs/guide/exe_verilator.rst @@ -99,10 +99,10 @@ Summary: .. option:: --bbox-sys Black box any unknown $system task or function calls. System tasks will - simply become no-operations, and system functions will be replaced with - unsized zero. Arguments to such functions will be parsed, but not - otherwise checked. This prevents errors when linting in the presence of - company specific PLI calls. + become no-operations, and system functions will be replaced with unsized + zero. Arguments to such functions will be parsed, but not otherwise + checked. This prevents errors when linting in the presence of company + specific PLI calls. Using this argument will likely cause incorrect simulation. diff --git a/docs/guide/faq.rst b/docs/guide/faq.rst index e6599dc3c..5cc4acd43 100644 --- a/docs/guide/faq.rst +++ b/docs/guide/faq.rst @@ -354,8 +354,8 @@ also use the "import DPI" SystemVerilog feature to call C code (see the chapter above). There is also limited VPI access to public signals. If you want something more complex, since Verilator emits standard C++ -code, you can simply write your own C++ routines that can access and modify -signal values without needing any PLI interface code, and call it with +code, you can write your own C++ routines that can access and modify signal +values without needing any PLI interface code, and call it with $c("{any_c++_statement}"). See the :ref:`Connecting` section. @@ -482,7 +482,7 @@ by your code or you'll get strange results. Should a module be in Verilog or SystemC? """"""""""""""""""""""""""""""""""""""""" -Sometimes there is a block that just interconnects instances, and have a +Sometimes there is a block that only interconnects instances, and have a choice as to if you write it in Verilog or SystemC. Everything else being equal, best performance is when Verilator sees all of the design. So, look at the hierarchy of your design, labeling instances as to if they are diff --git a/docs/guide/languages.rst b/docs/guide/languages.rst index c360b7429..c4c714351 100644 --- a/docs/guide/languages.rst +++ b/docs/guide/languages.rst @@ -92,7 +92,7 @@ appropriate code to detect failing cases at simulation runtime and print an Verilator likewise also asserts any "unique" or "priority" SystemVerilog keywords on case statement, as well as "unique" on if statements. However, -"priority if" is currently simply ignored. +"priority if" is currently ignored. .. _Language Limitations: @@ -174,9 +174,9 @@ Structures and Unions --------------------- Presently Verilator only supports packed structs and packed unions. Rand -and randc tags on members are simply ignored. All structures and unions -are represented as a single vector, which means that generating one member -of a structure from blocking, and another from non-blocking assignments is +and randc tags on members are ignored. All structures and unions are +represented as a single vector, which means that generating one member of a +structure from blocking, and another from non-blocking assignments is unsupported. diff --git a/docs/guide/simulating.rst b/docs/guide/simulating.rst index da78bf9dd..c6c5fba7b 100644 --- a/docs/guide/simulating.rst +++ b/docs/guide/simulating.rst @@ -433,8 +433,8 @@ directly without any prefix. If results from multiple simulations are to be used in generating the optimization, multiple simulation's profile.vlt may be concatenated externally, or each of the files may be fed as separate command line -options into Verilator. Verilator will simply sum the profile results, so -a longer running test will have proportionally more weight for optimization +options into Verilator. Verilator will sum the profile results, so a +longer running test will have proportionally more weight for optimization than a shorter running test. If you provide any profile feedback data to Verilator, and it cannot use diff --git a/docs/guide/warnings.rst b/docs/guide/warnings.rst index d36133992..e122fec90 100644 --- a/docs/guide/warnings.rst +++ b/docs/guide/warnings.rst @@ -12,7 +12,7 @@ Disabling Warnings Warnings may be disabled in multiple ways: #. Disable the warning in the source code. When the warning is printed it - will include a warning code. Simply surround the offending line with a + will include a warning code. Surround the offending line with a :code:`/*verilator&32;lint_off*/` and :code:`/*verilator&32;lint_on*/` metacomment pair: @@ -162,7 +162,7 @@ List Of Warnings always @(posedge clk) foo[0] <= ... always_comb foo[1] = ... - Simply use a different register for the flop: + Instead use a different register for the flop: .. code-block:: sv @@ -284,7 +284,7 @@ List Of Warnings .. TODO better example - Warns that it is simply better style to use casez, and "?" in place of + Warns that it is better style to use casez, and "?" in place of "x"'s. See `http://www.sunburst-design.com/papers/CummingsSNUG1999Boston_FullParallelCase_rev1_1.pdf `_ @@ -1212,10 +1212,10 @@ List Of Warnings .. include:: ../../docs/gen/ex_STMTDLY_msg.rst This is a warning because Verilator does not support delayed statements. - It will simply ignore all such delays. In many cases ignoring a delay - might be harmless, but if the delayed statement is, as in this example, - used to cause some important action at a later time, it might be an - important difference. + It will ignore all such delays. In many cases ignoring a delay might be + harmless, but if the delayed statement is, as in this example, used to + cause some important action at a later time, it might be an important + difference. Some possible workarounds: diff --git a/docs/internals.rst b/docs/internals.rst index 71fa886a0..62358f1d7 100644 --- a/docs/internals.rst +++ b/docs/internals.rst @@ -268,11 +268,11 @@ Estimating Logic Costs To compute the cost of any given path through the graph, Verilator estimates an execution cost for each task. Each macro-task has an execution -cost which is simply the sum of its tasks' costs. We assume that -communication overhead and synchronization overhead are zero, so the cost -of any given path through the graph is simply the sum of macro-task -execution costs. Sarkar does almost the same thing, except that he has -nonzero estimates for synchronization costs. +cost which is the sum of its tasks' costs. We assume that communication +overhead and synchronization overhead are zero, so the cost of any given +path through the graph is the sum of macro-task execution costs. Sarkar +does almost the same thing, except that he has nonzero estimates for +synchronization costs. Verilator's cost estimates are assigned by ``InstrCountCostVisitor``. This class is perhaps the most fragile piece of the multithread @@ -817,7 +817,7 @@ which you can install using cpan. There are some traps to avoid when running regression tests -- When checking the MANIFEST, the test will barf on unexpected code in the +- When checking the MANIFEST, the test will fail on unexpected code in the Verilator tree. So make sure to keep any such code outside the tree. - Not all Linux systems install Perldoc by default. This is needed for the @@ -1186,7 +1186,7 @@ anticipated to be ever implemented for the reasons indicated. IEEE 1800-2017 3.3 modules within modules Little/no tool support, and arguably not a good practice. IEEE 1800-2017 6.12 "shortreal" - Little/no tool support, and easily simply promoted to real. + Little/no tool support, and easily promoted to real. IEEE 1800-2017 11.11 Min, typ, max No SDF support so will always use typical. IEEE 1800-2017 11.12 "let" diff --git a/examples/make_tracing_c/sim_main.cpp b/examples/make_tracing_c/sim_main.cpp index c9585dfe9..04181850a 100644 --- a/examples/make_tracing_c/sim_main.cpp +++ b/examples/make_tracing_c/sim_main.cpp @@ -69,7 +69,7 @@ int main(int argc, char** argv, char** env) { // Historical note, before Verilator 4.200 Verilated::gotFinish() // was used above in place of contextp->gotFinish(). // Most of the contextp-> calls can use Verilated:: calls instead; - // the Verilated:: versions simply assume there's a single context + // the Verilated:: versions just assume there's a single context // being used (per thread). It's faster and clearer to use the // newer contextp-> versions. diff --git a/include/verilated.cpp b/include/verilated.cpp index 97dbb9263..782b8cf39 100644 --- a/include/verilated.cpp +++ b/include/verilated.cpp @@ -1678,7 +1678,7 @@ IData VL_VALUEPLUSARGS_INW(int rbits, const std::string& ld, WDataOutP rwp) VL_M VL_SET_WQ(rwp, VL_CVT_Q_D(temp)); break; } - default: // Other simulators simply return 0 in these cases and don't error out + default: // Other simulators return 0 in these cases and don't error out return 0; } _vl_clean_inplace_w(rbits, rwp); diff --git a/include/verilated_dpi.cpp b/include/verilated_dpi.cpp index eb152b7d4..0eefa6e5b 100644 --- a/include/verilated_dpi.cpp +++ b/include/verilated_dpi.cpp @@ -417,7 +417,7 @@ static void _vl_svPutBitArrElem(const svOpenArrayHandle d, svBit value, int narg } //====================================================================== -// DPI accessors that simply call above functions +// DPI accessors that call above functions void* svGetArrElemPtr(const svOpenArrayHandle h, int indx1, ...) { const VerilatedDpiOpenVar* const varp = _vl_openhandle_varp(h); diff --git a/include/verilated_imp.h b/include/verilated_imp.h index 078722183..24456e646 100644 --- a/include/verilated_imp.h +++ b/include/verilated_imp.h @@ -489,7 +489,7 @@ public: public: // But only for verilated.cpp // Symbol table destruction cleans up the entries for each scope. static void userEraseScope(const VerilatedScope* scopep) VL_MT_SAFE { - // Slow ok - called once/scope on destruction, so we simply iterate. + // Slow ok - called once/scope on destruction, so we only iterate. const VerilatedLockGuard lock{s().m_userMapMutex}; for (auto it = s().m_userMap.begin(); it != s().m_userMap.end();) { if (it->first.first == scopep) { diff --git a/nodist/fastcov.py b/nodist/fastcov.py index 5be4ca7bf..0c69495eb 100755 --- a/nodist/fastcov.py +++ b/nodist/fastcov.py @@ -610,7 +610,7 @@ def getGcovCoverage(args): coverage_files = getFilteredCoverageFiles(coverage_files, args.excludepre) logging.info("Found {} coverage files after filtering".format(len(coverage_files))) - # We "zero" the "counters" by simply deleting all gcda files + # We "zero" the "counters" by deleting all gcda files if args.zerocounters: removeFiles(coverage_files) logging.info("Removed {} .gcda files".format(len(coverage_files))) diff --git a/src/V3Assert.cpp b/src/V3Assert.cpp index 26b16ebd5..eaf8e3e71 100644 --- a/src/V3Assert.cpp +++ b/src/V3Assert.cpp @@ -262,7 +262,7 @@ private: if (itemp->isDefault()) has_default = true; } if (nodep->fullPragma() || nodep->priorityPragma()) { - // Simply need to add a default if there isn't one already + // Need to add a default if there isn't one already ++m_statAsFull; if (!has_default) { nodep->addItemsp(new AstCaseItem( diff --git a/src/V3Ast.h b/src/V3Ast.h index 902bb37ae..9665245dc 100644 --- a/src/V3Ast.h +++ b/src/V3Ast.h @@ -2562,7 +2562,7 @@ private: string m_text; protected: - // Node that simply puts text into the output stream + // Node that puts text into the output stream AstNodeText(VNType t, FileLine* fl, const string& textp) : AstNode{t, fl} { m_text = textp; // Copy it diff --git a/src/V3AstNodes.h b/src/V3AstNodes.h index 49cb900d8..962f0c1fc 100644 --- a/src/V3AstNodes.h +++ b/src/V3AstNodes.h @@ -4927,7 +4927,7 @@ private: bool m_generate; // Underneath a generate const bool m_implied; // Not inserted by user public: - // Node that simply puts name into the output stream + // Node that puts name into the output stream AstBegin(FileLine* fl, const string& name, AstNode* stmtsp, bool generate = false, bool implied = false) : ASTGEN_SUPER_Begin(fl, name, stmtsp) @@ -4951,7 +4951,7 @@ class AstFork final : public AstNodeBlock { private: VJoinType m_joinType; // Join keyword type public: - // Node that simply puts name into the output stream + // Node that puts name into the output stream AstFork(FileLine* fl, const string& name, AstNode* stmtsp) : ASTGEN_SUPER_Fork(fl, name, stmtsp) {} ASTNODE_NODE_FUNCS(Fork) diff --git a/src/V3AstUserAllocator.h b/src/V3AstUserAllocator.h index 3be1cf481..d230f0829 100644 --- a/src/V3AstUserAllocator.h +++ b/src/V3AstUserAllocator.h @@ -117,7 +117,7 @@ public: }; // User pointer allocator classes. T_Node is the type of node the allocator should be applied to -// and is simply there for a bit of extra type safety. T_Data is the type of the data structure +// and is there for a bit of extra type safety. T_Data is the type of the data structure // managed by the allocator. template class AstUser1Allocator final : public AstUserAllocatorBase {}; diff --git a/src/V3Case.cpp b/src/V3Case.cpp index db83eff66..403b785b0 100644 --- a/src/V3Case.cpp +++ b/src/V3Case.cpp @@ -384,7 +384,7 @@ private: VL_DANGLING(iconstp); condp = AstEq::newTyped(itemp->fileline(), and1p, and2p); } else { - // Not a caseX mask, we can simply build CASEEQ(cexpr icond) + // Not a caseX mask, we can build CASEEQ(cexpr icond) AstNode* const and1p = cexprp->cloneTree(false); AstNode* const and2p = icondp; condp = AstEq::newTyped(itemp->fileline(), and1p, and2p); diff --git a/src/V3Const.cpp b/src/V3Const.cpp index 6a782accd..927fd1a87 100644 --- a/src/V3Const.cpp +++ b/src/V3Const.cpp @@ -2658,7 +2658,7 @@ private: // SENTREE(... SENITEM(x), SENGATE(SENITEM(x),*) ...) => SENITEM(x) // Do we need the SENITEM's to be identical? No because we're // ORing between them; we just need to ensure that the result is at - // least as frequently activating. So we simply + // least as frequently activating. So we // SENGATE(SENITEM(x)) -> SENITEM(x), then let it collapse with the // other SENITEM(x). { diff --git a/src/V3Descope.cpp b/src/V3Descope.cpp index 29bdd3abc..3d13cdb8e 100644 --- a/src/V3Descope.cpp +++ b/src/V3Descope.cpp @@ -176,7 +176,7 @@ private: // newfuncp->addStmtsp(new AstStop(newfuncp->fileline())); if (debug() >= 9) newfuncp->dumpTree(cout, " newfunc: "); } else { - // Only a single function under this name, we can simply rename it + // Only a single function under this name, we can rename it UINFO(6, " Wrapping " << name << " just one " << topFuncp << endl); topFuncp->name(name); } diff --git a/src/V3EmitCFunc.h b/src/V3EmitCFunc.h index 3910417aa..2a6b1189d 100644 --- a/src/V3EmitCFunc.h +++ b/src/V3EmitCFunc.h @@ -1137,7 +1137,7 @@ public: } else if (nodep->isWide()) { UASSERT_OBJ(m_wideTempRefp, nodep, "Wide Constant w/ no temp"); emitConstant(nodep, m_wideTempRefp, ""); - m_wideTempRefp = nullptr; // We used it, barf if set it a second time + m_wideTempRefp = nullptr; // We used it, fail if set it a second time } else { emitConstant(nodep, nullptr, ""); } diff --git a/src/V3Life.cpp b/src/V3Life.cpp index 691e490b9..57ab3d0e5 100644 --- a/src/V3Life.cpp +++ b/src/V3Life.cpp @@ -178,7 +178,7 @@ public: } } void varUsageReplace(AstVarScope* nodep, AstVarRef* varrefp) { - // Variable rvalue. If it references a constant, we can simply replace it + // Variable rvalue. If it references a constant, we can replace it const auto it = m_map.find(nodep); if (it != m_map.end()) { if (AstConst* const constp = it->second.constNodep()) { diff --git a/src/V3LinkDot.cpp b/src/V3LinkDot.cpp index d8c03df52..d483ffd41 100644 --- a/src/V3LinkDot.cpp +++ b/src/V3LinkDot.cpp @@ -259,7 +259,7 @@ public: // table's import wouldn't warn } else if (VN_IS(nodep, Begin) && VN_IS(fnodep, Begin) && VN_AS(nodep, Begin)->generate()) { - // Begin: ... blocks often replicate under genif/genfor, so simply + // Begin: ... blocks often replicate under genif/genfor, so // suppress duplicate checks. See t_gen_forif.v for an example. } else { UINFO(4, "name " << name << endl); // Not always same as nodep->name diff --git a/src/V3MergeCond.cpp b/src/V3MergeCond.cpp index 79a73d4e3..767d7a30f 100644 --- a/src/V3MergeCond.cpp +++ b/src/V3MergeCond.cpp @@ -344,7 +344,7 @@ private: return true; } } - // Is it simply 'lhs = cond'? + // Is it 'lhs = cond'? if (assignp->rhsp()->sameTree(m_mgCondp)) return true; } } diff --git a/src/V3Number.cpp b/src/V3Number.cpp index df4622a95..801d98c2d 100644 --- a/src/V3Number.cpp +++ b/src/V3Number.cpp @@ -698,7 +698,7 @@ string V3Number::displayed(FileLine* fl, const string& vformat) const { // To get the number of digits required, we want to compute // log10(2**mantissabits) and round it up. To be able to handle // a very wide mantissa, we use log2(2**mantissabits)/log2(10), - // which is simply (+1.0 is for rounding bias): + // which is (+1.0 is for rounding bias): double dchars = mantissabits / 3.321928094887362 + 1.0; if (issigned) dchars++; // space for sign fmtsize = cvtToStr(int(dchars)); diff --git a/src/V3Scope.cpp b/src/V3Scope.cpp index 4d8280514..576931d75 100644 --- a/src/V3Scope.cpp +++ b/src/V3Scope.cpp @@ -138,7 +138,7 @@ private: } // Copy blocks into this scope - // If this is the first usage of the block ever, we can simply move the reference + // If this is the first usage of the block ever, we can move the reference iterateChildren(nodep); // ***Note m_scopep is passed back to the caller of the routine (above) diff --git a/src/V3Simulate.h b/src/V3Simulate.h index 9262e1ed3..b5fbdb234 100644 --- a/src/V3Simulate.h +++ b/src/V3Simulate.h @@ -70,7 +70,7 @@ class SimulateVisitor VL_NOT_FINAL : public VNVisitor { // Test the tree to see if it is conformant // Given a set of input values, find the output values // Both are done in this same visitor to reduce risk; if a visitor - // is missing, we will simply not apply the optimization, rather then bomb. + // is missing, we will not apply the optimization, rather then bomb. private: // NODE STATE diff --git a/src/V3TSP.cpp b/src/V3TSP.cpp index ec9f491aa..db80fbb82 100644 --- a/src/V3TSP.cpp +++ b/src/V3TSP.cpp @@ -142,7 +142,7 @@ private: struct EdgeListCmp final { bool operator()(const EdgeList* ap, const EdgeList* bp) const { - // Simply compare heads + // Compare heads return edgeCmp(bp->back(), ap->back()); } }; diff --git a/src/V3Task.cpp b/src/V3Task.cpp index 217a58e1f..0e150d31f 100644 --- a/src/V3Task.cpp +++ b/src/V3Task.cpp @@ -1281,7 +1281,7 @@ private: varScopep->user5(true); // Mark as already added // Note: We are ignoring function locals as they should not be referenced // anywhere outside of the enclosing AstCFunc, and therefore they are - // irrelevant for code ordering. This is simply an optimization to avoid adding + // irrelevant for code ordering. This is an optimization to avoid adding // useless nodes to the ordering graph in V3Order. if (varScopep->varp()->isFuncLocal()) return; writtenps.push_back(varScopep); @@ -1426,7 +1426,7 @@ private: "Ignoring return value of non-void function (IEEE 1800-2017 13.4.1)"); } // outvscp maybe non-nullptr if calling a function in a taskref, - // but if so we want to simply ignore the function result + // but if so we want to ignore the function result nodep->replaceWith(beginp); } // Cleanup diff --git a/src/V3WidthCommit.h b/src/V3WidthCommit.h index 606c1cf41..b4c745123 100644 --- a/src/V3WidthCommit.h +++ b/src/V3WidthCommit.h @@ -188,7 +188,7 @@ private: v3Global.rootp()->typeTablep()->addTypesp(nodep); } void visitIterateNodeDType(AstNodeDType* nodep) { - // Rather than use dtypeChg which may make new nodes, we simply edit in place, + // Rather than use dtypeChg which may make new nodes, we edit in place, // as we don't need to preserve any widthMin's, and every dtype with the same width // gets an identical edit. if (nodep->user1SetOnce()) return; // Process once diff --git a/src/verilog.y b/src/verilog.y index c5bac151a..a7230452e 100644 --- a/src/verilog.y +++ b/src/verilog.y @@ -1303,7 +1303,7 @@ port: // ==IEEE: port // // data_declarationVarFront // // // Though not type for interfaces, we factor out the port direction and type - // // so we can simply handle it in one place + // // so we can handle it in one place // // // IEEE: interface_port_header port_identifier { unpacked_dimension } // // Expanded interface_port_header @@ -5525,7 +5525,7 @@ pexpr: // IEEE: property_expr (The name pexpr is important as regexps j //UNSUP // // IEEE: '(' sexpr {',' sequence_match_item } ')' [ sequence_abbrev ] //UNSUP // // As sequence_expr includes expression_or_dist, and boolean_abbrev includes sequence_abbrev: //UNSUP // // '(' sequence_expr {',' sequence_match_item } ')' [ boolean_abbrev ] -//UNSUP // // "'(' sexpr ')' boolean_abbrev" matches "[sexpr:'(' expr ')'] boolean_abbrev" so we can simply drop it +//UNSUP // // "'(' sexpr ')' boolean_abbrev" matches "[sexpr:'(' expr ')'] boolean_abbrev" so we can drop it //UNSUP | '(' ~p~sexpr ')' { $$ = $1; $$ = ...; } //UNSUP | '(' ~p~sexpr ',' sequence_match_itemList ')' { } //UNSUP // diff --git a/test_regress/t/t_dpi_accessors.cpp b/test_regress/t/t_dpi_accessors.cpp index 54e7a9e18..d0de0d9a2 100644 --- a/test_regress/t/t_dpi_accessors.cpp +++ b/test_regress/t/t_dpi_accessors.cpp @@ -201,7 +201,7 @@ int main() { logReg(dut->clk, "read c", c, " (after clk)"); // "c" is continuously assigned as the inverse of "a", but in // Verilator, that means that it will only change value when "a" - // changes on the posedge of a clock. Put simply, "c" always holds the + // changes on the posedge of a clock. That is "c" always holds the // inverse of the "after clock" value of "a". checkResult(c == (1 - a), "Test of scalar wire reading failed."); } @@ -231,7 +231,7 @@ int main() { // "d" is continuously assigned as the (8-bit) bitwise inverse of "b", // but in Verilator, that means that it will only change value when - // "b" changes on the posedge of a clock. Put simply, "d" always holds + // "b" changes on the posedge of a clock. That is "d" always holds // the inverse of the "after clock" value of "b". checkResult(d == ((~b) & 0xff), "Test of vector wire reading failed."); } diff --git a/test_regress/t/t_order_dpi_export_1.v b/test_regress/t/t_order_dpi_export_1.v index 293c8a93e..cb608bad3 100644 --- a/test_regress/t/t_order_dpi_export_1.v +++ b/test_regress/t/t_order_dpi_export_1.v @@ -16,7 +16,7 @@ module testbench; endfunction; // Downstream signal dependent on clk demonstrates scheduling issue. - // The '$c("1") &' simply ensures that dependent_clk does not get + // The '$c("1") &' ensures that dependent_clk does not get // replaced with clk early and hence hiding the issue wire dependent_clk = $c1("1") & clk; diff --git a/test_regress/t/t_preproc_dos.pl b/test_regress/t/t_preproc_dos.pl index a32871293..f43a54cd5 100755 --- a/test_regress/t/t_preproc_dos.pl +++ b/test_regress/t/t_preproc_dos.pl @@ -13,7 +13,7 @@ scenarios(vlt => 1); top_filename("$Self->{obj_dir}/$Self->{name}.v"); golden_filename("$Self->{obj_dir}/$Self->{name}.out"); -# Rather then having to maintain a new .v and .out, simply add returns +# Rather then having to maintain a new .v and .out, add returns # to all lines of the existing t_preproc test. { From 9be4e7b576dc7272df6afcc05e239de24a214a29 Mon Sep 17 00:00:00 2001 From: Wilson Snyder Date: Thu, 31 Mar 2022 19:14:13 -0400 Subject: [PATCH 17/44] Fix Bison 3.8.2 error (#3366). --- Changes | 1 + src/bisonpre | 6 +++--- 2 files changed, 4 insertions(+), 3 deletions(-) diff --git a/Changes b/Changes index 16539baa6..25b7d3b41 100644 --- a/Changes +++ b/Changes @@ -16,6 +16,7 @@ Verilator 4.221 devel * Split --prof-threads into --prof-exec and --prof-pgo (#3365). [Geza Lore, Shunyao CAD] * Deprecate 'vluint64_t' and similar types (#3255). * Fix MSVC localtime_s (#3124). +* Fix Bison 3.8.2 error (#3366). [elike-ypq] Verilator 4.220 2022-03-12 diff --git a/src/bisonpre b/src/bisonpre index efebd9744..05b213d93 100755 --- a/src/bisonpre +++ b/src/bisonpre @@ -101,7 +101,7 @@ def bison_version_check(): def clean_output(filename, outname, is_output, is_c): print(" edit " + filename + " " + outname) - with open(filename) as fh: + with open(filename, "r", encoding="utf-8") as fh: lines = fh.readlines() basename = re.sub(r'.*/', '', tmp_prefix() + ".") @@ -165,7 +165,7 @@ def clean_output(filename, outname, is_output, is_c): def warning_check(filename): - with open(filename) as fh: + with open(filename, "r", encoding="utf-8") as fh: linenum = 0 for line in fh: linenum += 1 @@ -185,7 +185,7 @@ def clean_input(filename, outname): global Filename # pylint: disable=global-variable-undefined Filename = filename - with open(filename) as fh: + with open(filename, "r", encoding="utf-8") as fh: lines = fh.readlines() # Find "%tokens:" From c79ea88576b57d18f922ec29e27b23c284e774bc Mon Sep 17 00:00:00 2001 From: Geza Lore Date: Sat, 9 Apr 2022 20:24:40 +0100 Subject: [PATCH 18/44] Fix incorrect localization when encountering non-leaf functions. Fixes #3286. --- Changes | 1 + src/V3Localize.cpp | 28 +++++++-- test_regress/t/t_opt_localize_deep.pl | 22 +++++++ test_regress/t/t_opt_localize_deep.v | 83 +++++++++++++++++++++++++++ 4 files changed, 129 insertions(+), 5 deletions(-) create mode 100755 test_regress/t/t_opt_localize_deep.pl create mode 100644 test_regress/t/t_opt_localize_deep.v diff --git a/Changes b/Changes index 25b7d3b41..d605bbe74 100644 --- a/Changes +++ b/Changes @@ -17,6 +17,7 @@ Verilator 4.221 devel * Deprecate 'vluint64_t' and similar types (#3255). * Fix MSVC localtime_s (#3124). * Fix Bison 3.8.2 error (#3366). [elike-ypq] +* Fix rare bug in -Oz (V3Localize) (#3286). [Geza Lore, Shunyao CAD] Verilator 4.220 2022-03-12 diff --git a/src/V3Localize.cpp b/src/V3Localize.cpp index eaf8a5ea6..618b010ab 100644 --- a/src/V3Localize.cpp +++ b/src/V3Localize.cpp @@ -40,15 +40,15 @@ class LocalizeVisitor final : public VNVisitor { private: // NODE STATE // AstVarScope::user1() -> Bool indicating VarScope is not optimizable. + // AstCFunc::user1() -> Bool indicating CFunc is not a leaf function. // AstVarScope::user2() -> Bool indicating VarScope was fully assigned in the current // function. // AstVarScope::user3p() -> Set of CFuncs referencing this VarScope. (via m_accessors) // AstCFunc::user4p() -> Multimap of 'VarScope -> VarRefs that reference that VarScope' // in this function. (via m_references) - const VNUser1InUse m_inuser1; - const VNUser2InUse m_inuser2; - const VNUser3InUse m_inuser3; - const VNUser4InUse m_inuser4; + const VNUser1InUse m_user1InUse; + const VNUser3InUse m_user3InUse; + const VNUser4InUse m_user4InUse; AstUser3Allocator> m_accessors; AstUser4Allocator> @@ -69,6 +69,13 @@ private: && m_accessors(nodep).size() == 1); // .. a block temp used in a single CFunc } + bool existsNonLeaf(const std::unordered_set& funcps) { + for (const AstCFunc* const funcp : funcps) { + if (funcp->user1()) return true; + } + return false; + } + void moveVarScopes() { for (AstVarScope* const nodep : m_varScopeps) { if (!isOptimizable(nodep)) continue; // Not optimizable @@ -76,6 +83,12 @@ private: const std::unordered_set& funcps = m_accessors(nodep); if (funcps.empty()) continue; // No referencing functions at all + // If more than one referencing function, but not all are leaf + // functions, then don't localize, as one of the referencing + // functions might be calling another, which the current analysis + // cannot cope with. This should be rare (introduced by V3Depth). + if (funcps.size() > 1 && existsNonLeaf(funcps)) continue; + UINFO(4, "Localizing " << nodep << endl); ++m_statLocVars; @@ -121,11 +134,16 @@ private: { m_cfuncp = nodep; m_nodeDepth = 0; - AstNode::user2ClearTree(); // Check each function independently + const VNUser2InUse user2InUse; iterateChildrenConst(nodep); } } + virtual void visit(AstCCall* nodep) override { + m_cfuncp->user1(true); // Mark caller as not a leaf function + iterateChildrenConst(nodep); + } + virtual void visit(AstNodeAssign* nodep) override { // Analyze RHS first so "a = a + 1" is detected as a read before write iterate(nodep->rhsp()); diff --git a/test_regress/t/t_opt_localize_deep.pl b/test_regress/t/t_opt_localize_deep.pl new file mode 100755 index 000000000..7d49cd2cd --- /dev/null +++ b/test_regress/t/t_opt_localize_deep.pl @@ -0,0 +1,22 @@ +#!/usr/bin/env perl +if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +scenarios(simulator => 1); + +compile( + verilator_flags2 => ["--compiler msvc"], # We have deep expressions we want to test + ); + +execute( + check_finished => 1, + ); + +ok(1); +1; diff --git a/test_regress/t/t_opt_localize_deep.v b/test_regress/t/t_opt_localize_deep.v new file mode 100644 index 000000000..1c8267fc7 --- /dev/null +++ b/test_regress/t/t_opt_localize_deep.v @@ -0,0 +1,83 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2022 by Geza Lore. +// SPDX-License-Identifier: CC0-1.0 + +`ifdef verilator + `define dontOptimize $c1("1") +`else + `define dontOptimize 1'b1 +`endif + +module t (/*AUTOARG*/ + // Inputs + clk + ); + input clk; + + int cyc = 0; + int x = 0; + + always @(posedge clk) begin + cyc <= cyc + 1; + x = 32'hcafe1234; + + if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) + if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) + if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) + if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) + if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) + if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) + if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) + if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) + if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) + if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) + if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) + if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) + if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) + if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) + if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) + if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) + if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) + if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) + if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) + if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) + if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) + if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) + if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) + if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) + if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) + if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) + if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) + if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) + if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) + if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) + if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) + if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) + if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) + if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) + if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) + if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) + if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) + if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) + if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) + if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) + if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) + if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) + if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) + if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) + if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) + if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) + if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) + if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) + x = cyc; + + $write("[%0t] cyc=%0d x=%x\n", $time, cyc, x); + if (x !== cyc) $stop; + if (cyc == 99) begin + $write("*-* All Finished *-*\n"); + $finish; + end + end +endmodule From fbd568dc472dfd7d86e1e2b39f183b48a3e0b666 Mon Sep 17 00:00:00 2001 From: Geza Lore Date: Sun, 10 Apr 2022 11:37:41 +0100 Subject: [PATCH 19/44] Prep for multiple AstExecGraph. No functional change. --- src/V3Ast.h | 5 ++++ src/V3AstNodes.cpp | 5 ++-- src/V3AstNodes.h | 32 +++++++++++++--------- src/V3Clock.cpp | 3 ++- src/V3EmitCFunc.h | 8 +++--- src/V3EmitCSyms.cpp | 30 ++++++++------------- src/V3LifePost.cpp | 1 + src/V3Order.cpp | 11 ++++---- src/V3Partition.cpp | 65 +++++++++++++++++++++------------------------ src/V3Partition.h | 2 +- src/Verilator.cpp | 2 +- 11 files changed, 81 insertions(+), 83 deletions(-) diff --git a/src/V3Ast.h b/src/V3Ast.h index 9665245dc..1e717b6e5 100644 --- a/src/V3Ast.h +++ b/src/V3Ast.h @@ -2034,6 +2034,11 @@ template <> inline bool AstNode::privateMayBeUnder(const AstNode* template <> inline bool AstNode::privateMayBeUnder(const AstNode* nodep) { return !VN_IS(nodep, NodeStmt) && !VN_IS(nodep, NodeMath); } +template <> inline bool AstNode::privateMayBeUnder(const AstNode* nodep) { + if (VN_IS(nodep, ExecGraph)) return false; // Should not nest + if (VN_IS(nodep, NodeStmt)) return false; // Should be directly under CFunc + return true; +} inline std::ostream& operator<<(std::ostream& os, const AstNode* rhs) { if (!rhs) { diff --git a/src/V3AstNodes.cpp b/src/V3AstNodes.cpp index 14b15428a..08bcbd234 100644 --- a/src/V3AstNodes.cpp +++ b/src/V3AstNodes.cpp @@ -225,9 +225,10 @@ AstNodeBiop* AstEqWild::newTyped(FileLine* fl, AstNode* lhsp, AstNode* rhsp) { } } -AstExecGraph::AstExecGraph(FileLine* fileline) +AstExecGraph::AstExecGraph(FileLine* fileline, const string& name) : ASTGEN_SUPER_ExecGraph(fileline) - , m_depGraphp{new V3Graph} {} + , m_depGraphp{new V3Graph} + , m_name{name} {} AstExecGraph::~AstExecGraph() { VL_DO_DANGLING(delete m_depGraphp, m_depGraphp); } diff --git a/src/V3AstNodes.h b/src/V3AstNodes.h index 962f0c1fc..e4ba5a4c0 100644 --- a/src/V3AstNodes.h +++ b/src/V3AstNodes.h @@ -9199,27 +9199,30 @@ public: class AstExecGraph final : public AstNode { // For parallel execution, this node contains a dependency graph. Each - // node in the graph is an ExecMTask, which contains a body for the - // mtask, which contains a set of AstActive's, each of which calls a - // leaf AstCFunc. whew! + // vertex in the graph is an ExecMTask, which contains a body for the + // mtask (an AstMTaskBody), which contains sequentially executed statements. // - // The mtask bodies are also children of this node, so we can visit - // them without traversing the graph (it's not always needed to - // traverse the graph.) + // The AstMTaskBody nodes are also children of this node, so we can visit + // them without traversing the graph. private: - V3Graph* const m_depGraphp; // contains ExecMTask's + V3Graph* const m_depGraphp; // contains ExecMTask vertices + const string m_name; // Name of this AstExecGraph (for uniqueness at code generation) public: - explicit AstExecGraph(FileLine* fl); + explicit AstExecGraph(FileLine* fl, const string& name); ASTNODE_NODE_FUNCS_NO_DTOR(ExecGraph) virtual ~AstExecGraph() override; virtual const char* broken() const override { BROKEN_RTN(!m_depGraphp); return nullptr; } + virtual string name() const override { return m_name; } + V3Graph* depGraphp() { return m_depGraphp; } const V3Graph* depGraphp() const { return m_depGraphp; } - V3Graph* mutableDepGraphp() { return m_depGraphp; } - void addMTaskBody(AstMTaskBody* bodyp) { addOp1p(bodyp); } + // op1: The mtask bodies + AstMTaskBody* mTaskBodiesp() const { return VN_AS(op1p(), MTaskBody); } + void addMTaskBodyp(AstMTaskBody* bodyp) { addOp1p(bodyp); } + // op2: In later phases, the statements that start the parallel execution void addStmtsp(AstNode* stmtp) { addOp2p(stmtp); } }; @@ -9319,13 +9322,15 @@ private: AstConstPool* const m_constPoolp; // Reference to constant pool, for faster lookup AstPackage* m_dollarUnitPkgp = nullptr; // $unit AstCFunc* m_evalp = nullptr; // The '_eval' function - AstExecGraph* m_execGraphp = nullptr; // Execution MTask graph for threads>1 mode AstVarScope* m_dpiExportTriggerp = nullptr; // The DPI export trigger variable AstTopScope* m_topScopep = nullptr; // The singleton AstTopScope under the top module VTimescale m_timeunit; // Global time unit VTimescale m_timeprecision; // Global time precision bool m_changeRequest = false; // Have _change_request method bool m_timescaleSpecified = false; // Input HDL specified timescale + uint32_t m_nextFreeMTaskID = 1; // Next unique MTask ID within netlist + // starts at 1 so 0 means no MTask ID + uint32_t m_nextFreeMTaskProfilingID = 0; // Next unique ID to use for PGO public: AstNetlist(); ASTNODE_NODE_FUNCS(Netlist) @@ -9369,8 +9374,6 @@ public: } AstCFunc* evalp() const { return m_evalp; } void evalp(AstCFunc* evalp) { m_evalp = evalp; } - AstExecGraph* execGraphp() const { return m_execGraphp; } - void execGraphp(AstExecGraph* graphp) { m_execGraphp = graphp; } AstVarScope* dpiExportTriggerp() const { return m_dpiExportTriggerp; } void dpiExportTriggerp(AstVarScope* varScopep) { m_dpiExportTriggerp = varScopep; } AstTopScope* topScopep() const { return m_topScopep; } @@ -9390,6 +9393,9 @@ public: void timeprecisionMerge(FileLine*, const VTimescale& value); void timescaleSpecified(bool specified) { m_timescaleSpecified = specified; } bool timescaleSpecified() const { return m_timescaleSpecified; } + uint32_t allocNextMTaskID() { return m_nextFreeMTaskID++; } + uint32_t allocNextMTaskProfilingID() { return m_nextFreeMTaskProfilingID++; } + uint32_t usedMTaskProfilingIDs() const { return m_nextFreeMTaskProfilingID; } }; //###################################################################### diff --git a/src/V3Clock.cpp b/src/V3Clock.cpp index 77b655963..a9072fe29 100644 --- a/src/V3Clock.cpp +++ b/src/V3Clock.cpp @@ -411,7 +411,8 @@ private: } } virtual void visit(AstExecGraph* nodep) override { - for (m_mtaskBodyp = VN_AS(nodep->op1p(), MTaskBody); m_mtaskBodyp; + VL_RESTORER(m_mtaskBodyp); + for (m_mtaskBodyp = nodep->mTaskBodiesp(); m_mtaskBodyp; m_mtaskBodyp = VN_AS(m_mtaskBodyp->nextp(), MTaskBody)) { clearLastSen(); iterate(m_mtaskBodyp); diff --git a/src/V3EmitCFunc.h b/src/V3EmitCFunc.h index 2a6b1189d..127bf1032 100644 --- a/src/V3EmitCFunc.h +++ b/src/V3EmitCFunc.h @@ -1202,11 +1202,9 @@ public: emitVarReset(varp); } virtual void visit(AstExecGraph* nodep) override { - UASSERT_OBJ(nodep == v3Global.rootp()->execGraphp(), nodep, - "ExecGraph should be a singleton!"); - // The location of the AstExecGraph within the containing _eval() - // function is where we want to invoke the graph and wait for it to - // complete. Emitting the children does just that. + // The location of the AstExecGraph within the containing AstCFunc is where we want to + // invoke the graph and wait for it to complete. Emitting the children does just that. + UASSERT_OBJ(!nodep->mTaskBodiesp(), nodep, "These should have been lowered"); iterateChildrenConst(nodep); } virtual void visit(AstChangeDet* nodep) override { // diff --git a/src/V3EmitCSyms.cpp b/src/V3EmitCSyms.cpp index 131d3a304..f9baa3fd5 100644 --- a/src/V3EmitCSyms.cpp +++ b/src/V3EmitCSyms.cpp @@ -476,18 +476,8 @@ void EmitCSyms::emitSymHdr() { if (v3Global.opt.profPgo()) { puts("\n// PGO PROFILING\n"); - uint64_t maxProfilerId = 0; - if (v3Global.opt.mtasks()) { - for (const V3GraphVertex* vxp - = v3Global.rootp()->execGraphp()->depGraphp()->verticesBeginp(); - vxp; vxp = vxp->verticesNextp()) { - const ExecMTask* const mtp - = dynamic_cast(const_cast(vxp)); - if (maxProfilerId < mtp->profilerId()) maxProfilerId = mtp->profilerId(); - } - } - ++maxProfilerId; // As size must include 0 - puts("VlPgoProfiler<" + cvtToStr(maxProfilerId) + "> _vm_pgoProfiler;\n"); + const uint32_t usedMTaskProfilingIDs = v3Global.rootp()->usedMTaskProfilingIDs(); + puts("VlPgoProfiler<" + cvtToStr(usedMTaskProfilingIDs) + "> _vm_pgoProfiler;\n"); } if (!m_scopeNames.empty()) { // Scope names @@ -743,13 +733,15 @@ void EmitCSyms::emitSymImp() { if (v3Global.opt.profPgo()) { puts("// Configure profiling for PGO\n"); if (v3Global.opt.mtasks()) { - for (const V3GraphVertex* vxp - = v3Global.rootp()->execGraphp()->depGraphp()->verticesBeginp(); - vxp; vxp = vxp->verticesNextp()) { - ExecMTask* const mtp = dynamic_cast(const_cast(vxp)); - puts("_vm_pgoProfiler.addCounter(" + cvtToStr(mtp->profilerId()) + ", \"" - + mtp->hashName() + "\");\n"); - } + v3Global.rootp()->topModulep()->foreach( + [&](const AstExecGraph* execGraphp) { + for (const V3GraphVertex* vxp = execGraphp->depGraphp()->verticesBeginp(); vxp; + vxp = vxp->verticesNextp()) { + const ExecMTask* const mtp = static_cast(vxp); + puts("_vm_pgoProfiler.addCounter(" + cvtToStr(mtp->profilerId()) + ", \"" + + mtp->hashName() + "\");\n"); + } + }); } } diff --git a/src/V3LifePost.cpp b/src/V3LifePost.cpp index 07dbae5a5..14405ee3d 100644 --- a/src/V3LifePost.cpp +++ b/src/V3LifePost.cpp @@ -315,6 +315,7 @@ private: } virtual void visit(AstExecGraph* nodep) override { // Treat the ExecGraph like a call to each mtask body + UASSERT_OBJ(!m_mtasksGraphp, nodep, "Cannot handle more than one AstExecGraph"); m_mtasksGraphp = nodep->depGraphp(); for (V3GraphVertex* mtaskVxp = m_mtasksGraphp->verticesBeginp(); mtaskVxp; mtaskVxp = mtaskVxp->verticesNextp()) { diff --git a/src/V3Order.cpp b/src/V3Order.cpp index 529680624..090e81b7d 100644 --- a/src/V3Order.cpp +++ b/src/V3Order.cpp @@ -1954,9 +1954,8 @@ void OrderProcess::processMTasks() { // Create the AstExecGraph node which represents the execution // of the MTask graph. FileLine* const rootFlp = v3Global.rootp()->fileline(); - AstExecGraph* const execGraphp = new AstExecGraph(rootFlp); + AstExecGraph* const execGraphp = new AstExecGraph{rootFlp, "eval"}; m_scopetop.addActivep(execGraphp); - v3Global.rootp()->execGraphp(execGraphp); // Create CFuncs and bodies for each MTask. GraphStream emit_mtasks(&mtasks); @@ -1994,7 +1993,8 @@ void OrderProcess::processMTasks() { // and OrderLogicVertex's which are ephemeral to V3Order. // - The ExecMTask graph and the AstMTaskBody's produced here // persist until code generation time. - state.m_execMTaskp = new ExecMTask(execGraphp->mutableDepGraphp(), bodyp, mtaskp->id()); + V3Graph* const depGraphp = execGraphp->depGraphp(); + state.m_execMTaskp = new ExecMTask(depGraphp, bodyp, mtaskp->id()); // Cross-link each ExecMTask and MTaskBody // Q: Why even have two objects? // A: One is an AstNode, the other is a GraphVertex, @@ -2005,10 +2005,9 @@ void OrderProcess::processMTasks() { const AbstractLogicMTask* const fromp = dynamic_cast(fromVxp); const MTaskState& fromState = mtaskStates[fromp->id()]; - new V3GraphEdge(execGraphp->mutableDepGraphp(), fromState.m_execMTaskp, - state.m_execMTaskp, 1); + new V3GraphEdge(depGraphp, fromState.m_execMTaskp, state.m_execMTaskp, 1); } - execGraphp->addMTaskBody(bodyp); + execGraphp->addMTaskBodyp(bodyp); } } diff --git a/src/V3Partition.cpp b/src/V3Partition.cpp index 4c16c0aa3..18ca601d7 100644 --- a/src/V3Partition.cpp +++ b/src/V3Partition.cpp @@ -2112,8 +2112,8 @@ private: ThreadSchedule& operator=(ThreadSchedule&&) = default; // Debugging - void dumpDotFile(const string& filename) const; - void dumpDotFilePrefixedAlways(const string& nameComment) const; + void dumpDotFile(const V3Graph& graph, const string& filename) const; + void dumpDotFilePrefixedAlways(const V3Graph& graph, const string& nameComment) const; public: // Returns the number of cross-thread dependencies of the given MTask. If > 0, the MTask must @@ -2137,15 +2137,15 @@ public: }; //! Variant of dumpDotFilePrefixed without --dump option check -void ThreadSchedule::dumpDotFilePrefixedAlways(const string& nameComment) const { - dumpDotFile(v3Global.debugFilename(nameComment) + ".dot"); +void ThreadSchedule::dumpDotFilePrefixedAlways(const V3Graph& graph, + const string& nameComment) const { + dumpDotFile(graph, v3Global.debugFilename(nameComment) + ".dot"); } -void ThreadSchedule::dumpDotFile(const string& filename) const { +void ThreadSchedule::dumpDotFile(const V3Graph& graph, const string& filename) const { // This generates a file used by graphviz, https://www.graphviz.org const std::unique_ptr logp{V3File::new_ofstream(filename)}; if (logp->fail()) v3fatal("Can't write " << filename); - auto* const depGraph = v3Global.rootp()->execGraphp()->depGraphp(); // Header *logp << "digraph v3graph {\n"; @@ -2166,7 +2166,7 @@ void ThreadSchedule::dumpDotFile(const string& filename) const { // Find minimum cost MTask for scaling MTask node widths uint32_t minCost = UINT32_MAX; - for (const V3GraphVertex* vxp = depGraph->verticesBeginp(); vxp; vxp = vxp->verticesNextp()) { + for (const V3GraphVertex* vxp = graph.verticesBeginp(); vxp; vxp = vxp->verticesNextp()) { if (const ExecMTask* const mtaskp = dynamic_cast(vxp)) { minCost = minCost > mtaskp->cost() ? mtaskp->cost() : minCost; } @@ -2189,13 +2189,13 @@ void ThreadSchedule::dumpDotFile(const string& filename) const { }; // Emit MTasks - for (const V3GraphVertex* vxp = depGraph->verticesBeginp(); vxp; vxp = vxp->verticesNextp()) { + for (const V3GraphVertex* vxp = graph.verticesBeginp(); vxp; vxp = vxp->verticesNextp()) { if (const ExecMTask* const mtaskp = dynamic_cast(vxp)) emitMTask(mtaskp); } // Emit MTask dependency edges *logp << "\n // MTask dependencies\n"; - for (const V3GraphVertex* vxp = depGraph->verticesBeginp(); vxp; vxp = vxp->verticesNextp()) { + for (const V3GraphVertex* vxp = graph.verticesBeginp(); vxp; vxp = vxp->verticesNextp()) { if (const ExecMTask* const mtaskp = dynamic_cast(vxp)) { for (V3GraphEdge* edgep = mtaskp->outBeginp(); edgep; edgep = edgep->outNextp()) { const V3GraphVertex* const top = edgep->top(); @@ -2382,7 +2382,7 @@ public: } } - if (debug() >= 4) schedule.dumpDotFilePrefixedAlways("schedule"); + if (debug() >= 4) schedule.dumpDotFilePrefixedAlways(mtaskGraph, "schedule"); return schedule; } @@ -2659,15 +2659,14 @@ void V3Partition::go(V3Graph* mtasksp) { LogicMTask* const mtaskp = dynamic_cast(itp); sorted.insert(mtaskp); } - uint32_t nextId = 1; for (auto it = sorted.begin(); it != sorted.end(); ++it) { // We shouldn't perturb the sort order of the set, despite // changing the IDs, they should all just remain in the same // relative order. Confirm that: + const uint32_t nextId = v3Global.rootp()->allocNextMTaskID(); UASSERT(nextId <= (*it)->id(), "Should only shrink MTaskIDs here"); UINFO(4, "Reassigning MTask id " << (*it)->id() << " to id " << nextId << "\n"); (*it)->id(nextId); - ++nextId; } } @@ -2868,11 +2867,8 @@ static void finalizeCosts(V3Graph* execMTaskGraphp) { } // Assign profiler IDs - uint64_t profilerId = 0; - for (const V3GraphVertex* vxp = execMTaskGraphp->verticesBeginp(); vxp; - vxp = vxp->verticesNextp()) { - ExecMTask* const mtp = dynamic_cast(const_cast(vxp)); - mtp->profilerId(profilerId++); + for (V3GraphVertex* vxp = execMTaskGraphp->verticesBeginp(); vxp; vxp = vxp->verticesNextp()) { + static_cast(vxp)->profilerId(v3Global.rootp()->allocNextMTaskProfilingID()); } // Removing tasks may cause edges that were formerly non-transitive to @@ -2961,7 +2957,8 @@ static void addMTaskToFunction(const ThreadSchedule& schedule, const uint32_t th } } -static const std::vector createThreadFunctions(const ThreadSchedule& schedule) { +static const std::vector createThreadFunctions(const ThreadSchedule& schedule, + const string& tag) { AstNodeModule* const modp = v3Global.rootp()->topModulep(); FileLine* const fl = modp->fileline(); @@ -2971,8 +2968,7 @@ static const std::vector createThreadFunctions(const ThreadSchedule& for (const std::vector& thread : schedule.threads) { if (thread.empty()) continue; const uint32_t threadId = schedule.threadId(thread.front()); - string name = "__Vthread_"; - name += cvtToStr(threadId); + const string name{"__Vthread__" + tag + "__" + cvtToStr(threadId)}; AstCFunc* const funcp = new AstCFunc(fl, name, nullptr, "void"); modp->addStmtp(funcp); funcps.push_back(funcp); @@ -3048,32 +3044,31 @@ static void implementExecGraph(AstExecGraph* const execGraphp) { // Schedule the mtasks: statically associate each mtask with a thread, // and determine the order in which each thread will runs its mtasks. - const ThreadSchedule& schedule = PartPackMTasks().pack(*execGraphp->mutableDepGraphp()); + const ThreadSchedule& schedule = PartPackMTasks().pack(*execGraphp->depGraphp()); // Create a function to be run by each thread. Note this moves all AstMTaskBody nodes form the // AstExecGrap into the AstCFunc created - const std::vector& funcps = createThreadFunctions(schedule); + const std::vector& funcps = createThreadFunctions(schedule, execGraphp->name()); UASSERT(!funcps.empty(), "Non-empty ExecGraph yields no threads?"); // Start the thread functions at the point this AstExecGraph is located in the tree. addThreadStartToExecGraph(execGraphp, funcps); } -void V3Partition::finalize() { +void V3Partition::finalize(AstNetlist* netlistp) { // Called by Verilator top stage - AstExecGraph* const execGraphp = v3Global.rootp()->execGraphp(); - UASSERT(execGraphp, "Couldn't find AstExecGraph singleton."); + netlistp->topModulep()->foreach([&](AstExecGraph* execGraphp) { + // Back in V3Order, we partitioned mtasks using provisional cost + // estimates. However, V3Order precedes some optimizations (notably + // V3LifePost) that can change the cost of logic within each mtask. + // Now that logic is final, recompute the cost and priority of each + // ExecMTask. + fillinCosts(execGraphp->depGraphp()); + finalizeCosts(execGraphp->depGraphp()); - // Back in V3Order, we partitioned mtasks using provisional cost - // estimates. However, V3Order precedes some optimizations (notably - // V3LifePost) that can change the cost of logic within each mtask. - // Now that logic is final, recompute the cost and priority of each - // ExecMTask. - fillinCosts(execGraphp->mutableDepGraphp()); - finalizeCosts(execGraphp->mutableDepGraphp()); - - // Replace the graph body with its multi-threaded implementation. - implementExecGraph(execGraphp); + // Replace the graph body with its multi-threaded implementation. + implementExecGraph(execGraphp); + }); } void V3Partition::selfTest() { diff --git a/src/V3Partition.h b/src/V3Partition.h index 4ba4cc29e..c358599f4 100644 --- a/src/V3Partition.h +++ b/src/V3Partition.h @@ -62,7 +62,7 @@ public: // Operate on the final ExecMTask graph, immediately prior to code // generation time. - static void finalize(); + static void finalize(AstNetlist* netlistp); private: static void setupMTaskDeps(V3Graph* mtasksp, const Vx2MTaskMap* vx2mtaskp); diff --git a/src/Verilator.cpp b/src/Verilator.cpp index 7ba0c113a..e233a041c 100644 --- a/src/Verilator.cpp +++ b/src/Verilator.cpp @@ -503,7 +503,7 @@ static void process() { // threads. Must happen pre-EmitC which relies on the packing // order. Must happen post-V3LifePost which changes the relative // costs of mtasks. - V3Partition::finalize(); + V3Partition::finalize(v3Global.rootp()); } if (!v3Global.opt.lintOnly() && !v3Global.opt.xmlOnly() && !v3Global.opt.dpiHdrOnly()) { From f5f4e15ce279938a94c907b1e13ee8b42c90fa3c Mon Sep 17 00:00:00 2001 From: Wilson Snyder Date: Sun, 10 Apr 2022 10:31:58 -0400 Subject: [PATCH 20/44] Fix filenames with dots overwriting debug .vpp files (#3373). --- Changes | 1 + docs/guide/files.rst | 2 +- src/V3ParseImp.cpp | 5 +++-- 3 files changed, 5 insertions(+), 3 deletions(-) diff --git a/Changes b/Changes index d605bbe74..08bbaffbd 100644 --- a/Changes +++ b/Changes @@ -18,6 +18,7 @@ Verilator 4.221 devel * Fix MSVC localtime_s (#3124). * Fix Bison 3.8.2 error (#3366). [elike-ypq] * Fix rare bug in -Oz (V3Localize) (#3286). [Geza Lore, Shunyao CAD] +* Fix filenames with dots overwriting debug .vpp files (#3373). Verilator 4.220 2022-03-12 diff --git a/docs/guide/files.rst b/docs/guide/files.rst index 522855ce3..796a4c756 100644 --- a/docs/guide/files.rst +++ b/docs/guide/files.rst @@ -120,7 +120,7 @@ In certain debug and other modes, it also creates: - Debugging graph files (from --debug) * - *{prefix}{misc}*\ .tree - Debugging files (from --debug) - * - {mod_prefix}_{each_verilog_module}*{__n}*\ .vpp + * - {mod_prefix}_{each_verilog_base_filename}*\ .vpp - Pre-processed verilog (from --debug) After running Make, the C++ compiler may produce the following: diff --git a/src/V3ParseImp.cpp b/src/V3ParseImp.cpp index 00ee4a53c..de03355ef 100644 --- a/src/V3ParseImp.cpp +++ b/src/V3ParseImp.cpp @@ -268,6 +268,7 @@ void V3ParseImp::preprocDumps(std::ostream& os) { void V3ParseImp::parseFile(FileLine* fileline, const string& modfilename, bool inLibrary, const string& errmsg) { // "" for no error, make fake node + const string nondirname = V3Os::filenameNonDir(modfilename); const string modname = V3Os::filenameNonExt(modfilename); UINFO(2, __FUNCTION__ << ": " << modname << (inLibrary ? " [LIB]" : "") << endl); @@ -288,8 +289,8 @@ void V3ParseImp::parseFile(FileLine* fileline, const string& modfilename, bool i if (v3Global.opt.preprocOnly() || v3Global.opt.keepTempFiles()) { // Create output file with all the preprocessor output we buffered up - const string vppfilename - = v3Global.opt.hierTopDataDir() + "/" + v3Global.opt.prefix() + "_" + modname + ".vpp"; + const string vppfilename = v3Global.opt.hierTopDataDir() + "/" + v3Global.opt.prefix() + + "_" + nondirname + ".vpp"; std::ofstream* ofp = nullptr; std::ostream* osp; if (v3Global.opt.preprocOnly()) { From 5f333be9473820587990c060b7f55ed2020d5ae9 Mon Sep 17 00:00:00 2001 From: Wilson Snyder Date: Sun, 10 Apr 2022 19:40:27 -0400 Subject: [PATCH 21/44] Internals: Dump TraceDecl codes. --- src/V3AstNodes.cpp | 4 ++++ src/V3AstNodes.h | 1 + 2 files changed, 5 insertions(+) diff --git a/src/V3AstNodes.cpp b/src/V3AstNodes.cpp index 08bcbd234..fc6999853 100644 --- a/src/V3AstNodes.cpp +++ b/src/V3AstNodes.cpp @@ -1854,6 +1854,10 @@ void AstFork::dump(std::ostream& str) const { this->AstNode::dump(str); if (!joinType().join()) str << " [" << joinType() << "]"; } +void AstTraceDecl::dump(std::ostream& str) const { + this->AstNodeStmt::dump(str); + if (code()) str << " [code=" << code() << "]"; +} void AstTraceInc::dump(std::ostream& str) const { this->AstNodeStmt::dump(str); str << " -> "; diff --git a/src/V3AstNodes.h b/src/V3AstNodes.h index e4ba5a4c0..e1397b810 100644 --- a/src/V3AstNodes.h +++ b/src/V3AstNodes.h @@ -5330,6 +5330,7 @@ public: dtypeFrom(valuep); addNOp1p(valuep); } + virtual void dump(std::ostream& str) const override; virtual int instrCount() const override { return 100; } // Large... ASTNODE_NODE_FUNCS(TraceDecl) virtual string name() const override { return m_showname; } From 08e0a397d3db5c203e9535971b42977efaf57257 Mon Sep 17 00:00:00 2001 From: HungMingWu Date: Tue, 12 Apr 2022 18:53:52 +0800 Subject: [PATCH 22/44] Fix debugi-V3Param null pointer fault (#3380) (#3381) Signed-off-by: HungMingWu --- src/V3Param.cpp | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/V3Param.cpp b/src/V3Param.cpp index 02f545516..a898b0de7 100644 --- a/src/V3Param.cpp +++ b/src/V3Param.cpp @@ -781,7 +781,7 @@ public: bool any_overrides = false; // Must always clone __Vrcm (recursive modules) if (nodep->recursive()) any_overrides = true; - if (debug() > 8) nodep->paramsp()->dumpTreeAndNext(cout, "-cellparams: "); + if (debug() > 8 && nodep->paramsp()) nodep->paramsp()->dumpTreeAndNext(cout, "-cellparams: "); if (srcModp->hierBlock()) { longname = parameterizedHierBlockName(srcModp, nodep->paramsp()); From b7f2bb0e802c3374e3706187ab604124c16a0719 Mon Sep 17 00:00:00 2001 From: github action Date: Tue, 12 Apr 2022 10:54:48 +0000 Subject: [PATCH 23/44] Apply 'make format' --- src/V3Param.cpp | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/src/V3Param.cpp b/src/V3Param.cpp index a898b0de7..ea1936ae3 100644 --- a/src/V3Param.cpp +++ b/src/V3Param.cpp @@ -781,7 +781,8 @@ public: bool any_overrides = false; // Must always clone __Vrcm (recursive modules) if (nodep->recursive()) any_overrides = true; - if (debug() > 8 && nodep->paramsp()) nodep->paramsp()->dumpTreeAndNext(cout, "-cellparams: "); + if (debug() > 8 && nodep->paramsp()) + nodep->paramsp()->dumpTreeAndNext(cout, "-cellparams: "); if (srcModp->hierBlock()) { longname = parameterizedHierBlockName(srcModp, nodep->paramsp()); From baff64a43d1dd17a6adea070082437d754d1ea27 Mon Sep 17 00:00:00 2001 From: Julien Margetts <56540603+margej@users.noreply.github.com> Date: Tue, 12 Apr 2022 12:04:31 +0100 Subject: [PATCH 24/44] Add VK_USER_OBJS dependency to --create-lib library (#3370) (#3382). --- Changes | 1 + src/V3EmitMk.cpp | 4 ++-- 2 files changed, 3 insertions(+), 2 deletions(-) diff --git a/Changes b/Changes index 08bbaffbd..91b355795 100644 --- a/Changes +++ b/Changes @@ -19,6 +19,7 @@ Verilator 4.221 devel * Fix Bison 3.8.2 error (#3366). [elike-ypq] * Fix rare bug in -Oz (V3Localize) (#3286). [Geza Lore, Shunyao CAD] * Fix filenames with dots overwriting debug .vpp files (#3373). +* Fix including VK_USER_OBJS in make library (#3370). [Julien Margetts] Verilator 4.220 2022-03-12 diff --git a/src/V3EmitMk.cpp b/src/V3EmitMk.cpp index e625a74a5..a39c3f3ee 100644 --- a/src/V3EmitMk.cpp +++ b/src/V3EmitMk.cpp @@ -248,8 +248,8 @@ public: } if (!v3Global.opt.libCreate().empty()) { - const string libCreateDeps = "$(VK_OBJS) $(VK_GLOBAL_OBJS) " + v3Global.opt.libCreate() - + ".o $(VM_HIER_LIBS)"; + const string libCreateDeps = "$(VK_OBJS) $(VK_USER_OBJS) $(VK_GLOBAL_OBJS) " + + v3Global.opt.libCreate() + ".o $(VM_HIER_LIBS)"; of.puts("\n### Library rules from --lib-create\n"); // The rule to create .a is defined in verilated.mk, so just define dependency here. of.puts(v3Global.opt.libCreateName(false) + ": " + libCreateDeps + "\n"); From 7bfc1a00a723cd91d8d52c146b5e7b45844a2ed6 Mon Sep 17 00:00:00 2001 From: Wilson Snyder Date: Thu, 14 Apr 2022 09:14:44 -0400 Subject: [PATCH 25/44] Fix tracing interfaces inside interfaces (#3309). --- Changes | 2 +- src/V3Inline.cpp | 9 +- src/V3TraceDecl.cpp | 46 +++-- test_regress/t/t_interface_ref_trace.out | 25 ++- test_regress/t/t_interface_ref_trace.v | 6 + test_regress/t/t_interface_ref_trace_fst.out | 172 ++++++++++-------- .../t/t_interface_ref_trace_fst_sc.out | 172 ++++++++++-------- 7 files changed, 261 insertions(+), 171 deletions(-) diff --git a/Changes b/Changes index 91b355795..12f8458f1 100644 --- a/Changes +++ b/Changes @@ -18,10 +18,10 @@ Verilator 4.221 devel * Fix MSVC localtime_s (#3124). * Fix Bison 3.8.2 error (#3366). [elike-ypq] * Fix rare bug in -Oz (V3Localize) (#3286). [Geza Lore, Shunyao CAD] +* Fix tracing interfaces inside interfaces (#3309). [Kevin Millis] * Fix filenames with dots overwriting debug .vpp files (#3373). * Fix including VK_USER_OBJS in make library (#3370). [Julien Margetts] - Verilator 4.220 2022-03-12 ========================== diff --git a/src/V3Inline.cpp b/src/V3Inline.cpp index eabbca566..2c451c62c 100644 --- a/src/V3Inline.cpp +++ b/src/V3Inline.cpp @@ -647,7 +647,11 @@ private: m_scope += "__DOT__" + nodep->name(); } - if (AstModule* const modp = VN_CAST(nodep->modp(), Module)) { + if (VN_IS(nodep->modp(), Iface)) { + nodep->addIntfRefp(new AstIntfRef{nodep->fileline(), m_scope}); + } + { + AstNodeModule* const modp = nodep->modp(); // Pass Cell pointers down to the next module for (AstPin* pinp = nodep->pinsp(); pinp; pinp = VN_AS(pinp->nextp(), Pin)) { AstVar* const varp = pinp->modVarp(); @@ -666,9 +670,6 @@ private: } iterateChildren(modp); - } else if (VN_IS(nodep->modp(), Iface)) { - nodep->addIntfRefp(new AstIntfRef(nodep->fileline(), m_scope)); - // No need to iterate on interface cells } } virtual void visit(AstAssignVarScope* nodep) override { diff --git a/src/V3TraceDecl.cpp b/src/V3TraceDecl.cpp index 5859ff819..15669c0d1 100644 --- a/src/V3TraceDecl.cpp +++ b/src/V3TraceDecl.cpp @@ -190,6 +190,27 @@ private: std::string getScopeChar(VltTraceScope sct) { return std::string(1, (char)(0x80 + sct)); } + std::string addAboveInterface(const std::string& scopeName) { + std::string out; + // Hierarchical interfaces didn't know if interface vs module + // above them. so convert a scope string to have the interface character. + // Uses list of scopes to see what's an interface above. + size_t begin = 0; + while (true) { + const size_t end = scopeName.find(' ', begin); + if (end == string::npos) break; + const string& extra = scopeName.substr(begin, end - begin); + out += extra; + if (m_scopeSubFuncps.count(out + getScopeChar(VLT_TRACE_SCOPE_INTERFACE) + " ")) { + out += getScopeChar(VLT_TRACE_SCOPE_INTERFACE) + " "; + } else { + out += " "; + } + begin = end + 1; + } + return out; + } + void addTraceDecl(const VNumRange& arrayRange, int widthOverride) { // If !=0, is packed struct/array where basicp size // misreflects one element @@ -199,8 +220,10 @@ private: } else if (const AstBasicDType* const bdtypep = m_traValuep->dtypep()->basicp()) { bitRange = bdtypep->nrange(); } - addToSubFunc(new AstTraceDecl{m_traVscp->fileline(), m_traName, m_traVscp->varp(), - m_traValuep->cloneTree(false), bitRange, arrayRange}); + auto* const newp + = new AstTraceDecl{m_traVscp->fileline(), m_traName, m_traVscp->varp(), + m_traValuep->cloneTree(false), bitRange, arrayRange}; + addToSubFunc(newp); } void addIgnore(const char* why) { @@ -217,17 +240,14 @@ private: UASSERT_OBJ(!m_traVscp, nodep, "Should not nest"); UASSERT_OBJ(m_traName.empty(), nodep, "Should not nest"); - FileLine* const flp = nodep->fileline(); + VL_RESTORER(m_currScopep); m_currScopep = nodep; // Gather all signals under this AstScope iterateChildrenConst(nodep); // If nothing to trace in this scope, then job done - if (m_signals.empty()) { - m_currScopep = nullptr; - return; - } + if (m_signals.empty()) return; // Sort signals, first by enclosing instance, then by source location, then by name std::stable_sort(m_signals.begin(), m_signals.end(), [](const Signal& a, const Signal& b) { @@ -239,6 +259,7 @@ private: }); // Build trace initialization functions for this AstScope + FileLine* const flp = nodep->fileline(); PathAdjustor pathAdjustor{flp, [&](AstNodeStmt* stmtp) { addToSubFunc(stmtp); }}; for (const Signal& signal : m_signals) { // Adjust name prefix based on path in hierarchy @@ -278,6 +299,7 @@ private: scopeName = scopeName.substr(0, lastDot + 1); const size_t scopeLen = scopeName.length(); + UASSERT_OBJ(cellp->intfRefp(), cellp, "Interface without tracing reference"); for (AstIntfRef *irp = cellp->intfRefp(), *nextIrp; irp; irp = nextIrp) { nextIrp = VN_AS(irp->nextp(), IntfRef); @@ -288,6 +310,9 @@ private: string scopeName = AstNode::vcdName(irp->name()); if (scopeName.substr(0, 4) == "TOP ") scopeName.erase(0, 4); + // Note this insert doesn't know what above is interfaces. + // Perhaps all scopes should be changed to include the VLT_TRACE_SCOPE characters. + // Instead we fix up when printing m_scopeSubFuncps scopeName += getScopeChar(VLT_TRACE_SCOPE_INTERFACE) + ' '; m_scopeSubFuncps.emplace(scopeName, m_subFuncps); @@ -300,8 +325,6 @@ private: if (VString::startsWith(scopeName, "TOP ")) scopeName.erase(0, 4); m_scopeSubFuncps.emplace(scopeName, std::move(m_subFuncps)); } - - m_currScopep = nullptr; } virtual void visit(AstVarScope* nodep) override { UASSERT_OBJ(m_currScopep, nodep, "AstVarScope not under AstScope"); @@ -454,9 +477,10 @@ public: // Build top level trace initialization functions PathAdjustor pathAdjustor{flp, [&](AstNodeStmt* stmtp) { addToTopFunc(stmtp); }}; for (const auto& item : m_scopeSubFuncps) { + const std::string scopeName = item.first; + const std::string scopeNameInterfaced = addAboveInterface(scopeName); // Adjust name prefix based on path in hierarchy - pathAdjustor.adjust(item.first); - + pathAdjustor.adjust(scopeNameInterfaced); // Call all sub functions for this path for (AstCFunc* const subFuncp : item.second) { AstCCall* const callp = new AstCCall{flp, subFuncp}; diff --git a/test_regress/t/t_interface_ref_trace.out b/test_regress/t/t_interface_ref_trace.out index 67a6e327b..5e2a4c6b1 100644 --- a/test_regress/t/t_interface_ref_trace.out +++ b/test_regress/t/t_interface_ref_trace.out @@ -1,7 +1,6 @@ $version Generated by VerilatedVcd $end -$date Wed Dec 4 07:47:51 2019 - $end -$timescale 1ps $end +$date Thu Apr 14 07:06:40 2022 $end +$timescale 1ps $end $scope module top $end $var wire 1 0 clk $end @@ -57,6 +56,10 @@ $timescale 1ps $end $var wire 1 0 clk $end $var wire 32 # cyc [31:0] $end $var wire 32 * value [31:0] $end + $scope interface inner $end + $var wire 32 # cyc [31:0] $end + $var wire 32 3 value [31:0] $end + $upscope $end $scope struct the_struct $end $var wire 32 + val100 [31:0] $end $var wire 32 , val200 [31:0] $end @@ -130,6 +133,10 @@ $timescale 1ps $end $var wire 1 0 clk $end $var wire 32 # cyc [31:0] $end $var wire 32 - value [31:0] $end + $scope interface inner $end + $var wire 32 # cyc [31:0] $end + $var wire 32 4 value [31:0] $end + $upscope $end $scope struct the_struct $end $var wire 32 . val100 [31:0] $end $var wire 32 / val200 [31:0] $end @@ -180,6 +187,10 @@ $timescale 1ps $end $var wire 1 0 clk $end $var wire 32 # cyc [31:0] $end $var wire 32 $ value [31:0] $end + $scope interface inner $end + $var wire 32 # cyc [31:0] $end + $var wire 32 1 value [31:0] $end + $upscope $end $scope struct the_struct $end $var wire 32 % val100 [31:0] $end $var wire 32 & val200 [31:0] $end @@ -189,6 +200,10 @@ $timescale 1ps $end $var wire 1 0 clk $end $var wire 32 # cyc [31:0] $end $var wire 32 ' value [31:0] $end + $scope interface inner $end + $var wire 32 # cyc [31:0] $end + $var wire 32 2 value [31:0] $end + $upscope $end $scope struct the_struct $end $var wire 32 ( val100 [31:0] $end $var wire 32 ) val200 [31:0] $end @@ -236,6 +251,10 @@ b00000000000000000000001111101010 - b00000000000000000000010001001110 . b00000000000000000000010010110010 / 00 +b00000000000000000000000000000000 1 +b00000000000000000000000000000000 2 +b00000000000000000000000000000000 3 +b00000000000000000000000000000000 4 #10 b00000000000000000000000000000001 # b00000000000000000000000000000010 $ diff --git a/test_regress/t/t_interface_ref_trace.v b/test_regress/t/t_interface_ref_trace.v index a3fabda04..0f2577d47 100644 --- a/test_regress/t/t_interface_ref_trace.v +++ b/test_regress/t/t_interface_ref_trace.v @@ -11,10 +11,16 @@ typedef struct packed { integer val200; } struct_t; +// This interface is not connected to any cells +interface ifc_inner(input integer cyc); + integer value; +endinterface + interface ifc (input logic clk, input integer cyc); integer value; struct_t the_struct; + ifc_inner inner (.*); endinterface module t (/*AUTOARG*/ diff --git a/test_regress/t/t_interface_ref_trace_fst.out b/test_regress/t/t_interface_ref_trace_fst.out index f26bb0647..858d03801 100644 --- a/test_regress/t/t_interface_ref_trace_fst.out +++ b/test_regress/t/t_interface_ref_trace_fst.out @@ -1,5 +1,5 @@ $date - Tue Feb 22 23:55:07 2022 + Thu Apr 14 07:06:50 2022 $end $version @@ -59,6 +59,10 @@ $upscope $end $upscope $end $upscope $end $scope interface intf_in_sub_all $end +$scope interface inner $end +$var wire 32 " cyc [31:0] $end +$var integer 32 , value [31:0] $end +$upscope $end $var wire 1 ! clk $end $var wire 32 " cyc [31:0] $end $var integer 32 ) value [31:0] $end @@ -113,10 +117,10 @@ $scope module ac3 $end $scope interface intf_for_check $end $var wire 1 ! clk $end $var wire 32 " cyc [31:0] $end -$var integer 32 , value [31:0] $end +$var integer 32 - value [31:0] $end $scope struct the_struct $end -$var logic 32 - val100 [31:0] $end -$var logic 32 . val200 [31:0] $end +$var logic 32 . val100 [31:0] $end +$var logic 32 / val200 [31:0] $end $upscope $end $upscope $end $upscope $end @@ -124,20 +128,24 @@ $scope module as3 $end $scope interface intf_for_struct $end $var wire 1 ! clk $end $var wire 32 " cyc [31:0] $end -$var integer 32 , value [31:0] $end +$var integer 32 - value [31:0] $end $scope struct the_struct $end -$var logic 32 - val100 [31:0] $end -$var logic 32 . val200 [31:0] $end +$var logic 32 . val100 [31:0] $end +$var logic 32 / val200 [31:0] $end $upscope $end $upscope $end $upscope $end $scope interface intf_in_sub_all $end +$scope interface inner $end +$var wire 32 " cyc [31:0] $end +$var integer 32 0 value [31:0] $end +$upscope $end $var wire 1 ! clk $end $var wire 32 " cyc [31:0] $end -$var integer 32 , value [31:0] $end +$var integer 32 - value [31:0] $end $scope struct the_struct $end -$var logic 32 - val100 [31:0] $end -$var logic 32 . val200 [31:0] $end +$var logic 32 . val100 [31:0] $end +$var logic 32 / val200 [31:0] $end $upscope $end $upscope $end $scope interface intf_one $end @@ -182,6 +190,10 @@ $upscope $end $upscope $end $upscope $end $scope interface intf_1 $end +$scope interface inner $end +$var wire 32 " cyc [31:0] $end +$var integer 32 1 value [31:0] $end +$upscope $end $var wire 1 ! clk $end $var wire 32 " cyc [31:0] $end $var integer 32 # value [31:0] $end @@ -191,6 +203,10 @@ $var logic 32 % val200 [31:0] $end $upscope $end $upscope $end $scope interface intf_2 $end +$scope interface inner $end +$var wire 32 " cyc [31:0] $end +$var integer 32 2 value [31:0] $end +$upscope $end $var wire 1 ! clk $end $var wire 32 " cyc [31:0] $end $var integer 32 & value [31:0] $end @@ -226,9 +242,13 @@ $upscope $end $enddefinitions $end #0 $dumpvars -b00000000000000000000010010110010 . -b00000000000000000000010001001110 - -b00000000000000000000001111101010 , +b00000000000000000000000000000000 2 +b00000000000000000000000000000000 1 +b00000000000000000000000000000000 0 +b00000000000000000000010010110010 / +b00000000000000000000010001001110 . +b00000000000000000000001111101010 - +b00000000000000000000000000000000 , b00000000000000000000010010110001 + b00000000000000000000010001001101 * b00000000000000000000001111101001 ) @@ -253,16 +273,16 @@ b00000000000000000000000011001011 ( b00000000000000000000001111101010 ) b00000000000000000000010001001110 * b00000000000000000000010010110010 + -b00000000000000000000001111101011 , -b00000000000000000000010001001111 - -b00000000000000000000010010110011 . +b00000000000000000000001111101011 - +b00000000000000000000010001001111 . +b00000000000000000000010010110011 / #15 0! #20 1! -b00000000000000000000010010110100 . -b00000000000000000000010001010000 - -b00000000000000000000001111101100 , +b00000000000000000000010010110100 / +b00000000000000000000010001010000 . +b00000000000000000000001111101100 - b00000000000000000000010010110011 + b00000000000000000000010001001111 * b00000000000000000000001111101011 ) @@ -287,16 +307,16 @@ b00000000000000000000000011001101 ( b00000000000000000000001111101100 ) b00000000000000000000010001010000 * b00000000000000000000010010110100 + -b00000000000000000000001111101101 , -b00000000000000000000010001010001 - -b00000000000000000000010010110101 . +b00000000000000000000001111101101 - +b00000000000000000000010001010001 . +b00000000000000000000010010110101 / #35 0! #40 1! -b00000000000000000000010010110110 . -b00000000000000000000010001010010 - -b00000000000000000000001111101110 , +b00000000000000000000010010110110 / +b00000000000000000000010001010010 . +b00000000000000000000001111101110 - b00000000000000000000010010110101 + b00000000000000000000010001010001 * b00000000000000000000001111101101 ) @@ -321,16 +341,16 @@ b00000000000000000000000011001111 ( b00000000000000000000001111101110 ) b00000000000000000000010001010010 * b00000000000000000000010010110110 + -b00000000000000000000001111101111 , -b00000000000000000000010001010011 - -b00000000000000000000010010110111 . +b00000000000000000000001111101111 - +b00000000000000000000010001010011 . +b00000000000000000000010010110111 / #55 0! #60 1! -b00000000000000000000010010111000 . -b00000000000000000000010001010100 - -b00000000000000000000001111110000 , +b00000000000000000000010010111000 / +b00000000000000000000010001010100 . +b00000000000000000000001111110000 - b00000000000000000000010010110111 + b00000000000000000000010001010011 * b00000000000000000000001111101111 ) @@ -355,16 +375,16 @@ b00000000000000000000000011010001 ( b00000000000000000000001111110000 ) b00000000000000000000010001010100 * b00000000000000000000010010111000 + -b00000000000000000000001111110001 , -b00000000000000000000010001010101 - -b00000000000000000000010010111001 . +b00000000000000000000001111110001 - +b00000000000000000000010001010101 . +b00000000000000000000010010111001 / #75 0! #80 1! -b00000000000000000000010010111010 . -b00000000000000000000010001010110 - -b00000000000000000000001111110010 , +b00000000000000000000010010111010 / +b00000000000000000000010001010110 . +b00000000000000000000001111110010 - b00000000000000000000010010111001 + b00000000000000000000010001010101 * b00000000000000000000001111110001 ) @@ -389,16 +409,16 @@ b00000000000000000000000011010011 ( b00000000000000000000001111110010 ) b00000000000000000000010001010110 * b00000000000000000000010010111010 + -b00000000000000000000001111110011 , -b00000000000000000000010001010111 - -b00000000000000000000010010111011 . +b00000000000000000000001111110011 - +b00000000000000000000010001010111 . +b00000000000000000000010010111011 / #95 0! #100 1! -b00000000000000000000010010111100 . -b00000000000000000000010001011000 - -b00000000000000000000001111110100 , +b00000000000000000000010010111100 / +b00000000000000000000010001011000 . +b00000000000000000000001111110100 - b00000000000000000000010010111011 + b00000000000000000000010001010111 * b00000000000000000000001111110011 ) @@ -423,16 +443,16 @@ b00000000000000000000000011010101 ( b00000000000000000000001111110100 ) b00000000000000000000010001011000 * b00000000000000000000010010111100 + -b00000000000000000000001111110101 , -b00000000000000000000010001011001 - -b00000000000000000000010010111101 . +b00000000000000000000001111110101 - +b00000000000000000000010001011001 . +b00000000000000000000010010111101 / #115 0! #120 1! -b00000000000000000000010010111110 . -b00000000000000000000010001011010 - -b00000000000000000000001111110110 , +b00000000000000000000010010111110 / +b00000000000000000000010001011010 . +b00000000000000000000001111110110 - b00000000000000000000010010111101 + b00000000000000000000010001011001 * b00000000000000000000001111110101 ) @@ -457,16 +477,16 @@ b00000000000000000000000011010111 ( b00000000000000000000001111110110 ) b00000000000000000000010001011010 * b00000000000000000000010010111110 + -b00000000000000000000001111110111 , -b00000000000000000000010001011011 - -b00000000000000000000010010111111 . +b00000000000000000000001111110111 - +b00000000000000000000010001011011 . +b00000000000000000000010010111111 / #135 0! #140 1! -b00000000000000000000010011000000 . -b00000000000000000000010001011100 - -b00000000000000000000001111111000 , +b00000000000000000000010011000000 / +b00000000000000000000010001011100 . +b00000000000000000000001111111000 - b00000000000000000000010010111111 + b00000000000000000000010001011011 * b00000000000000000000001111110111 ) @@ -491,16 +511,16 @@ b00000000000000000000000011011001 ( b00000000000000000000001111111000 ) b00000000000000000000010001011100 * b00000000000000000000010011000000 + -b00000000000000000000001111111001 , -b00000000000000000000010001011101 - -b00000000000000000000010011000001 . +b00000000000000000000001111111001 - +b00000000000000000000010001011101 . +b00000000000000000000010011000001 / #155 0! #160 1! -b00000000000000000000010011000010 . -b00000000000000000000010001011110 - -b00000000000000000000001111111010 , +b00000000000000000000010011000010 / +b00000000000000000000010001011110 . +b00000000000000000000001111111010 - b00000000000000000000010011000001 + b00000000000000000000010001011101 * b00000000000000000000001111111001 ) @@ -525,16 +545,16 @@ b00000000000000000000000011011011 ( b00000000000000000000001111111010 ) b00000000000000000000010001011110 * b00000000000000000000010011000010 + -b00000000000000000000001111111011 , -b00000000000000000000010001011111 - -b00000000000000000000010011000011 . +b00000000000000000000001111111011 - +b00000000000000000000010001011111 . +b00000000000000000000010011000011 / #175 0! #180 1! -b00000000000000000000010011000100 . -b00000000000000000000010001100000 - -b00000000000000000000001111111100 , +b00000000000000000000010011000100 / +b00000000000000000000010001100000 . +b00000000000000000000001111111100 - b00000000000000000000010011000011 + b00000000000000000000010001011111 * b00000000000000000000001111111011 ) @@ -559,16 +579,16 @@ b00000000000000000000000011011101 ( b00000000000000000000001111111100 ) b00000000000000000000010001100000 * b00000000000000000000010011000100 + -b00000000000000000000001111111101 , -b00000000000000000000010001100001 - -b00000000000000000000010011000101 . +b00000000000000000000001111111101 - +b00000000000000000000010001100001 . +b00000000000000000000010011000101 / #195 0! #200 1! -b00000000000000000000010011000110 . -b00000000000000000000010001100010 - -b00000000000000000000001111111110 , +b00000000000000000000010011000110 / +b00000000000000000000010001100010 . +b00000000000000000000001111111110 - b00000000000000000000010011000101 + b00000000000000000000010001100001 * b00000000000000000000001111111101 ) @@ -593,6 +613,6 @@ b00000000000000000000000011011111 ( b00000000000000000000001111111110 ) b00000000000000000000010001100010 * b00000000000000000000010011000110 + -b00000000000000000000001111111111 , -b00000000000000000000010001100011 - -b00000000000000000000010011000111 . +b00000000000000000000001111111111 - +b00000000000000000000010001100011 . +b00000000000000000000010011000111 / diff --git a/test_regress/t/t_interface_ref_trace_fst_sc.out b/test_regress/t/t_interface_ref_trace_fst_sc.out index dbbfe4f3b..7131845ae 100644 --- a/test_regress/t/t_interface_ref_trace_fst_sc.out +++ b/test_regress/t/t_interface_ref_trace_fst_sc.out @@ -1,5 +1,5 @@ $date - Tue Feb 22 23:55:19 2022 + Thu Apr 14 07:06:59 2022 $end $version @@ -58,6 +58,10 @@ $upscope $end $upscope $end $upscope $end $scope interface intf_in_sub_all $end +$scope interface inner $end +$var wire 32 " cyc [31:0] $end +$var integer 32 , value [31:0] $end +$upscope $end $var wire 1 ! clk $end $var wire 32 " cyc [31:0] $end $var integer 32 ) value [31:0] $end @@ -112,10 +116,10 @@ $scope module ac3 $end $scope interface intf_for_check $end $var wire 1 ! clk $end $var wire 32 " cyc [31:0] $end -$var integer 32 , value [31:0] $end +$var integer 32 - value [31:0] $end $scope struct the_struct $end -$var logic 32 - val100 [31:0] $end -$var logic 32 . val200 [31:0] $end +$var logic 32 . val100 [31:0] $end +$var logic 32 / val200 [31:0] $end $upscope $end $upscope $end $upscope $end @@ -123,20 +127,24 @@ $scope module as3 $end $scope interface intf_for_struct $end $var wire 1 ! clk $end $var wire 32 " cyc [31:0] $end -$var integer 32 , value [31:0] $end +$var integer 32 - value [31:0] $end $scope struct the_struct $end -$var logic 32 - val100 [31:0] $end -$var logic 32 . val200 [31:0] $end +$var logic 32 . val100 [31:0] $end +$var logic 32 / val200 [31:0] $end $upscope $end $upscope $end $upscope $end $scope interface intf_in_sub_all $end +$scope interface inner $end +$var wire 32 " cyc [31:0] $end +$var integer 32 0 value [31:0] $end +$upscope $end $var wire 1 ! clk $end $var wire 32 " cyc [31:0] $end -$var integer 32 , value [31:0] $end +$var integer 32 - value [31:0] $end $scope struct the_struct $end -$var logic 32 - val100 [31:0] $end -$var logic 32 . val200 [31:0] $end +$var logic 32 . val100 [31:0] $end +$var logic 32 / val200 [31:0] $end $upscope $end $upscope $end $scope interface intf_one $end @@ -181,6 +189,10 @@ $upscope $end $upscope $end $upscope $end $scope interface intf_1 $end +$scope interface inner $end +$var wire 32 " cyc [31:0] $end +$var integer 32 1 value [31:0] $end +$upscope $end $var wire 1 ! clk $end $var wire 32 " cyc [31:0] $end $var integer 32 # value [31:0] $end @@ -190,6 +202,10 @@ $var logic 32 % val200 [31:0] $end $upscope $end $upscope $end $scope interface intf_2 $end +$scope interface inner $end +$var wire 32 " cyc [31:0] $end +$var integer 32 2 value [31:0] $end +$upscope $end $var wire 1 ! clk $end $var wire 32 " cyc [31:0] $end $var integer 32 & value [31:0] $end @@ -225,9 +241,13 @@ $upscope $end $enddefinitions $end #0 $dumpvars -b00000000000000000000010010110010 . -b00000000000000000000010001001110 - -b00000000000000000000001111101010 , +b00000000000000000000000000000000 2 +b00000000000000000000000000000000 1 +b00000000000000000000000000000000 0 +b00000000000000000000010010110010 / +b00000000000000000000010001001110 . +b00000000000000000000001111101010 - +b00000000000000000000000000000000 , b00000000000000000000010010110001 + b00000000000000000000010001001101 * b00000000000000000000001111101001 ) @@ -252,9 +272,9 @@ b00000000000000000000000011001011 ( b00000000000000000000001111101010 ) b00000000000000000000010001001110 * b00000000000000000000010010110010 + -b00000000000000000000001111101011 , -b00000000000000000000010001001111 - -b00000000000000000000010010110011 . +b00000000000000000000001111101011 - +b00000000000000000000010001001111 . +b00000000000000000000010010110011 / #11 #12 #13 @@ -267,9 +287,9 @@ b00000000000000000000010010110011 . #19 #20 1! -b00000000000000000000010010110100 . -b00000000000000000000010001010000 - -b00000000000000000000001111101100 , +b00000000000000000000010010110100 / +b00000000000000000000010001010000 . +b00000000000000000000001111101100 - b00000000000000000000010010110011 + b00000000000000000000010001001111 * b00000000000000000000001111101011 ) @@ -302,9 +322,9 @@ b00000000000000000000000011001101 ( b00000000000000000000001111101100 ) b00000000000000000000010001010000 * b00000000000000000000010010110100 + -b00000000000000000000001111101101 , -b00000000000000000000010001010001 - -b00000000000000000000010010110101 . +b00000000000000000000001111101101 - +b00000000000000000000010001010001 . +b00000000000000000000010010110101 / #31 #32 #33 @@ -317,9 +337,9 @@ b00000000000000000000010010110101 . #39 #40 1! -b00000000000000000000010010110110 . -b00000000000000000000010001010010 - -b00000000000000000000001111101110 , +b00000000000000000000010010110110 / +b00000000000000000000010001010010 . +b00000000000000000000001111101110 - b00000000000000000000010010110101 + b00000000000000000000010001010001 * b00000000000000000000001111101101 ) @@ -352,9 +372,9 @@ b00000000000000000000000011001111 ( b00000000000000000000001111101110 ) b00000000000000000000010001010010 * b00000000000000000000010010110110 + -b00000000000000000000001111101111 , -b00000000000000000000010001010011 - -b00000000000000000000010010110111 . +b00000000000000000000001111101111 - +b00000000000000000000010001010011 . +b00000000000000000000010010110111 / #51 #52 #53 @@ -367,9 +387,9 @@ b00000000000000000000010010110111 . #59 #60 1! -b00000000000000000000010010111000 . -b00000000000000000000010001010100 - -b00000000000000000000001111110000 , +b00000000000000000000010010111000 / +b00000000000000000000010001010100 . +b00000000000000000000001111110000 - b00000000000000000000010010110111 + b00000000000000000000010001010011 * b00000000000000000000001111101111 ) @@ -402,9 +422,9 @@ b00000000000000000000000011010001 ( b00000000000000000000001111110000 ) b00000000000000000000010001010100 * b00000000000000000000010010111000 + -b00000000000000000000001111110001 , -b00000000000000000000010001010101 - -b00000000000000000000010010111001 . +b00000000000000000000001111110001 - +b00000000000000000000010001010101 . +b00000000000000000000010010111001 / #71 #72 #73 @@ -417,9 +437,9 @@ b00000000000000000000010010111001 . #79 #80 1! -b00000000000000000000010010111010 . -b00000000000000000000010001010110 - -b00000000000000000000001111110010 , +b00000000000000000000010010111010 / +b00000000000000000000010001010110 . +b00000000000000000000001111110010 - b00000000000000000000010010111001 + b00000000000000000000010001010101 * b00000000000000000000001111110001 ) @@ -452,9 +472,9 @@ b00000000000000000000000011010011 ( b00000000000000000000001111110010 ) b00000000000000000000010001010110 * b00000000000000000000010010111010 + -b00000000000000000000001111110011 , -b00000000000000000000010001010111 - -b00000000000000000000010010111011 . +b00000000000000000000001111110011 - +b00000000000000000000010001010111 . +b00000000000000000000010010111011 / #91 #92 #93 @@ -467,9 +487,9 @@ b00000000000000000000010010111011 . #99 #100 1! -b00000000000000000000010010111100 . -b00000000000000000000010001011000 - -b00000000000000000000001111110100 , +b00000000000000000000010010111100 / +b00000000000000000000010001011000 . +b00000000000000000000001111110100 - b00000000000000000000010010111011 + b00000000000000000000010001010111 * b00000000000000000000001111110011 ) @@ -502,9 +522,9 @@ b00000000000000000000000011010101 ( b00000000000000000000001111110100 ) b00000000000000000000010001011000 * b00000000000000000000010010111100 + -b00000000000000000000001111110101 , -b00000000000000000000010001011001 - -b00000000000000000000010010111101 . +b00000000000000000000001111110101 - +b00000000000000000000010001011001 . +b00000000000000000000010010111101 / #111 #112 #113 @@ -517,9 +537,9 @@ b00000000000000000000010010111101 . #119 #120 1! -b00000000000000000000010010111110 . -b00000000000000000000010001011010 - -b00000000000000000000001111110110 , +b00000000000000000000010010111110 / +b00000000000000000000010001011010 . +b00000000000000000000001111110110 - b00000000000000000000010010111101 + b00000000000000000000010001011001 * b00000000000000000000001111110101 ) @@ -552,9 +572,9 @@ b00000000000000000000000011010111 ( b00000000000000000000001111110110 ) b00000000000000000000010001011010 * b00000000000000000000010010111110 + -b00000000000000000000001111110111 , -b00000000000000000000010001011011 - -b00000000000000000000010010111111 . +b00000000000000000000001111110111 - +b00000000000000000000010001011011 . +b00000000000000000000010010111111 / #131 #132 #133 @@ -567,9 +587,9 @@ b00000000000000000000010010111111 . #139 #140 1! -b00000000000000000000010011000000 . -b00000000000000000000010001011100 - -b00000000000000000000001111111000 , +b00000000000000000000010011000000 / +b00000000000000000000010001011100 . +b00000000000000000000001111111000 - b00000000000000000000010010111111 + b00000000000000000000010001011011 * b00000000000000000000001111110111 ) @@ -602,9 +622,9 @@ b00000000000000000000000011011001 ( b00000000000000000000001111111000 ) b00000000000000000000010001011100 * b00000000000000000000010011000000 + -b00000000000000000000001111111001 , -b00000000000000000000010001011101 - -b00000000000000000000010011000001 . +b00000000000000000000001111111001 - +b00000000000000000000010001011101 . +b00000000000000000000010011000001 / #151 #152 #153 @@ -617,9 +637,9 @@ b00000000000000000000010011000001 . #159 #160 1! -b00000000000000000000010011000010 . -b00000000000000000000010001011110 - -b00000000000000000000001111111010 , +b00000000000000000000010011000010 / +b00000000000000000000010001011110 . +b00000000000000000000001111111010 - b00000000000000000000010011000001 + b00000000000000000000010001011101 * b00000000000000000000001111111001 ) @@ -652,9 +672,9 @@ b00000000000000000000000011011011 ( b00000000000000000000001111111010 ) b00000000000000000000010001011110 * b00000000000000000000010011000010 + -b00000000000000000000001111111011 , -b00000000000000000000010001011111 - -b00000000000000000000010011000011 . +b00000000000000000000001111111011 - +b00000000000000000000010001011111 . +b00000000000000000000010011000011 / #171 #172 #173 @@ -667,9 +687,9 @@ b00000000000000000000010011000011 . #179 #180 1! -b00000000000000000000010011000100 . -b00000000000000000000010001100000 - -b00000000000000000000001111111100 , +b00000000000000000000010011000100 / +b00000000000000000000010001100000 . +b00000000000000000000001111111100 - b00000000000000000000010011000011 + b00000000000000000000010001011111 * b00000000000000000000001111111011 ) @@ -702,9 +722,9 @@ b00000000000000000000000011011101 ( b00000000000000000000001111111100 ) b00000000000000000000010001100000 * b00000000000000000000010011000100 + -b00000000000000000000001111111101 , -b00000000000000000000010001100001 - -b00000000000000000000010011000101 . +b00000000000000000000001111111101 - +b00000000000000000000010001100001 . +b00000000000000000000010011000101 / #191 #192 #193 @@ -717,9 +737,9 @@ b00000000000000000000010011000101 . #199 #200 1! -b00000000000000000000010011000110 . -b00000000000000000000010001100010 - -b00000000000000000000001111111110 , +b00000000000000000000010011000110 / +b00000000000000000000010001100010 . +b00000000000000000000001111111110 - b00000000000000000000010011000101 + b00000000000000000000010001100001 * b00000000000000000000001111111101 ) @@ -752,9 +772,9 @@ b00000000000000000000000011011111 ( b00000000000000000000001111111110 ) b00000000000000000000010001100010 * b00000000000000000000010011000110 + -b00000000000000000000001111111111 , -b00000000000000000000010001100011 - -b00000000000000000000010011000111 . +b00000000000000000000001111111111 - +b00000000000000000000010001100011 . +b00000000000000000000010011000111 / #211 #212 #213 From 880a9be3b10763b1d0b68414c1fa02700b3377d2 Mon Sep 17 00:00:00 2001 From: HungMingWu Date: Tue, 19 Apr 2022 01:03:56 +0800 Subject: [PATCH 26/44] Internal: Add C++20ish reverse_view for range loops. No functional change (#3388). Signed-off-by: HungMingWu --- include/verilated_types.h | 8 ++++---- include/verilatedos.h | 13 +++++++++++++ src/V3EmitMk.cpp | 4 ++-- src/V3Inline.cpp | 3 +-- src/V3LinkJump.cpp | 8 ++++---- src/V3ParseSym.h | 3 +-- src/V3Partition.cpp | 12 ++++++------ src/V3Simulate.h | 6 +++--- 8 files changed, 34 insertions(+), 23 deletions(-) diff --git a/include/verilated_types.h b/include/verilated_types.h index 43bad0b4b..8e8da1941 100644 --- a/include/verilated_types.h +++ b/include/verilated_types.h @@ -410,16 +410,16 @@ public: } template VlQueue find_last(Func with_func) const { IData index = m_deque.size() - 1; - for (auto it = m_deque.rbegin(); it != m_deque.rend(); ++it) { - if (with_func(index, *it)) return VlQueue::cons(*it); + for (auto& item : vlstd::reverse_view(m_deque)) { + if (with_func(index, item)) return VlQueue::cons(item); --index; } return VlQueue{}; } template VlQueue find_last_index(Func with_func) const { IData index = m_deque.size() - 1; - for (auto it = m_deque.rbegin(); it != m_deque.rend(); ++it) { - if (with_func(index, *it)) return VlQueue::cons(index); + for (auto& item : vlstd::reverse_view(m_deque)) { + if (with_func(index, item)) return VlQueue::cons(index); --index; } return VlQueue{}; diff --git a/include/verilatedos.h b/include/verilatedos.h index 797ffab99..28412cac4 100644 --- a/include/verilatedos.h +++ b/include/verilatedos.h @@ -521,6 +521,19 @@ using ssize_t = uint32_t; ///< signed size_t; returned from read() // Conversions namespace vlstd { + +template struct reverse_wrapper { + const T& m_v; + + explicit reverse_wrapper(const T& a_v) + : m_v(a_v) {} + inline auto begin() -> decltype(m_v.rbegin()) { return m_v.rbegin(); } + inline auto end() -> decltype(m_v.rend()) { return m_v.rend(); } +}; + +// C++20's std::ranges::reverse_view +template reverse_wrapper reverse_view(const T& v) { return reverse_wrapper(v); } + // C++17's std::as_const template T const& as_const(T& v) { return v; } }; // namespace vlstd diff --git a/src/V3EmitMk.cpp b/src/V3EmitMk.cpp index a39c3f3ee..ce75cb136 100644 --- a/src/V3EmitMk.cpp +++ b/src/V3EmitMk.cpp @@ -333,8 +333,8 @@ class EmitMkHierVerilation final { const V3HierBlockPlan::HierVector blocks = m_planp->hierBlocksSorted(); // leaf comes first // List in order of leaf-last order so that linker can resolve dependency - for (auto it = blocks.rbegin(); it != blocks.rend(); ++it) { - of.puts("\t" + (*it)->hierLib(true) + " \\\n"); + for (auto& block : vlstd::reverse_view(blocks)) { + of.puts("\t" + block->hierLib(true) + " \\\n"); } of.puts("\n"); diff --git a/src/V3Inline.cpp b/src/V3Inline.cpp index 2c451c62c..c882b10c3 100644 --- a/src/V3Inline.cpp +++ b/src/V3Inline.cpp @@ -190,8 +190,7 @@ private: // Iterate through all modules in bottom-up order. // Make a final inlining decision for each. - for (auto it = m_allMods.rbegin(); it != m_allMods.rend(); ++it) { - AstNodeModule* const modp = *it; + for (AstNodeModule* const modp : vlstd::reverse_view(m_allMods)) { // If we're going to inline some modules into this one, // update user4 (statement count) to reflect that: diff --git a/src/V3LinkJump.cpp b/src/V3LinkJump.cpp index c46f2f82a..f7f68c28a 100644 --- a/src/V3LinkJump.cpp +++ b/src/V3LinkJump.cpp @@ -263,10 +263,10 @@ private: UINFO(8, " DISABLE " << nodep << endl); iterateChildren(nodep); AstNodeBlock* blockp = nullptr; - for (auto it = m_blockStack.rbegin(); it != m_blockStack.rend(); ++it) { - UINFO(9, " UNDERBLK " << *it << endl); - if ((*it)->name() == nodep->name()) { - blockp = *it; + for (AstNodeBlock* const stackp : vlstd::reverse_view(m_blockStack)) { + UINFO(9, " UNDERBLK " << stackp << endl); + if (stackp->name() == nodep->name()) { + blockp = stackp; break; } } diff --git a/src/V3ParseSym.h b/src/V3ParseSym.h index 4da0c735c..998dac016 100644 --- a/src/V3ParseSym.h +++ b/src/V3ParseSym.h @@ -128,8 +128,7 @@ public: } void showUpward() { // LCOV_EXCL_START UINFO(1, "ParseSym Stack:\n"); - for (auto it = m_sympStack.rbegin(); it != m_sympStack.rend(); ++it) { - VSymEnt* const symp = *it; + for (VSymEnt* const symp : vlstd::reverse_view(m_sympStack)) { UINFO(1, " " << symp->nodep() << endl); } UINFO(1, "ParseSym Current: " << symCurrentp()->nodep() << endl); diff --git a/src/V3Partition.cpp b/src/V3Partition.cpp index 18ca601d7..a4177c214 100644 --- a/src/V3Partition.cpp +++ b/src/V3Partition.cpp @@ -526,9 +526,9 @@ public: } void checkRelativesCp(GraphWay way) const { const EdgeSet& edges = m_edges[way]; - for (EdgeSet::const_reverse_iterator it = edges.rbegin(); it != edges.rend(); ++it) { - const LogicMTask* const relativep = (*it).key(); - const uint32_t cachedCp = (*it).value(); + for (const auto& edge : vlstd::reverse_view(edges)) { + const LogicMTask* const relativep = edge.key(); + const uint32_t cachedCp = edge.value(); partCheckCachedScoreVsActual(cachedCp, relativep->critPathCost(way.invert()) + relativep->stepCost()); } @@ -555,12 +555,12 @@ public: // wayEdgeEndp(way, withoutp). This should take 2 iterations max. const EdgeSet& edges = m_edges[way.invert()]; uint32_t result = 0; - for (EdgeSet::const_reverse_iterator it = edges.rbegin(); it != edges.rend(); ++it) { - if ((*it).key() != withoutp->furtherp(way.invert())) { + for (const auto& edge : vlstd::reverse_view(edges)) { + if (edge.key() != withoutp->furtherp(way.invert())) { // Use the cached cost. It could be a small overestimate // due to stepping. This is consistent with critPathCost() // which also returns the cached cost. - result = (*it).value(); + result = edge.value(); break; } } diff --git a/src/V3Simulate.h b/src/V3Simulate.h index b5fbdb234..d5a7453ac 100644 --- a/src/V3Simulate.h +++ b/src/V3Simulate.h @@ -182,11 +182,11 @@ public: } m_whyNotOptimizable = why; std::ostringstream stack; - for (auto it = m_callStack.rbegin(); it != m_callStack.rend(); ++it) { - AstFuncRef* const funcp = (*it)->m_funcp; + for (auto& callstack : vlstd::reverse_view(m_callStack)) { + AstFuncRef* const funcp = callstack->m_funcp; stack << "\n " << funcp->fileline() << "... Called from " << funcp->prettyName() << "() with parameters:"; - V3TaskConnects* tconnects = (*it)->m_tconnects; + V3TaskConnects* tconnects = callstack->m_tconnects; for (V3TaskConnects::iterator conIt = tconnects->begin(); conIt != tconnects->end(); ++conIt) { AstVar* const portp = conIt->first; From 5f0e1fae7fe5bebefd4e95da3e18f0a2de1c8d41 Mon Sep 17 00:00:00 2001 From: Geza Lore Date: Fri, 22 Apr 2022 22:39:45 +0100 Subject: [PATCH 27/44] Simplify and clarify reporting of enclosing instance Rename AstNodeModule::hierName -> someInstanceName and explain that this is only used for user messages. Rename AstNode::locationStr -> instanceStr and simplify implementation. In particular, do not report an instance if we can't find a reasonable guess. --- src/V3Ast.cpp | 56 +++++++++++------------------- src/V3Ast.h | 9 ++--- src/V3Error.cpp | 8 ++--- src/V3Error.h | 2 +- src/V3FileLine.cpp | 6 ++-- src/V3FileLine.h | 2 +- src/V3Hasher.cpp | 3 +- src/V3Param.cpp | 19 +++++----- test_regress/t/t_force_bad_rw.out | 1 - test_regress/t/t_fuzz_eqne_bad.out | 1 - 10 files changed, 46 insertions(+), 61 deletions(-) diff --git a/src/V3Ast.cpp b/src/V3Ast.cpp index 5a18c98ee..1bd2cc14e 100644 --- a/src/V3Ast.cpp +++ b/src/V3Ast.cpp @@ -1135,49 +1135,33 @@ void AstNode::v3errorEndFatal(std::ostringstream& str) const { VL_UNREACHABLE } -string AstNode::locationStr() const { - string str = "... In instance "; - const AstNode* backp = this; - int itmax = 10000; // Max iterations before giving up on location search - while (backp) { - if (VL_UNCOVERABLE(--itmax < 0)) { - // Likely some circular back link, and V3Ast is trying to report a low-level error - UINFO(1, "Ran out of iterations finding locationStr on " << backp << endl); - return ""; // LCOV_EXCL_LINE - } - const AstScope* scopep; - if ((scopep = VN_CAST(backp, Scope))) { - // The design is flattened and there are no useful scopes - // This is probably because of inlining - if (scopep->isTop()) break; +string AstNode::instanceStr() const { + // Max iterations before giving up on location search, + // in case we have some circular reference bug. + constexpr unsigned maxIterations = 10000; + unsigned iterCount = 0; - str += scopep->prettyName(); - return str; + for (const AstNode* backp = this; backp; backp = backp->backp(), ++iterCount) { + if (VL_UNCOVERABLE(iterCount >= maxIterations)) return ""; // LCOV_EXCL_LINE + + // Prefer the enclosing scope, if there is one. This is always under the enclosing module, + // so just pick it up when encountered + if (const AstScope* const scopep = VN_CAST(backp, Scope)) { + return scopep->isTop() ? "" : "... In instance " + scopep->prettyName(); } - backp = backp->backp(); - } - backp = this; - while (backp) { - const AstModule* modp; - const AstNodeVarRef* nvrp; - if ((modp = VN_CAST(backp, Module)) && !modp->hierName().empty()) { - str += modp->hierName(); - return str; - } else if ((nvrp = VN_CAST(backp, NodeVarRef))) { - const string prettyName = nvrp->prettyName(); - // VarRefs have not been flattened yet and do not contain location information - if (prettyName != nvrp->name()) { - str += prettyName; - return str; - } + + // If scopes don't exist, report an example instance of the enclosing module + if (const AstModule* const modp = VN_CAST(backp, Module)) { + const string instanceName = modp->someInstanceName(); + return instanceName.empty() ? "" : "... In instance " + instanceName; } - backp = backp->backp(); } + return ""; } void AstNode::v3errorEnd(std::ostringstream& str) const { if (!m_fileline) { - V3Error::v3errorEnd(str, locationStr()); + V3Error::v3errorEnd(str, instanceStr()); } else { std::ostringstream nsstr; nsstr << str.str(); @@ -1187,7 +1171,7 @@ void AstNode::v3errorEnd(std::ostringstream& str) const { const_cast(this)->dump(nsstr); nsstr << endl; } - m_fileline->v3errorEnd(nsstr, locationStr()); + m_fileline->v3errorEnd(nsstr, instanceStr()); } } diff --git a/src/V3Ast.h b/src/V3Ast.h index 1e717b6e5..9ddf48e43 100644 --- a/src/V3Ast.h +++ b/src/V3Ast.h @@ -1447,7 +1447,7 @@ private: bool gateOnly); void deleteTreeIter(); void deleteNode(); - string locationStr() const; + string instanceStr() const; public: static void relinkOneLink(AstNode*& pointpr, AstNode* newp); @@ -3077,7 +3077,8 @@ class AstNodeModule VL_NOT_FINAL : public AstNode { private: string m_name; // Name of the module const string m_origName; // Name of the module, ignoring name() changes, for dot lookup - string m_hierName; // Hierarchical name for errors, etc. + string m_someInstanceName; // Hierarchical name of some arbitrary instance of this module. + // Used for user messages only. bool m_modPublic : 1; // Module has public references bool m_modTrace : 1; // Tracing this module bool m_inLibrary : 1; // From a library, no error if not used, never top level @@ -3119,8 +3120,8 @@ public: // ACCESSORS virtual void name(const string& name) override { m_name = name; } virtual string origName() const override { return m_origName; } - string hierName() const { return m_hierName; } - void hierName(const string& hierName) { m_hierName = hierName; } + string someInstanceName() const { return m_someInstanceName; } + void someInstanceName(const string& name) { m_someInstanceName = name; } bool inLibrary() const { return m_inLibrary; } void inLibrary(bool flag) { m_inLibrary = flag; } void level(int level) { m_level = level; } diff --git a/src/V3Error.cpp b/src/V3Error.cpp index 9452c9ff8..1f1f8d08f 100644 --- a/src/V3Error.cpp +++ b/src/V3Error.cpp @@ -183,7 +183,7 @@ void V3Error::suppressThisWarning() { string V3Error::warnMore() { return string(msgPrefix().size(), ' '); } -void V3Error::v3errorEnd(std::ostringstream& sstr, const string& locationStr) { +void V3Error::v3errorEnd(std::ostringstream& sstr, const string& extra) { #if defined(__COVERITY__) || defined(__cppcheck__) if (s_errorCode == V3ErrorCode::EC_FATAL) __coverity_panic__(x); #endif @@ -209,10 +209,10 @@ void V3Error::v3errorEnd(std::ostringstream& sstr, const string& locationStr) { // Suppress duplicate messages if (s_messages.find(msg) != s_messages.end()) return; s_messages.insert(msg); - if (!locationStr.empty()) { - const string locationMsg = warnMore() + locationStr + "\n"; + if (!extra.empty()) { + const string extraMsg = warnMore() + extra + "\n"; const size_t pos = msg.find('\n'); - msg.insert(pos + 1, locationMsg); + msg.insert(pos + 1, extraMsg); } // Output if ( diff --git a/src/V3Error.h b/src/V3Error.h index b0b4663d7..077260995 100644 --- a/src/V3Error.h +++ b/src/V3Error.h @@ -313,7 +313,7 @@ public: static void vlAbortOrExit(); static void vlAbort(); // static, but often overridden in classes. - static void v3errorEnd(std::ostringstream& sstr, const string& locationStr = ""); + static void v3errorEnd(std::ostringstream& sstr, const string& extra = ""); }; // Global versions, so that if the class doesn't define a operator, we get the functions anyways. diff --git a/src/V3FileLine.cpp b/src/V3FileLine.cpp index 29d99d7c4..fa5e324fe 100644 --- a/src/V3FileLine.cpp +++ b/src/V3FileLine.cpp @@ -340,15 +340,15 @@ void FileLine::modifyStateInherit(const FileLine* fromp) { } } -void FileLine::v3errorEnd(std::ostringstream& sstr, const string& locationStr) { +void FileLine::v3errorEnd(std::ostringstream& sstr, const string& extra) { std::ostringstream nsstr; if (lastLineno()) nsstr << this; nsstr << sstr.str(); nsstr << endl; std::ostringstream lstr; - if (!locationStr.empty()) { + if (!extra.empty()) { lstr << std::setw(ascii().length()) << " " - << ": " << locationStr; + << ": " << extra; } m_waive = V3Config::waive(this, V3Error::errorCode(), sstr.str()); if (warnIsOff(V3Error::errorCode()) || m_waive) { diff --git a/src/V3FileLine.h b/src/V3FileLine.h index dbc437588..1928e8f5a 100644 --- a/src/V3FileLine.h +++ b/src/V3FileLine.h @@ -245,7 +245,7 @@ public: void modifyWarnOff(V3ErrorCode code, bool flag) { warnOff(code, flag); } // OPERATORS - void v3errorEnd(std::ostringstream& str, const string& locationStr = ""); + void v3errorEnd(std::ostringstream& str, const string& extra = ""); void v3errorEndFatal(std::ostringstream& str); /// When building an error, prefix for printing continuation lines /// e.g. information referring to the same FileLine as before diff --git a/src/V3Hasher.cpp b/src/V3Hasher.cpp index 56652e647..10c53d4c8 100644 --- a/src/V3Hasher.cpp +++ b/src/V3Hasher.cpp @@ -299,9 +299,8 @@ private: m_hash += hashNodeAndIterate(nodep, HASH_DTYPE, HASH_CHILDREN, [=]() {}); } virtual void visit(AstNodeModule* nodep) override { - m_hash += hashNodeAndIterate(nodep, HASH_DTYPE, false, [=]() { + m_hash += hashNodeAndIterate(nodep, HASH_DTYPE, false, [=]() { // m_hash += nodep->origName(); - m_hash += nodep->hierName(); }); } virtual void visit(AstNodePreSel* nodep) override { diff --git a/src/V3Param.cpp b/src/V3Param.cpp index ea1936ae3..ebd55b526 100644 --- a/src/V3Param.cpp +++ b/src/V3Param.cpp @@ -761,7 +761,7 @@ class ParamProcessor final { } public: - void cellDeparam(AstCell* nodep, AstNodeModule* modp, const string& hierName) { + void cellDeparam(AstCell* nodep, AstNodeModule* modp, const string& someInstanceName) { m_modp = modp; // Cell: Check for parameters in the instantiation. // We always run this, even if no parameters, as need to look for interfaces, @@ -772,7 +772,7 @@ public: // Evaluate all module constants V3Const::constifyParamsEdit(nodep); AstNodeModule* const srcModp = nodep->modp(); - srcModp->hierName(hierName + "." + nodep->name()); + srcModp->someInstanceName(someInstanceName + "." + nodep->name()); // Make sure constification worked // Must be a separate loop, as constant conversion may have changed some pointers. @@ -857,11 +857,11 @@ class ParamVisitor final : public VNVisitor { // METHODS VL_DEBUG_FUNC; // Declare debug() - void visitCellDeparam(AstCell* nodep, const string& hierName) { + void visitCellDeparam(AstCell* nodep, const string& someInstanceName) { // Cell: Check for parameters in the instantiation. iterateChildren(nodep); UASSERT_OBJ(nodep->modp(), nodep, "Not linked?"); - m_processor.cellDeparam(nodep, m_modp, hierName); + m_processor.cellDeparam(nodep, m_modp, someInstanceName); // Remember to process the child module at the end of the module m_todoModps.emplace(nodep->modp()->level(), nodep->modp()); } @@ -877,8 +877,11 @@ class ParamVisitor final : public VNVisitor { // again m_modp = nodep; UINFO(4, " MOD " << nodep << endl); - if (m_modp->hierName().empty()) m_modp->hierName(m_modp->origName()); + if (m_modp->someInstanceName().empty()) { + m_modp->someInstanceName(m_modp->origName()); + } iterateChildren(nodep); + // Note above iterate may add to m_todoModps // // Process interface cells, then non-interface which may ref an interface cell @@ -886,13 +889,13 @@ class ParamVisitor final : public VNVisitor { for (AstCell* const cellp : m_cellps) { if ((nonIf == 0 && VN_IS(cellp->modp(), Iface)) || (nonIf == 1 && !VN_IS(cellp->modp(), Iface))) { - string fullName(m_modp->hierName()); + string someInstanceName(m_modp->someInstanceName()); if (const string* const genHierNamep = (string*)cellp->user5p()) { - fullName += *genHierNamep; + someInstanceName += *genHierNamep; cellp->user5p(nullptr); VL_DO_DANGLING(delete genHierNamep, genHierNamep); } - VL_DO_DANGLING(visitCellDeparam(cellp, fullName), cellp); + VL_DO_DANGLING(visitCellDeparam(cellp, someInstanceName), cellp); } } } diff --git a/test_regress/t/t_force_bad_rw.out b/test_regress/t/t_force_bad_rw.out index caa8482e2..0b287ff80 100644 --- a/test_regress/t/t_force_bad_rw.out +++ b/test_regress/t/t_force_bad_rw.out @@ -1,5 +1,4 @@ %Error: t/t_force_bad_rw.v:14:20: Unsupported: Signals used via read-write reference cannot be forced - : ... In instance t.unnamedblk1.unnamedblk1.index 14 | foreach (ass[index]) begin | ^~~~~ %Error: Exiting due to diff --git a/test_regress/t/t_fuzz_eqne_bad.out b/test_regress/t/t_fuzz_eqne_bad.out index 08bd37daf..a04d877ab 100644 --- a/test_regress/t/t_fuzz_eqne_bad.out +++ b/test_regress/t/t_fuzz_eqne_bad.out @@ -1,5 +1,4 @@ %Error: t/t_fuzz_eqne_bad.v:12:23: Slice operator VARREF 't.b' on non-slicable (e.g. non-vector) right-hand-side operand - : ... In instance t.b 12 | initial c = (a != &b); | ^ %Error: Exiting due to From 8189416d0c0c6de80237bf29d084f21a020f1651 Mon Sep 17 00:00:00 2001 From: Geza Lore Date: Fri, 22 Apr 2022 21:48:03 +0100 Subject: [PATCH 28/44] Partial cleanup of V3Param. No functional change. --- src/V3Param.cpp | 137 +++++++++++++++++++++++------------------------- 1 file changed, 65 insertions(+), 72 deletions(-) diff --git a/src/V3Param.cpp b/src/V3Param.cpp index ebd55b526..bfad0f84c 100644 --- a/src/V3Param.cpp +++ b/src/V3Param.cpp @@ -847,78 +847,74 @@ class ParamVisitor final : public VNVisitor { ParamProcessor m_processor; // De-parameterize a cell, build modules UnrollStateful m_unroller; // Loop unroller - AstNodeModule* m_modp = nullptr; // Current module being processed + bool m_iterateModule = false; // Iterating module body string m_generateHierName; // Generate portion of hierarchy name string m_unlinkedTxt; // Text for AstUnlinkedRef - std::deque m_cellps; // Cells left to process (in this module) - - std::multimap m_todoModps; // Modules left to process + std::deque m_cellps; // Cells left to process (in current module) // METHODS VL_DEBUG_FUNC; // Declare debug() - void visitCellDeparam(AstCell* nodep, const string& someInstanceName) { - // Cell: Check for parameters in the instantiation. - iterateChildren(nodep); - UASSERT_OBJ(nodep->modp(), nodep, "Not linked?"); - m_processor.cellDeparam(nodep, m_modp, someInstanceName); - // Remember to process the child module at the end of the module - m_todoModps.emplace(nodep->modp()->level(), nodep->modp()); - } - void visitModules() { - // Loop on all modules left to process - // Hitting a cell adds to the appropriate level of this level-sorted list, - // so since cells originally exist top->bottom we process in top->bottom order too. - while (!m_todoModps.empty()) { - const auto itm = m_todoModps.cbegin(); - AstNodeModule* const nodep = itm->second; - m_todoModps.erase(itm); - if (!nodep->user5SetOnce()) { // Process once; note clone() must clear so we do it - // again - m_modp = nodep; - UINFO(4, " MOD " << nodep << endl); - if (m_modp->someInstanceName().empty()) { - m_modp->someInstanceName(m_modp->origName()); - } - iterateChildren(nodep); + void visitCells(AstNodeModule* nodep) { + UASSERT_OBJ(!m_iterateModule, nodep, "Should not nest"); + std::multimap workQueue; + workQueue.emplace(nodep->level(), nodep); + m_generateHierName = ""; + m_iterateModule = true; - // Note above iterate may add to m_todoModps - // - // Process interface cells, then non-interface which may ref an interface cell - for (int nonIf = 0; nonIf < 2; ++nonIf) { - for (AstCell* const cellp : m_cellps) { - if ((nonIf == 0 && VN_IS(cellp->modp(), Iface)) - || (nonIf == 1 && !VN_IS(cellp->modp(), Iface))) { - string someInstanceName(m_modp->someInstanceName()); - if (const string* const genHierNamep = (string*)cellp->user5p()) { - someInstanceName += *genHierNamep; - cellp->user5p(nullptr); - VL_DO_DANGLING(delete genHierNamep, genHierNamep); - } - VL_DO_DANGLING(visitCellDeparam(cellp, someInstanceName), cellp); - } + // Visit all cells under module, recursively + do { + const auto itm = workQueue.cbegin(); + AstNodeModule* const modp = itm->second; + workQueue.erase(itm); + + // Process once; note user5 will be cleared on specialization, so we will do the + // specialized module if needed + if (modp->user5SetOnce()) continue; + + // TODO: this really should be an assert, but classes and hier_blocks are special... + if (modp->someInstanceName().empty()) modp->someInstanceName(modp->origName()); + + // Iterate the body + iterateChildren(modp); + + // Process interface cells, then non-interface cells, which may reference an interface + // cell. + for (bool doInterface : {true, false}) { + for (AstCell* const cellp : m_cellps) { + if (doInterface != VN_IS(cellp->modp(), Iface)) continue; + + // Visit parameters in the instantiation. + iterateChildren(cellp); + + // Update path + string someInstanceName(modp->someInstanceName()); + if (const string* const genHierNamep = cellp->user5u().to()) { + someInstanceName += *genHierNamep; + cellp->user5p(nullptr); + VL_DO_DANGLING(delete genHierNamep, genHierNamep); } + + // Apply parameter specialization + m_processor.cellDeparam(cellp, modp, someInstanceName); + + // Add the (now potentially specialized) child module to the work queue + workQueue.emplace(cellp->modp()->level(), cellp->modp()); } - m_cellps.clear(); - m_modp = nullptr; - UINFO(4, " MOD-done\n"); } - } + m_cellps.clear(); + } while (!workQueue.empty()); + + m_iterateModule = false; } // VISITORS virtual void visit(AstNodeModule* nodep) override { - if (nodep->dead()) { - UINFO(4, " MOD-dead. " << nodep << endl); // Marked by LinkDot - return; - } else if (nodep->recursiveClone()) { - // Fake, made for recursive elimination - UINFO(4, " MOD-recursive-dead. " << nodep << endl); - nodep->dead(true); // So Dead checks won't count references to it - return; - } - // - if (!nodep->dead() && VN_IS(nodep, Class)) { + if (nodep->recursiveClone()) nodep->dead(true); // Fake, made for recursive elimination + if (nodep->dead()) return; // Marked by LinkDot (and above) + + // Warn on unsupported parametrised class + if (VN_IS(nodep, Class)) { for (AstNode* stmtp = nodep->stmtsp(); stmtp; stmtp = stmtp->nextp()) { if (const AstVar* const varp = VN_CAST(stmtp, Var)) { if (varp->isParam()) { @@ -927,24 +923,21 @@ class ParamVisitor final : public VNVisitor { } } } - // - if (m_modp) { + + if (m_iterateModule) { // Iterating body UINFO(4, " MOD-under-MOD. " << nodep << endl); iterateChildren(nodep); - } else if (nodep->level() <= 2 // Haven't added top yet, so level 2 is the top - || VN_IS(nodep, Class) // Nor moved classes - || VN_IS(nodep, Package)) { // Likewise haven't done wrapTopPackages yet - // Add request to END of modules left to process - m_todoModps.emplace(nodep->level(), nodep); - m_generateHierName = ""; - visitModules(); - } else if (nodep->user5()) { - UINFO(4, " MOD-done " << nodep << endl); // Already did it - } else { - // Should have been done by now, if not dead - UINFO(4, " MOD-dead? " << nodep << endl); + return; + } + + // Start traversal at root-like things + if (nodep->level() <= 2 // Haven't added top yet, so level 2 is the top + || VN_IS(nodep, Class) // Nor moved classes + || VN_IS(nodep, Package)) { // Likewise haven't done wrapTopPackages yet + visitCells(nodep); } } + virtual void visit(AstCell* nodep) override { // Must do ifaces first, so push to list and do in proper order string* const genHierNamep = new string(m_generateHierName); From 0b74e9b354057d09f57f6969bfe0d6b08af04bb9 Mon Sep 17 00:00:00 2001 From: Geza Lore Date: Sat, 23 Apr 2022 13:06:20 +0100 Subject: [PATCH 29/44] Ensure topological ordering of module list. At the end of V3Param, fix up the module list to be topologically sorted. We need to do this at the end as a later instantiation of a recursive module might instantiate an earlier specialization, which we cannot know until we processed everything. The rest of the compiler depends on the module list being topologically sorted. Fixes #3393 --- Changes | 1 + src/V3Param.cpp | 67 ++++++++++++++++++---- test_regress/t/t_recursive_module_bug_2.pl | 16 ++++++ test_regress/t/t_recursive_module_bug_2.v | 21 +++++++ 4 files changed, 95 insertions(+), 10 deletions(-) create mode 100755 test_regress/t/t_recursive_module_bug_2.pl create mode 100644 test_regress/t/t_recursive_module_bug_2.v diff --git a/Changes b/Changes index 12f8458f1..8a8a34272 100644 --- a/Changes +++ b/Changes @@ -21,6 +21,7 @@ Verilator 4.221 devel * Fix tracing interfaces inside interfaces (#3309). [Kevin Millis] * Fix filenames with dots overwriting debug .vpp files (#3373). * Fix including VK_USER_OBJS in make library (#3370). [Julien Margetts] +* Fix crash in recursive module inlining (#3393). [david-sawatzke] Verilator 4.220 2022-03-12 ========================== diff --git a/src/V3Param.cpp b/src/V3Param.cpp index bfad0f84c..607639ed9 100644 --- a/src/V3Param.cpp +++ b/src/V3Param.cpp @@ -555,14 +555,12 @@ class ParamProcessor final { cellp->v3error("Exceeded maximum --module-recursion-depth of " << v3Global.opt.moduleRecursionDepth()); } - // Keep tree sorted by level. Append to end of sub-list at the same level. This is - // important because due to the way recursive modules are handled, different - // parametrizations of the same recursive module end up with the same level (which in - // itself is a bit unfortunate). Nevertheless, as a later parametrization must not be above - // an earlier parametrization of a recursive module, it is sufficient to add to the end of - // the sub-list to keep the modules topologically sorted. + // Keep tree sorted by level. Note: Different parametrizations of the same recursive module + // end up with the same level, which we will need to fix up at the end, as we do not know + // up front how recursive modules are expanded, and a later expansion might re-use an + // earlier expansion (see t_recursive_module_bug_2). AstNodeModule* insertp = srcModp; - while (VN_IS(insertp->nextp(), NodeModule) + while (insertp->nextp() && VN_AS(insertp->nextp(), NodeModule)->level() <= newmodp->level()) { insertp = VN_AS(insertp->nextp(), NodeModule); } @@ -843,6 +841,9 @@ public: // Process parameter visitor class ParamVisitor final : public VNVisitor { + // NODE STATE + // AstNodeModule::user1 -> bool: already fixed level + // STATE ParamProcessor m_processor; // De-parameterize a cell, build modules UnrollStateful m_unroller; // Loop unroller @@ -852,6 +853,9 @@ class ParamVisitor final : public VNVisitor { string m_unlinkedTxt; // Text for AstUnlinkedRef std::deque m_cellps; // Cells left to process (in current module) + // Map from AstNodeModule to set of all AstNodeModules that instantiates it. + std::unordered_map> m_parentps; + // METHODS VL_DEBUG_FUNC; // Declare debug() @@ -900,6 +904,9 @@ class ParamVisitor final : public VNVisitor { // Add the (now potentially specialized) child module to the work queue workQueue.emplace(cellp->modp()->level(), cellp->modp()); + + // Add to the hierarchy registry + m_parentps[cellp->modp()].insert(modp); } } m_cellps.clear(); @@ -908,6 +915,18 @@ class ParamVisitor final : public VNVisitor { m_iterateModule = false; } + // Fix up level of module, based on who instantiates it + void fixLevel(AstNodeModule* modp) { + if (modp->user1SetOnce()) return; // Already fixed + if (m_parentps[modp].empty()) return; // Leave top levels alone + int maxParentLevel = 0; + for (AstNodeModule* parentp : m_parentps[modp]) { + fixLevel(parentp); // Ensure parent level is correct + maxParentLevel = std::max(maxParentLevel, parentp->level()); + } + if (modp->level() <= maxParentLevel) modp->level(maxParentLevel + 1); + } + // VISITORS virtual void visit(AstNodeModule* nodep) override { if (nodep->recursiveClone()) nodep->dead(true); // Fake, made for recursive elimination @@ -1191,10 +1210,38 @@ class ParamVisitor final : public VNVisitor { public: // CONSTRUCTORS - explicit ParamVisitor(AstNetlist* nodep) - : m_processor{nodep} { + explicit ParamVisitor(AstNetlist* netlistp) + : m_processor{netlistp} { // Relies on modules already being in top-down-order - iterate(nodep); + iterate(netlistp); + + // Re-sort module list to be in topological order and fix-up incorrect levels. We need to + // do this globally at the end due to the presence of recursive modules, which might be + // expanded in orders that reuse earlier specializations later at a lower level. + { + // Gather modules + std::vector modps; + for (AstNodeModule *modp = netlistp->modulesp(), *nextp; modp; modp = nextp) { + nextp = VN_AS(modp->nextp(), NodeModule); + modp->unlinkFrBack(); + modps.push_back(modp); + } + + // Fix-up levels + { + const VNUser1InUse user1InUse; + for (AstNodeModule* const modp : modps) fixLevel(modp); + } + + // Sort by level + std::stable_sort(modps.begin(), modps.end(), + [](const AstNodeModule* ap, const AstNodeModule* bp) { + return ap->level() < bp->level(); + }); + + // Re-insert modules + for (AstNodeModule* const modp : modps) netlistp->addModulep(modp); + } } virtual ~ParamVisitor() override = default; VL_UNCOPYABLE(ParamVisitor); diff --git a/test_regress/t/t_recursive_module_bug_2.pl b/test_regress/t/t_recursive_module_bug_2.pl new file mode 100755 index 000000000..2ef6db6a2 --- /dev/null +++ b/test_regress/t/t_recursive_module_bug_2.pl @@ -0,0 +1,16 @@ +#!/usr/bin/env perl +if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2022 by Geza Lore. This program is free software; you can +# redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +scenarios(simulator => 1); + +compile(); + +ok(1); +1; diff --git a/test_regress/t/t_recursive_module_bug_2.v b/test_regress/t/t_recursive_module_bug_2.v new file mode 100644 index 000000000..fd47d945b --- /dev/null +++ b/test_regress/t/t_recursive_module_bug_2.v @@ -0,0 +1,21 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// Copyright 2022 by Geza Lore. This program is free software; you can +// redistribute it and/or modify it under the terms of either the GNU +// Lesser General Public License Version 3 or the Perl Artistic License +// Version 2.0. + +module a #(parameter N) (); + generate if (N > 1) begin + // With N == 5, this will first expand N == 2, then expand N == 3, + // which instantiates N == 2. This requires fixing up topological order + // in V3Param. + a #(.N( N/2)) sub_lo(); + a #(.N(N-N/2)) sub_hi(); + end + endgenerate +endmodule + +module top(); + a #(.N(5)) root (); +endmodule From f1ea30f2572faca64ee2851bfe40dc95de0abd8a Mon Sep 17 00:00:00 2001 From: Geza Lore Date: Sat, 23 Apr 2022 14:03:37 +0100 Subject: [PATCH 30/44] Use iterate*Const V3EmitV visitors. No functional change. --- src/V3EmitV.cpp | 194 ++++++++++++++++++++++++------------------------ src/V3EmitV.h | 4 +- 2 files changed, 99 insertions(+), 99 deletions(-) diff --git a/src/V3EmitV.cpp b/src/V3EmitV.cpp index ecec3802e..e04c15e4d 100644 --- a/src/V3EmitV.cpp +++ b/src/V3EmitV.cpp @@ -52,10 +52,10 @@ class EmitVBaseVisitor VL_NOT_FINAL : public EmitCBaseVisitor { } // VISITORS - virtual void visit(AstNetlist* nodep) override { iterateAndNextNull(nodep->modulesp()); } + virtual void visit(AstNetlist* nodep) override { iterateAndNextConstNull(nodep->modulesp()); } virtual void visit(AstNodeModule* nodep) override { putfs(nodep, nodep->verilogKwd() + " " + prefixNameProtect(nodep) + ";\n"); - iterateChildren(nodep); + iterateChildrenConst(nodep); putqs(nodep, "end" + nodep->verilogKwd() + "\n"); } virtual void visit(AstPort* nodep) override {} @@ -65,7 +65,7 @@ class EmitVBaseVisitor VL_NOT_FINAL : public EmitCBaseVisitor { puts(nodep->prettyName()); puts(";\n"); // Only putfs the first time for each visitor; later for same node is putqs - iterateAndNextNull(nodep->stmtsp()); + iterateAndNextConstNull(nodep->stmtsp()); putfs(nodep, nodep->isFunction() ? "endfunction\n" : "endtask\n"); } @@ -75,7 +75,7 @@ class EmitVBaseVisitor VL_NOT_FINAL : public EmitCBaseVisitor { } else { putbs("begin : " + nodep->name() + "\n"); } - iterateChildren(nodep); + iterateChildrenConst(nodep); puts("end\n"); } virtual void visit(AstFork* nodep) override { @@ -84,75 +84,75 @@ class EmitVBaseVisitor VL_NOT_FINAL : public EmitCBaseVisitor { } else { putbs("fork : " + nodep->name() + "\n"); } - iterateChildren(nodep); + iterateChildrenConst(nodep); puts(nodep->joinType().verilogKwd()); puts("\n"); } virtual void visit(AstFinal* nodep) override { putfs(nodep, "final begin\n"); - iterateChildren(nodep); + iterateChildrenConst(nodep); putqs(nodep, "end\n"); } virtual void visit(AstInitial* nodep) override { putfs(nodep, "initial begin\n"); - iterateChildren(nodep); + iterateChildrenConst(nodep); putqs(nodep, "end\n"); } - virtual void visit(AstInitialAutomatic* nodep) override { iterateChildren(nodep); } + virtual void visit(AstInitialAutomatic* nodep) override { iterateChildrenConst(nodep); } virtual void visit(AstAlways* nodep) override { putfs(nodep, "always "); if (m_sensesp) { - iterateAndNextNull(m_sensesp); + iterateAndNextConstNull(m_sensesp); } // In active else { - iterateAndNextNull(nodep->sensesp()); + iterateAndNextConstNull(nodep->sensesp()); } putbs(" begin\n"); - iterateAndNextNull(nodep->bodysp()); + iterateAndNextConstNull(nodep->bodysp()); putqs(nodep, "end\n"); } virtual void visit(AstAlwaysPublic* nodep) override { putfs(nodep, "/*verilator public_flat_rw "); if (m_sensesp) { - iterateAndNextNull(m_sensesp); + iterateAndNextConstNull(m_sensesp); } // In active else { - iterateAndNextNull(nodep->sensesp()); + iterateAndNextConstNull(nodep->sensesp()); } putqs(nodep, " "); - iterateAndNextNull(nodep->bodysp()); + iterateAndNextConstNull(nodep->bodysp()); putqs(nodep, "*/\n"); } virtual void visit(AstNodeAssign* nodep) override { if (VN_IS(nodep, AssignForce)) puts("force "); - iterateAndNextNull(nodep->lhsp()); + iterateAndNextConstNull(nodep->lhsp()); putfs(nodep, " " + nodep->verilogKwd() + " "); - iterateAndNextNull(nodep->rhsp()); + iterateAndNextConstNull(nodep->rhsp()); if (!m_suppressSemi) puts(";\n"); } virtual void visit(AstAssignDly* nodep) override { - iterateAndNextNull(nodep->lhsp()); + iterateAndNextConstNull(nodep->lhsp()); putfs(nodep, " <= "); - iterateAndNextNull(nodep->rhsp()); + iterateAndNextConstNull(nodep->rhsp()); puts(";\n"); } virtual void visit(AstAssignAlias* nodep) override { putbs("alias "); - iterateAndNextNull(nodep->lhsp()); + iterateAndNextConstNull(nodep->lhsp()); putfs(nodep, " = "); - iterateAndNextNull(nodep->rhsp()); + iterateAndNextConstNull(nodep->rhsp()); if (!m_suppressSemi) puts(";\n"); } virtual void visit(AstAssignW* nodep) override { putfs(nodep, "assign "); - iterateAndNextNull(nodep->lhsp()); + iterateAndNextConstNull(nodep->lhsp()); putbs(" = "); - iterateAndNextNull(nodep->rhsp()); + iterateAndNextConstNull(nodep->rhsp()); if (!m_suppressSemi) puts(";\n"); } virtual void visit(AstRelease* nodep) override { puts("release "); - iterateAndNextNull(nodep->lhsp()); + iterateAndNextConstNull(nodep->lhsp()); if (!m_suppressSemi) puts(";\n"); } virtual void visit(AstBreak*) override { @@ -172,7 +172,7 @@ class EmitVBaseVisitor VL_NOT_FINAL : public EmitCBaseVisitor { putfs(nodep, ""); puts(nodep->edgeType().verilogKwd()); if (nodep->sensp()) puts(" "); - iterateChildren(nodep); + iterateChildrenConst(nodep); } virtual void visit(AstNodeCase* nodep) override { putfs(nodep, ""); @@ -183,7 +183,7 @@ class EmitVBaseVisitor VL_NOT_FINAL : public EmitCBaseVisitor { } puts(nodep->verilogKwd()); puts(" ("); - iterateAndNextNull(nodep->exprp()); + iterateAndNextConstNull(nodep->exprp()); puts(")\n"); if (const AstCase* const casep = VN_CAST(nodep, Case)) { if (casep->fullPragma() || casep->parallelPragma()) { @@ -192,22 +192,22 @@ class EmitVBaseVisitor VL_NOT_FINAL : public EmitCBaseVisitor { if (casep->parallelPragma()) puts(" parallel_case"); } } - iterateAndNextNull(nodep->itemsp()); + iterateAndNextConstNull(nodep->itemsp()); putqs(nodep, "endcase\n"); } virtual void visit(AstCaseItem* nodep) override { if (nodep->condsp()) { - iterateAndNextNull(nodep->condsp()); + iterateAndNextConstNull(nodep->condsp()); } else { putbs("default"); } putfs(nodep, ": begin "); - iterateAndNextNull(nodep->bodysp()); + iterateAndNextConstNull(nodep->bodysp()); putqs(nodep, "end\n"); } virtual void visit(AstComment* nodep) override { puts(string("// ") + nodep->name() + "\n"); - iterateChildren(nodep); + iterateChildrenConst(nodep); } virtual void visit(AstContinue*) override { putbs("continue"); @@ -222,13 +222,13 @@ class EmitVBaseVisitor VL_NOT_FINAL : public EmitCBaseVisitor { putfs(nodep, nodep->verilogKwd()); putbs("("); if (fileOrStrgp) { - iterateAndNextNull(fileOrStrgp); + iterateAndNextConstNull(fileOrStrgp); putbs(", "); } putsQuoted(text); for (AstNode* expp = exprsp; expp; expp = expp->nextp()) { puts(", "); - iterateAndNextNull(expp); + iterateAndNextConstNull(expp); } puts(");\n"); } @@ -254,32 +254,32 @@ class EmitVBaseVisitor VL_NOT_FINAL : public EmitCBaseVisitor { virtual void visit(AstFOpen* nodep) override { putfs(nodep, nodep->verilogKwd()); putbs("("); - iterateAndNextNull(nodep->filenamep()); + iterateAndNextConstNull(nodep->filenamep()); putbs(", "); - iterateAndNextNull(nodep->modep()); + iterateAndNextConstNull(nodep->modep()); puts(");\n"); } virtual void visit(AstFOpenMcd* nodep) override { putfs(nodep, nodep->verilogKwd()); putbs("("); - iterateAndNextNull(nodep->filenamep()); + iterateAndNextConstNull(nodep->filenamep()); puts(");\n"); } virtual void visit(AstFClose* nodep) override { putfs(nodep, nodep->verilogKwd()); putbs("("); - if (nodep->filep()) iterateAndNextNull(nodep->filep()); + if (nodep->filep()) iterateAndNextConstNull(nodep->filep()); puts(");\n"); } virtual void visit(AstFFlush* nodep) override { putfs(nodep, nodep->verilogKwd()); putbs("("); - if (nodep->filep()) iterateAndNextNull(nodep->filep()); + if (nodep->filep()) iterateAndNextConstNull(nodep->filep()); puts(");\n"); } virtual void visit(AstJumpBlock* nodep) override { putbs("begin : label" + cvtToStr(nodep->labelNum()) + "\n"); - if (nodep->stmtsp()) iterateAndNextNull(nodep->stmtsp()); + if (nodep->stmtsp()) iterateAndNextConstNull(nodep->stmtsp()); puts("end\n"); } virtual void visit(AstJumpGo* nodep) override { @@ -291,27 +291,27 @@ class EmitVBaseVisitor VL_NOT_FINAL : public EmitCBaseVisitor { virtual void visit(AstNodeReadWriteMem* nodep) override { putfs(nodep, nodep->verilogKwd()); putbs("("); - if (nodep->filenamep()) iterateAndNextNull(nodep->filenamep()); + if (nodep->filenamep()) iterateAndNextConstNull(nodep->filenamep()); putbs(", "); - if (nodep->memp()) iterateAndNextNull(nodep->memp()); + if (nodep->memp()) iterateAndNextConstNull(nodep->memp()); if (nodep->lsbp()) { putbs(", "); - iterateAndNextNull(nodep->lsbp()); + iterateAndNextConstNull(nodep->lsbp()); } if (nodep->msbp()) { putbs(", "); - iterateAndNextNull(nodep->msbp()); + iterateAndNextConstNull(nodep->msbp()); } puts(");\n"); } virtual void visit(AstSysFuncAsTask* nodep) override { - iterateAndNextNull(nodep->lhsp()); + iterateAndNextConstNull(nodep->lhsp()); puts(";\n"); } virtual void visit(AstSysIgnore* nodep) override { putfs(nodep, nodep->verilogKwd()); putbs("("); - iterateAndNextNull(nodep->exprsp()); + iterateAndNextConstNull(nodep->exprsp()); puts(");\n"); } virtual void visit(AstNodeFor* nodep) override { @@ -319,31 +319,31 @@ class EmitVBaseVisitor VL_NOT_FINAL : public EmitCBaseVisitor { { VL_RESTORER(m_suppressSemi); m_suppressSemi = true; - iterateAndNextNull(nodep->initsp()); + iterateAndNextConstNull(nodep->initsp()); puts(";"); - iterateAndNextNull(nodep->condp()); + iterateAndNextConstNull(nodep->condp()); puts(";"); - iterateAndNextNull(nodep->incsp()); + iterateAndNextConstNull(nodep->incsp()); } puts(") begin\n"); - iterateAndNextNull(nodep->bodysp()); + iterateAndNextConstNull(nodep->bodysp()); putqs(nodep, "end\n"); } virtual void visit(AstRepeat* nodep) override { putfs(nodep, "repeat ("); - iterateAndNextNull(nodep->countp()); + iterateAndNextConstNull(nodep->countp()); puts(") begin\n"); - iterateAndNextNull(nodep->bodysp()); + iterateAndNextConstNull(nodep->bodysp()); putfs(nodep, "end\n"); } virtual void visit(AstWhile* nodep) override { - iterateAndNextNull(nodep->precondsp()); + iterateAndNextConstNull(nodep->precondsp()); putfs(nodep, "while ("); - iterateAndNextNull(nodep->condp()); + iterateAndNextConstNull(nodep->condp()); puts(") begin\n"); - iterateAndNextNull(nodep->bodysp()); - iterateAndNextNull(nodep->incsp()); - iterateAndNextNull(nodep->precondsp()); // Need to recompute before next loop + iterateAndNextConstNull(nodep->bodysp()); + iterateAndNextConstNull(nodep->incsp()); + iterateAndNextConstNull(nodep->precondsp()); // Need to recompute before next loop putfs(nodep, "end\n"); } virtual void visit(AstNodeIf* nodep) override { @@ -354,28 +354,28 @@ class EmitVBaseVisitor VL_NOT_FINAL : public EmitCBaseVisitor { if (ifp->unique0Pragma()) puts("unique0 "); } puts("if ("); - iterateAndNextNull(nodep->condp()); + iterateAndNextConstNull(nodep->condp()); puts(") begin\n"); - iterateAndNextNull(nodep->ifsp()); + iterateAndNextConstNull(nodep->ifsp()); if (nodep->elsesp()) { putqs(nodep, "end\n"); putqs(nodep, "else begin\n"); - iterateAndNextNull(nodep->elsesp()); + iterateAndNextConstNull(nodep->elsesp()); } putqs(nodep, "end\n"); } virtual void visit(AstPast* nodep) override { putfs(nodep, "$past("); - iterateAndNextNull(nodep->exprp()); + iterateAndNextConstNull(nodep->exprp()); if (nodep->ticksp()) { puts(", "); - iterateAndNextNull(nodep->ticksp()); + iterateAndNextConstNull(nodep->ticksp()); } puts(")"); } virtual void visit(AstReturn* nodep) override { putfs(nodep, "return "); - iterateAndNextNull(nodep->lhsp()); + iterateAndNextConstNull(nodep->lhsp()); puts(";\n"); } virtual void visit(AstStop* nodep) override { putfs(nodep, "$stop;\n"); } @@ -401,22 +401,22 @@ class EmitVBaseVisitor VL_NOT_FINAL : public EmitCBaseVisitor { virtual void visit(AstScopeName* nodep) override {} virtual void visit(AstCStmt* nodep) override { putfs(nodep, "$_CSTMT("); - iterateAndNextNull(nodep->bodysp()); + iterateAndNextConstNull(nodep->bodysp()); puts(");\n"); } virtual void visit(AstCMath* nodep) override { putfs(nodep, "$_CMATH("); - iterateAndNextNull(nodep->bodysp()); + iterateAndNextConstNull(nodep->bodysp()); puts(");\n"); } virtual void visit(AstUCStmt* nodep) override { putfs(nodep, "$c("); - iterateAndNextNull(nodep->bodysp()); + iterateAndNextConstNull(nodep->bodysp()); puts(");\n"); } virtual void visit(AstUCFunc* nodep) override { putfs(nodep, "$c("); - iterateAndNextNull(nodep->bodysp()); + iterateAndNextConstNull(nodep->bodysp()); puts(")"); } @@ -450,27 +450,27 @@ class EmitVBaseVisitor VL_NOT_FINAL : public EmitCBaseVisitor { case 'k': putbs(""); break; case 'l': { UASSERT_OBJ(lhsp, nodep, "emitVerilog() references undef node"); - iterateAndNextNull(lhsp); + iterateAndNextConstNull(lhsp); break; } case 'r': { UASSERT_OBJ(rhsp, nodep, "emitVerilog() references undef node"); - iterateAndNextNull(rhsp); + iterateAndNextConstNull(rhsp); break; } case 't': { UASSERT_OBJ(thsp, nodep, "emitVerilog() references undef node"); - iterateAndNextNull(thsp); + iterateAndNextConstNull(thsp); break; } case 'o': { UASSERT_OBJ(thsp, nodep, "emitVerilog() references undef node"); - iterateAndNextNull(fhsp); + iterateAndNextConstNull(fhsp); break; } case 'd': { UASSERT_OBJ(nodep->dtypep(), nodep, "emitVerilog() references undef node"); - iterateAndNextNull(nodep->dtypep()); + iterateAndNextConstNull(nodep->dtypep()); break; } default: nodep->v3fatalSrc("Unknown emitVerilog format code: %" << c); break; @@ -494,10 +494,10 @@ class EmitVBaseVisitor VL_NOT_FINAL : public EmitCBaseVisitor { } virtual void visit(AstAttrOf* nodep) override { putfs(nodep, "$_ATTROF("); - iterateAndNextNull(nodep->fromp()); + iterateAndNextConstNull(nodep->fromp()); if (nodep->dimp()) { putbs(", "); - iterateAndNextNull(nodep->dimp()); + iterateAndNextConstNull(nodep->dimp()); } puts(")"); } @@ -516,11 +516,11 @@ class EmitVBaseVisitor VL_NOT_FINAL : public EmitCBaseVisitor { } virtual void visit(AstNodeCond* nodep) override { putbs("("); - iterateAndNextNull(nodep->condp()); + iterateAndNextConstNull(nodep->condp()); putfs(nodep, " ? "); - iterateAndNextNull(nodep->expr1p()); + iterateAndNextConstNull(nodep->expr1p()); putbs(" : "); - iterateAndNextNull(nodep->expr2p()); + iterateAndNextConstNull(nodep->expr2p()); puts(")"); } virtual void visit(AstRange* nodep) override { @@ -532,21 +532,21 @@ class EmitVBaseVisitor VL_NOT_FINAL : public EmitCBaseVisitor { puts(cvtToStr(nodep->rightConst())); puts("]"); } else { - iterateAndNextNull(nodep->leftp()); + iterateAndNextConstNull(nodep->leftp()); puts(":"); - iterateAndNextNull(nodep->rightp()); + iterateAndNextConstNull(nodep->rightp()); puts("]"); } } virtual void visit(AstSel* nodep) override { - iterateAndNextNull(nodep->fromp()); + iterateAndNextConstNull(nodep->fromp()); puts("["); if (VN_IS(nodep->lsbp(), Const)) { if (nodep->widthp()->isOne()) { if (VN_IS(nodep->lsbp(), Const)) { puts(cvtToStr(VN_AS(nodep->lsbp(), Const)->toSInt())); } else { - iterateAndNextNull(nodep->lsbp()); + iterateAndNextConstNull(nodep->lsbp()); } } else { puts(cvtToStr(VN_AS(nodep->lsbp(), Const)->toSInt() @@ -555,20 +555,20 @@ class EmitVBaseVisitor VL_NOT_FINAL : public EmitCBaseVisitor { puts(cvtToStr(VN_AS(nodep->lsbp(), Const)->toSInt())); } } else { - iterateAndNextNull(nodep->lsbp()); + iterateAndNextConstNull(nodep->lsbp()); putfs(nodep, "+:"); - iterateAndNextNull(nodep->widthp()); + iterateAndNextConstNull(nodep->widthp()); puts("]"); } puts("]"); } virtual void visit(AstSliceSel* nodep) override { - iterateAndNextNull(nodep->fromp()); + iterateAndNextConstNull(nodep->fromp()); puts(cvtToStr(nodep->declRange())); } virtual void visit(AstTypedef* nodep) override { putfs(nodep, "typedef "); - iterateAndNextNull(nodep->dtypep()); + iterateAndNextConstNull(nodep->dtypep()); puts(" "); puts(nodep->prettyName()); puts(";\n"); @@ -578,7 +578,7 @@ class EmitVBaseVisitor VL_NOT_FINAL : public EmitCBaseVisitor { putfs(nodep, nodep->prettyName()); if (nodep->rangep()) { puts(" "); - iterateAndNextNull(nodep->rangep()); + iterateAndNextConstNull(nodep->rangep()); puts(" "); } else if (nodep->isRanged()) { puts(" ["); @@ -592,14 +592,14 @@ class EmitVBaseVisitor VL_NOT_FINAL : public EmitCBaseVisitor { } virtual void visit(AstNodeArrayDType* nodep) override { iterate(nodep->subDTypep()); - iterateAndNextNull(nodep->rangep()); + iterateAndNextConstNull(nodep->rangep()); } virtual void visit(AstNodeUOrStructDType* nodep) override { puts(nodep->verilogKwd() + " "); if (nodep->packed()) puts("packed "); puts("\n"); puts("{"); - iterateAndNextNull(nodep->membersp()); + iterateAndNextConstNull(nodep->membersp()); puts("}"); } virtual void visit(AstMemberDType* nodep) override { @@ -616,10 +616,10 @@ class EmitVBaseVisitor VL_NOT_FINAL : public EmitCBaseVisitor { putfs(nodep, nodep->prettyName()); } puts("("); - iterateAndNextNull(nodep->pinsp()); + iterateAndNextConstNull(nodep->pinsp()); puts(")"); } - virtual void visit(AstArg* nodep) override { iterateAndNextNull(nodep->exprp()); } + virtual void visit(AstArg* nodep) override { iterateAndNextConstNull(nodep->exprp()); } virtual void visit(AstPrintTimeScale* nodep) override { puts(nodep->verilogKwd()); puts(";\n"); @@ -654,8 +654,8 @@ class EmitVBaseVisitor VL_NOT_FINAL : public EmitCBaseVisitor { virtual void visit(AstConst* nodep) override { putfs(nodep, nodep->num().ascii(true, true)); } // Just iterate - virtual void visit(AstTopScope* nodep) override { iterateChildren(nodep); } - virtual void visit(AstScope* nodep) override { iterateChildren(nodep); } + virtual void visit(AstTopScope* nodep) override { iterateChildrenConst(nodep); } + virtual void visit(AstScope* nodep) override { iterateChildrenConst(nodep); } virtual void visit(AstVar* nodep) override { if (nodep->isIO()) { putfs(nodep, nodep->verilogKwd()); @@ -686,7 +686,7 @@ class EmitVBaseVisitor VL_NOT_FINAL : public EmitCBaseVisitor { } virtual void visit(AstActive* nodep) override { m_sensesp = nodep->sensesp(); - iterateAndNextNull(nodep->stmtsp()); + iterateAndNextConstNull(nodep->stmtsp()); m_sensesp = nullptr; } virtual void visit(AstParseRef* nodep) override { puts(nodep->prettyName()); } @@ -700,7 +700,7 @@ class EmitVBaseVisitor VL_NOT_FINAL : public EmitCBaseVisitor { // Default virtual void visit(AstNode* nodep) override { puts(string("\n???? // ") + nodep->prettyTypeName() + "\n"); - iterateChildren(nodep); + iterateChildrenConst(nodep); // Not v3fatalSrc so we keep processing if (!m_suppressUnknown) { nodep->v3error( @@ -754,10 +754,10 @@ class EmitVStreamVisitor final : public EmitVBaseVisitor { virtual void putqs(AstNode*, const string& str) override { putbs(str); } public: - EmitVStreamVisitor(AstNode* nodep, std::ostream& os) + EmitVStreamVisitor(const AstNode* nodep, std::ostream& os) : EmitVBaseVisitor{false, nullptr} , m_os(os) { // Need () or GCC 4.8 false warning - iterate(nodep); + iterate(const_cast(nodep)); } virtual ~EmitVStreamVisitor() override = default; }; @@ -828,12 +828,12 @@ class EmitVPrefixedVisitor final : public EmitVBaseVisitor { } public: - EmitVPrefixedVisitor(AstNode* nodep, std::ostream& os, const string& prefix, int flWidth, + EmitVPrefixedVisitor(const AstNode* nodep, std::ostream& os, const string& prefix, int flWidth, AstSenTree* domainp, bool user3mark) : EmitVBaseVisitor{false, domainp} , m_formatter{os, prefix, flWidth} { if (user3mark) VNUser3InUse::check(); - iterate(nodep); + iterate(const_cast(nodep)); } virtual ~EmitVPrefixedVisitor() override = default; }; @@ -841,11 +841,11 @@ public: //###################################################################### // EmitV class functions -void V3EmitV::verilogForTree(AstNode* nodep, std::ostream& os) { +void V3EmitV::verilogForTree(const AstNode* nodep, std::ostream& os) { { EmitVStreamVisitor{nodep, os}; } } -void V3EmitV::verilogPrefixedTree(AstNode* nodep, std::ostream& os, const string& prefix, +void V3EmitV::verilogPrefixedTree(const AstNode* nodep, std::ostream& os, const string& prefix, int flWidth, AstSenTree* domainp, bool user3mark) { { EmitVPrefixedVisitor{nodep, os, prefix, flWidth, domainp, user3mark}; } } diff --git a/src/V3EmitV.h b/src/V3EmitV.h index e2be6ab25..6e74823ae 100644 --- a/src/V3EmitV.h +++ b/src/V3EmitV.h @@ -27,8 +27,8 @@ class AstSenTree; class V3EmitV final { public: - static void verilogForTree(AstNode* nodep, std::ostream& os = std::cout); - static void verilogPrefixedTree(AstNode* nodep, std::ostream& os, const string& prefix, + static void verilogForTree(const AstNode* nodep, std::ostream& os = std::cout); + static void verilogPrefixedTree(const AstNode* nodep, std::ostream& os, const string& prefix, int flWidth, AstSenTree* domainp, bool user3mark); static void emitvFiles(); static void debugEmitV(const string& filename); From a9cd2998e5193bd81a539af7630141053e5897a9 Mon Sep 17 00:00:00 2001 From: Geza Lore Date: Sat, 23 Apr 2022 14:06:26 +0100 Subject: [PATCH 31/44] Don't mangle run-time library method names. --- Changes | 1 + src/V3EmitCFunc.h | 2 +- 2 files changed, 2 insertions(+), 1 deletion(-) diff --git a/Changes b/Changes index 8a8a34272..016f91f50 100644 --- a/Changes +++ b/Changes @@ -22,6 +22,7 @@ Verilator 4.221 devel * Fix filenames with dots overwriting debug .vpp files (#3373). * Fix including VK_USER_OBJS in make library (#3370). [Julien Margetts] * Fix crash in recursive module inlining (#3393). [david-sawatzke] +* Fix --protect-ids mangling names of library methods. [Geza Lore, Shunyao CAD] Verilator 4.220 2022-03-12 ========================== diff --git a/src/V3EmitCFunc.h b/src/V3EmitCFunc.h index 127bf1032..4bdfb1c57 100644 --- a/src/V3EmitCFunc.h +++ b/src/V3EmitCFunc.h @@ -406,7 +406,7 @@ public: virtual void visit(AstCMethodHard* nodep) override { iterate(nodep->fromp()); puts("."); - puts(nodep->nameProtect()); + puts(nodep->name()); puts("("); bool comma = false; for (AstNode* subnodep = nodep->pinsp(); subnodep; subnodep = subnodep->nextp()) { From b22e368b25c5afcb5985b84b6e3223decbf3e340 Mon Sep 17 00:00:00 2001 From: Geza Lore Date: Sat, 23 Apr 2022 14:16:19 +0100 Subject: [PATCH 32/44] Add default parameters to some Ast nodes for convenience Also update usage to utilize. No functional change. --- src/V3Assert.cpp | 12 +++++------- src/V3AstNodes.h | 8 ++++---- src/V3Case.cpp | 5 ++--- src/V3Clock.cpp | 6 +++--- src/V3Delayed.cpp | 3 +-- src/V3Descope.cpp | 2 +- src/V3MergeCond.cpp | 2 +- src/V3Table.cpp | 2 +- src/V3Trace.cpp | 2 +- src/V3Unknown.cpp | 3 +-- src/V3Width.cpp | 40 +++++++++++++++++----------------------- src/verilog.y | 4 ++-- 12 files changed, 39 insertions(+), 50 deletions(-) diff --git a/src/V3Assert.cpp b/src/V3Assert.cpp index eaf8e3e71..dd58d3674 100644 --- a/src/V3Assert.cpp +++ b/src/V3Assert.cpp @@ -98,7 +98,7 @@ private: ? static_cast( new AstCMath(fl, "vlSymsp->_vm_contextp__->assertOn()", 1)) : static_cast(new AstConst(fl, AstConst::BitFalse())))), - nodep, nullptr); + nodep); newp->user1(true); // Don't assert/cover this if return newp; } @@ -154,7 +154,7 @@ private: } if (bodysp && passsp) bodysp = bodysp->addNext(passsp); - ifp = new AstIf(nodep->fileline(), propp, bodysp, nullptr); + ifp = new AstIf(nodep->fileline(), propp, bodysp); bodysp = ifp; } else if (VN_IS(nodep, Assert) || VN_IS(nodep, AssertIntrinsic)) { if (nodep->immediate()) { @@ -313,8 +313,7 @@ private: AstIf* const ifp = new AstIf( nodep->fileline(), new AstLogNot(nodep->fileline(), ohot), newFireAssert(nodep, - "synthesis parallel_case, but multiple matches found"), - nullptr); + "synthesis parallel_case, but multiple matches found")); ifp->branchPred(VBranchPred::BP_UNLIKELY); nodep->addNotParallelp(ifp); } @@ -384,7 +383,7 @@ private: new AstLogAnd{fl, new AstLogNot{fl, newMonitorOffVarRefp(nodep, VAccess::READ)}, new AstEq{fl, new AstConst{fl, monNum}, newMonitorNumVarRefp(nodep, VAccess::READ)}}, - stmtsp, nullptr}; + stmtsp}; ifp->branchPred(VBranchPred::BP_UNLIKELY); AstNode* const newp = new AstAlwaysPostponed{fl, ifp}; m_modp->addStmtp(newp); @@ -402,8 +401,7 @@ private: nodep->replaceWith(newsetp); // Add "always_comb if (__Vstrobe) begin $display(...); __Vstrobe = '0; end" AstNode* const stmtsp = nodep; - AstIf* const ifp - = new AstIf{fl, new AstVarRef{fl, varp, VAccess::READ}, stmtsp, nullptr}; + AstIf* const ifp = new AstIf{fl, new AstVarRef{fl, varp, VAccess::READ}, stmtsp}; ifp->branchPred(VBranchPred::BP_UNLIKELY); AstNode* const newp = new AstAlwaysPostponed{fl, ifp}; stmtsp->addNext(new AstAssign{fl, new AstVarRef{fl, varp, VAccess::WRITE}, diff --git a/src/V3AstNodes.h b/src/V3AstNodes.h index e1397b810..1c86aad29 100644 --- a/src/V3AstNodes.h +++ b/src/V3AstNodes.h @@ -1914,14 +1914,14 @@ private: bool m_pure = false; // Pure optimizable public: AstCMethodHard(FileLine* fl, AstNode* fromp, VFlagChildDType, const string& name, - AstNode* pinsp) + AstNode* pinsp = nullptr) : ASTGEN_SUPER_CMethodHard(fl, false) , m_name{name} { setOp1p(fromp); dtypep(nullptr); // V3Width will resolve addNOp2p(pinsp); } - AstCMethodHard(FileLine* fl, AstNode* fromp, const string& name, AstNode* pinsp) + AstCMethodHard(FileLine* fl, AstNode* fromp, const string& name, AstNode* pinsp = nullptr) : ASTGEN_SUPER_CMethodHard(fl, false) , m_name{name} { setOp1p(fromp); @@ -4610,7 +4610,7 @@ public: class AstWhile final : public AstNodeStmt { public: - AstWhile(FileLine* fl, AstNode* condp, AstNode* bodysp, AstNode* incsp = nullptr) + AstWhile(FileLine* fl, AstNode* condp, AstNode* bodysp = nullptr, AstNode* incsp = nullptr) : ASTGEN_SUPER_While(fl) { setOp2p(condp); addNOp3p(bodysp); @@ -4714,7 +4714,7 @@ private: bool m_unique0Pragma; // unique0 case bool m_priorityPragma; // priority case public: - AstIf(FileLine* fl, AstNode* condp, AstNode* ifsp, AstNode* elsesp = nullptr) + AstIf(FileLine* fl, AstNode* condp, AstNode* ifsp = nullptr, AstNode* elsesp = nullptr) : ASTGEN_SUPER_If(fl, condp, ifsp, elsesp) { m_uniquePragma = false; m_unique0Pragma = false; diff --git a/src/V3Case.cpp b/src/V3Case.cpp index 403b785b0..161f7db7e 100644 --- a/src/V3Case.cpp +++ b/src/V3Case.cpp @@ -427,8 +427,7 @@ private: if (++depth > CASE_ENCODER_GROUP_DEPTH) depth = 1; if (depth == 1) { // First group or starting new group itemnextp = nullptr; - AstIf* const newp - = new AstIf(itemp->fileline(), ifexprp->cloneTree(true), nullptr, nullptr); + AstIf* const newp = new AstIf(itemp->fileline(), ifexprp->cloneTree(true)); if (groupnextp) { groupnextp->addElsesp(newp); } else { @@ -448,7 +447,7 @@ private: VL_DO_DANGLING(itemexprp->deleteTree(), itemexprp); itemexprp = new AstConst(itemp->fileline(), AstConst::BitTrue()); } - AstIf* const newp = new AstIf(itemp->fileline(), itemexprp, istmtsp, nullptr); + AstIf* const newp = new AstIf(itemp->fileline(), itemexprp, istmtsp); if (itemnextp) { itemnextp->addElsesp(newp); } else { diff --git a/src/V3Clock.cpp b/src/V3Clock.cpp index a9072fe29..a8b8f7006 100644 --- a/src/V3Clock.cpp +++ b/src/V3Clock.cpp @@ -185,7 +185,7 @@ private: AstIf* makeActiveIf(AstSenTree* sensesp) { AstNode* const senEqnp = createSenseEquation(sensesp->sensesp()); UASSERT_OBJ(senEqnp, sensesp, "No sense equation, shouldn't be in sequent activation."); - AstIf* const newifp = new AstIf(sensesp->fileline(), senEqnp, nullptr, nullptr); + AstIf* const newifp = new AstIf(sensesp->fileline(), senEqnp); return newifp; } void clearLastSen() { @@ -310,8 +310,8 @@ private: AstNode* const origp = nodep->origp()->unlinkFrBack(); AstNode* const changeWrp = nodep->changep()->unlinkFrBack(); AstNode* const changeRdp = ConvertWriteRefsToRead::main(changeWrp->cloneTree(false)); - AstIf* const newp = new AstIf( - nodep->fileline(), new AstXor(nodep->fileline(), origp, changeRdp), incp, nullptr); + AstIf* const newp + = new AstIf(nodep->fileline(), new AstXor(nodep->fileline(), origp, changeRdp), incp); // We could add another IF to detect posedges, and only increment if so. // It's another whole branch though versus a potential memory miss. // We'll go with the miss. diff --git a/src/V3Delayed.cpp b/src/V3Delayed.cpp index f16223128..57fe02833 100644 --- a/src/V3Delayed.cpp +++ b/src/V3Delayed.cpp @@ -351,8 +351,7 @@ private: "Delayed assignment misoptimized; prev var found w/o associated IF"); } else { postLogicp = new AstIf(nodep->fileline(), - new AstVarRef(nodep->fileline(), setvscp, VAccess::READ), - nullptr, nullptr); + new AstVarRef(nodep->fileline(), setvscp, VAccess::READ)); UINFO(9, " Created " << postLogicp << endl); finalp->addStmtp(postLogicp); finalp->user3p(setvscp); // Remember IF's vset variable diff --git a/src/V3Descope.cpp b/src/V3Descope.cpp index 3d13cdb8e..9e6aea78f 100644 --- a/src/V3Descope.cpp +++ b/src/V3Descope.cpp @@ -161,7 +161,7 @@ private: new AstCMath(funcp->fileline(), string("&(") + funcp->scopep()->nameVlSym() + ")", 64)), - returnp, nullptr); + returnp); newfuncp->addStmtsp(ifp); } else { newfuncp->addStmtsp(returnp); diff --git a/src/V3MergeCond.cpp b/src/V3MergeCond.cpp index 767d7a30f..77b2ea935 100644 --- a/src/V3MergeCond.cpp +++ b/src/V3MergeCond.cpp @@ -266,7 +266,7 @@ private: // and we also need to keep track of it for comparisons later. m_mgCondp = m_mgCondp->cloneTree(false); // Create equivalent 'if' statement and insert it before the first node - AstIf* const resultp = new AstIf(m_mgCondp->fileline(), m_mgCondp, nullptr, nullptr); + AstIf* const resultp = new AstIf(m_mgCondp->fileline(), m_mgCondp); m_mgFirstp->addHereThisAsNext(resultp); // Unzip the list and insert under branches AstNode* nextp = m_mgFirstp; diff --git a/src/V3Table.cpp b/src/V3Table.cpp index 3233e39fe..822407b4c 100644 --- a/src/V3Table.cpp +++ b/src/V3Table.cpp @@ -367,7 +367,7 @@ private: AstNode* const condp = new AstAnd(fl, select(fl, outputAssignedTableVscp, indexVscp), new AstConst(fl, outputChgMask)); - outsetp = new AstIf(fl, condp, outsetp, nullptr); + outsetp = new AstIf(fl, condp, outsetp); } stmtsp->addNext(outsetp); diff --git a/src/V3Trace.cpp b/src/V3Trace.cpp index 82d688252..cffd498f4 100644 --- a/src/V3Trace.cpp +++ b/src/V3Trace.cpp @@ -656,7 +656,7 @@ private: condp = condp ? new AstOr(flp, condp, selp) : selp; } } - ifp = new AstIf(flp, condp, nullptr, nullptr); + ifp = new AstIf(flp, condp); if (!always) ifp->branchPred(VBranchPred::BP_UNLIKELY); subFuncp->addStmtsp(ifp); subStmts += ifp->nodeCount(); diff --git a/src/V3Unknown.cpp b/src/V3Unknown.cpp index d71317e58..0df1ff3a6 100644 --- a/src/V3Unknown.cpp +++ b/src/V3Unknown.cpp @@ -127,8 +127,7 @@ private: (needDly ? static_cast( new AstAssignDly(fl, prep, new AstVarRef(fl, varp, VAccess::READ))) : static_cast( - new AstAssign(fl, prep, new AstVarRef(fl, varp, VAccess::READ)))), - nullptr); + new AstAssign(fl, prep, new AstVarRef(fl, varp, VAccess::READ))))); newp->branchPred(VBranchPred::BP_LIKELY); newp->isBoundsCheck(true); if (debug() >= 9) newp->dumpTree(cout, " _new: "); diff --git a/src/V3Width.cpp b/src/V3Width.cpp index e968decd3..f4c350d6e 100644 --- a/src/V3Width.cpp +++ b/src/V3Width.cpp @@ -1366,7 +1366,7 @@ private: switch (nodep->attrType()) { case VAttrType::DIM_SIZE: { AstNode* const newp = new AstCMethodHard( - nodep->fileline(), nodep->fromp()->unlinkFrBack(), "size", nullptr); + nodep->fileline(), nodep->fromp()->unlinkFrBack(), "size"); newp->dtypeSetSigned32(); newp->didWidth(true); newp->protect(false); @@ -1384,7 +1384,7 @@ private: case VAttrType::DIM_RIGHT: case VAttrType::DIM_HIGH: { AstNode* const sizep = new AstCMethodHard( - nodep->fileline(), nodep->fromp()->unlinkFrBack(), "size", nullptr); + nodep->fileline(), nodep->fromp()->unlinkFrBack(), "size"); sizep->dtypeSetSigned32(); sizep->didWidth(true); sizep->protect(false); @@ -2676,8 +2676,8 @@ private: if (nodep->name() == "num" // function int num() || nodep->name() == "size") { methodOkArguments(nodep, 0, 0); - newp = new AstCMethodHard(nodep->fileline(), nodep->fromp()->unlinkFrBack(), "size", - nullptr); // So don't need num() + newp = new AstCMethodHard(nodep->fileline(), nodep->fromp()->unlinkFrBack(), + "size"); // So don't need num() newp->dtypeSetSigned32(); } else if (nodep->name() == "first" // function int first(ref index) || nodep->name() == "last" // @@ -2703,7 +2703,7 @@ private: methodCallLValueRecurse(nodep, nodep->fromp(), VAccess::WRITE); if (!nodep->pinsp()) { newp = new AstCMethodHard(nodep->fileline(), nodep->fromp()->unlinkFrBack(), - "clear", nullptr); + "clear"); newp->makeStatement(); } else { AstNode* const index_exprp = methodCallAssocIndexExpr(nodep, adtypep); @@ -2731,7 +2731,7 @@ private: methodOkArguments(nodep, 0, 0); methodCallLValueRecurse(nodep, nodep->fromp(), VAccess::READ); newp = new AstCMethodHard(nodep->fileline(), nodep->fromp()->unlinkFrBack(), - nodep->name(), nullptr); + nodep->name()); if (nodep->name() == "unique_index") { newp->dtypep(queueDTypeIndexedBy(adtypep->keyDTypep())); } else { @@ -2794,19 +2794,16 @@ private: if (nodep->name() == "at") { // Created internally for [] methodOkArguments(nodep, 1, 1); methodCallLValueRecurse(nodep, nodep->fromp(), VAccess::WRITE); - newp = new AstCMethodHard(nodep->fileline(), nodep->fromp()->unlinkFrBack(), "at", - nullptr); + newp = new AstCMethodHard(nodep->fileline(), nodep->fromp()->unlinkFrBack(), "at"); newp->dtypeFrom(adtypep->subDTypep()); } else if (nodep->name() == "size") { methodOkArguments(nodep, 0, 0); - newp = new AstCMethodHard(nodep->fileline(), nodep->fromp()->unlinkFrBack(), "size", - nullptr); + newp = new AstCMethodHard(nodep->fileline(), nodep->fromp()->unlinkFrBack(), "size"); newp->dtypeSetSigned32(); } else if (nodep->name() == "delete") { // function void delete() methodOkArguments(nodep, 0, 0); methodCallLValueRecurse(nodep, nodep->fromp(), VAccess::WRITE); - newp = new AstCMethodHard(nodep->fileline(), nodep->fromp()->unlinkFrBack(), "clear", - nullptr); + newp = new AstCMethodHard(nodep->fileline(), nodep->fromp()->unlinkFrBack(), "clear"); newp->makeStatement(); } else if (nodep->name() == "and" || nodep->name() == "or" || nodep->name() == "xor" || nodep->name() == "sum" || nodep->name() == "product") { @@ -2837,7 +2834,7 @@ private: methodOkArguments(nodep, 0, 0); methodCallLValueRecurse(nodep, nodep->fromp(), VAccess::READ); newp = new AstCMethodHard(nodep->fileline(), nodep->fromp()->unlinkFrBack(), - nodep->name(), nullptr); + nodep->name()); if (nodep->name() == "unique_index") { newp->dtypep(newp->findQueueIndexDType()); } else { @@ -2883,27 +2880,25 @@ private: if (nodep->name() == "at") { // Created internally for [] methodOkArguments(nodep, 1, 1); methodCallLValueRecurse(nodep, nodep->fromp(), VAccess::WRITE); - newp = new AstCMethodHard(nodep->fileline(), nodep->fromp()->unlinkFrBack(), "at", - nullptr); + newp = new AstCMethodHard(nodep->fileline(), nodep->fromp()->unlinkFrBack(), "at"); newp->dtypeFrom(adtypep->subDTypep()); } else if (nodep->name() == "num" // function int num() || nodep->name() == "size") { methodOkArguments(nodep, 0, 0); - newp = new AstCMethodHard(nodep->fileline(), nodep->fromp()->unlinkFrBack(), "size", - nullptr); + newp = new AstCMethodHard(nodep->fileline(), nodep->fromp()->unlinkFrBack(), "size"); newp->dtypeSetSigned32(); } else if (nodep->name() == "delete") { // function void delete([input integer index]) methodOkArguments(nodep, 0, 1); methodCallLValueRecurse(nodep, nodep->fromp(), VAccess::WRITE); if (!nodep->pinsp()) { newp = new AstCMethodHard(nodep->fileline(), nodep->fromp()->unlinkFrBack(), - "clear", nullptr); + "clear"); newp->makeStatement(); } else { AstNode* const index_exprp = methodCallQueueIndexExpr(nodep); if (index_exprp->isZero()) { // delete(0) is a pop_front newp = new AstCMethodHard(nodep->fileline(), nodep->fromp()->unlinkFrBack(), - "pop_front", nullptr); + "pop_front"); newp->dtypeFrom(adtypep->subDTypep()); newp->makeStatement(); } else { @@ -2933,7 +2928,7 @@ private: // Returns element, so method both consumes (reads) and modifies the queue methodCallLValueRecurse(nodep, nodep->fromp(), VAccess::READWRITE); newp = new AstCMethodHard(nodep->fileline(), nodep->fromp()->unlinkFrBack(), - nodep->name(), nullptr); + nodep->name()); newp->dtypeFrom(adtypep->subDTypep()); if (!nodep->firstAbovep()) newp->makeStatement(); } else if (nodep->name() == "push_back" || nodep->name() == "push_front") { @@ -2972,7 +2967,7 @@ private: methodOkArguments(nodep, 0, 0); methodCallLValueRecurse(nodep, nodep->fromp(), VAccess::READ); newp = new AstCMethodHard(nodep->fileline(), nodep->fromp()->unlinkFrBack(), - nodep->name(), nullptr); + nodep->name()); if (nodep->name() == "unique_index") { newp->dtypep(newp->findQueueIndexDType()); } else { @@ -3850,8 +3845,7 @@ private: } else if (VN_IS(fromDtp, DynArrayDType) || VN_IS(fromDtp, QueueDType)) { if (varp) { auto* const leftp = new AstConst{fl, AstConst::Signed32{}, 0}; - auto* const sizep - = new AstCMethodHard{fl, fromp->cloneTree(false), "size", nullptr}; + auto* const sizep = new AstCMethodHard{fl, fromp->cloneTree(false), "size"}; sizep->dtypeSetSigned32(); sizep->didWidth(true); sizep->protect(false); diff --git a/src/verilog.y b/src/verilog.y index a7230452e..7c660fc62 100644 --- a/src/verilog.y +++ b/src/verilog.y @@ -3111,7 +3111,7 @@ statement_item: // IEEE: statement_item // // // IEEE: conditional_statement | unique_priorityE yIF '(' expr ')' stmtBlock %prec prLOWER_THAN_ELSE - { AstIf* const newp = new AstIf{$2, $4, $6, nullptr}; + { AstIf* const newp = new AstIf{$2, $4, $6}; $$ = newp; if ($1 == uniq_UNIQUE) newp->uniquePragma(true); if ($1 == uniq_UNIQUE0) newp->unique0Pragma(true); @@ -3180,7 +3180,7 @@ statement_item: // IEEE: statement_item $$ = $2->cloneTree(true); $$->addNext(new AstWhile($1,$5,$2)); } - else $$ = new AstWhile($1,$5,nullptr); } + else $$ = new AstWhile($1,$5); } // // IEEE says array_identifier here, but dotted accepted in VMM and 1800-2009 | yFOREACH '(' idClassSelForeach ')' stmtBlock { $$ = new AstForeach($1, $3, $5); } // From 9abab2c36668d363e7756a6f91325b97ea3d074b Mon Sep 17 00:00:00 2001 From: Geza Lore Date: Sat, 23 Apr 2022 14:44:48 +0100 Subject: [PATCH 33/44] Add separate AstInitialStatic node for static initializers Static variable initializers run before initial blocks, so use an explicitly different procedure type for them. This also enables us to now raise errors for assignments to const variables in initial blocks. --- Changes | 1 + src/V3Active.cpp | 8 ++++++++ src/V3AstNodes.h | 11 ++++++++++- src/V3Cdc.cpp | 1 + src/V3Class.cpp | 7 ++++++- src/V3EmitV.cpp | 1 + src/V3LinkParse.cpp | 2 +- src/V3Order.cpp | 3 +++ src/V3Width.cpp | 3 ++- 9 files changed, 33 insertions(+), 4 deletions(-) diff --git a/Changes b/Changes index 016f91f50..acac7dee0 100644 --- a/Changes +++ b/Changes @@ -15,6 +15,7 @@ Verilator 4.221 devel * Split --prof-threads into --prof-exec and --prof-pgo (#3365). [Geza Lore, Shunyao CAD] * Deprecate 'vluint64_t' and similar types (#3255). +* Raise error on assignment to const in initial blocks. [Geza Lore, Shunyao CAD] * Fix MSVC localtime_s (#3124). * Fix Bison 3.8.2 error (#3366). [elike-ypq] * Fix rare bug in -Oz (V3Localize) (#3286). [Geza Lore, Shunyao CAD] diff --git a/src/V3Active.cpp b/src/V3Active.cpp index 043f05233..a0ed963ef 100644 --- a/src/V3Active.cpp +++ b/src/V3Active.cpp @@ -422,6 +422,14 @@ private: virtual void visit(AstActive* nodep) override { // Actives are being formed, so we can ignore any already made } + virtual void visit(AstInitialStatic* nodep) override { + // Relink to IACTIVE, unless already under it + UINFO(4, " INITIAL " << nodep << endl); + const ActiveDlyVisitor dlyvisitor{nodep, ActiveDlyVisitor::CT_INITIAL}; + AstActive* const wantactivep = m_namer.getIActive(nodep->fileline()); + nodep->unlinkFrBack(); + wantactivep->addStmtsp(nodep); + } virtual void visit(AstInitial* nodep) override { // Relink to IACTIVE, unless already under it UINFO(4, " INITIAL " << nodep << endl); diff --git a/src/V3AstNodes.h b/src/V3AstNodes.h index 1c86aad29..5082ae08d 100644 --- a/src/V3AstNodes.h +++ b/src/V3AstNodes.h @@ -3407,7 +3407,7 @@ public: }; class AstInitialAutomatic final : public AstNodeProcedure { - // initial for automatic variables + // Automatic variable initialization // That is, it runs every function start, or class construction public: AstInitialAutomatic(FileLine* fl, AstNode* bodysp) @@ -3415,6 +3415,15 @@ public: ASTNODE_NODE_FUNCS(InitialAutomatic) }; +class AstInitialStatic final : public AstNodeProcedure { + // Static variable initialization + // That is, it runs at the beginning of simulation, before 'initial' blocks +public: + AstInitialStatic(FileLine* fl, AstNode* bodysp) + : ASTGEN_SUPER_InitialStatic(fl, bodysp) {} + ASTNODE_NODE_FUNCS(InitialStatic) +}; + class AstAlways final : public AstNodeProcedure { const VAlwaysKwd m_keyword; diff --git a/src/V3Cdc.cpp b/src/V3Cdc.cpp index 871a5fd8c..acb305ab0 100644 --- a/src/V3Cdc.cpp +++ b/src/V3Cdc.cpp @@ -716,6 +716,7 @@ private: // Ignores virtual void visit(AstInitial*) override {} virtual void visit(AstInitialAutomatic*) override {} + virtual void visit(AstInitialStatic*) override {} virtual void visit(AstTraceDecl*) override {} virtual void visit(AstCoverToggle*) override {} virtual void visit(AstNodeDType*) override {} diff --git a/src/V3Class.cpp b/src/V3Class.cpp index c7bbc91c3..6a7a3ce4f 100644 --- a/src/V3Class.cpp +++ b/src/V3Class.cpp @@ -153,6 +153,11 @@ private: iterateChildren(nodep); if (m_packageScopep) { m_toScopeMoves.push_back(std::make_pair(nodep, m_packageScopep)); } } + virtual void visit(AstInitialStatic* nodep) override { + // But not AstInitialAutomatic, which remains under the class + iterateChildren(nodep); + if (m_packageScopep) { m_toScopeMoves.push_back(std::make_pair(nodep, m_packageScopep)); } + } virtual void visit(AstNodeMath* nodep) override {} // Short circuit virtual void visit(AstNodeStmt* nodep) override {} // Short circuit @@ -173,7 +178,7 @@ public: vscp->scopep(scopep); vscp->unlinkFrBack(); scopep->addVarp(vscp); - } else if (VN_IS(nodep, Initial)) { + } else if (VN_IS(nodep, Initial) || VN_IS(nodep, InitialStatic)) { nodep->unlinkFrBack(); scopep->addActivep(nodep); } else { diff --git a/src/V3EmitV.cpp b/src/V3EmitV.cpp index e04c15e4d..594795fa5 100644 --- a/src/V3EmitV.cpp +++ b/src/V3EmitV.cpp @@ -99,6 +99,7 @@ class EmitVBaseVisitor VL_NOT_FINAL : public EmitCBaseVisitor { putqs(nodep, "end\n"); } virtual void visit(AstInitialAutomatic* nodep) override { iterateChildrenConst(nodep); } + virtual void visit(AstInitialStatic* nodep) override { iterateChildrenConst(nodep); } virtual void visit(AstAlways* nodep) override { putfs(nodep, "always "); if (m_sensesp) { diff --git a/src/V3LinkParse.cpp b/src/V3LinkParse.cpp index b99b8e3a9..df1e36436 100644 --- a/src/V3LinkParse.cpp +++ b/src/V3LinkParse.cpp @@ -275,7 +275,7 @@ private: if (nodep->lifetime().isAutomatic()) { nodep->addNextHere(new AstInitialAutomatic{newfl, assp}); } else { - nodep->addNextHere(new AstInitial{newfl, assp}); + nodep->addNextHere(new AstInitialStatic{newfl, assp}); } } // 4. Under blocks, it's an initial value to be under an assign else { diff --git a/src/V3Order.cpp b/src/V3Order.cpp index 090e81b7d..9007ce8f2 100644 --- a/src/V3Order.cpp +++ b/src/V3Order.cpp @@ -662,6 +662,9 @@ class OrderBuildVisitor final : public VNVisitor { virtual void visit(AstInitialAutomatic* nodep) override { // iterateLogic(nodep); } + virtual void visit(AstInitialStatic* nodep) override { // + iterateLogic(nodep); + } virtual void visit(AstAlways* nodep) override { // iterateLogic(nodep); } diff --git a/src/V3Width.cpp b/src/V3Width.cpp index f4c350d6e..45a78ac8c 100644 --- a/src/V3Width.cpp +++ b/src/V3Width.cpp @@ -2041,7 +2041,8 @@ private: if (nodep->access().isWriteOrRW() && nodep->varp()->direction() == VDirection::CONSTREF) { nodep->v3error("Assigning to const ref variable: " << nodep->prettyNameQ()); } else if (nodep->access().isWriteOrRW() && nodep->varp()->isConst() && !m_paramsOnly - && (!m_ftaskp || !m_ftaskp->isConstructor()) && !VN_IS(m_procedurep, Initial)) { + && (!m_ftaskp || !m_ftaskp->isConstructor()) + && !VN_IS(m_procedurep, InitialStatic)) { // Too loose, but need to allow our generated first assignment // Move this to a property of the AstInitial block nodep->v3error("Assigning to const variable: " << nodep->prettyNameQ()); From 62337bb6accc133e588077b751598a77df80a77a Mon Sep 17 00:00:00 2001 From: Geza Lore Date: Sat, 23 Apr 2022 14:46:39 +0100 Subject: [PATCH 34/44] Future proofing some tests. No functional change. --- test_regress/t/t_c_this.pl | 23 ++++++++++++++++------- test_regress/t/t_event.v | 4 ++-- test_regress/t/t_order_multialways.v | 4 ++-- 3 files changed, 20 insertions(+), 11 deletions(-) diff --git a/test_regress/t/t_c_this.pl b/test_regress/t/t_c_this.pl index b8edcffb4..93c3b5200 100755 --- a/test_regress/t/t_c_this.pl +++ b/test_regress/t/t_c_this.pl @@ -8,19 +8,28 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); di # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 -scenarios(vlt => 1); +scenarios(simulator => 1); compile(); if ($Self->{vlt_all}) { # The word 'this' (but only the whole word 'this' should have been replaced # in the contents. - my $file = glob_one("$Self->{obj_dir}/$Self->{VM_PREFIX}___024root__DepSet_*__0.cpp"); - my $text = file_contents($file); - error("$file has 'this->clk'") if ($text =~ m/\bthis->clk\b/); - error("$file does not have 'xthis'") if ($text !~ m/\bxthis\b/); - error("$file does not have 'thisx'") if ($text !~ m/\bthisx\b/); - error("$file does not have 'xthisx'") if ($text !~ m/\bxthisx\b/); + my $has_this = 0; + my $has_xthis = 0; + my $has_thisx = 0; + my $has_xthisx = 0; + for my $file (glob_all("$Self->{obj_dir}/$Self->{VM_PREFIX}___024root__DepSet_*__0.cpp")) { + my $text = file_contents($file); + $has_this = 1 if ($text =~ m/\bthis->clk\b/); + $has_xthis = 1 if ($text =~ m/\bxthis\b/); + $has_thisx = 1 if ($text =~ m/\bthisx\b/); + $has_xthisx = 1 if ($text =~ m/\bxthisx\b/); + } + error("Some file has 'this->clk'") if $has_this; + error("No file has 'xthis'") if !$has_xthis; + error("No file has 'thisx'") if !$has_thisx; + error("No file has 'xthisx'") if !$has_xthisx; } ok(1); diff --git a/test_regress/t/t_event.v b/test_regress/t/t_event.v index 0f5384c14..9bf376779 100644 --- a/test_regress/t/t_event.v +++ b/test_regress/t/t_event.v @@ -22,9 +22,9 @@ module t(/*AUTOARG*/ event ev [3:0]; `endif - int cyc; + int cyc = 0; - int last_event; + int last_event = 0; always @(e1) begin `WRITE_VERBOSE(("[%0t] e1\n", $time)); if (!e1.triggered) $stop; diff --git a/test_regress/t/t_order_multialways.v b/test_regress/t/t_order_multialways.v index 63f75c5eb..65d500455 100644 --- a/test_regress/t/t_order_multialways.v +++ b/test_regress/t/t_order_multialways.v @@ -25,11 +25,11 @@ module t (/*AUTOARG*/ // verilator lint_off UNOPTFLAT reg [31:0] e2,f2,g2,h2; - always @ (/*AS*/f2) begin + always @ (/*AS*/f2, g2) begin h2 = {g2[15:0], g2[31:16]}; g2 = {f2[15:0], f2[31:16]}; end - always @ (/*AS*/in_a) begin + always @ (/*AS*/in_a, e2) begin f2 = {e2[15:0], e2[31:16]}; e2 = in_a; end From 2b91d764b55e3256bf0c2a5320cf18e86d4d831e Mon Sep 17 00:00:00 2001 From: Aliaksei Chapyzhenka Date: Sat, 23 Apr 2022 12:11:46 -0700 Subject: [PATCH 35/44] Added missing #include (#3392) Fixes #3390 --- docs/CONTRIBUTORS | 1 + src/V3Const.cpp | 1 + 2 files changed, 2 insertions(+) diff --git a/docs/CONTRIBUTORS b/docs/CONTRIBUTORS index 7906a039f..2a6d4735e 100644 --- a/docs/CONTRIBUTORS +++ b/docs/CONTRIBUTORS @@ -7,6 +7,7 @@ Adrien Le Masle Ahmed El-Mahmoudy Alex Chadwick Àlex Torregrosa +Aliaksei Chapyzhenka Ameya Vikram Singh Andreas Kuster Chris Randall diff --git a/src/V3Const.cpp b/src/V3Const.cpp index 927fd1a87..9152d8cd6 100644 --- a/src/V3Const.cpp +++ b/src/V3Const.cpp @@ -33,6 +33,7 @@ #include "V3UniqueNames.h" #include +#include #include //###################################################################### From a6d678d41d3fce53ff7b7d8ccd59a86a0c630a00 Mon Sep 17 00:00:00 2001 From: Yoda Lee Date: Thu, 28 Apr 2022 06:40:36 +0800 Subject: [PATCH 36/44] Fix hang in generate symbol references (#3391) (#3398) --- docs/CONTRIBUTORS | 1 + src/V3LinkDot.cpp | 3 +- test_regress/t/t_func_link.pl | 21 ++++++++++++++ test_regress/t/t_func_link.v | 54 +++++++++++++++++++++++++++++++++++ 4 files changed, 78 insertions(+), 1 deletion(-) create mode 100755 test_regress/t/t_func_link.pl create mode 100644 test_regress/t/t_func_link.v diff --git a/docs/CONTRIBUTORS b/docs/CONTRIBUTORS index 2a6d4735e..09dbb5642 100644 --- a/docs/CONTRIBUTORS +++ b/docs/CONTRIBUTORS @@ -113,6 +113,7 @@ Veripool API Bot Victor Besyakov Wilson Snyder Xi Zhang +Yoda Lee Yossi Nivin Yuri Victorovich Yutetsu TAKATSUKASA diff --git a/src/V3LinkDot.cpp b/src/V3LinkDot.cpp index d483ffd41..535f57b40 100644 --- a/src/V3LinkDot.cpp +++ b/src/V3LinkDot.cpp @@ -675,13 +675,14 @@ public: << ((lookupSymp->symPrefix() == "") ? "" : " as ") << ((lookupSymp->symPrefix() == "") ? "" : lookupSymp->symPrefix() + dotname) << " at se" << lookupSymp << endl); - const string prefix = lookupSymp->symPrefix(); + string prefix = lookupSymp->symPrefix(); VSymEnt* foundp = nullptr; while (!foundp) { foundp = lookupSymp->findIdFallback(prefix + dotname); // Might be nullptr if (prefix.empty()) break; const string nextPrefix = removeLastInlineScope(prefix); if (prefix == nextPrefix) break; + prefix = nextPrefix; } if (!foundp) baddot = dotname; return foundp; diff --git a/test_regress/t/t_func_link.pl b/test_regress/t/t_func_link.pl new file mode 100755 index 000000000..a65ad0e19 --- /dev/null +++ b/test_regress/t/t_func_link.pl @@ -0,0 +1,21 @@ +#!/usr/bin/env perl +if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2012 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +scenarios(simulator => 1); + +compile( + ); + +execute( + check_finished => 1, + ); + +ok(1); +1; diff --git a/test_regress/t/t_func_link.v b/test_regress/t/t_func_link.v new file mode 100644 index 000000000..8921a89cc --- /dev/null +++ b/test_regress/t/t_func_link.v @@ -0,0 +1,54 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2012 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 + +module Test(/*AUTOARG*/ + // Outputs + out, + // Inputs + clk, in + ); + + // Replace this module with the device under test. + // + // Change the code in the t module to apply values to the inputs and + // merge the output values into the result vector. + + input clk; + input [31:0] in; + output reg [31:0] out; + integer cyc = 0; + + SubTest subtest(.out); + + always @(posedge clk) begin +`ifdef TEST_VERBOSE + $write("[%0t] cyc==%0d\n", $time, cyc); +`endif + cyc <= cyc + 1; + if (cyc < 99) begin + subtest.block.set(in); + end + else begin + $write("[%0t] cyc==%0d\n", $time, cyc); + $write("*-* All Finished *-*\n"); + $finish; + end + end +endmodule + +module SubTest( + output logic[31:0] out +); + + if (1) begin : block + + function void set(logic[31:0] in); + out <= in; + endfunction + + end : block + +endmodule From 5de1c619c8187a92d44fdaf5e2f4c6f2793c9f71 Mon Sep 17 00:00:00 2001 From: Kamil Rakoczy Date: Thu, 28 Apr 2022 12:11:31 +0200 Subject: [PATCH 37/44] Fix foreach segmentation fault (#3400). --- docs/CONTRIBUTORS | 1 + src/V3Width.cpp | 3 ++- test_regress/t/t_foreach.v | 2 -- 3 files changed, 3 insertions(+), 3 deletions(-) diff --git a/docs/CONTRIBUTORS b/docs/CONTRIBUTORS index 09dbb5642..d4dd640f7 100644 --- a/docs/CONTRIBUTORS +++ b/docs/CONTRIBUTORS @@ -55,6 +55,7 @@ Josh Redford Julie Schwartz Julien Margetts Kaleb Barrett +Kamil Rakoczy Kanad Kanhere Keith Colbert Kevin Kiningham diff --git a/src/V3Width.cpp b/src/V3Width.cpp index 45a78ac8c..17e302ccc 100644 --- a/src/V3Width.cpp +++ b/src/V3Width.cpp @@ -3794,8 +3794,9 @@ private: const AstSelLoopVars* const loopsp = VN_CAST(nodep->arrayp(), SelLoopVars); UASSERT_OBJ(loopsp, nodep, "No loop variables under foreach"); // if (debug()) nodep->dumpTree(cout, "-foreach-old: "); + userIterateAndNext(loopsp->fromp(), WidthVP(SELF, BOTH).p()); AstNode* const fromp = loopsp->fromp(); - userIterateAndNext(fromp, WidthVP(SELF, BOTH).p()); + UASSERT_OBJ(fromp->dtypep(), fromp, "Missing data type"); AstNodeDType* fromDtp = fromp->dtypep()->skipRefp(); // Split into for loop AstNode* bodyp = nodep->bodysp(); // Might be null diff --git a/test_regress/t/t_foreach.v b/test_regress/t/t_foreach.v index 826abc114..c1405a73c 100644 --- a/test_regress/t/t_foreach.v +++ b/test_regress/t/t_foreach.v @@ -112,12 +112,10 @@ module t (/*AUTOARG*/); strarray[1].mid.subarray[1] = 5; strarray[2].mid.subarray[0] = 6; strarray[2].mid.subarray[1] = 7; -`ifndef VERILATOR // Unsupported foreach (strarray[s]) foreach (strarray[s].mid.subarray[ss]) add += strarray[s].mid.subarray[ss]; `checkh(add, 'h19); -`endif add = 0; foreach (oned[i]) begin From 8395004d25189b51bd164887ea99a49364252697 Mon Sep 17 00:00:00 2001 From: Geza Lore Date: Fri, 29 Apr 2022 15:44:22 +0100 Subject: [PATCH 38/44] Add AstNode::exists and AstNode::forall predicates --- src/V3Ast.h | 112 +++++++++++++++++++++++++++++++++++++++++++--------- 1 file changed, 93 insertions(+), 19 deletions(-) diff --git a/src/V3Ast.h b/src/V3Ast.h index 9ddf48e43..4c306da80 100644 --- a/src/V3Ast.h +++ b/src/V3Ast.h @@ -1972,47 +1972,121 @@ private: } while (nodep); } -public: - // Traverse subtree and call given function 'f' in pre-order on each node that has type 'T'. - // Prefer 'foreach' over simple VNVisitor that only needs to handle a single (or a few) node - // types, as it's easier to write, but more importantly, the dispatch to the operation function - // in 'foreach' should be completely predictable by branch target caches in modern CPUs, - // while it is basically unpredictable for VNVisitor. - template void foreach (std::function f) { + template + static bool predicateImpl( + // Using std::conditional for const correctness in the public 'foreach' functions + typename std::conditional::value, const AstNode*, AstNode*>::type + nodep, + std::function p) { + + // Note: Using a loop to iterate the nextp() chain, instead of tail recursion, because + // debug builds don't eliminate tail calls, causing stack overflow on long lists of nodes. + do { + // Prefetch children and next + ASTNODE_PREFETCH(nodep->op1p()); + ASTNODE_PREFETCH(nodep->op2p()); + ASTNODE_PREFETCH(nodep->op3p()); + ASTNODE_PREFETCH(nodep->op4p()); + if /* TODO: 'constexpr' in C++17 */ (VisitNext) ASTNODE_PREFETCH(nodep->nextp()); + + // Apply function in pre-order + if (privateTypeTest::type>(nodep)) { + if (p(static_cast(nodep)) != Default) return !Default; + } + + // Traverse children (including their 'nextp()' chains), unless futile + if (mayBeUnder::type>(nodep)) { + if (AstNode* const op1p = nodep->op1p()) { + if (predicateImpl(op1p, p) != Default) return !Default; + } + if (AstNode* const op2p = nodep->op2p()) { + if (predicateImpl(op2p, p) != Default) return !Default; + } + if (AstNode* const op3p = nodep->op3p()) { + if (predicateImpl(op3p, p) != Default) return !Default; + } + if (AstNode* const op4p = nodep->op4p()) { + if (predicateImpl(op4p, p) != Default) return !Default; + } + } + + // Traverse 'nextp()' chain if requested + if /* TODO: 'constexpr' in C++17 */ (VisitNext) { + nodep = nodep->nextp(); + } else { + break; + } + } while (nodep); + + return Default; + } + + template constexpr static void checkTypeParameter() { static_assert(!std::is_const::value, "Type parameter 'T_Node' should not be const qualified"); static_assert(std::is_base_of::value, "Type parameter 'T_Node' must be a subtype of AstNode"); + } + +public: + // Traverse subtree and call given function 'f' in pre-order on each node that has type + // 'T_Node'. Prefer 'foreach' over simple VNVisitor that only needs to handle a single (or a + // few) node types, as it's easier to write, but more importantly, the dispatch to the + // operation function in 'foreach' should be completely predictable by branch target caches in + // modern CPUs, while it is basically unpredictable for VNVisitor. + template void foreach (std::function f) { + checkTypeParameter(); foreachImpl(this, f); } // Same as above, but for 'const' nodes template void foreach (std::function f) const { - static_assert(!std::is_const::value, - "Type parameter 'T_Node' should not be const qualified"); - static_assert(std::is_base_of::value, - "Type parameter 'T_Node' must be a subtype of AstNode"); + checkTypeParameter(); foreachImpl(this, f); } // Same as 'foreach' but also follows 'this->nextp()' template void foreachAndNext(std::function f) { - static_assert(!std::is_const::value, - "Type parameter 'T_Node' should not be const qualified"); - static_assert(std::is_base_of::value, - "Type parameter 'T_Node' must be a subtype of AstNode"); + checkTypeParameter(); foreachImpl(this, f); } // Same as 'foreach' but also follows 'this->nextp()' template void foreachAndNext(std::function f) const { - static_assert(!std::is_const::value, - "Type parameter 'T_Node' should not be const qualified"); - static_assert(std::is_base_of::value, - "Type parameter 'T_Node' must be a subtype of AstNode"); + checkTypeParameter(); foreachImpl(this, f); } + // Given a predicate function 'p' return true if and only if there exists a node of type + // 'T_Node' that satisfies the predicate 'p'. Returns false if no node of type 'T_Node' is + // present. Traversal is performed in some arbitrary order and is terminated as soon as the + // result can be determined. + template bool exists(std::function p) { + checkTypeParameter(); + return predicateImpl(this, p); + } + + // Same as above, but for 'const' nodes + template void exists(std::function p) const { + checkTypeParameter(); + return predicateImpl(this, p); + } + + // Given a predicate function 'p' return true if and only if all nodes of type + // 'T_Node' satisfy the predicate 'p'. Returns true if no node of type 'T_Node' is + // present. Traversal is performed in some arbitrary order and is terminated as soon as the + // result can be determined. + template bool forall(std::function p) { + checkTypeParameter(); + return predicateImpl(this, p); + } + + // Same as above, but for 'const' nodes + template void forall(std::function p) const { + checkTypeParameter(); + return predicateImpl(this, p); + } + int nodeCount() const { // TODO: this should really return size_t, but need to fix use sites int count = 0; From 49c90ecbce45bd61df00bdfb5837823bfa25f9e3 Mon Sep 17 00:00:00 2001 From: Geza Lore Date: Fri, 29 Apr 2022 16:32:02 +0100 Subject: [PATCH 39/44] Issue consistent INITIALDLY/COMBDLY/BLKSEQ warnings Some cases of warnings about the use of blocking and non-blocking assignments in combinational vs sequential processes were suppressed in a way that is inconsistent with the *actual* current execution model of Verilator. Turning these back on to, well, warn the user that these might cause unexpected results. V5 will clean these up, but until then err on the side of caution. Fixes #864. --- Changes | 1 + src/V3Active.cpp | 105 +++++++++++------------- test_regress/t/t_delay_stmtdly_bad.out | 4 +- test_regress/t/t_initial_dlyass_bad.out | 8 +- test_regress/t/t_lint_blksync_bad.out | 12 ++- test_regress/t/t_lint_latch_1.out | 9 ++ test_regress/t/t_lint_latch_1.pl | 2 + test_regress/t/t_lint_latch_5.out | 13 +++ test_regress/t/t_lint_latch_5.pl | 2 + test_regress/t/t_lint_latch_bad.out | 16 ++-- test_regress/t/t_lint_latch_bad_2.out | 10 ++- test_regress/t/t_lint_latch_bad_3.out | 32 ++++++-- test_regress/t/t_lint_nolatch_bad.out | 10 ++- 13 files changed, 139 insertions(+), 85 deletions(-) create mode 100644 test_regress/t/t_lint_latch_1.out create mode 100644 test_regress/t/t_lint_latch_5.out diff --git a/Changes b/Changes index acac7dee0..ad4f5463c 100644 --- a/Changes +++ b/Changes @@ -16,6 +16,7 @@ Verilator 4.221 devel * Split --prof-threads into --prof-exec and --prof-pgo (#3365). [Geza Lore, Shunyao CAD] * Deprecate 'vluint64_t' and similar types (#3255). * Raise error on assignment to const in initial blocks. [Geza Lore, Shunyao CAD] +* Issue INITIALDLY/COMBDLY/BLKSEQ warnings consistent with Verilator execution. [Geza Lore, Shunyao CAD] * Fix MSVC localtime_s (#3124). * Fix Bison 3.8.2 error (#3366). [elike-ypq] * Fix rare bug in -Oz (V3Localize) (#3286). [Geza Lore, Shunyao CAD] diff --git a/src/V3Active.cpp b/src/V3Active.cpp index a0ed963ef..9f1758bbb 100644 --- a/src/V3Active.cpp +++ b/src/V3Active.cpp @@ -321,75 +321,70 @@ public: }; //###################################################################### -// Active AssignDly replacement functions +// Replace unsupported non-blocking assignments with blocking assignments class ActiveDlyVisitor final : public ActiveBaseVisitor { public: - enum CheckType : uint8_t { CT_SEQ, CT_COMBO, CT_INITIAL, CT_LATCH }; + enum CheckType : uint8_t { CT_SEQ, CT_COMB, CT_INITIAL }; private: - const CheckType m_check; // Combo logic or other - const AstNode* const m_alwaysp; // Always we're under - const AstNode* m_assignp = nullptr; // In assign + // MEMBERS + const CheckType m_check; // Process type we are checking + // VISITORS virtual void visit(AstAssignDly* nodep) override { - if (m_check != CT_SEQ) { - // Convert to a non-delayed assignment - UINFO(5, " ASSIGNDLY " << nodep << endl); - if (m_check == CT_INITIAL) { - nodep->v3warn(INITIALDLY, "Delayed assignments (<=) in initial or final block\n" - << nodep->warnMore() - << "... Suggest blocking assignments (=)"); - } else if (m_check == CT_LATCH) { - // Suppress. Shouldn't matter that the interior of the latch races - } else if (!(VN_IS(nodep->lhsp(), VarRef) - && VN_AS(nodep->lhsp(), VarRef)->varp()->isLatched())) { - nodep->v3warn(COMBDLY, "Delayed assignments (<=) in non-clocked" - " (non flop or latch) block\n" - << nodep->warnMore() - << "... Suggest blocking assignments (=)"); - // Conversely, we could also suggest latches use delayed assignments, as - // recommended by Cliff Cummings? - } - AstNode* const newp = new AstAssign(nodep->fileline(), nodep->lhsp()->unlinkFrBack(), - nodep->rhsp()->unlinkFrBack()); - nodep->replaceWith(newp); - VL_DO_DANGLING(nodep->deleteTree(), nodep); + // Non-blocking assignments are OK in sequential processes + if (m_check == CT_SEQ) return; + + // Issue appropriate warning + if (m_check == CT_INITIAL) { + nodep->v3warn(INITIALDLY, + "Non-blocking assignment '<=' in initial/final block\n" + << nodep->warnMore() + << "... This will be executed as a blocking assignment '='!"); + } else { + nodep->v3warn(COMBDLY, + "Non-blocking assignment '<=' in combinational logic process\n" + << nodep->warnMore() + << "... This will be executed as a blocking assignment '='!"); } + + // Convert to blocking assignment + nodep->replaceWith(new AstAssign{nodep->fileline(), // + nodep->lhsp()->unlinkFrBack(), // + nodep->rhsp()->unlinkFrBack()}); + VL_DO_DANGLING(nodep->deleteTree(), nodep); } + virtual void visit(AstAssign* nodep) override { - if (m_check == CT_SEQ) { - VL_RESTORER(m_assignp); - m_assignp = nodep; - iterateAndNextNull(nodep->lhsp()); - } - } - virtual void visit(AstVarRef* nodep) override { - const AstVar* const varp = nodep->varp(); - if (m_check == CT_SEQ && m_assignp && !varp->isUsedLoopIdx() // Ignore loop indices - && !varp->isTemp()) { - // Allow turning off warnings on the always, or the variable also - if (!m_alwaysp->fileline()->warnIsOff(V3ErrorCode::BLKSEQ) - && !m_assignp->fileline()->warnIsOff(V3ErrorCode::BLKSEQ) - && !varp->fileline()->warnIsOff(V3ErrorCode::BLKSEQ)) { - m_assignp->v3warn(BLKSEQ, - "Blocking assignments (=) in sequential (flop or latch) block\n" - << m_assignp->warnMore() - << "... Suggest delayed assignments (<=)"); - m_alwaysp->fileline()->modifyWarnOff( - V3ErrorCode::BLKSEQ, true); // Complain just once for the entire always - varp->fileline()->modifyWarnOff(V3ErrorCode::BLKSEQ, true); - } - } + // Blocking assignments are always OK in combinational (and initial/final) processes + if (m_check != CT_SEQ) return; + + const bool ignore = nodep->lhsp()->forall([&](const AstVarRef* refp) { + // Ignore reads (e.g.: index expressions) + if (refp->access().isReadOnly()) return true; + const AstVar* const varp = refp->varp(); + // Ignore ... + return varp->isUsedLoopIdx() // ... loop indices + || varp->isTemp() // ... temporaries + || varp->fileline()->warnIsOff(V3ErrorCode::BLKSEQ); // ... user said so + }); + + if (ignore) return; + + nodep->v3warn(BLKSEQ, + "Blocking assignment '=' in sequential logic process\n" + << nodep->warnMore() // + << "... Suggest using delayed assignment '<='"); } + //-------------------- virtual void visit(AstNode* nodep) override { iterateChildren(nodep); } public: // CONSTRUCTORS ActiveDlyVisitor(AstNode* nodep, CheckType check) - : m_check{check} - , m_alwaysp{nodep} { + : m_check{check} { iterate(nodep); } virtual ~ActiveDlyVisitor() override = default; @@ -535,12 +530,8 @@ private: // Warn and/or convert any delayed assignments if (combo && !sequent) { + ActiveDlyVisitor{nodep, ActiveDlyVisitor::CT_COMB}; const ActiveLatchCheckVisitor latchvisitor{nodep, kwd}; - if (kwd == VAlwaysKwd::ALWAYS_LATCH) { - ActiveDlyVisitor{nodep, ActiveDlyVisitor::CT_LATCH}; - } else { - ActiveDlyVisitor{nodep, ActiveDlyVisitor::CT_COMBO}; - } } else if (!combo && sequent) { ActiveDlyVisitor{nodep, ActiveDlyVisitor::CT_SEQ}; } diff --git a/test_regress/t/t_delay_stmtdly_bad.out b/test_regress/t/t_delay_stmtdly_bad.out index 8b8482f3e..87c088ddc 100644 --- a/test_regress/t/t_delay_stmtdly_bad.out +++ b/test_regress/t/t_delay_stmtdly_bad.out @@ -20,8 +20,8 @@ : ... In instance t 20 | dly_s_t dly_s; | ^~~~~ -%Warning-BLKSEQ: t/t_delay.v:37:20: Blocking assignments (=) in sequential (flop or latch) block - : ... Suggest delayed assignments (<=) +%Warning-BLKSEQ: t/t_delay.v:37:20: Blocking assignment '=' in sequential logic process + : ... Suggest using delayed assignment '<=' 37 | dly_s.dly = 55; | ^ %Error: Exiting due to diff --git a/test_regress/t/t_initial_dlyass_bad.out b/test_regress/t/t_initial_dlyass_bad.out index 686788c11..dfebc49eb 100644 --- a/test_regress/t/t_initial_dlyass_bad.out +++ b/test_regress/t/t_initial_dlyass_bad.out @@ -1,11 +1,11 @@ -%Warning-INITIALDLY: t/t_initial_dlyass.v:18:9: Delayed assignments (<=) in initial or final block - : ... Suggest blocking assignments (=) +%Warning-INITIALDLY: t/t_initial_dlyass.v:18:9: Non-blocking assignment '<=' in initial/final block + : ... This will be executed as a blocking assignment '='! 18 | a <= 22; | ^~ ... For warning description see https://verilator.org/warn/INITIALDLY?v=latest ... Use "/* verilator lint_off INITIALDLY */" and lint_on around source to disable this message. -%Warning-INITIALDLY: t/t_initial_dlyass.v:19:9: Delayed assignments (<=) in initial or final block - : ... Suggest blocking assignments (=) +%Warning-INITIALDLY: t/t_initial_dlyass.v:19:9: Non-blocking assignment '<=' in initial/final block + : ... This will be executed as a blocking assignment '='! 19 | b <= 33; | ^~ %Error: Exiting due to diff --git a/test_regress/t/t_lint_blksync_bad.out b/test_regress/t/t_lint_blksync_bad.out index 5491f6d0e..a9ca1c217 100644 --- a/test_regress/t/t_lint_blksync_bad.out +++ b/test_regress/t/t_lint_blksync_bad.out @@ -1,11 +1,15 @@ -%Warning-BLKSEQ: t/t_lint_blksync_bad.v:24:16: Blocking assignments (=) in sequential (flop or latch) block - : ... Suggest delayed assignments (<=) +%Warning-BLKSEQ: t/t_lint_blksync_bad.v:24:16: Blocking assignment '=' in sequential logic process + : ... Suggest using delayed assignment '<=' 24 | sync_blk = 1'b1; | ^ ... For warning description see https://verilator.org/warn/BLKSEQ?v=latest ... Use "/* verilator lint_off BLKSEQ */" and lint_on around source to disable this message. -%Warning-COMBDLY: t/t_lint_blksync_bad.v:31:18: Delayed assignments (<=) in non-clocked (non flop or latch) block - : ... Suggest blocking assignments (=) +%Warning-BLKSEQ: t/t_lint_blksync_bad.v:25:17: Blocking assignment '=' in sequential logic process + : ... Suggest using delayed assignment '<=' + 25 | sync_blk2 = 1'b1; + | ^ +%Warning-COMBDLY: t/t_lint_blksync_bad.v:31:18: Non-blocking assignment '<=' in combinational logic process + : ... This will be executed as a blocking assignment '='! 31 | combo_nblk <= 1'b1; | ^~ *** See https://verilator.org/warn/COMBDLY before disabling this, diff --git a/test_regress/t/t_lint_latch_1.out b/test_regress/t/t_lint_latch_1.out new file mode 100644 index 000000000..22f8aceb5 --- /dev/null +++ b/test_regress/t/t_lint_latch_1.out @@ -0,0 +1,9 @@ +%Warning-COMBDLY: t/t_lint_latch_1.v:14:10: Non-blocking assignment '<=' in combinational logic process + : ... This will be executed as a blocking assignment '='! + 14 | o <= b; + | ^~ + ... For warning description see https://verilator.org/warn/COMBDLY?v=latest + ... Use "/* verilator lint_off COMBDLY */" and lint_on around source to disable this message. + *** See https://verilator.org/warn/COMBDLY before disabling this, + else you may end up with different sim results. +%Error: Exiting due to diff --git a/test_regress/t/t_lint_latch_1.pl b/test_regress/t/t_lint_latch_1.pl index 629a44bbb..07964a1b5 100755 --- a/test_regress/t/t_lint_latch_1.pl +++ b/test_regress/t/t_lint_latch_1.pl @@ -11,6 +11,8 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); di scenarios(vlt => 1); lint( + fails => 1, + expect_filename => $Self->{golden_filename}, ); ok(1); diff --git a/test_regress/t/t_lint_latch_5.out b/test_regress/t/t_lint_latch_5.out new file mode 100644 index 000000000..30dab57fe --- /dev/null +++ b/test_regress/t/t_lint_latch_5.out @@ -0,0 +1,13 @@ +%Warning-COMBDLY: t/t_lint_latch_5.v:13:13: Non-blocking assignment '<=' in combinational logic process + : ... This will be executed as a blocking assignment '='! + 13 | z[0] <= a[0]; + | ^~ + ... For warning description see https://verilator.org/warn/COMBDLY?v=latest + ... Use "/* verilator lint_off COMBDLY */" and lint_on around source to disable this message. + *** See https://verilator.org/warn/COMBDLY before disabling this, + else you may end up with different sim results. +%Warning-COMBDLY: t/t_lint_latch_5.v:17:13: Non-blocking assignment '<=' in combinational logic process + : ... This will be executed as a blocking assignment '='! + 17 | z[1] <= a[1]; + | ^~ +%Error: Exiting due to diff --git a/test_regress/t/t_lint_latch_5.pl b/test_regress/t/t_lint_latch_5.pl index 629a44bbb..07964a1b5 100755 --- a/test_regress/t/t_lint_latch_5.pl +++ b/test_regress/t/t_lint_latch_5.pl @@ -11,6 +11,8 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); di scenarios(vlt => 1); lint( + fails => 1, + expect_filename => $Self->{golden_filename}, ); ok(1); diff --git a/test_regress/t/t_lint_latch_bad.out b/test_regress/t/t_lint_latch_bad.out index e4c196c62..e24bb171c 100644 --- a/test_regress/t/t_lint_latch_bad.out +++ b/test_regress/t/t_lint_latch_bad.out @@ -1,12 +1,16 @@ +%Warning-COMBDLY: t/t_lint_latch_bad.v:18:10: Non-blocking assignment '<=' in combinational logic process + : ... This will be executed as a blocking assignment '='! + 18 | bl <= a; + | ^~ + ... For warning description see https://verilator.org/warn/COMBDLY?v=latest + ... Use "/* verilator lint_off COMBDLY */" and lint_on around source to disable this message. + *** See https://verilator.org/warn/COMBDLY before disabling this, + else you may end up with different sim results. %Warning-NOLATCH: t/t_lint_latch_bad.v:17:4: No latches detected in always_latch block 17 | always_latch begin | ^~~~~~~~~~~~ - ... For warning description see https://verilator.org/warn/NOLATCH?v=latest - ... Use "/* verilator lint_off NOLATCH */" and lint_on around source to disable this message. -%Warning-COMBDLY: t/t_lint_latch_bad.v:25:10: Delayed assignments (<=) in non-clocked (non flop or latch) block - : ... Suggest blocking assignments (=) +%Warning-COMBDLY: t/t_lint_latch_bad.v:25:10: Non-blocking assignment '<=' in combinational logic process + : ... This will be executed as a blocking assignment '='! 25 | bc <= a; | ^~ - *** See https://verilator.org/warn/COMBDLY before disabling this, - else you may end up with different sim results. %Error: Exiting due to diff --git a/test_regress/t/t_lint_latch_bad_2.out b/test_regress/t/t_lint_latch_bad_2.out index 129267f09..d5fb68aec 100644 --- a/test_regress/t/t_lint_latch_bad_2.out +++ b/test_regress/t/t_lint_latch_bad_2.out @@ -1,7 +1,13 @@ +%Warning-COMBDLY: t/t_lint_latch_bad_2.v:13:10: Non-blocking assignment '<=' in combinational logic process + : ... This will be executed as a blocking assignment '='! + 13 | o <= b; + | ^~ + ... For warning description see https://verilator.org/warn/COMBDLY?v=latest + ... Use "/* verilator lint_off COMBDLY */" and lint_on around source to disable this message. + *** See https://verilator.org/warn/COMBDLY before disabling this, + else you may end up with different sim results. %Warning-LATCH: t/t_lint_latch_bad_2.v:11:4: Latch inferred for signal 'o' (not all control paths of combinational always assign a value) : ... Suggest use of always_latch for intentional latches 11 | always @(a or b) | ^~~~~~ - ... For warning description see https://verilator.org/warn/LATCH?v=latest - ... Use "/* verilator lint_off LATCH */" and lint_on around source to disable this message. %Error: Exiting due to diff --git a/test_regress/t/t_lint_latch_bad_3.out b/test_regress/t/t_lint_latch_bad_3.out index 17b014783..b154019fa 100644 --- a/test_regress/t/t_lint_latch_bad_3.out +++ b/test_regress/t/t_lint_latch_bad_3.out @@ -1,13 +1,29 @@ +%Warning-COMBDLY: t/t_lint_latch_bad_3.v:25:8: Non-blocking assignment '<=' in combinational logic process + : ... This will be executed as a blocking assignment '='! + 25 | o5 <= 1'b0; + | ^~ + ... For warning description see https://verilator.org/warn/COMBDLY?v=latest + ... Use "/* verilator lint_off COMBDLY */" and lint_on around source to disable this message. + *** See https://verilator.org/warn/COMBDLY before disabling this, + else you may end up with different sim results. +%Warning-COMBDLY: t/t_lint_latch_bad_3.v:37:16: Non-blocking assignment '<=' in combinational logic process + : ... This will be executed as a blocking assignment '='! + 37 | o5 <= 1'b1; + | ^~ +%Warning-COMBDLY: t/t_lint_latch_bad_3.v:42:16: Non-blocking assignment '<=' in combinational logic process + : ... This will be executed as a blocking assignment '='! + 42 | o5 <= a; + | ^~ +%Warning-COMBDLY: t/t_lint_latch_bad_3.v:63:16: Non-blocking assignment '<=' in combinational logic process + : ... This will be executed as a blocking assignment '='! + 63 | o5 <= ~b; + | ^~ +%Warning-COMBDLY: t/t_lint_latch_bad_3.v:70:12: Non-blocking assignment '<=' in combinational logic process + : ... This will be executed as a blocking assignment '='! + 70 | o4 <= 1'b0; + | ^~ %Warning-LATCH: t/t_lint_latch_bad_3.v:18:1: Latch inferred for signal 'o5' (not all control paths of combinational always assign a value) : ... Suggest use of always_latch for intentional latches 18 | always @(reset or en or a or b) | ^~~~~~ - ... For warning description see https://verilator.org/warn/LATCH?v=latest - ... Use "/* verilator lint_off LATCH */" and lint_on around source to disable this message. -%Warning-COMBDLY: t/t_lint_latch_bad_3.v:70:12: Delayed assignments (<=) in non-clocked (non flop or latch) block - : ... Suggest blocking assignments (=) - 70 | o4 <= 1'b0; - | ^~ - *** See https://verilator.org/warn/COMBDLY before disabling this, - else you may end up with different sim results. %Error: Exiting due to diff --git a/test_regress/t/t_lint_nolatch_bad.out b/test_regress/t/t_lint_nolatch_bad.out index f4683645e..764e77aaa 100644 --- a/test_regress/t/t_lint_nolatch_bad.out +++ b/test_regress/t/t_lint_nolatch_bad.out @@ -1,6 +1,12 @@ +%Warning-COMBDLY: t/t_lint_nolatch_bad.v:13:10: Non-blocking assignment '<=' in combinational logic process + : ... This will be executed as a blocking assignment '='! + 13 | o <= b; + | ^~ + ... For warning description see https://verilator.org/warn/COMBDLY?v=latest + ... Use "/* verilator lint_off COMBDLY */" and lint_on around source to disable this message. + *** See https://verilator.org/warn/COMBDLY before disabling this, + else you may end up with different sim results. %Warning-NOLATCH: t/t_lint_nolatch_bad.v:11:4: No latches detected in always_latch block 11 | always_latch @(a or b) | ^~~~~~~~~~~~ - ... For warning description see https://verilator.org/warn/NOLATCH?v=latest - ... Use "/* verilator lint_off NOLATCH */" and lint_on around source to disable this message. %Error: Exiting due to From 915ceb2d049b99c96d5241e9aabeeb8a8811967a Mon Sep 17 00:00:00 2001 From: Wilson Snyder Date: Sun, 1 May 2022 10:10:00 -0400 Subject: [PATCH 40/44] Tests: Untabify tests. No functional change. --- test_regress/t/t_alw_combdly.v | 30 +- test_regress/t/t_alw_dly.v | 44 +- test_regress/t/t_alw_split.v | 52 +- test_regress/t/t_alw_splitord.v | 174 +- test_regress/t/t_array_packed_sysfunct.v | 20 +- test_regress/t/t_array_query.v | 4 +- test_regress/t/t_array_rev.v | 4 +- test_regress/t/t_arraysel_wide.v | 4 +- test_regress/t/t_assert_basic.v | 32 +- test_regress/t/t_assert_cover.v | 66 +- test_regress/t/t_assert_disable_iff.v | 4 +- test_regress/t/t_assert_synth.v | 94 +- test_regress/t/t_attr_parenstar.v | 4 +- test_regress/t/t_bench_mux4k.v | 42 +- test_regress/t/t_bind.v | 14 +- test_regress/t/t_bind2.v | 22 +- test_regress/t/t_bitsel_slice.v | 38 +- test_regress/t/t_bitsel_struct3.v | 12 +- test_regress/t/t_blocking.v | 92 +- test_regress/t/t_case_66bits.v | 12 +- test_regress/t/t_case_auto1.v | 92 +- test_regress/t/t_case_deep.v | 496 +- test_regress/t/t_case_dupitems.v | 38 +- test_regress/t/t_case_group.v | 4 +- test_regress/t/t_case_huge.v | 312 +- test_regress/t/t_case_huge_sub.v | 520 +- test_regress/t/t_case_huge_sub2.v | 516 +- test_regress/t/t_case_huge_sub3.v | 514 +- test_regress/t/t_case_huge_sub4.v | 72 +- test_regress/t/t_case_inside.v | 30 +- test_regress/t/t_case_itemwidth.v | 120 +- test_regress/t/t_case_nest.v | 98 +- test_regress/t/t_case_onehot.v | 50 +- test_regress/t/t_case_orig.v | 218 +- test_regress/t/t_case_reducer.v | 48 +- test_regress/t/t_case_wild.v | 68 +- test_regress/t/t_case_write1_tasks.v | 6280 ++++++++--------- test_regress/t/t_case_write2_tasks.v | 6248 ++++++++-------- test_regress/t/t_case_x.v | 46 +- test_regress/t/t_cast.v | 4 +- test_regress/t/t_chg_first.v | 30 +- test_regress/t/t_clk_2in.v | 48 +- test_regress/t/t_clk_concat.v | 66 +- test_regress/t/t_clk_concat2.v | 66 +- test_regress/t/t_clk_concat3.v | 58 +- test_regress/t/t_clk_concat4.v | 62 +- test_regress/t/t_clk_concat5.v | 64 +- test_regress/t/t_clk_concat6.v | 80 +- test_regress/t/t_clk_condflop.v | 90 +- test_regress/t/t_clk_condflop_nord.v | 90 +- test_regress/t/t_clk_dpulse.v | 10 +- test_regress/t/t_clk_dsp.v | 154 +- test_regress/t/t_clk_first.v | 78 +- test_regress/t/t_clk_gate_ext.v | 4 +- test_regress/t/t_clk_gater.v | 100 +- test_regress/t/t_clk_gen.v | 66 +- test_regress/t/t_clk_latch.v | 32 +- test_regress/t/t_clk_latchgate.v | 34 +- test_regress/t/t_clk_powerdn.v | 116 +- test_regress/t/t_clk_vecgen1.v | 66 +- test_regress/t/t_clocker.v | 4 +- test_regress/t/t_concat_opt.v | 10 +- test_regress/t/t_cover_sva_notflat.v | 42 +- test_regress/t/t_cover_toggle.v | 76 +- test_regress/t/t_detectarray_1.v | 6 +- test_regress/t/t_detectarray_2.v | 6 +- test_regress/t/t_detectarray_3.v | 4 +- test_regress/t/t_dpi_accessors.v | 8 +- test_regress/t/t_dpi_imp_gen.v | 8 +- test_regress/t/t_dpi_import.v | 44 +- test_regress/t/t_dpi_qw.v | 4 +- test_regress/t/t_dpi_shortcircuit.v | 22 +- test_regress/t/t_dpi_shortcircuit2.v | 20 +- test_regress/t/t_dpi_var.v | 20 +- test_regress/t/t_embed1.v | 88 +- test_regress/t/t_embed1_child.v | 4 +- test_regress/t/t_embed1_wrap.v | 30 +- test_regress/t/t_emit_constw.v | 70 +- test_regress/t/t_enum.v | 26 +- test_regress/t/t_enum_func.v | 48 +- test_regress/t/t_enum_huge_methods_bad.out | 12 +- test_regress/t/t_enum_huge_methods_bad.v | 18 +- test_regress/t/t_enum_int.v | 104 +- test_regress/t/t_enum_large_methods.v | 34 +- test_regress/t/t_enum_name2.v | 10 +- test_regress/t/t_enum_public.v | 8 +- test_regress/t/t_enum_type_methods.v | 68 +- test_regress/t/t_enum_type_pins.v | 22 +- test_regress/t/t_extend.v | 22 +- test_regress/t/t_extend_class.v | 16 +- test_regress/t/t_flag_compiler.v | 48 +- test_regress/t/t_flag_topmodule_inline.v | 4 +- test_regress/t/t_for_break.v | 96 +- test_regress/t/t_for_count.v | 52 +- test_regress/t/t_for_funcbound.v | 44 +- test_regress/t/t_for_init_bug.v | 8 +- test_regress/t/t_for_local.v | 60 +- test_regress/t/t_for_loop.v | 184 +- test_regress/t/t_func.v | 32 +- test_regress/t/t_func_begin2.v | 8 +- test_regress/t/t_func_check.v | 30 +- test_regress/t/t_func_const.v | 38 +- test_regress/t/t_func_crc.v | 64 +- test_regress/t/t_func_dotted.v | 26 +- test_regress/t/t_func_endian.v | 52 +- test_regress/t/t_func_first.v | 20 +- test_regress/t/t_func_flip.v | 28 +- test_regress/t/t_func_gen.v | 30 +- test_regress/t/t_func_graphcirc.v | 22 +- test_regress/t/t_func_grey.v | 22 +- test_regress/t/t_func_lib_sub.v | 8 +- test_regress/t/t_func_mlog2.v | 46 +- test_regress/t/t_func_named.v | 16 +- test_regress/t/t_func_noinl.v | 82 +- test_regress/t/t_func_numones.v | 20 +- test_regress/t/t_func_outfirst.v | 44 +- test_regress/t/t_func_outp.v | 58 +- test_regress/t/t_func_paramed.v | 66 +- test_regress/t/t_func_plog.v | 64 +- test_regress/t/t_func_public.v | 152 +- test_regress/t/t_func_rand.v | 4 +- test_regress/t/t_func_range.v | 38 +- test_regress/t/t_func_real_abs.v | 10 +- test_regress/t/t_func_real_param.v | 10 +- test_regress/t/t_func_regfirst.v | 76 +- test_regress/t/t_func_return.v | 26 +- test_regress/t/t_func_sum.v | 40 +- test_regress/t/t_func_twocall.v | 64 +- test_regress/t/t_func_under2.v | 6 +- test_regress/t/t_func_wide.v | 22 +- test_regress/t/t_fuzz_eof_bad.v | 2 +- test_regress/t/t_gantt_io_arm.dat | 64 +- test_regress/t/t_gate_array.v | 40 +- test_regress/t/t_gate_elim.v | 90 +- test_regress/t/t_gate_implicit.v | 42 +- test_regress/t/t_gated_clk_1.v | 18 +- test_regress/t/t_gen_alw.v | 48 +- test_regress/t/t_gen_assign.v | 30 +- test_regress/t/t_gen_cond_bitrange.v | 76 +- test_regress/t/t_gen_cond_const.v | 12 +- test_regress/t/t_gen_defparam.v | 4 +- test_regress/t/t_gen_for.v | 102 +- test_regress/t/t_gen_for0.v | 18 +- test_regress/t/t_gen_for1.v | 52 +- test_regress/t/t_gen_for_shuffle.v | 40 +- test_regress/t/t_gen_forif.v | 48 +- test_regress/t/t_gen_if.v | 14 +- test_regress/t/t_gen_inc.v | 104 +- test_regress/t/t_gen_index.v | 16 +- test_regress/t/t_gen_intdot.v | 30 +- test_regress/t/t_gen_intdot2.v | 82 +- test_regress/t/t_gen_local.v | 16 +- test_regress/t/t_gen_lsb.v | 44 +- test_regress/t/t_if_deep.v | 40 +- test_regress/t/t_init_concat.v | 82 +- test_regress/t/t_initial.v | 30 +- test_regress/t/t_initial_edge.v | 32 +- test_regress/t/t_inside.v | 36 +- test_regress/t/t_inside_wild.v | 38 +- test_regress/t/t_inst_aport.v | 38 +- test_regress/t/t_inst_array.v | 36 +- test_regress/t/t_inst_array_partial.v | 54 +- test_regress/t/t_inst_ccall.v | 34 +- test_regress/t/t_inst_comma.v | 34 +- test_regress/t/t_inst_darray.v | 52 +- test_regress/t/t_inst_dff.v | 74 +- test_regress/t/t_inst_dtree.v | 10 +- test_regress/t/t_inst_first.v | 138 +- test_regress/t/t_inst_first_a.v | 16 +- test_regress/t/t_inst_first_b.v | 14 +- test_regress/t/t_inst_implicit.v | 12 +- test_regress/t/t_inst_mnpipe.v | 22 +- test_regress/t/t_inst_notunsized.v | 68 +- test_regress/t/t_inst_signed.v | 30 +- test_regress/t/t_inst_slice.v | 44 +- test_regress/t/t_inst_sv.v | 48 +- test_regress/t/t_inst_tree.v | 38 +- test_regress/t/t_inst_v2k.v | 48 +- test_regress/t/t_inst_wideconst.v | 66 +- test_regress/t/t_interface1.v | 10 +- test_regress/t/t_interface1_modport.v | 12 +- test_regress/t/t_interface2.v | 48 +- test_regress/t/t_interface_array.v | 18 +- test_regress/t/t_interface_array2.v | 8 +- test_regress/t/t_interface_array_modport.v | 6 +- test_regress/t/t_interface_arraymux.v | 10 +- test_regress/t/t_interface_down.v | 24 +- test_regress/t/t_interface_down_gen.v | 28 +- test_regress/t/t_interface_dups.v | 42 +- test_regress/t/t_interface_gen.v | 16 +- test_regress/t/t_interface_gen12.v | 6 +- test_regress/t/t_interface_gen2.v | 28 +- test_regress/t/t_interface_gen3.v | 28 +- test_regress/t/t_interface_gen4.v | 18 +- test_regress/t/t_interface_gen6.v | 16 +- test_regress/t/t_interface_gen7.v | 28 +- test_regress/t/t_interface_modport.v | 54 +- test_regress/t/t_interface_modport_export.v | 20 +- test_regress/t/t_interface_modport_import.v | 16 +- test_regress/t/t_interface_param1.v | 6 +- test_regress/t/t_interface_parameter_access.v | 28 +- test_regress/t/t_interface_ref_trace.v | 22 +- test_regress/t/t_interface_star.v | 6 +- test_regress/t/t_interface_twod.v | 14 +- test_regress/t/t_langext_2.v | 36 +- test_regress/t/t_leak.v | 4 +- test_regress/t/t_lib_prot.v | 2 +- test_regress/t/t_lib_prot_secret.v | 2 +- test_regress/t/t_lint_blksync_loop.v | 58 +- test_regress/t/t_lint_comb_use.v | 6 +- test_regress/t/t_lint_inherit.v | 20 +- test_regress/t/t_lint_latch_bad_3.v | 28 +- test_regress/t/t_lint_unsup_mixed.v | 8 +- test_regress/t/t_math_clog2.v | 76 +- test_regress/t/t_math_cmp.v | 104 +- test_regress/t/t_math_concat.v | 102 +- test_regress/t/t_math_concat0.v | 46 +- test_regress/t/t_math_concat64.v | 70 +- test_regress/t/t_math_cond_huge.v | 548 +- test_regress/t/t_math_const.v | 180 +- test_regress/t/t_math_div.v | 162 +- test_regress/t/t_math_divw.v | 132 +- test_regress/t/t_math_eq.v | 50 +- test_regress/t/t_math_equal.v | 84 +- test_regress/t/t_math_imm.v | 76 +- test_regress/t/t_math_imm2.v | 20 +- test_regress/t/t_math_mul.v | 12 +- test_regress/t/t_math_pick.v | 48 +- test_regress/t/t_math_pow.v | 124 +- test_regress/t/t_math_pow2.v | 32 +- test_regress/t/t_math_pow3.v | 20 +- test_regress/t/t_math_pow4.v | 24 +- test_regress/t/t_math_pow5.v | 60 +- test_regress/t/t_math_precedence.v | 112 +- test_regress/t/t_math_repl.v | 126 +- test_regress/t/t_math_reverse.v | 50 +- test_regress/t/t_math_shift_rep.v | 36 +- test_regress/t/t_math_shift_sel.v | 44 +- test_regress/t/t_math_shiftrs.v | 70 +- test_regress/t/t_math_signed.v | 158 +- test_regress/t/t_math_signed2.v | 16 +- test_regress/t/t_math_signed3.v | 42 +- test_regress/t/t_math_signed4.v | 6 +- test_regress/t/t_math_signed5.v | 20 +- test_regress/t/t_math_signed7.v | 32 +- test_regress/t/t_math_signed_wire.v | 8 +- test_regress/t/t_math_svl.v | 146 +- test_regress/t/t_math_svl2.v | 40 +- test_regress/t/t_math_swap.v | 130 +- test_regress/t/t_math_trig.v | 166 +- test_regress/t/t_math_vgen.v | 98 +- test_regress/t/t_math_vliw.v | 112 +- test_regress/t/t_mem.v | 54 +- test_regress/t/t_mem_banks.v | 72 +- test_regress/t/t_mem_fifo.v | 66 +- test_regress/t/t_mem_file.v | 142 +- test_regress/t/t_mem_first.v | 128 +- test_regress/t/t_mem_func.v | 60 +- test_regress/t/t_mem_iforder.v | 82 +- test_regress/t/t_mem_multi_io.v | 10 +- test_regress/t/t_mem_multi_io3.v | 32 +- test_regress/t/t_mem_multidim.v | 86 +- test_regress/t/t_mem_multiwire.v | 46 +- test_regress/t/t_mem_packed.v | 82 +- test_regress/t/t_mem_shift.v | 30 +- test_regress/t/t_mem_slice.v | 72 +- test_regress/t/t_mem_slice_conc_bad.v | 80 +- test_regress/t/t_mem_twoedge.v | 66 +- test_regress/t/t_mod_interface_array0.v | 4 +- test_regress/t/t_mod_interface_array1.v | 4 +- test_regress/t/t_mod_interface_array2.v | 4 +- test_regress/t/t_mod_recurse.v | 86 +- test_regress/t/t_optm_if_array.v | 8 +- test_regress/t/t_order.v | 96 +- test_regress/t/t_order_2d.v | 36 +- test_regress/t/t_order_comboclkloop.v | 46 +- test_regress/t/t_order_comboloop.v | 36 +- test_regress/t/t_order_doubleloop.v | 58 +- test_regress/t/t_order_first.v | 12 +- test_regress/t/t_order_multialways.v | 38 +- test_regress/t/t_order_multidriven.v | 4 +- test_regress/t/t_package_abs.v | 16 +- test_regress/t/t_package_dimport.v | 8 +- test_regress/t/t_package_param.v | 6 +- test_regress/t/t_param.v | 16 +- test_regress/t/t_param_array.v | 70 +- test_regress/t/t_param_bit_sel.v | 6 +- test_regress/t/t_param_ceil.v | 10 +- test_regress/t/t_param_chain.v | 8 +- test_regress/t/t_param_first.v | 130 +- test_regress/t/t_param_first_a.v | 8 +- test_regress/t/t_param_first_b.v | 8 +- test_regress/t/t_param_if_blk.v | 96 +- test_regress/t/t_param_long.v | 4 +- test_regress/t/t_param_module.v | 4 +- test_regress/t/t_param_named.v | 6 +- test_regress/t/t_param_no_parentheses.v | 16 +- test_regress/t/t_param_public.v | 4 +- test_regress/t/t_param_repl.v | 38 +- test_regress/t/t_param_sel.v | 42 +- test_regress/t/t_param_wide_io.v | 6 +- test_regress/t/t_preproc.out | 427 +- test_regress/t/t_preproc.v | 2 + test_regress/t/t_preproc_comments.out | 411 +- test_regress/t/t_preproc_def09.v | 8 +- test_regress/t/t_preproc_ifdef.v | 32 +- test_regress/t/t_repeat.v | 28 +- test_regress/t/t_rnd.v | 28 +- test_regress/t/t_savable.v | 60 +- test_regress/t/t_select_bound1.v | 42 +- test_regress/t/t_select_bound2.v | 44 +- test_regress/t/t_select_index.v | 26 +- test_regress/t/t_select_index2.v | 12 +- test_regress/t/t_select_lhs_oob.v | 66 +- test_regress/t/t_select_lhs_oob2.v | 136 +- test_regress/t/t_select_little.v | 40 +- test_regress/t/t_select_loop.v | 48 +- test_regress/t/t_select_negative.v | 34 +- test_regress/t/t_select_plus.v | 82 +- test_regress/t/t_select_plus_mul_pow2.v | 52 +- test_regress/t/t_select_plusloop.v | 60 +- test_regress/t/t_select_runtime_range.v | 78 +- test_regress/t/t_select_set.v | 58 +- test_regress/t/t_slice_init.v | 4 +- test_regress/t/t_stream.v | 90 +- test_regress/t/t_stream2.v | 52 +- test_regress/t/t_stream3.v | 64 +- test_regress/t/t_string.v | 82 +- test_regress/t/t_struct_array.v | 4 +- test_regress/t/t_struct_param.v | 12 +- test_regress/t/t_struct_port.v | 46 +- test_regress/t/t_struct_portsel.v | 36 +- test_regress/t/t_struct_unaligned.v | 26 +- test_regress/t/t_sv_conditional.v | 138 +- test_regress/t/t_sv_cpu.v | 26 +- test_regress/t/t_sv_cpu_code/ac.sv | 28 +- test_regress/t/t_sv_cpu_code/pads.sv | 4 +- test_regress/t/t_sys_file_basic.v | 400 +- test_regress/t/t_sys_rand.v | 12 +- test_regress/t/t_sys_time.v | 12 +- test_regress/t/t_table_fsm.v | 88 +- test_regress/t/t_trace_array.v | 6 +- test_regress/t/t_trace_decoration.v | 4 +- test_regress/t/t_trace_param.v | 6 +- test_regress/t/t_tri_array.v | 44 +- test_regress/t/t_tri_array_bufif.v | 60 +- test_regress/t/t_tri_dangle.v | 10 +- test_regress/t/t_tri_eqcase.v | 52 +- test_regress/t/t_tri_gen.v | 4 +- test_regress/t/t_tri_public.v | 12 +- test_regress/t/t_tri_pull01.v | 34 +- test_regress/t/t_tri_pull2_bad.v | 4 +- test_regress/t/t_tri_unconn.v | 6 +- test_regress/t/t_tri_various.v | 172 +- test_regress/t/t_typedef_param.v | 46 +- test_regress/t/t_typedef_port.v | 58 +- test_regress/t/t_typedef_signed.v | 40 +- test_regress/t/t_udp_noname.v | 6 +- test_regress/t/t_uniqueif.v | 48 +- test_regress/t/t_unopt_array.v | 50 +- test_regress/t/t_unopt_bound.v | 8 +- test_regress/t/t_unoptflat_simple.v | 4 +- test_regress/t/t_unoptflat_simple_3.v | 12 +- test_regress/t/t_unroll_forfor.v | 14 +- test_regress/t/t_unroll_signed.v | 236 +- test_regress/t/t_vams_wreal.v | 44 +- test_regress/t/t_var_assign_landr.v | 40 +- test_regress/t/t_var_escape.v | 8 +- test_regress/t/t_var_in_assign.v | 28 +- test_regress/t/t_var_init.v | 6 +- test_regress/t/t_var_life.v | 148 +- test_regress/t/t_var_local.v | 44 +- test_regress/t/t_var_outoforder.v | 62 +- test_regress/t/t_var_overcmp.v | 56 +- test_regress/t/t_var_overzero.v | 70 +- test_regress/t/t_var_pinsizes.v | 20 +- test_regress/t/t_var_rsvd.v | 8 +- test_regress/t/t_var_tieout.v | 26 +- test_regress/t/t_var_types.v | 270 +- test_regress/t/t_var_xref_gen.v | 8 +- test_regress/t/t_vpi_get.v | 6 +- test_regress/t/t_vpi_memory.v | 14 +- test_regress/t/t_vpi_unimpl.v | 4 +- test_regress/t/t_vpi_var.v | 36 +- test_regress/t/t_wire_types.v | 20 +- test_regress/t/t_xml_debugcheck.out | 878 +-- test_regress/t/t_xml_tag.out | 8 +- test_regress/t/t_xml_tag.v | 8 +- 388 files changed, 17153 insertions(+), 17145 deletions(-) diff --git a/test_regress/t/t_alw_combdly.v b/test_regress/t/t_alw_combdly.v index 38cdc0694..88e554a1b 100644 --- a/test_regress/t/t_alw_combdly.v +++ b/test_regress/t/t_alw_combdly.v @@ -41,21 +41,21 @@ module t (/*AUTOARG*/ always @ (posedge clk) begin if (cyc!=0) begin - cyc<=cyc+1; - if (cyc==1) begin - a <= 32'hfeed0000; - b <= 32'h0000face; - end - if (cyc==2) begin - if (c != 32'hfeedface) $stop; - end - if (cyc==3) begin - if (h != 32'hfeedface) $stop; - end - if (cyc==7) begin - $write("*-* All Finished *-*\n"); - $finish; - end + cyc<=cyc+1; + if (cyc==1) begin + a <= 32'hfeed0000; + b <= 32'h0000face; + end + if (cyc==2) begin + if (c != 32'hfeedface) $stop; + end + if (cyc==3) begin + if (h != 32'hfeedface) $stop; + end + if (cyc==7) begin + $write("*-* All Finished *-*\n"); + $finish; + end end end endmodule diff --git a/test_regress/t/t_alw_dly.v b/test_regress/t/t_alw_dly.v index 0cc82e2e6..e43a8012f 100644 --- a/test_regress/t/t_alw_dly.v +++ b/test_regress/t/t_alw_dly.v @@ -31,34 +31,34 @@ module t (/*AUTOARG*/ always @ (posedge clk) begin posedge_wr_clocks = (clk &~ prev_wr_clocks); //surefire lint_off_line SEQASS - prev_wr_clocks = prev_wr_clocks | posedge_wr_clocks; //surefire lint_off_line SEQASS + prev_wr_clocks = prev_wr_clocks | posedge_wr_clocks; //surefire lint_off_line SEQASS if (posedge_wr_clocks) begin - //$write("[%0t] Wrclk\n", $time); - m_dout <= m_din; + //$write("[%0t] Wrclk\n", $time); + m_dout <= m_din; end end always @ (posedge clk) begin if (cyc!=0) begin - cyc<=cyc+1; - if (cyc==1) begin - $write(" %x\n",comb_pos_1); - m_din <= 32'hfeed; - end - if (cyc==2) begin - $write(" %x\n",comb_pos_1); - m_din <= 32'he11e; - end - if (cyc==3) begin - m_din <= 32'he22e; - $write(" %x\n",comb_pos_1); - if (m_dout!=32'hfeed) $stop; - end - if (cyc==4) begin - if (m_dout!=32'he11e) $stop; - $write("*-* All Finished *-*\n"); - $finish; - end + cyc<=cyc+1; + if (cyc==1) begin + $write(" %x\n",comb_pos_1); + m_din <= 32'hfeed; + end + if (cyc==2) begin + $write(" %x\n",comb_pos_1); + m_din <= 32'he11e; + end + if (cyc==3) begin + m_din <= 32'he22e; + $write(" %x\n",comb_pos_1); + if (m_dout!=32'hfeed) $stop; + end + if (cyc==4) begin + if (m_dout!=32'he11e) $stop; + $write("*-* All Finished *-*\n"); + $finish; + end end end endmodule diff --git a/test_regress/t/t_alw_split.v b/test_regress/t/t_alw_split.v index b6b1e7efa..52f52daa6 100644 --- a/test_regress/t/t_alw_split.v +++ b/test_regress/t/t_alw_split.v @@ -59,35 +59,35 @@ module t (/*AUTOARG*/ // (The checker block is an exception, it won't split.) always @ (posedge clk) begin if (cyc!=0) begin - cyc<=cyc+1; - if (cyc==1) begin - m_din <= 16'hfeed; - end - if (cyc==3) begin - end - if (cyc==4) begin - m_din <= 16'he11e; - //$write(" A %x %x\n", a_split_1, a_split_2); - if (!(a_split_1==16'hfeed && a_split_2==16'hfeed)) $stop; - if (!(d_split_1==16'h0112 && d_split_2==16'h0112)) $stop; + cyc<=cyc+1; + if (cyc==1) begin + m_din <= 16'hfeed; + end + if (cyc==3) begin + end + if (cyc==4) begin + m_din <= 16'he11e; + //$write(" A %x %x\n", a_split_1, a_split_2); + if (!(a_split_1==16'hfeed && a_split_2==16'hfeed)) $stop; + if (!(d_split_1==16'h0112 && d_split_2==16'h0112)) $stop; if (!(h_split_1==16'hfeed && h_split_2==16'h0112)) $stop; - end - if (cyc==5) begin - m_din <= 16'he22e; - if (!(a_split_1==16'he11e && a_split_2==16'he11e)) $stop; - if (!(d_split_1==16'h0112 && d_split_2==16'h0112)) $stop; + end + if (cyc==5) begin + m_din <= 16'he22e; + if (!(a_split_1==16'he11e && a_split_2==16'he11e)) $stop; + if (!(d_split_1==16'h0112 && d_split_2==16'h0112)) $stop; if (!(h_split_1==16'hfeed && h_split_2==16'h0112)) $stop; - end - if (cyc==6) begin - m_din <= 16'he33e; - if (!(a_split_1==16'he22e && a_split_2==16'he22e)) $stop; - if (!(d_split_1==16'h1ee1 && d_split_2==16'h0112)) $stop; + end + if (cyc==6) begin + m_din <= 16'he33e; + if (!(a_split_1==16'he22e && a_split_2==16'he22e)) $stop; + if (!(d_split_1==16'h1ee1 && d_split_2==16'h0112)) $stop; if (!(h_split_1==16'he11e && h_split_2==16'h1ee1)) $stop; - end - if (cyc==7) begin - $write("*-* All Finished *-*\n"); - $finish; - end + end + if (cyc==7) begin + $write("*-* All Finished *-*\n"); + $finish; + end end end // always @ (posedge clk) diff --git a/test_regress/t/t_alw_splitord.v b/test_regress/t/t_alw_splitord.v index b6529f97c..98f15f2b8 100644 --- a/test_regress/t/t_alw_splitord.v +++ b/test_regress/t/t_alw_splitord.v @@ -18,27 +18,27 @@ module t (/*AUTOARG*/ reg [15:0] c_split_1, c_split_2, c_split_3, c_split_4, c_split_5; always @ (posedge clk) begin if (cyc==0) begin - /*AUTORESET*/ - // Beginning of autoreset for uninitialized flops - c_split_1 <= 16'h0; - c_split_2 <= 16'h0; - c_split_3 <= 16'h0; - c_split_4 <= 0; - c_split_5 <= 0; - // End of automatics + /*AUTORESET*/ + // Beginning of autoreset for uninitialized flops + c_split_1 <= 16'h0; + c_split_2 <= 16'h0; + c_split_3 <= 16'h0; + c_split_4 <= 0; + c_split_5 <= 0; + // End of automatics end else begin - c_split_1 <= m_din; - c_split_2 <= c_split_1; - c_split_3 <= c_split_2 & {16{(cyc!=0)}}; - if (cyc==1) begin - c_split_4 <= 16'h4; - c_split_5 <= 16'h5; - end - else begin - c_split_4 <= c_split_3; - c_split_5 <= c_split_4; - end + c_split_1 <= m_din; + c_split_2 <= c_split_1; + c_split_3 <= c_split_2 & {16{(cyc!=0)}}; + if (cyc==1) begin + c_split_4 <= 16'h4; + c_split_5 <= 16'h5; + end + else begin + c_split_4 <= c_split_3; + c_split_5 <= c_split_4; + end end end @@ -46,29 +46,29 @@ module t (/*AUTOARG*/ reg [15:0] d_split_1, d_split_2; always @ (posedge clk) begin if (cyc==0) begin - /*AUTORESET*/ - // Beginning of autoreset for uninitialized flops - d_split_1 <= 16'h0; - d_split_2 <= 16'h0; - // End of automatics + /*AUTORESET*/ + // Beginning of autoreset for uninitialized flops + d_split_1 <= 16'h0; + d_split_2 <= 16'h0; + // End of automatics end else begin - d_split_1 <= m_din; - d_split_2 <= d_split_1; - d_split_1 <= ~m_din; + d_split_1 <= m_din; + d_split_2 <= d_split_1; + d_split_1 <= ~m_din; end end // Not OK always @ (posedge clk) begin if (cyc==0) begin - /*AUTORESET*/ - // Beginning of autoreset for uninitialized flops - // End of automatics + /*AUTORESET*/ + // Beginning of autoreset for uninitialized flops + // End of automatics end else begin - $write(" foo %x", m_din); - $write(" bar %x\n", m_din); + $write(" foo %x", m_din); + $write(" bar %x\n", m_din); end end @@ -76,15 +76,15 @@ module t (/*AUTOARG*/ reg [15:0] e_split_1, e_split_2; always @ (posedge clk) begin if (cyc==0) begin - /*AUTORESET*/ - // Beginning of autoreset for uninitialized flops - e_split_1 = 16'h0; - e_split_2 = 16'h0; - // End of automatics + /*AUTORESET*/ + // Beginning of autoreset for uninitialized flops + e_split_1 = 16'h0; + e_split_2 = 16'h0; + // End of automatics end else begin - e_split_1 = m_din; - e_split_2 = e_split_1; + e_split_1 = m_din; + e_split_2 = e_split_1; end end @@ -92,61 +92,61 @@ module t (/*AUTOARG*/ reg [15:0] f_split_1, f_split_2; always @ (posedge clk) begin if (cyc==0) begin - /*AUTORESET*/ - // Beginning of autoreset for uninitialized flops - f_split_1 = 16'h0; - f_split_2 = 16'h0; - // End of automatics + /*AUTORESET*/ + // Beginning of autoreset for uninitialized flops + f_split_1 = 16'h0; + f_split_2 = 16'h0; + // End of automatics end else begin - f_split_2 = f_split_1; - f_split_1 = m_din; + f_split_2 = f_split_1; + f_split_1 = m_din; end end always @ (posedge clk) begin if (cyc!=0) begin - //$write(" C %d %x %x\n", cyc, c_split_1, c_split_2); - cyc<=cyc+1; - if (cyc==1) begin - m_din <= 16'hfeed; - end - if (cyc==3) begin - end - if (cyc==4) begin - m_din <= 16'he11e; - if (!(d_split_1==16'h0112 && d_split_2==16'h0112)) $stop; - if (!(e_split_1==16'hfeed && e_split_2==16'hfeed)) $stop; - if (!(f_split_1==16'hfeed && f_split_2==16'hfeed)) $stop; - end - if (cyc==5) begin - m_din <= 16'he22e; - if (!(d_split_1==16'h0112 && d_split_2==16'h0112)) $stop; - // Two valid orderings, as we don't know which posedge clk gets evaled first - if (!(e_split_1==16'hfeed && e_split_2==16'hfeed) && !(e_split_1==16'he11e && e_split_2==16'he11e)) $stop; - if (!(f_split_1==16'hfeed && f_split_2==16'hfeed) && !(f_split_1==16'he11e && f_split_2==16'hfeed)) $stop; - end - if (cyc==6) begin - m_din <= 16'he33e; - if (!(c_split_1==16'he11e && c_split_2==16'hfeed && c_split_3==16'hfeed)) $stop; - if (!(d_split_1==16'h1ee1 && d_split_2==16'h0112)) $stop; - // Two valid orderings, as we don't know which posedge clk gets evaled first - if (!(e_split_1==16'he11e && e_split_2==16'he11e) && !(e_split_1==16'he22e && e_split_2==16'he22e)) $stop; - if (!(f_split_1==16'he11e && f_split_2==16'hfeed) && !(f_split_1==16'he22e && f_split_2==16'he11e)) $stop; - end - if (cyc==7) begin - m_din <= 16'he44e; - if (!(c_split_1==16'he22e && c_split_2==16'he11e && c_split_3==16'hfeed)) $stop; - end - if (cyc==8) begin - m_din <= 16'he55e; - if (!(c_split_1==16'he33e && c_split_2==16'he22e && c_split_3==16'he11e - && c_split_4==16'hfeed && c_split_5==16'hfeed)) $stop; - end - if (cyc==9) begin - $write("*-* All Finished *-*\n"); - $finish; - end + //$write(" C %d %x %x\n", cyc, c_split_1, c_split_2); + cyc<=cyc+1; + if (cyc==1) begin + m_din <= 16'hfeed; + end + if (cyc==3) begin + end + if (cyc==4) begin + m_din <= 16'he11e; + if (!(d_split_1==16'h0112 && d_split_2==16'h0112)) $stop; + if (!(e_split_1==16'hfeed && e_split_2==16'hfeed)) $stop; + if (!(f_split_1==16'hfeed && f_split_2==16'hfeed)) $stop; + end + if (cyc==5) begin + m_din <= 16'he22e; + if (!(d_split_1==16'h0112 && d_split_2==16'h0112)) $stop; + // Two valid orderings, as we don't know which posedge clk gets evaled first + if (!(e_split_1==16'hfeed && e_split_2==16'hfeed) && !(e_split_1==16'he11e && e_split_2==16'he11e)) $stop; + if (!(f_split_1==16'hfeed && f_split_2==16'hfeed) && !(f_split_1==16'he11e && f_split_2==16'hfeed)) $stop; + end + if (cyc==6) begin + m_din <= 16'he33e; + if (!(c_split_1==16'he11e && c_split_2==16'hfeed && c_split_3==16'hfeed)) $stop; + if (!(d_split_1==16'h1ee1 && d_split_2==16'h0112)) $stop; + // Two valid orderings, as we don't know which posedge clk gets evaled first + if (!(e_split_1==16'he11e && e_split_2==16'he11e) && !(e_split_1==16'he22e && e_split_2==16'he22e)) $stop; + if (!(f_split_1==16'he11e && f_split_2==16'hfeed) && !(f_split_1==16'he22e && f_split_2==16'he11e)) $stop; + end + if (cyc==7) begin + m_din <= 16'he44e; + if (!(c_split_1==16'he22e && c_split_2==16'he11e && c_split_3==16'hfeed)) $stop; + end + if (cyc==8) begin + m_din <= 16'he55e; + if (!(c_split_1==16'he33e && c_split_2==16'he22e && c_split_3==16'he11e + && c_split_4==16'hfeed && c_split_5==16'hfeed)) $stop; + end + if (cyc==9) begin + $write("*-* All Finished *-*\n"); + $finish; + end end end endmodule diff --git a/test_regress/t/t_array_packed_sysfunct.v b/test_regress/t/t_array_packed_sysfunct.v index fbbdec136..2c3c7520f 100644 --- a/test_regress/t/t_array_packed_sysfunct.v +++ b/test_regress/t/t_array_packed_sysfunct.v @@ -83,8 +83,8 @@ module t (/*AUTOARG*/ $write("cnt[30:4]=%0d slc=%0d dim=%0d wdt=%0d\n", cnt[30:4], slc, dim, wdt); `endif if (cnt[30:4]==1) begin - // big endian - if (slc==0) begin + // big endian + if (slc==0) begin // full array `checkh($dimensions (array_bg), 3); `checkh($bits (array_bg), WA*WB*WC); @@ -96,7 +96,7 @@ module t (/*AUTOARG*/ `checkh($increment (array_bg, dim), 1 ); `checkh($size (array_bg, dim), wdt ); end - end else if (slc==1) begin + end else if (slc==1) begin // single array element `checkh($dimensions (array_bg[2]), 2); `checkh($bits (array_bg[2]), WB*WC); @@ -109,7 +109,7 @@ module t (/*AUTOARG*/ `checkh($size (array_bg[2], dim-1), wdt ); end `ifndef VERILATOR // Unsupported slices don't maintain size correctly - end else if (slc==2) begin + end else if (slc==2) begin // half array `checkh($dimensions (array_bg[WA/2+1:2]), 3); `checkh($bits (array_bg[WA/2+1:2]), WA/2*WB*WC); @@ -122,10 +122,10 @@ module t (/*AUTOARG*/ `checkh($size (array_bg[WA/2+1:2], dim), wdt); end `endif - end + end end else if (cnt[30:4]==2) begin - // little endian - if (slc==0) begin + // little endian + if (slc==0) begin // full array `checkh($dimensions (array_lt), 3); `checkh($bits (array_lt), WA*WB*WC); @@ -137,7 +137,7 @@ module t (/*AUTOARG*/ `checkh($increment (array_lt, dim), -1 ); `checkh($size (array_lt, dim), wdt ); end - end else if (slc==1) begin + end else if (slc==1) begin // single array element `checkh($dimensions (array_lt[2]), 2); `checkh($bits (array_lt[2]), WB*WC); @@ -150,7 +150,7 @@ module t (/*AUTOARG*/ `checkh($size (array_lt[2], dim-1), wdt ); end `ifndef VERILATOR // Unsupported slices don't maintain size correctly - end else if (slc==2) begin + end else if (slc==2) begin // half array `checkh($dimensions (array_lt[2:WA/2+1]), 3); `checkh($bits (array_lt[2:WA/2+1]), WA/2*WB*WC); @@ -163,7 +163,7 @@ module t (/*AUTOARG*/ `checkh($size (array_lt[2:WA/2+1], dim), wdt ); end `endif - end + end end end diff --git a/test_regress/t/t_array_query.v b/test_regress/t/t_array_query.v index 5f824d520..b57a10494 100644 --- a/test_regress/t/t_array_query.v +++ b/test_regress/t/t_array_query.v @@ -20,8 +20,8 @@ module t (/*AUTOARG*/ reg c; array_test array_test_i (/*AUTOINST*/ - // Inputs - .clk (clk)); + // Inputs + .clk (clk)); endmodule diff --git a/test_regress/t/t_array_rev.v b/test_regress/t/t_array_rev.v index 79dbb15e0..47594bf5f 100644 --- a/test_regress/t/t_array_rev.v +++ b/test_regress/t/t_array_rev.v @@ -11,7 +11,7 @@ module t (/*AUTOARG*/ input clk; - integer cyc = 0; + integer cyc = 0; // verilator lint_off LITENDIAN logic arrd [0:1] = '{ 1'b1, 1'b0 }; // verilator lint_on LITENDIAN @@ -19,7 +19,7 @@ module t (/*AUTOARG*/ logic localbkw [1:0]; arr_rev arr_rev_u ( - .arrbkw (arrd), + .arrbkw (arrd), .y0(y0), .y1(y1) ); diff --git a/test_regress/t/t_arraysel_wide.v b/test_regress/t/t_arraysel_wide.v index 943216e4e..9f15a890b 100644 --- a/test_regress/t/t_arraysel_wide.v +++ b/test_regress/t/t_arraysel_wide.v @@ -11,13 +11,13 @@ module t (/*AUTOARG*/ inibble, onibble ); - input [3:0] inibble; + input [3:0] inibble; input [106:0] onibble; output reg [3:0] nnext [0:7]; // verilator lint_off WIDTH - wire [2:0] selline = (onibble >>> 102) & 7; + wire [2:0] selline = (onibble >>> 102) & 7; // verilator lint_on WIDTH always_comb begin diff --git a/test_regress/t/t_assert_basic.v b/test_regress/t/t_assert_basic.v index 0d718015d..6fa5271e8 100644 --- a/test_regress/t/t_assert_basic.v +++ b/test_regress/t/t_assert_basic.v @@ -11,7 +11,7 @@ module t (/*AUTOARG*/ input clk; - reg toggle; + reg toggle; integer cyc; initial cyc=1; wire [7:0] cyc_copy = cyc[7:0]; @@ -26,24 +26,24 @@ module t (/*AUTOARG*/ always @ (posedge clk) begin if (cyc!=0) begin - cyc <= cyc + 1; - toggle <= !cyc[0]; + cyc <= cyc + 1; + toggle <= !cyc[0]; if (cyc==7) assert (cyc[0] == cyc[1]); // bug743 - if (cyc==9) begin + if (cyc==9) begin `ifdef FAILING_ASSERTIONS - assert (0) else $info; - assert (0) else $info("Info message"); - assume (0) else $info("Info message from failing assumption"); - assert (0) else $info("Info message, cyc=%d", cyc); - InWarningBlock: assert (0) else $warning("Warning.... 1.0=%f 2.0=%f", 1.0, 2.0); - InErrorBlock: assert (0) else $error("Error...."); - assert (0) else $fatal(1,"Fatal...."); + assert (0) else $info; + assert (0) else $info("Info message"); + assume (0) else $info("Info message from failing assumption"); + assert (0) else $info("Info message, cyc=%d", cyc); + InWarningBlock: assert (0) else $warning("Warning.... 1.0=%f 2.0=%f", 1.0, 2.0); + InErrorBlock: assert (0) else $error("Error...."); + assert (0) else $fatal(1,"Fatal...."); `endif - end - if (cyc==10) begin - $write("*-* All Finished *-*\n"); - $finish; - end + end + if (cyc==10) begin + $write("*-* All Finished *-*\n"); + $finish; + end end end diff --git a/test_regress/t/t_assert_cover.v b/test_regress/t/t_assert_cover.v index b80282802..26a51005a 100644 --- a/test_regress/t/t_assert_cover.v +++ b/test_regress/t/t_assert_cover.v @@ -10,28 +10,28 @@ module t (/*AUTOARG*/ ); input clk; - reg toggle; + reg toggle; integer cyc; initial cyc=1; Test test (/*AUTOINST*/ - // Inputs - .clk (clk), - .toggle (toggle), - .cyc (cyc[31:0])); + // Inputs + .clk (clk), + .toggle (toggle), + .cyc (cyc[31:0])); Sub sub1 (.*); Sub sub2 (.*); always @ (posedge clk) begin if (cyc!=0) begin - cyc <= cyc + 1; - toggle <= !cyc[0]; - if (cyc==9) begin - end - if (cyc==10) begin - $write("*-* All Finished *-*\n"); - $finish; - end + cyc <= cyc + 1; + toggle <= !cyc[0]; + if (cyc==9) begin + end + if (cyc==10) begin + $write("*-* All Finished *-*\n"); + $finish; + end end end @@ -89,9 +89,9 @@ module Test genvar i; generate for (i=0; i<32; i=i+1) - begin: cycval - CycCover_i: `covclk( cyc[i] ); - end + begin: cycval + CycCover_i: `covclk( cyc[i] ); + end endgenerate `ifndef verilator // Unsupported @@ -99,8 +99,8 @@ module Test // Using a more complicated property property C1; @(posedge clk) - disable iff (!toggle) - cyc==5; + disable iff (!toggle) + cyc==5; endproperty cover property (C1) $display("*COVER: Cyc==5"); @@ -111,35 +111,35 @@ module Test // Each bin value must be <= 32 bits. Strange. cyc_value : coverpoint cyc { - } + } cyc_bined : coverpoint cyc { - bins zero = {0}; - bins low = {1,5}; - // Note 5 is also in the bin above. Only the first bin matching is counted. - bins mid = {[5:$]}; - // illegal_bins // Has precidence over "first matching bin", creates assertion - // ignore_bins // Not counted, and not part of total + bins zero = {0}; + bins low = {1,5}; + // Note 5 is also in the bin above. Only the first bin matching is counted. + bins mid = {[5:$]}; + // illegal_bins // Has precidence over "first matching bin", creates assertion + // ignore_bins // Not counted, and not part of total } toggle : coverpoint (toggle) { - bins off = {0}; - bins on = {1}; + bins off = {0}; + bins on = {1}; } cyc5 : coverpoint (cyc==5) { - bins five = {1}; + bins five = {1}; } - // option.at_least = {number}; // Default 1 - Hits to be considered covered + // option.at_least = {number}; // Default 1 - Hits to be considered covered // option.auto_bin_max = {number}; // Default 64 // option.comment = {string} - // option.goal = {number}; // Default 90% + // option.goal = {number}; // Default 90% // option.name = {string} - // option.per_instance = 1; // Default 0 - each instance separately counted (cadence default is 1) - // option.weight = {number}; // Default 1 + // option.per_instance = 1; // Default 0 - each instance separately counted (cadence default is 1) + // option.weight = {number}; // Default 1 // CROSS value_and_toggle: // else default is ___X__ - cross cyc_value, toggle; + cross cyc_value, toggle; endgroup counter1 c1 = new(); `endif diff --git a/test_regress/t/t_assert_disable_iff.v b/test_regress/t/t_assert_disable_iff.v index de74764dc..7a5b2b2fd 100644 --- a/test_regress/t/t_assert_disable_iff.v +++ b/test_regress/t/t_assert_disable_iff.v @@ -13,8 +13,8 @@ module t (/*AUTOARG*/ integer cyc; initial cyc=1; Test test (/*AUTOINST*/ - // Inputs - .clk (clk)); + // Inputs + .clk (clk)); always @ (posedge clk) begin if (cyc!=0) begin diff --git a/test_regress/t/t_assert_synth.v b/test_regress/t/t_assert_synth.v index 2a8f27e2b..f9d10ea2d 100644 --- a/test_regress/t/t_assert_synth.v +++ b/test_regress/t/t_assert_synth.v @@ -11,11 +11,11 @@ module t (/*AUTOARG*/ input clk; - reg a; initial a = 1'b1; - reg b_fc; initial b_fc = 1'b0; - reg b_pc; initial b_pc = 1'b0; - reg b_oh; initial b_oh = 1'b0; - reg b_oc; initial b_oc = 1'b0; + reg a; initial a = 1'b1; + reg b_fc; initial b_fc = 1'b0; + reg b_pc; initial b_pc = 1'b0; + reg b_oh; initial b_oh = 1'b0; + reg b_oc; initial b_oc = 1'b0; wire a_l = ~a; wire b_oc_l = ~b_oc; @@ -32,16 +32,16 @@ module t (/*AUTOARG*/ `else case ({a,b_fc}) `endif - 2'b0_0: ; - 2'b0_1: ; - 2'b1_0: ; - // Note no default + 2'b0_0: ; + 2'b0_1: ; + 2'b1_0: ; + // Note no default endcase priority case ({a,b_fc}) - 2'b0_0: ; - 2'b0_1: ; - 2'b1_0: ; - // Note no default + 2'b0_0: ; + 2'b0_1: ; + 2'b1_0: ; + // Note no default endcase end @@ -55,8 +55,8 @@ module t (/*AUTOARG*/ case (1'b1) // synopsys parallel_full `endif `endif - a: ; - b_pc: ; + a: ; + b_pc: ; endcase end @@ -68,46 +68,46 @@ module t (/*AUTOARG*/ integer cyc; initial cyc=1; always @ (posedge clk) begin if (cyc!=0) begin - cyc <= cyc + 1; - if (cyc==1) begin - a <= 1'b1; - b_fc <= 1'b0; - b_pc <= 1'b0; - b_oh <= 1'b0; - b_oc <= 1'b0; - end - if (cyc==2) begin - a <= 1'b0; - b_fc <= 1'b1; - b_pc <= 1'b1; - b_oh <= 1'b1; - b_oc <= 1'b1; - end - if (cyc==3) begin - a <= 1'b1; - b_fc <= 1'b0; - b_pc <= 1'b0; - b_oh <= 1'b0; - b_oc <= 1'b0; - end - if (cyc==4) begin + cyc <= cyc + 1; + if (cyc==1) begin + a <= 1'b1; + b_fc <= 1'b0; + b_pc <= 1'b0; + b_oh <= 1'b0; + b_oc <= 1'b0; + end + if (cyc==2) begin + a <= 1'b0; + b_fc <= 1'b1; + b_pc <= 1'b1; + b_oh <= 1'b1; + b_oc <= 1'b1; + end + if (cyc==3) begin + a <= 1'b1; + b_fc <= 1'b0; + b_pc <= 1'b0; + b_oh <= 1'b0; + b_oc <= 1'b0; + end + if (cyc==4) begin `ifdef FAILING_FULL - b_fc <= 1'b1; + b_fc <= 1'b1; `endif `ifdef FAILING_PARALLEL - b_pc <= 1'b1; + b_pc <= 1'b1; `endif `ifdef FAILING_OH - b_oh <= 1'b1; + b_oh <= 1'b1; `endif `ifdef FAILING_OC - b_oc <= 1'b1; + b_oc <= 1'b1; `endif - end - if (cyc==10) begin - $write("*-* All Finished *-*\n"); - $finish; - end + end + if (cyc==10) begin + $write("*-* All Finished *-*\n"); + $finish; + end end end diff --git a/test_regress/t/t_attr_parenstar.v b/test_regress/t/t_attr_parenstar.v index d96199a74..6aef83e9d 100644 --- a/test_regress/t/t_attr_parenstar.v +++ b/test_regress/t/t_attr_parenstar.v @@ -26,12 +26,12 @@ module t (/*AUTOARG*/ // Not legal in some simulators, legal in others // always @(* // cmt -// ) begin +// ) begin // if (clk) begin end // end always @ (* - ) begin + ) begin if (clk) begin end end diff --git a/test_regress/t/t_bench_mux4k.v b/test_regress/t/t_bench_mux4k.v index 10be1c273..b2936a7b8 100644 --- a/test_regress/t/t_bench_mux4k.v +++ b/test_regress/t/t_bench_mux4k.v @@ -26,19 +26,19 @@ module t (/*AUTOARG*/ /*AUTOWIRE*/ // Beginning of automatic wires (for undeclared instantiated-module outputs) - wire [`DATA_WIDTH-1:0] datao; // From mux4096 of mux4096.v + wire [`DATA_WIDTH-1:0] datao; // From mux4096 of mux4096.v // End of automatics reg [`DATA_WIDTH*`MUX1_SIZE*`MUX2_SIZE-1:0] datai; - reg [`ADDR_WIDTH-1:0] addr; + reg [`ADDR_WIDTH-1:0] addr; // Mux: takes in addr and datai and outputs datao mux4096 mux4096 (/*AUTOINST*/ - // Outputs - .datao (datao[`DATA_WIDTH-1:0]), - // Inputs - .datai (datai[`DATA_WIDTH*`MUX1_SIZE*`MUX2_SIZE-1:0]), - .addr (addr[`ADDR_WIDTH-1:0])); + // Outputs + .datao (datao[`DATA_WIDTH-1:0]), + // Inputs + .datai (datai[`DATA_WIDTH*`MUX1_SIZE*`MUX2_SIZE-1:0]), + .addr (addr[`ADDR_WIDTH-1:0])); // calculate what the answer should be from datai. This is bit @@ -48,9 +48,9 @@ module t (/*AUTOARG*/ integer j; always @(datai or addr) begin for(j=0;j<`DATA_WIDTH;j=j+1) begin - /* verilator lint_off WIDTH */ - datao_check[j] = datai >> ((`MUX1_SIZE*`MUX2_SIZE*j)+addr); - /* verilator lint_on WIDTH */ + /* verilator lint_off WIDTH */ + datao_check[j] = datai >> ((`MUX1_SIZE*`MUX2_SIZE*j)+addr); + /* verilator lint_on WIDTH */ end end @@ -59,19 +59,19 @@ module t (/*AUTOARG*/ always @ (posedge clk) begin // initial the input data with random values if (addr == 0) begin - result = 1; - datai = 0; - for(i=0; i<`MUX1_SIZE*`MUX2_SIZE; i=i+1) begin - /* verilator lint_off WIDTH */ - datai = (datai << `DATA_WIDTH) | ($random & {`DATA_WIDTH{1'b1}}); - /* verilator lint_on WIDTH */ - end + result = 1; + datai = 0; + for(i=0; i<`MUX1_SIZE*`MUX2_SIZE; i=i+1) begin + /* verilator lint_off WIDTH */ + datai = (datai << `DATA_WIDTH) | ($random & {`DATA_WIDTH{1'b1}}); + /* verilator lint_on WIDTH */ + end end addr <= addr + 1; if (datao_check != datao) begin - result = 0; - $stop; + result = 0; + $stop; end `ifdef TEST_VERBOSE @@ -79,8 +79,8 @@ module t (/*AUTOARG*/ `endif // only run the first 10 addresses for now if (addr > 10) begin - $write("*-* All Finished *-*\n"); - $finish; + $write("*-* All Finished *-*\n"); + $finish; end end diff --git a/test_regress/t/t_bind.v b/test_regress/t/t_bind.v index 33b2abaaf..27d98879b 100644 --- a/test_regress/t/t_bind.v +++ b/test_regress/t/t_bind.v @@ -17,14 +17,14 @@ module t (/*AUTOARG*/ ExampInst i (// Outputs - .o (o[31:0]), + .o (o[31:0]), // Inputs - .i (1'b0) + .i (1'b0) /*AUTOINST*/); Prog p (/*AUTOINST*/ - // Inputs - .si (si)); + // Inputs + .si (si)); always @ (posedge clk) begin if (!a_finished) $stop; @@ -37,7 +37,7 @@ endmodule module InstModule ( output logic [31:0] so, - input si + input si ); assign so = {32{si}}; endmodule @@ -52,9 +52,9 @@ module ExampInst (o,i); InstModule instName (// Outputs - .so (o[31:0]), + .so (o[31:0]), // Inputs - .si (i) + .si (i) /*AUTOINST*/); //bind InstModule Prog instProg diff --git a/test_regress/t/t_bind2.v b/test_regress/t/t_bind2.v index fd97a54d7..67f8e04f5 100644 --- a/test_regress/t/t_bind2.v +++ b/test_regress/t/t_bind2.v @@ -14,8 +14,8 @@ module t (/*AUTOARG*/ ); input clk; reg [7:0] p1; - reg [7:0] p2; - reg [7:0] p3; + reg [7:0] p2; + reg [7:0] p3; initial begin p1 = 8'h01; @@ -28,16 +28,16 @@ module t (/*AUTOARG*/ parameter int param3 = 8'h13; targetmod i_targetmod (/*AUTOINST*/ - // Inputs - .clk (clk)); + // Inputs + .clk (clk)); //Binding i_targetmod to mycheck --instantiates i_mycheck inside i_targetmod - //param1 not over-riden (as mycheck) (=> 0x31) - //param2 explicitly bound to targetmod value (=> 0x22) - //param3 explicitly bound to top value (=> 0x13) - //p1 implictly bound (.*), takes value from targetmod (=> 0x04) - //p2 explictly bound to targetmod (=> 0x05) - //p3 explictly bound to top (=> 0x03) + //param1 not over-riden (as mycheck) (=> 0x31) + //param2 explicitly bound to targetmod value (=> 0x22) + //param3 explicitly bound to top value (=> 0x13) + //p1 implictly bound (.*), takes value from targetmod (=> 0x04) + //p2 explictly bound to targetmod (=> 0x05) + //p3 explictly bound to top (=> 0x03) // Alternative unsupported form is i_targetmod bind targetmod mycheck @@ -50,7 +50,7 @@ module t (/*AUTOARG*/ endmodule module targetmod (input clk); - reg [7:0] p1; + reg [7:0] p1; reg [7:0] p2; reg [7:0] p3; diff --git a/test_regress/t/t_bitsel_slice.v b/test_regress/t/t_bitsel_slice.v index d8f9d9ad8..e644592ba 100644 --- a/test_regress/t/t_bitsel_slice.v +++ b/test_regress/t/t_bitsel_slice.v @@ -10,24 +10,24 @@ module t (/*AUTOARG*/ ); input clk; - integer cyc = 0; - reg [63:0] crc; - reg [63:0] sum; + integer cyc = 0; + reg [63:0] crc; + reg [63:0] sum; logic [2:0] [1:0] in; always @* in = crc[5:0]; /*AUTOWIRE*/ // Beginning of automatic wires (for undeclared instantiated-module outputs) - logic [1:0] [1:0] out; // From test of Test.v + logic [1:0] [1:0] out; // From test of Test.v // End of automatics Test test (/*AUTOINST*/ - // Outputs - .out (out/*[1:0][1:0]*/), - // Inputs - .clk (clk), - .in (in/*[2:0][1:0]*/)); + // Outputs + .out (out/*[1:0][1:0]*/), + // Inputs + .clk (clk), + .in (in/*[2:0][1:0]*/)); // Aggregate outputs into a single result vector wire [63:0] result = {60'h0, out[1],out[0]}; @@ -41,23 +41,23 @@ module t (/*AUTOARG*/ crc <= {crc[62:0], crc[63] ^ crc[2] ^ crc[0]}; sum <= result ^ {sum[62:0], sum[63] ^ sum[2] ^ sum[0]}; if (cyc==0) begin - // Setup - crc <= 64'h5aef0c8d_d70a4497; - sum <= 64'h0; + // Setup + crc <= 64'h5aef0c8d_d70a4497; + sum <= 64'h0; end else if (cyc<10) begin - sum <= 64'h0; + sum <= 64'h0; end else if (cyc<90) begin end else if (cyc==99) begin - $write("[%0t] cyc==%0d crc=%x sum=%x\n", $time, cyc, crc, sum); - if (crc !== 64'hc77bb9b3784ea091) $stop; - // What checksum will we end up with (above print should match) + $write("[%0t] cyc==%0d crc=%x sum=%x\n", $time, cyc, crc, sum); + if (crc !== 64'hc77bb9b3784ea091) $stop; + // What checksum will we end up with (above print should match) `define EXPECTED_SUM 64'hdc21e42d85441511 - if (sum !== `EXPECTED_SUM) $stop; - $write("*-* All Finished *-*\n"); - $finish; + if (sum !== `EXPECTED_SUM) $stop; + $write("*-* All Finished *-*\n"); + $finish; end end diff --git a/test_regress/t/t_bitsel_struct3.v b/test_regress/t/t_bitsel_struct3.v index 5edb5d0a8..0b7d276da 100644 --- a/test_regress/t/t_bitsel_struct3.v +++ b/test_regress/t/t_bitsel_struct3.v @@ -30,9 +30,9 @@ module t(/*AUTOARG*/ union packed { logic [31:0] [7:0] idx; - struct packed { - logic [15:0] z, y, x; - logic [25:0] [7:0] r; + struct packed { + logic [15:0] z, y, x; + logic [25:0] [7:0] r; } nam; } gpr; @@ -40,9 +40,9 @@ module t(/*AUTOARG*/ initial begin b = {16'h8765,16'h4321}; - a = b[19:12]; // This works - c = b[8+:8]; // This fails - d = b[11-:8]; // This fails + a = b[19:12]; // This works + c = b[8+:8]; // This fails + d = b[11-:8]; // This fails `checkh(a, 8'h54); `checkh(c, 8'h43); `checkh(d, 8'h32); diff --git a/test_regress/t/t_blocking.v b/test_regress/t/t_blocking.v index fa6ec64de..1f8013fbc 100644 --- a/test_regress/t/t_blocking.v +++ b/test_regress/t/t_blocking.v @@ -24,50 +24,50 @@ module t (/*AUTOARG*/ // surefire lint_off STMINI // surefire lint_off NBAJAM - always @ (posedge clk) begin // filp-flops with asynchronous reset + always @ (posedge clk) begin // filp-flops with asynchronous reset if (0) begin - _mode <= 0; + _mode <= 0; end else begin - _mode <= _mode + 1; - if (_mode==0) begin - $write("[%0t] t_blocking: Running\n", $time); - a <= 8'd0; - b <= 8'd0; - c <= 8'd0; - end - else if (_mode==1) begin - if (a !== 8'd0) $stop; - if (b !== 8'd0) $stop; - if (c !== 8'd0) $stop; - a <= b; - b <= 8'd1; - c <= b; - if (a !== 8'd0) $stop; - if (b !== 8'd0) $stop; - if (c !== 8'd0) $stop; - end - else if (_mode==2) begin - if (a !== 8'd0) $stop; - if (b !== 8'd1) $stop; - if (c !== 8'd0) $stop; - a <= b; - b <= 8'd2; - c <= b; - if (a !== 8'd0) $stop; - if (b !== 8'd1) $stop; - if (c !== 8'd0) $stop; - end - else if (_mode==3) begin - if (a !== 8'd1) $stop; - if (b !== 8'd2) $stop; - if (c !== 8'd1) $stop; - end - else if (_mode==4) begin - if (mode_d3r != 8'd1) $stop; - $write("*-* All Finished *-*\n"); - $finish; - end + _mode <= _mode + 1; + if (_mode==0) begin + $write("[%0t] t_blocking: Running\n", $time); + a <= 8'd0; + b <= 8'd0; + c <= 8'd0; + end + else if (_mode==1) begin + if (a !== 8'd0) $stop; + if (b !== 8'd0) $stop; + if (c !== 8'd0) $stop; + a <= b; + b <= 8'd1; + c <= b; + if (a !== 8'd0) $stop; + if (b !== 8'd0) $stop; + if (c !== 8'd0) $stop; + end + else if (_mode==2) begin + if (a !== 8'd0) $stop; + if (b !== 8'd1) $stop; + if (c !== 8'd0) $stop; + a <= b; + b <= 8'd2; + c <= b; + if (a !== 8'd0) $stop; + if (b !== 8'd1) $stop; + if (c !== 8'd0) $stop; + end + else if (_mode==3) begin + if (a !== 8'd1) $stop; + if (b !== 8'd2) $stop; + if (c !== 8'd1) $stop; + end + else if (_mode==4) begin + if (mode_d3r != 8'd1) $stop; + $write("*-* All Finished *-*\n"); + $finish; + end end end @@ -81,15 +81,15 @@ module t (/*AUTOARG*/ // surefire lint_off SEQASS always @ (posedge clk) begin if (_mode==1) begin - bits[14:13] <= 2'b11; - bits[12] <= 1'b1; + bits[14:13] <= 2'b11; + bits[12] <= 1'b1; end if (_mode==2) begin - bits[11:10] <= 2'b10; - bits[13] <= 0; + bits[11:10] <= 2'b10; + bits[13] <= 0; end if (_mode==3) begin - if (bits !== 5'b10110) $stop; + if (bits !== 5'b10110) $stop; end end diff --git a/test_regress/t/t_case_66bits.v b/test_regress/t/t_case_66bits.v index 95333a83b..b461f237a 100644 --- a/test_regress/t/t_case_66bits.v +++ b/test_regress/t/t_case_66bits.v @@ -15,12 +15,12 @@ module t (/*AUTOARG*/ always @(posedge clk) begin case(idx) - 1: idx = 100; - 100: begin - $write("*-* All Finished *-*\n"); - $finish; - end - default: $stop; + 1: idx = 100; + 100: begin + $write("*-* All Finished *-*\n"); + $finish; + end + default: $stop; endcase end diff --git a/test_regress/t/t_case_auto1.v b/test_regress/t/t_case_auto1.v index 6d82878b6..a7cba372a 100644 --- a/test_regress/t/t_case_auto1.v +++ b/test_regress/t/t_case_auto1.v @@ -12,35 +12,35 @@ module t (/*AUTOARG*/ input clk; localparam // synopsys enum En_State - EP_State_IDLE = {3'b000,5'd00}, - EP_State_CMDSHIFT0 = {3'b001,5'd00}, - EP_State_CMDSHIFT13 = {3'b001,5'd13}, - EP_State_CMDSHIFT14 = {3'b001,5'd14}, - EP_State_CMDSHIFT15 = {3'b001,5'd15}, - EP_State_CMDSHIFT16 = {3'b001,5'd16}, - EP_State_DWAIT = {3'b010,5'd00}, - EP_State_DSHIFT0 = {3'b100,5'd00}, - EP_State_DSHIFT1 = {3'b100,5'd01}, - EP_State_DSHIFT15 = {3'b100,5'd15}; + EP_State_IDLE = {3'b000,5'd00}, + EP_State_CMDSHIFT0 = {3'b001,5'd00}, + EP_State_CMDSHIFT13 = {3'b001,5'd13}, + EP_State_CMDSHIFT14 = {3'b001,5'd14}, + EP_State_CMDSHIFT15 = {3'b001,5'd15}, + EP_State_CMDSHIFT16 = {3'b001,5'd16}, + EP_State_DWAIT = {3'b010,5'd00}, + EP_State_DSHIFT0 = {3'b100,5'd00}, + EP_State_DSHIFT1 = {3'b100,5'd01}, + EP_State_DSHIFT15 = {3'b100,5'd15}; - reg [7:0] /* synopsys enum En_State */ - m_state_xr; // Last command, for debugging + reg [7:0] /* synopsys enum En_State */ + m_state_xr; // Last command, for debugging /*AUTOASCIIENUM("m_state_xr", "m_stateAscii_xr", "EP_State_")*/ // Beginning of automatic ASCII enum decoding - reg [79:0] m_stateAscii_xr; // Decode of m_state_xr + reg [79:0] m_stateAscii_xr; // Decode of m_state_xr always @(m_state_xr) begin case ({m_state_xr}) - EP_State_IDLE: m_stateAscii_xr = "idle "; - EP_State_CMDSHIFT0: m_stateAscii_xr = "cmdshift0 "; - EP_State_CMDSHIFT13: m_stateAscii_xr = "cmdshift13"; - EP_State_CMDSHIFT14: m_stateAscii_xr = "cmdshift14"; - EP_State_CMDSHIFT15: m_stateAscii_xr = "cmdshift15"; - EP_State_CMDSHIFT16: m_stateAscii_xr = "cmdshift16"; - EP_State_DWAIT: m_stateAscii_xr = "dwait "; - EP_State_DSHIFT0: m_stateAscii_xr = "dshift0 "; - EP_State_DSHIFT1: m_stateAscii_xr = "dshift1 "; - EP_State_DSHIFT15: m_stateAscii_xr = "dshift15 "; - default: m_stateAscii_xr = "%Error "; + EP_State_IDLE: m_stateAscii_xr = "idle "; + EP_State_CMDSHIFT0: m_stateAscii_xr = "cmdshift0 "; + EP_State_CMDSHIFT13: m_stateAscii_xr = "cmdshift13"; + EP_State_CMDSHIFT14: m_stateAscii_xr = "cmdshift14"; + EP_State_CMDSHIFT15: m_stateAscii_xr = "cmdshift15"; + EP_State_CMDSHIFT16: m_stateAscii_xr = "cmdshift16"; + EP_State_DWAIT: m_stateAscii_xr = "dwait "; + EP_State_DSHIFT0: m_stateAscii_xr = "dshift0 "; + EP_State_DSHIFT1: m_stateAscii_xr = "dshift1 "; + EP_State_DSHIFT15: m_stateAscii_xr = "dshift15 "; + default: m_stateAscii_xr = "%Error "; endcase end // End of automatics @@ -48,28 +48,28 @@ module t (/*AUTOARG*/ integer cyc; initial cyc=1; always @ (posedge clk) begin if (cyc!=0) begin - cyc <= cyc + 1; - //$write("%d %x %x %x\n", cyc, data, wrapcheck_a, wrapcheck_b); - if (cyc==1) begin - m_state_xr <= EP_State_IDLE; - end - if (cyc==2) begin - if (m_stateAscii_xr != "idle ") $stop; - m_state_xr <= EP_State_CMDSHIFT13; - end - if (cyc==3) begin - if (m_stateAscii_xr != "cmdshift13") $stop; - m_state_xr <= EP_State_CMDSHIFT16; - end - if (cyc==4) begin - if (m_stateAscii_xr != "cmdshift16") $stop; - m_state_xr <= EP_State_DWAIT; - end - if (cyc==9) begin - if (m_stateAscii_xr != "dwait ") $stop; - $write("*-* All Finished *-*\n"); - $finish; - end + cyc <= cyc + 1; + //$write("%d %x %x %x\n", cyc, data, wrapcheck_a, wrapcheck_b); + if (cyc==1) begin + m_state_xr <= EP_State_IDLE; + end + if (cyc==2) begin + if (m_stateAscii_xr != "idle ") $stop; + m_state_xr <= EP_State_CMDSHIFT13; + end + if (cyc==3) begin + if (m_stateAscii_xr != "cmdshift13") $stop; + m_state_xr <= EP_State_CMDSHIFT16; + end + if (cyc==4) begin + if (m_stateAscii_xr != "cmdshift16") $stop; + m_state_xr <= EP_State_DWAIT; + end + if (cyc==9) begin + if (m_stateAscii_xr != "dwait ") $stop; + $write("*-* All Finished *-*\n"); + $finish; + end end end diff --git a/test_regress/t/t_case_deep.v b/test_regress/t/t_case_deep.v index 1041a0281..ced8ee44d 100644 --- a/test_regress/t/t_case_deep.v +++ b/test_regress/t/t_case_deep.v @@ -10,28 +10,28 @@ module t (/*AUTOARG*/ ); input clk; - integer cyc = 0; - reg [63:0] crc; - reg [63:0] sum; + integer cyc = 0; + reg [63:0] crc; + reg [63:0] sum; // Take CRC data and apply to testblock inputs wire [33:0] in = crc[33:0]; /*AUTOWIRE*/ // Beginning of automatic wires (for undeclared instantiated-module outputs) - wire [31:0] code; // From test of Test.v - wire [4:0] len; // From test of Test.v - wire next; // From test of Test.v + wire [31:0] code; // From test of Test.v + wire [4:0] len; // From test of Test.v + wire next; // From test of Test.v // End of automatics Test test (/*AUTOINST*/ - // Outputs - .next (next), - .code (code[31:0]), - .len (len[4:0]), - // Inputs - .clk (clk), - .in (in[33:0])); + // Outputs + .next (next), + .code (code[31:0]), + .len (len[4:0]), + // Inputs + .clk (clk), + .in (in[33:0])); // Aggregate outputs into a single result vector wire [63:0] result = {26'h0, next, len, code}; @@ -48,20 +48,20 @@ module t (/*AUTOARG*/ crc <= {crc[62:0], crc[63] ^ crc[2] ^ crc[0]}; sum <= result ^ {sum[62:0], sum[63] ^ sum[2] ^ sum[0]}; if (cyc==0) begin - // Setup - crc <= 64'h5aef0c8d_d70a4497; + // Setup + crc <= 64'h5aef0c8d_d70a4497; end else if (cyc<10) begin - sum <= 64'h0; + sum <= 64'h0; end else if (cyc<90) begin end else if (cyc==99) begin - $write("[%0t] cyc==%0d crc=%x sum=%x\n", $time, cyc, crc, sum); - if (crc !== 64'hc77bb9b3784ea091) $stop; - if (sum !== `EXPECTED_SUM) $stop; - $write("*-* All Finished *-*\n"); - $finish; + $write("[%0t] cyc==%0d crc=%x sum=%x\n", $time, cyc, crc, sum); + if (crc !== 64'hc77bb9b3784ea091) $stop; + if (sum !== `EXPECTED_SUM) $stop; + $write("*-* All Finished *-*\n"); + $finish; end end @@ -76,15 +76,15 @@ module Test (/*AUTOARG*/ input clk; input [33:0] in; - output next; + output next; output [31:0] code; - output [4:0] len; + output [4:0] len; /*AUTOREG*/ // Beginning of automatic regs (for this module's undeclared outputs) - reg [31:0] code; - reg [4:0] len; - reg next; + reg [31:0] code; + reg [4:0] len; + reg next; // End of automatics /* @@ -99,31 +99,31 @@ pat: my ($try, $val, $mask); try: for ($try=0; ; $try++) { - next pat if $try>50; - $val = 0; - for (my $bit=23; $bit>(23-$len); $bit--) { - my $b = int(rand()*2); - $val |= (1<<$bit) if $b; - } - $mask = (1<<(23-$len+1))-1; - for (my $testval = $val; $testval <= ($val + $mask); $testval ++) { - next try if $used[$testval]; - } - last; + next pat if $try>50; + $val = 0; + for (my $bit=23; $bit>(23-$len); $bit--) { + my $b = int(rand()*2); + $val |= (1<<$bit) if $b; + } + $mask = (1<<(23-$len+1))-1; + for (my $testval = $val; $testval <= ($val + $mask); $testval ++) { + next try if $used[$testval]; + } + last; } my $bits = ""; my $val2 = 0; for (my $bit=23; $bit>(23-$len); $bit--) { - my $b = ($val & (1<<$bit)); - $bits .= $b?'1':'0'; + my $b = ($val & (1<<$bit)); + $bits .= $b?'1':'0'; } for (my $testval = $val; $testval <= ($val + $mask); $testval++) { - $used[$testval]= 1; #printf "U%08x\n", $testval; + $used[$testval]= 1; #printf "U%08x\n", $testval; } if ($try<90) { - printf +(" 24'b%s: {next, len, code} = {in[%02d], 5'd%02d, 32'd%03d};\n" - ,$bits.("?"x(24-$len)), 31-$len, $len, $pat); - $pat++; + printf +(" 24'b%s: {next, len, code} = {in[%02d], 5'd%02d, 32'd%03d};\n" + ,$bits.("?"x(24-$len)), 31-$len, $len, $pat); + $pat++; } } */ @@ -133,211 +133,211 @@ pat: code = 32'd0; len = 5'b11111; casez (in[31:8]) - 24'b1010????????????????????: {next, len, code} = {in[27], 5'd04, 32'd000}; - 24'b1100????????????????????: {next, len, code} = {in[27], 5'd04, 32'd001}; - 24'b0110????????????????????: {next, len, code} = {in[27], 5'd04, 32'd002}; - 24'b1001????????????????????: {next, len, code} = {in[27], 5'd04, 32'd003}; - 24'b1101????????????????????: {next, len, code} = {in[27], 5'd04, 32'd004}; - 24'b0011????????????????????: {next, len, code} = {in[27], 5'd04, 32'd005}; - 24'b0001????????????????????: {next, len, code} = {in[27], 5'd04, 32'd006}; - 24'b10001???????????????????: {next, len, code} = {in[26], 5'd05, 32'd007}; - 24'b01110???????????????????: {next, len, code} = {in[26], 5'd05, 32'd008}; - 24'b01000???????????????????: {next, len, code} = {in[26], 5'd05, 32'd009}; - 24'b00001???????????????????: {next, len, code} = {in[26], 5'd05, 32'd010}; - 24'b11100???????????????????: {next, len, code} = {in[26], 5'd05, 32'd011}; - 24'b01011???????????????????: {next, len, code} = {in[26], 5'd05, 32'd012}; - 24'b100001??????????????????: {next, len, code} = {in[25], 5'd06, 32'd013}; - 24'b111110??????????????????: {next, len, code} = {in[25], 5'd06, 32'd014}; - 24'b010010??????????????????: {next, len, code} = {in[25], 5'd06, 32'd015}; - 24'b001011??????????????????: {next, len, code} = {in[25], 5'd06, 32'd016}; - 24'b101110??????????????????: {next, len, code} = {in[25], 5'd06, 32'd017}; - 24'b111011??????????????????: {next, len, code} = {in[25], 5'd06, 32'd018}; - 24'b0111101?????????????????: {next, len, code} = {in[24], 5'd07, 32'd020}; - 24'b0010100?????????????????: {next, len, code} = {in[24], 5'd07, 32'd021}; - 24'b0111111?????????????????: {next, len, code} = {in[24], 5'd07, 32'd022}; - 24'b1011010?????????????????: {next, len, code} = {in[24], 5'd07, 32'd023}; - 24'b1000000?????????????????: {next, len, code} = {in[24], 5'd07, 32'd024}; - 24'b1011111?????????????????: {next, len, code} = {in[24], 5'd07, 32'd025}; - 24'b1110100?????????????????: {next, len, code} = {in[24], 5'd07, 32'd026}; - 24'b01111100????????????????: {next, len, code} = {in[23], 5'd08, 32'd027}; - 24'b00000110????????????????: {next, len, code} = {in[23], 5'd08, 32'd028}; - 24'b00000101????????????????: {next, len, code} = {in[23], 5'd08, 32'd029}; - 24'b01001100????????????????: {next, len, code} = {in[23], 5'd08, 32'd030}; - 24'b10110110????????????????: {next, len, code} = {in[23], 5'd08, 32'd031}; - 24'b00100110????????????????: {next, len, code} = {in[23], 5'd08, 32'd032}; - 24'b11110010????????????????: {next, len, code} = {in[23], 5'd08, 32'd033}; - 24'b010011101???????????????: {next, len, code} = {in[22], 5'd09, 32'd034}; - 24'b001000000???????????????: {next, len, code} = {in[22], 5'd09, 32'd035}; - 24'b010101111???????????????: {next, len, code} = {in[22], 5'd09, 32'd036}; - 24'b010101010???????????????: {next, len, code} = {in[22], 5'd09, 32'd037}; - 24'b010011011???????????????: {next, len, code} = {in[22], 5'd09, 32'd038}; - 24'b010100011???????????????: {next, len, code} = {in[22], 5'd09, 32'd039}; - 24'b010101000???????????????: {next, len, code} = {in[22], 5'd09, 32'd040}; - 24'b1111010101??????????????: {next, len, code} = {in[21], 5'd10, 32'd041}; - 24'b0010001000??????????????: {next, len, code} = {in[21], 5'd10, 32'd042}; - 24'b0101001101??????????????: {next, len, code} = {in[21], 5'd10, 32'd043}; - 24'b0010010100??????????????: {next, len, code} = {in[21], 5'd10, 32'd044}; - 24'b1011001110??????????????: {next, len, code} = {in[21], 5'd10, 32'd045}; - 24'b1111000011??????????????: {next, len, code} = {in[21], 5'd10, 32'd046}; - 24'b0101000000??????????????: {next, len, code} = {in[21], 5'd10, 32'd047}; - 24'b1111110000??????????????: {next, len, code} = {in[21], 5'd10, 32'd048}; - 24'b10110111010?????????????: {next, len, code} = {in[20], 5'd11, 32'd049}; - 24'b11110000011?????????????: {next, len, code} = {in[20], 5'd11, 32'd050}; - 24'b01001111011?????????????: {next, len, code} = {in[20], 5'd11, 32'd051}; - 24'b00101011011?????????????: {next, len, code} = {in[20], 5'd11, 32'd052}; - 24'b01010010100?????????????: {next, len, code} = {in[20], 5'd11, 32'd053}; - 24'b11110111100?????????????: {next, len, code} = {in[20], 5'd11, 32'd054}; - 24'b00100111001?????????????: {next, len, code} = {in[20], 5'd11, 32'd055}; - 24'b10110001010?????????????: {next, len, code} = {in[20], 5'd11, 32'd056}; - 24'b10000010000?????????????: {next, len, code} = {in[20], 5'd11, 32'd057}; - 24'b111111101100????????????: {next, len, code} = {in[19], 5'd12, 32'd058}; - 24'b100000111110????????????: {next, len, code} = {in[19], 5'd12, 32'd059}; - 24'b100000110010????????????: {next, len, code} = {in[19], 5'd12, 32'd060}; - 24'b100000111001????????????: {next, len, code} = {in[19], 5'd12, 32'd061}; - 24'b010100101111????????????: {next, len, code} = {in[19], 5'd12, 32'd062}; - 24'b001000001100????????????: {next, len, code} = {in[19], 5'd12, 32'd063}; - 24'b000001111111????????????: {next, len, code} = {in[19], 5'd12, 32'd064}; - 24'b011111010100????????????: {next, len, code} = {in[19], 5'd12, 32'd065}; - 24'b1110101111101???????????: {next, len, code} = {in[18], 5'd13, 32'd066}; - 24'b0100110101110???????????: {next, len, code} = {in[18], 5'd13, 32'd067}; - 24'b1111111011011???????????: {next, len, code} = {in[18], 5'd13, 32'd068}; - 24'b0101011011001???????????: {next, len, code} = {in[18], 5'd13, 32'd069}; - 24'b0010000101100???????????: {next, len, code} = {in[18], 5'd13, 32'd070}; - 24'b1111111101101???????????: {next, len, code} = {in[18], 5'd13, 32'd071}; - 24'b1011110010110???????????: {next, len, code} = {in[18], 5'd13, 32'd072}; - 24'b0101010111010???????????: {next, len, code} = {in[18], 5'd13, 32'd073}; - 24'b1111011010010???????????: {next, len, code} = {in[18], 5'd13, 32'd074}; - 24'b01010100100011??????????: {next, len, code} = {in[17], 5'd14, 32'd075}; - 24'b10110000110010??????????: {next, len, code} = {in[17], 5'd14, 32'd076}; - 24'b10111101001111??????????: {next, len, code} = {in[17], 5'd14, 32'd077}; - 24'b10110000010101??????????: {next, len, code} = {in[17], 5'd14, 32'd078}; - 24'b00101011001111??????????: {next, len, code} = {in[17], 5'd14, 32'd079}; - 24'b00100000101100??????????: {next, len, code} = {in[17], 5'd14, 32'd080}; - 24'b11111110010111??????????: {next, len, code} = {in[17], 5'd14, 32'd081}; - 24'b10110010100000??????????: {next, len, code} = {in[17], 5'd14, 32'd082}; - 24'b11101011101000??????????: {next, len, code} = {in[17], 5'd14, 32'd083}; - 24'b01010000011111??????????: {next, len, code} = {in[17], 5'd14, 32'd084}; - 24'b101111011001011?????????: {next, len, code} = {in[16], 5'd15, 32'd085}; - 24'b101111010001100?????????: {next, len, code} = {in[16], 5'd15, 32'd086}; - 24'b100000111100111?????????: {next, len, code} = {in[16], 5'd15, 32'd087}; - 24'b001010101011000?????????: {next, len, code} = {in[16], 5'd15, 32'd088}; - 24'b111111100100001?????????: {next, len, code} = {in[16], 5'd15, 32'd089}; - 24'b001001011000010?????????: {next, len, code} = {in[16], 5'd15, 32'd090}; - 24'b011110011001011?????????: {next, len, code} = {in[16], 5'd15, 32'd091}; - 24'b111111111111010?????????: {next, len, code} = {in[16], 5'd15, 32'd092}; - 24'b101111001010011?????????: {next, len, code} = {in[16], 5'd15, 32'd093}; - 24'b100000110000111?????????: {next, len, code} = {in[16], 5'd15, 32'd094}; - 24'b0010010000000101????????: {next, len, code} = {in[15], 5'd16, 32'd095}; - 24'b0010010010101001????????: {next, len, code} = {in[15], 5'd16, 32'd096}; - 24'b1111011010110010????????: {next, len, code} = {in[15], 5'd16, 32'd097}; - 24'b0010010001100100????????: {next, len, code} = {in[15], 5'd16, 32'd098}; - 24'b0101011101110100????????: {next, len, code} = {in[15], 5'd16, 32'd099}; - 24'b0101011010001111????????: {next, len, code} = {in[15], 5'd16, 32'd100}; - 24'b0010000110011111????????: {next, len, code} = {in[15], 5'd16, 32'd101}; - 24'b0101010010000101????????: {next, len, code} = {in[15], 5'd16, 32'd102}; - 24'b1110101011000000????????: {next, len, code} = {in[15], 5'd16, 32'd103}; - 24'b1111000000110010????????: {next, len, code} = {in[15], 5'd16, 32'd104}; - 24'b0111100010001101????????: {next, len, code} = {in[15], 5'd16, 32'd105}; - 24'b00100010110001100???????: {next, len, code} = {in[14], 5'd17, 32'd106}; - 24'b00100010101101010???????: {next, len, code} = {in[14], 5'd17, 32'd107}; - 24'b11111110111100000???????: {next, len, code} = {in[14], 5'd17, 32'd108}; - 24'b00100000111010000???????: {next, len, code} = {in[14], 5'd17, 32'd109}; - 24'b00100111011101001???????: {next, len, code} = {in[14], 5'd17, 32'd110}; - 24'b11111110111000011???????: {next, len, code} = {in[14], 5'd17, 32'd111}; - 24'b11110001101000100???????: {next, len, code} = {in[14], 5'd17, 32'd112}; - 24'b11101011101011101???????: {next, len, code} = {in[14], 5'd17, 32'd113}; - 24'b01010000100101011???????: {next, len, code} = {in[14], 5'd17, 32'd114}; - 24'b00100100110011001???????: {next, len, code} = {in[14], 5'd17, 32'd115}; - 24'b01001110010101000???????: {next, len, code} = {in[14], 5'd17, 32'd116}; - 24'b010011110101001000??????: {next, len, code} = {in[13], 5'd18, 32'd117}; - 24'b111010101110010010??????: {next, len, code} = {in[13], 5'd18, 32'd118}; - 24'b001001001001111000??????: {next, len, code} = {in[13], 5'd18, 32'd119}; - 24'b101111000110111101??????: {next, len, code} = {in[13], 5'd18, 32'd120}; - 24'b101101111010101001??????: {next, len, code} = {in[13], 5'd18, 32'd121}; - 24'b111101110010111110??????: {next, len, code} = {in[13], 5'd18, 32'd122}; - 24'b010100100011010000??????: {next, len, code} = {in[13], 5'd18, 32'd123}; - 24'b001001001111011001??????: {next, len, code} = {in[13], 5'd18, 32'd124}; - 24'b010100110010001001??????: {next, len, code} = {in[13], 5'd18, 32'd125}; - 24'b111010110000111000??????: {next, len, code} = {in[13], 5'd18, 32'd126}; - 24'b111010110011000101??????: {next, len, code} = {in[13], 5'd18, 32'd127}; - 24'b010100001000111001??????: {next, len, code} = {in[13], 5'd18, 32'd128}; - 24'b1000001011000110100?????: {next, len, code} = {in[12], 5'd19, 32'd129}; - 24'b0010010111001110110?????: {next, len, code} = {in[12], 5'd19, 32'd130}; - 24'b0101011001000001101?????: {next, len, code} = {in[12], 5'd19, 32'd131}; - 24'b0101000010010101011?????: {next, len, code} = {in[12], 5'd19, 32'd132}; - 24'b1111011111101001101?????: {next, len, code} = {in[12], 5'd19, 32'd133}; - 24'b1011001000101010110?????: {next, len, code} = {in[12], 5'd19, 32'd134}; - 24'b1011000001000100001?????: {next, len, code} = {in[12], 5'd19, 32'd135}; - 24'b1110101100010011001?????: {next, len, code} = {in[12], 5'd19, 32'd136}; - 24'b0010010111010111110?????: {next, len, code} = {in[12], 5'd19, 32'd137}; - 24'b0010010001100111100?????: {next, len, code} = {in[12], 5'd19, 32'd138}; - 24'b1011001011100000101?????: {next, len, code} = {in[12], 5'd19, 32'd139}; - 24'b1011000100010100101?????: {next, len, code} = {in[12], 5'd19, 32'd140}; - 24'b1111111001000111011?????: {next, len, code} = {in[12], 5'd19, 32'd141}; - 24'b00100010111101101101????: {next, len, code} = {in[11], 5'd20, 32'd142}; - 24'b10000010101010101101????: {next, len, code} = {in[11], 5'd20, 32'd143}; - 24'b10110010100101001101????: {next, len, code} = {in[11], 5'd20, 32'd144}; - 24'b01010110111100010000????: {next, len, code} = {in[11], 5'd20, 32'd145}; - 24'b10110111110011001001????: {next, len, code} = {in[11], 5'd20, 32'd146}; - 24'b11111101101100100101????: {next, len, code} = {in[11], 5'd20, 32'd147}; - 24'b10110000010100100001????: {next, len, code} = {in[11], 5'd20, 32'd148}; - 24'b10110010011010110110????: {next, len, code} = {in[11], 5'd20, 32'd149}; - 24'b01111001010000011000????: {next, len, code} = {in[11], 5'd20, 32'd150}; - 24'b11110110001011011011????: {next, len, code} = {in[11], 5'd20, 32'd151}; - 24'b01010000100100001011????: {next, len, code} = {in[11], 5'd20, 32'd152}; - 24'b10110001100101110111????: {next, len, code} = {in[11], 5'd20, 32'd153}; - 24'b10111100110111101000????: {next, len, code} = {in[11], 5'd20, 32'd154}; - 24'b01010001010111010000????: {next, len, code} = {in[11], 5'd20, 32'd155}; - 24'b01010100111110001110????: {next, len, code} = {in[11], 5'd20, 32'd156}; - 24'b11111110011001100111????: {next, len, code} = {in[11], 5'd20, 32'd157}; - 24'b11110111111101010001????: {next, len, code} = {in[11], 5'd20, 32'd158}; - 24'b10110000010111100000????: {next, len, code} = {in[11], 5'd20, 32'd159}; - 24'b01001111100001000101????: {next, len, code} = {in[11], 5'd20, 32'd160}; - 24'b01010010000111010110????: {next, len, code} = {in[11], 5'd20, 32'd161}; - 24'b11101010101011101111????: {next, len, code} = {in[11], 5'd20, 32'd162}; - 24'b11111110010011100011????: {next, len, code} = {in[11], 5'd20, 32'd163}; - 24'b01010111001111101111????: {next, len, code} = {in[11], 5'd20, 32'd164}; - 24'b10110001111111111101????: {next, len, code} = {in[11], 5'd20, 32'd165}; - 24'b10110001001100110000????: {next, len, code} = {in[11], 5'd20, 32'd166}; - 24'b11110100011000111101????: {next, len, code} = {in[11], 5'd20, 32'd167}; - 24'b00101011101110100011????: {next, len, code} = {in[11], 5'd20, 32'd168}; - 24'b01010000011011111110????: {next, len, code} = {in[11], 5'd20, 32'd169}; - 24'b00000111000010000010????: {next, len, code} = {in[11], 5'd20, 32'd170}; - 24'b00101010000011001000????: {next, len, code} = {in[11], 5'd20, 32'd171}; - 24'b01001110010100101110????: {next, len, code} = {in[11], 5'd20, 32'd172}; - 24'b11110000000010000000????: {next, len, code} = {in[11], 5'd20, 32'd173}; - 24'b01001101011001111001????: {next, len, code} = {in[11], 5'd20, 32'd174}; - 24'b11110111000111010101????: {next, len, code} = {in[11], 5'd20, 32'd175}; - 24'b01111001101001110110????: {next, len, code} = {in[11], 5'd20, 32'd176}; - 24'b11110000101011101111????: {next, len, code} = {in[11], 5'd20, 32'd177}; - 24'b00100100100110101010????: {next, len, code} = {in[11], 5'd20, 32'd178}; - 24'b11110001011011000011????: {next, len, code} = {in[11], 5'd20, 32'd179}; - 24'b01010111001000110011????: {next, len, code} = {in[11], 5'd20, 32'd180}; - 24'b01111000000100010101????: {next, len, code} = {in[11], 5'd20, 32'd181}; - 24'b00100101101011001101????: {next, len, code} = {in[11], 5'd20, 32'd182}; - 24'b10110010110000111001????: {next, len, code} = {in[11], 5'd20, 32'd183}; - 24'b10110000101010000011????: {next, len, code} = {in[11], 5'd20, 32'd184}; - 24'b00100100111110001101????: {next, len, code} = {in[11], 5'd20, 32'd185}; - 24'b01111001101001101011????: {next, len, code} = {in[11], 5'd20, 32'd186}; - 24'b01010001000000010001????: {next, len, code} = {in[11], 5'd20, 32'd187}; - 24'b11110101111111101110????: {next, len, code} = {in[11], 5'd20, 32'd188}; - 24'b10000010111110110011????: {next, len, code} = {in[11], 5'd20, 32'd189}; - 24'b00000100011110100111????: {next, len, code} = {in[11], 5'd20, 32'd190}; - 24'b11111101001111101100????: {next, len, code} = {in[11], 5'd20, 32'd191}; - 24'b00101011100011110000????: {next, len, code} = {in[11], 5'd20, 32'd192}; - 24'b00100100111001011001????: {next, len, code} = {in[11], 5'd20, 32'd193}; - 24'b10000010101000000100????: {next, len, code} = {in[11], 5'd20, 32'd194}; - 24'b11110001001000111100????: {next, len, code} = {in[11], 5'd20, 32'd195}; - 24'b10111100011010011001????: {next, len, code} = {in[11], 5'd20, 32'd196}; - 24'b000000??????????????????: begin - casez (in[33:32]) - 2'b1?: {next, len, code} = {1'b0, 5'd18, 32'd197}; - 2'b01: {next, len, code} = {1'b0, 5'd19, 32'd198}; - 2'b00: {next, len, code} = {1'b0, 5'd19, 32'd199}; - default: ; - endcase - end - default: ; + 24'b1010????????????????????: {next, len, code} = {in[27], 5'd04, 32'd000}; + 24'b1100????????????????????: {next, len, code} = {in[27], 5'd04, 32'd001}; + 24'b0110????????????????????: {next, len, code} = {in[27], 5'd04, 32'd002}; + 24'b1001????????????????????: {next, len, code} = {in[27], 5'd04, 32'd003}; + 24'b1101????????????????????: {next, len, code} = {in[27], 5'd04, 32'd004}; + 24'b0011????????????????????: {next, len, code} = {in[27], 5'd04, 32'd005}; + 24'b0001????????????????????: {next, len, code} = {in[27], 5'd04, 32'd006}; + 24'b10001???????????????????: {next, len, code} = {in[26], 5'd05, 32'd007}; + 24'b01110???????????????????: {next, len, code} = {in[26], 5'd05, 32'd008}; + 24'b01000???????????????????: {next, len, code} = {in[26], 5'd05, 32'd009}; + 24'b00001???????????????????: {next, len, code} = {in[26], 5'd05, 32'd010}; + 24'b11100???????????????????: {next, len, code} = {in[26], 5'd05, 32'd011}; + 24'b01011???????????????????: {next, len, code} = {in[26], 5'd05, 32'd012}; + 24'b100001??????????????????: {next, len, code} = {in[25], 5'd06, 32'd013}; + 24'b111110??????????????????: {next, len, code} = {in[25], 5'd06, 32'd014}; + 24'b010010??????????????????: {next, len, code} = {in[25], 5'd06, 32'd015}; + 24'b001011??????????????????: {next, len, code} = {in[25], 5'd06, 32'd016}; + 24'b101110??????????????????: {next, len, code} = {in[25], 5'd06, 32'd017}; + 24'b111011??????????????????: {next, len, code} = {in[25], 5'd06, 32'd018}; + 24'b0111101?????????????????: {next, len, code} = {in[24], 5'd07, 32'd020}; + 24'b0010100?????????????????: {next, len, code} = {in[24], 5'd07, 32'd021}; + 24'b0111111?????????????????: {next, len, code} = {in[24], 5'd07, 32'd022}; + 24'b1011010?????????????????: {next, len, code} = {in[24], 5'd07, 32'd023}; + 24'b1000000?????????????????: {next, len, code} = {in[24], 5'd07, 32'd024}; + 24'b1011111?????????????????: {next, len, code} = {in[24], 5'd07, 32'd025}; + 24'b1110100?????????????????: {next, len, code} = {in[24], 5'd07, 32'd026}; + 24'b01111100????????????????: {next, len, code} = {in[23], 5'd08, 32'd027}; + 24'b00000110????????????????: {next, len, code} = {in[23], 5'd08, 32'd028}; + 24'b00000101????????????????: {next, len, code} = {in[23], 5'd08, 32'd029}; + 24'b01001100????????????????: {next, len, code} = {in[23], 5'd08, 32'd030}; + 24'b10110110????????????????: {next, len, code} = {in[23], 5'd08, 32'd031}; + 24'b00100110????????????????: {next, len, code} = {in[23], 5'd08, 32'd032}; + 24'b11110010????????????????: {next, len, code} = {in[23], 5'd08, 32'd033}; + 24'b010011101???????????????: {next, len, code} = {in[22], 5'd09, 32'd034}; + 24'b001000000???????????????: {next, len, code} = {in[22], 5'd09, 32'd035}; + 24'b010101111???????????????: {next, len, code} = {in[22], 5'd09, 32'd036}; + 24'b010101010???????????????: {next, len, code} = {in[22], 5'd09, 32'd037}; + 24'b010011011???????????????: {next, len, code} = {in[22], 5'd09, 32'd038}; + 24'b010100011???????????????: {next, len, code} = {in[22], 5'd09, 32'd039}; + 24'b010101000???????????????: {next, len, code} = {in[22], 5'd09, 32'd040}; + 24'b1111010101??????????????: {next, len, code} = {in[21], 5'd10, 32'd041}; + 24'b0010001000??????????????: {next, len, code} = {in[21], 5'd10, 32'd042}; + 24'b0101001101??????????????: {next, len, code} = {in[21], 5'd10, 32'd043}; + 24'b0010010100??????????????: {next, len, code} = {in[21], 5'd10, 32'd044}; + 24'b1011001110??????????????: {next, len, code} = {in[21], 5'd10, 32'd045}; + 24'b1111000011??????????????: {next, len, code} = {in[21], 5'd10, 32'd046}; + 24'b0101000000??????????????: {next, len, code} = {in[21], 5'd10, 32'd047}; + 24'b1111110000??????????????: {next, len, code} = {in[21], 5'd10, 32'd048}; + 24'b10110111010?????????????: {next, len, code} = {in[20], 5'd11, 32'd049}; + 24'b11110000011?????????????: {next, len, code} = {in[20], 5'd11, 32'd050}; + 24'b01001111011?????????????: {next, len, code} = {in[20], 5'd11, 32'd051}; + 24'b00101011011?????????????: {next, len, code} = {in[20], 5'd11, 32'd052}; + 24'b01010010100?????????????: {next, len, code} = {in[20], 5'd11, 32'd053}; + 24'b11110111100?????????????: {next, len, code} = {in[20], 5'd11, 32'd054}; + 24'b00100111001?????????????: {next, len, code} = {in[20], 5'd11, 32'd055}; + 24'b10110001010?????????????: {next, len, code} = {in[20], 5'd11, 32'd056}; + 24'b10000010000?????????????: {next, len, code} = {in[20], 5'd11, 32'd057}; + 24'b111111101100????????????: {next, len, code} = {in[19], 5'd12, 32'd058}; + 24'b100000111110????????????: {next, len, code} = {in[19], 5'd12, 32'd059}; + 24'b100000110010????????????: {next, len, code} = {in[19], 5'd12, 32'd060}; + 24'b100000111001????????????: {next, len, code} = {in[19], 5'd12, 32'd061}; + 24'b010100101111????????????: {next, len, code} = {in[19], 5'd12, 32'd062}; + 24'b001000001100????????????: {next, len, code} = {in[19], 5'd12, 32'd063}; + 24'b000001111111????????????: {next, len, code} = {in[19], 5'd12, 32'd064}; + 24'b011111010100????????????: {next, len, code} = {in[19], 5'd12, 32'd065}; + 24'b1110101111101???????????: {next, len, code} = {in[18], 5'd13, 32'd066}; + 24'b0100110101110???????????: {next, len, code} = {in[18], 5'd13, 32'd067}; + 24'b1111111011011???????????: {next, len, code} = {in[18], 5'd13, 32'd068}; + 24'b0101011011001???????????: {next, len, code} = {in[18], 5'd13, 32'd069}; + 24'b0010000101100???????????: {next, len, code} = {in[18], 5'd13, 32'd070}; + 24'b1111111101101???????????: {next, len, code} = {in[18], 5'd13, 32'd071}; + 24'b1011110010110???????????: {next, len, code} = {in[18], 5'd13, 32'd072}; + 24'b0101010111010???????????: {next, len, code} = {in[18], 5'd13, 32'd073}; + 24'b1111011010010???????????: {next, len, code} = {in[18], 5'd13, 32'd074}; + 24'b01010100100011??????????: {next, len, code} = {in[17], 5'd14, 32'd075}; + 24'b10110000110010??????????: {next, len, code} = {in[17], 5'd14, 32'd076}; + 24'b10111101001111??????????: {next, len, code} = {in[17], 5'd14, 32'd077}; + 24'b10110000010101??????????: {next, len, code} = {in[17], 5'd14, 32'd078}; + 24'b00101011001111??????????: {next, len, code} = {in[17], 5'd14, 32'd079}; + 24'b00100000101100??????????: {next, len, code} = {in[17], 5'd14, 32'd080}; + 24'b11111110010111??????????: {next, len, code} = {in[17], 5'd14, 32'd081}; + 24'b10110010100000??????????: {next, len, code} = {in[17], 5'd14, 32'd082}; + 24'b11101011101000??????????: {next, len, code} = {in[17], 5'd14, 32'd083}; + 24'b01010000011111??????????: {next, len, code} = {in[17], 5'd14, 32'd084}; + 24'b101111011001011?????????: {next, len, code} = {in[16], 5'd15, 32'd085}; + 24'b101111010001100?????????: {next, len, code} = {in[16], 5'd15, 32'd086}; + 24'b100000111100111?????????: {next, len, code} = {in[16], 5'd15, 32'd087}; + 24'b001010101011000?????????: {next, len, code} = {in[16], 5'd15, 32'd088}; + 24'b111111100100001?????????: {next, len, code} = {in[16], 5'd15, 32'd089}; + 24'b001001011000010?????????: {next, len, code} = {in[16], 5'd15, 32'd090}; + 24'b011110011001011?????????: {next, len, code} = {in[16], 5'd15, 32'd091}; + 24'b111111111111010?????????: {next, len, code} = {in[16], 5'd15, 32'd092}; + 24'b101111001010011?????????: {next, len, code} = {in[16], 5'd15, 32'd093}; + 24'b100000110000111?????????: {next, len, code} = {in[16], 5'd15, 32'd094}; + 24'b0010010000000101????????: {next, len, code} = {in[15], 5'd16, 32'd095}; + 24'b0010010010101001????????: {next, len, code} = {in[15], 5'd16, 32'd096}; + 24'b1111011010110010????????: {next, len, code} = {in[15], 5'd16, 32'd097}; + 24'b0010010001100100????????: {next, len, code} = {in[15], 5'd16, 32'd098}; + 24'b0101011101110100????????: {next, len, code} = {in[15], 5'd16, 32'd099}; + 24'b0101011010001111????????: {next, len, code} = {in[15], 5'd16, 32'd100}; + 24'b0010000110011111????????: {next, len, code} = {in[15], 5'd16, 32'd101}; + 24'b0101010010000101????????: {next, len, code} = {in[15], 5'd16, 32'd102}; + 24'b1110101011000000????????: {next, len, code} = {in[15], 5'd16, 32'd103}; + 24'b1111000000110010????????: {next, len, code} = {in[15], 5'd16, 32'd104}; + 24'b0111100010001101????????: {next, len, code} = {in[15], 5'd16, 32'd105}; + 24'b00100010110001100???????: {next, len, code} = {in[14], 5'd17, 32'd106}; + 24'b00100010101101010???????: {next, len, code} = {in[14], 5'd17, 32'd107}; + 24'b11111110111100000???????: {next, len, code} = {in[14], 5'd17, 32'd108}; + 24'b00100000111010000???????: {next, len, code} = {in[14], 5'd17, 32'd109}; + 24'b00100111011101001???????: {next, len, code} = {in[14], 5'd17, 32'd110}; + 24'b11111110111000011???????: {next, len, code} = {in[14], 5'd17, 32'd111}; + 24'b11110001101000100???????: {next, len, code} = {in[14], 5'd17, 32'd112}; + 24'b11101011101011101???????: {next, len, code} = {in[14], 5'd17, 32'd113}; + 24'b01010000100101011???????: {next, len, code} = {in[14], 5'd17, 32'd114}; + 24'b00100100110011001???????: {next, len, code} = {in[14], 5'd17, 32'd115}; + 24'b01001110010101000???????: {next, len, code} = {in[14], 5'd17, 32'd116}; + 24'b010011110101001000??????: {next, len, code} = {in[13], 5'd18, 32'd117}; + 24'b111010101110010010??????: {next, len, code} = {in[13], 5'd18, 32'd118}; + 24'b001001001001111000??????: {next, len, code} = {in[13], 5'd18, 32'd119}; + 24'b101111000110111101??????: {next, len, code} = {in[13], 5'd18, 32'd120}; + 24'b101101111010101001??????: {next, len, code} = {in[13], 5'd18, 32'd121}; + 24'b111101110010111110??????: {next, len, code} = {in[13], 5'd18, 32'd122}; + 24'b010100100011010000??????: {next, len, code} = {in[13], 5'd18, 32'd123}; + 24'b001001001111011001??????: {next, len, code} = {in[13], 5'd18, 32'd124}; + 24'b010100110010001001??????: {next, len, code} = {in[13], 5'd18, 32'd125}; + 24'b111010110000111000??????: {next, len, code} = {in[13], 5'd18, 32'd126}; + 24'b111010110011000101??????: {next, len, code} = {in[13], 5'd18, 32'd127}; + 24'b010100001000111001??????: {next, len, code} = {in[13], 5'd18, 32'd128}; + 24'b1000001011000110100?????: {next, len, code} = {in[12], 5'd19, 32'd129}; + 24'b0010010111001110110?????: {next, len, code} = {in[12], 5'd19, 32'd130}; + 24'b0101011001000001101?????: {next, len, code} = {in[12], 5'd19, 32'd131}; + 24'b0101000010010101011?????: {next, len, code} = {in[12], 5'd19, 32'd132}; + 24'b1111011111101001101?????: {next, len, code} = {in[12], 5'd19, 32'd133}; + 24'b1011001000101010110?????: {next, len, code} = {in[12], 5'd19, 32'd134}; + 24'b1011000001000100001?????: {next, len, code} = {in[12], 5'd19, 32'd135}; + 24'b1110101100010011001?????: {next, len, code} = {in[12], 5'd19, 32'd136}; + 24'b0010010111010111110?????: {next, len, code} = {in[12], 5'd19, 32'd137}; + 24'b0010010001100111100?????: {next, len, code} = {in[12], 5'd19, 32'd138}; + 24'b1011001011100000101?????: {next, len, code} = {in[12], 5'd19, 32'd139}; + 24'b1011000100010100101?????: {next, len, code} = {in[12], 5'd19, 32'd140}; + 24'b1111111001000111011?????: {next, len, code} = {in[12], 5'd19, 32'd141}; + 24'b00100010111101101101????: {next, len, code} = {in[11], 5'd20, 32'd142}; + 24'b10000010101010101101????: {next, len, code} = {in[11], 5'd20, 32'd143}; + 24'b10110010100101001101????: {next, len, code} = {in[11], 5'd20, 32'd144}; + 24'b01010110111100010000????: {next, len, code} = {in[11], 5'd20, 32'd145}; + 24'b10110111110011001001????: {next, len, code} = {in[11], 5'd20, 32'd146}; + 24'b11111101101100100101????: {next, len, code} = {in[11], 5'd20, 32'd147}; + 24'b10110000010100100001????: {next, len, code} = {in[11], 5'd20, 32'd148}; + 24'b10110010011010110110????: {next, len, code} = {in[11], 5'd20, 32'd149}; + 24'b01111001010000011000????: {next, len, code} = {in[11], 5'd20, 32'd150}; + 24'b11110110001011011011????: {next, len, code} = {in[11], 5'd20, 32'd151}; + 24'b01010000100100001011????: {next, len, code} = {in[11], 5'd20, 32'd152}; + 24'b10110001100101110111????: {next, len, code} = {in[11], 5'd20, 32'd153}; + 24'b10111100110111101000????: {next, len, code} = {in[11], 5'd20, 32'd154}; + 24'b01010001010111010000????: {next, len, code} = {in[11], 5'd20, 32'd155}; + 24'b01010100111110001110????: {next, len, code} = {in[11], 5'd20, 32'd156}; + 24'b11111110011001100111????: {next, len, code} = {in[11], 5'd20, 32'd157}; + 24'b11110111111101010001????: {next, len, code} = {in[11], 5'd20, 32'd158}; + 24'b10110000010111100000????: {next, len, code} = {in[11], 5'd20, 32'd159}; + 24'b01001111100001000101????: {next, len, code} = {in[11], 5'd20, 32'd160}; + 24'b01010010000111010110????: {next, len, code} = {in[11], 5'd20, 32'd161}; + 24'b11101010101011101111????: {next, len, code} = {in[11], 5'd20, 32'd162}; + 24'b11111110010011100011????: {next, len, code} = {in[11], 5'd20, 32'd163}; + 24'b01010111001111101111????: {next, len, code} = {in[11], 5'd20, 32'd164}; + 24'b10110001111111111101????: {next, len, code} = {in[11], 5'd20, 32'd165}; + 24'b10110001001100110000????: {next, len, code} = {in[11], 5'd20, 32'd166}; + 24'b11110100011000111101????: {next, len, code} = {in[11], 5'd20, 32'd167}; + 24'b00101011101110100011????: {next, len, code} = {in[11], 5'd20, 32'd168}; + 24'b01010000011011111110????: {next, len, code} = {in[11], 5'd20, 32'd169}; + 24'b00000111000010000010????: {next, len, code} = {in[11], 5'd20, 32'd170}; + 24'b00101010000011001000????: {next, len, code} = {in[11], 5'd20, 32'd171}; + 24'b01001110010100101110????: {next, len, code} = {in[11], 5'd20, 32'd172}; + 24'b11110000000010000000????: {next, len, code} = {in[11], 5'd20, 32'd173}; + 24'b01001101011001111001????: {next, len, code} = {in[11], 5'd20, 32'd174}; + 24'b11110111000111010101????: {next, len, code} = {in[11], 5'd20, 32'd175}; + 24'b01111001101001110110????: {next, len, code} = {in[11], 5'd20, 32'd176}; + 24'b11110000101011101111????: {next, len, code} = {in[11], 5'd20, 32'd177}; + 24'b00100100100110101010????: {next, len, code} = {in[11], 5'd20, 32'd178}; + 24'b11110001011011000011????: {next, len, code} = {in[11], 5'd20, 32'd179}; + 24'b01010111001000110011????: {next, len, code} = {in[11], 5'd20, 32'd180}; + 24'b01111000000100010101????: {next, len, code} = {in[11], 5'd20, 32'd181}; + 24'b00100101101011001101????: {next, len, code} = {in[11], 5'd20, 32'd182}; + 24'b10110010110000111001????: {next, len, code} = {in[11], 5'd20, 32'd183}; + 24'b10110000101010000011????: {next, len, code} = {in[11], 5'd20, 32'd184}; + 24'b00100100111110001101????: {next, len, code} = {in[11], 5'd20, 32'd185}; + 24'b01111001101001101011????: {next, len, code} = {in[11], 5'd20, 32'd186}; + 24'b01010001000000010001????: {next, len, code} = {in[11], 5'd20, 32'd187}; + 24'b11110101111111101110????: {next, len, code} = {in[11], 5'd20, 32'd188}; + 24'b10000010111110110011????: {next, len, code} = {in[11], 5'd20, 32'd189}; + 24'b00000100011110100111????: {next, len, code} = {in[11], 5'd20, 32'd190}; + 24'b11111101001111101100????: {next, len, code} = {in[11], 5'd20, 32'd191}; + 24'b00101011100011110000????: {next, len, code} = {in[11], 5'd20, 32'd192}; + 24'b00100100111001011001????: {next, len, code} = {in[11], 5'd20, 32'd193}; + 24'b10000010101000000100????: {next, len, code} = {in[11], 5'd20, 32'd194}; + 24'b11110001001000111100????: {next, len, code} = {in[11], 5'd20, 32'd195}; + 24'b10111100011010011001????: {next, len, code} = {in[11], 5'd20, 32'd196}; + 24'b000000??????????????????: begin + casez (in[33:32]) + 2'b1?: {next, len, code} = {1'b0, 5'd18, 32'd197}; + 2'b01: {next, len, code} = {1'b0, 5'd19, 32'd198}; + 2'b00: {next, len, code} = {1'b0, 5'd19, 32'd199}; + default: ; + endcase + end + default: ; endcase end endmodule diff --git a/test_regress/t/t_case_dupitems.v b/test_regress/t/t_case_dupitems.v index 74d91c740..4c8911985 100644 --- a/test_regress/t/t_case_dupitems.v +++ b/test_regress/t/t_case_dupitems.v @@ -10,23 +10,23 @@ module t (/*AUTOARG*/ ); input clk; - integer cyc = 0; - reg [63:0] crc; - reg [63:0] sum; + integer cyc = 0; + reg [63:0] crc; + reg [63:0] sum; // Take CRC data and apply to testblock inputs wire [1:0] in = crc[1:0]; /*AUTOWIRE*/ // Beginning of automatic wires (for undeclared instantiated-module outputs) - wire [1:0] out; // From test of Test.v + wire [1:0] out; // From test of Test.v // End of automatics Test test (/*AUTOINST*/ - // Outputs - .out (out[1:0]), - // Inputs - .in (in[1:0])); + // Outputs + .out (out[1:0]), + // Inputs + .in (in[1:0])); // Aggregate outputs into a single result vector wire [63:0] result = {62'h0, out}; @@ -43,20 +43,20 @@ module t (/*AUTOARG*/ crc <= {crc[62:0], crc[63] ^ crc[2] ^ crc[0]}; sum <= result ^ {sum[62:0], sum[63] ^ sum[2] ^ sum[0]}; if (cyc==0) begin - // Setup - crc <= 64'h5aef0c8d_d70a4497; + // Setup + crc <= 64'h5aef0c8d_d70a4497; end else if (cyc<10) begin - sum <= 64'h0; + sum <= 64'h0; end else if (cyc<90) begin end else if (cyc==99) begin - $write("[%0t] cyc==%0d crc=%x sum=%x\n", $time, cyc, crc, sum); - if (crc !== 64'hc77bb9b3784ea091) $stop; - if (sum !== `EXPECTED_SUM) $stop; - $write("*-* All Finished *-*\n"); - $finish; + $write("[%0t] cyc==%0d crc=%x sum=%x\n", $time, cyc, crc, sum); + if (crc !== 64'hc77bb9b3784ea091) $stop; + if (sum !== `EXPECTED_SUM) $stop; + $write("*-* All Finished *-*\n"); + $finish; end end @@ -73,9 +73,9 @@ module Test (/*AUTOARG*/ always @* begin // bug99: Internal Error: ../V3Ast.cpp:495: New node already linked? case (in[1:0]) - 2'd0, 2'd1, 2'd2, 2'd3: begin - out = in; - end + 2'd0, 2'd1, 2'd2, 2'd3: begin + out = in; + end endcase end endmodule diff --git a/test_regress/t/t_case_group.v b/test_regress/t/t_case_group.v index 0c7f1e625..34525c73e 100644 --- a/test_regress/t/t_case_group.v +++ b/test_regress/t/t_case_group.v @@ -6,8 +6,8 @@ module t ( - input i_clk, - input [6:0] i_input, + input i_clk, + input [6:0] i_input, output logic o_output ); diff --git a/test_regress/t/t_case_huge.v b/test_regress/t/t_case_huge.v index cff27ca14..655ff379a 100644 --- a/test_regress/t/t_case_huge.v +++ b/test_regress/t/t_case_huge.v @@ -23,118 +23,118 @@ module t (/*AUTOARG*/ /*AUTOWIRE*/ // Beginning of automatic wires (for undeclared instantiated-module outputs) - wire [9:0] outa0; // From s0 of t_case_huge_sub.v - wire [9:0] outa1; // From s1 of t_case_huge_sub.v - wire [9:0] outa2; // From s2 of t_case_huge_sub.v - wire [9:0] outa3; // From s3 of t_case_huge_sub.v - wire [9:0] outa4; // From s4 of t_case_huge_sub.v - wire [9:0] outa5; // From s5 of t_case_huge_sub.v - wire [9:0] outa6; // From s6 of t_case_huge_sub.v - wire [9:0] outa7; // From s7 of t_case_huge_sub.v - wire [1:0] outb0; // From s0 of t_case_huge_sub.v - wire [1:0] outb1; // From s1 of t_case_huge_sub.v - wire [1:0] outb2; // From s2 of t_case_huge_sub.v - wire [1:0] outb3; // From s3 of t_case_huge_sub.v - wire [1:0] outb4; // From s4 of t_case_huge_sub.v - wire [1:0] outb5; // From s5 of t_case_huge_sub.v - wire [1:0] outb6; // From s6 of t_case_huge_sub.v - wire [1:0] outb7; // From s7 of t_case_huge_sub.v - wire outc0; // From s0 of t_case_huge_sub.v - wire outc1; // From s1 of t_case_huge_sub.v - wire outc2; // From s2 of t_case_huge_sub.v - wire outc3; // From s3 of t_case_huge_sub.v - wire outc4; // From s4 of t_case_huge_sub.v - wire outc5; // From s5 of t_case_huge_sub.v - wire outc6; // From s6 of t_case_huge_sub.v - wire outc7; // From s7 of t_case_huge_sub.v - wire [9:0] outq; // From q of t_case_huge_sub4.v - wire [3:0] outr; // From sub3 of t_case_huge_sub3.v - wire [9:0] outsmall; // From sub2 of t_case_huge_sub2.v + wire [9:0] outa0; // From s0 of t_case_huge_sub.v + wire [9:0] outa1; // From s1 of t_case_huge_sub.v + wire [9:0] outa2; // From s2 of t_case_huge_sub.v + wire [9:0] outa3; // From s3 of t_case_huge_sub.v + wire [9:0] outa4; // From s4 of t_case_huge_sub.v + wire [9:0] outa5; // From s5 of t_case_huge_sub.v + wire [9:0] outa6; // From s6 of t_case_huge_sub.v + wire [9:0] outa7; // From s7 of t_case_huge_sub.v + wire [1:0] outb0; // From s0 of t_case_huge_sub.v + wire [1:0] outb1; // From s1 of t_case_huge_sub.v + wire [1:0] outb2; // From s2 of t_case_huge_sub.v + wire [1:0] outb3; // From s3 of t_case_huge_sub.v + wire [1:0] outb4; // From s4 of t_case_huge_sub.v + wire [1:0] outb5; // From s5 of t_case_huge_sub.v + wire [1:0] outb6; // From s6 of t_case_huge_sub.v + wire [1:0] outb7; // From s7 of t_case_huge_sub.v + wire outc0; // From s0 of t_case_huge_sub.v + wire outc1; // From s1 of t_case_huge_sub.v + wire outc2; // From s2 of t_case_huge_sub.v + wire outc3; // From s3 of t_case_huge_sub.v + wire outc4; // From s4 of t_case_huge_sub.v + wire outc5; // From s5 of t_case_huge_sub.v + wire outc6; // From s6 of t_case_huge_sub.v + wire outc7; // From s7 of t_case_huge_sub.v + wire [9:0] outq; // From q of t_case_huge_sub4.v + wire [3:0] outr; // From sub3 of t_case_huge_sub3.v + wire [9:0] outsmall; // From sub2 of t_case_huge_sub2.v // End of automatics t_case_huge_sub2 sub2 ( - // Outputs - .outa (outsmall[9:0]), - /*AUTOINST*/ - // Inputs - .index (index[9:0])); + // Outputs + .outa (outsmall[9:0]), + /*AUTOINST*/ + // Inputs + .index (index[9:0])); t_case_huge_sub3 sub3 (/*AUTOINST*/ - // Outputs - .outr (outr[3:0]), - // Inputs - .clk (clk), - .index (index[9:0])); + // Outputs + .outr (outr[3:0]), + // Inputs + .clk (clk), + .index (index[9:0])); /* t_case_huge_sub AUTO_TEMPLATE ( - .outa (outa@[]), - .outb (outb@[]), - .outc (outc@[]), - .index (index@[])); + .outa (outa@[]), + .outb (outb@[]), + .outc (outc@[]), + .index (index@[])); */ t_case_huge_sub s0 (/*AUTOINST*/ - // Outputs - .outa (outa0[9:0]), // Templated - .outb (outb0[1:0]), // Templated - .outc (outc0), // Templated - // Inputs - .index (index0[7:0])); // Templated + // Outputs + .outa (outa0[9:0]), // Templated + .outb (outb0[1:0]), // Templated + .outc (outc0), // Templated + // Inputs + .index (index0[7:0])); // Templated t_case_huge_sub s1 (/*AUTOINST*/ - // Outputs - .outa (outa1[9:0]), // Templated - .outb (outb1[1:0]), // Templated - .outc (outc1), // Templated - // Inputs - .index (index1[7:0])); // Templated + // Outputs + .outa (outa1[9:0]), // Templated + .outb (outb1[1:0]), // Templated + .outc (outc1), // Templated + // Inputs + .index (index1[7:0])); // Templated t_case_huge_sub s2 (/*AUTOINST*/ - // Outputs - .outa (outa2[9:0]), // Templated - .outb (outb2[1:0]), // Templated - .outc (outc2), // Templated - // Inputs - .index (index2[7:0])); // Templated + // Outputs + .outa (outa2[9:0]), // Templated + .outb (outb2[1:0]), // Templated + .outc (outc2), // Templated + // Inputs + .index (index2[7:0])); // Templated t_case_huge_sub s3 (/*AUTOINST*/ - // Outputs - .outa (outa3[9:0]), // Templated - .outb (outb3[1:0]), // Templated - .outc (outc3), // Templated - // Inputs - .index (index3[7:0])); // Templated + // Outputs + .outa (outa3[9:0]), // Templated + .outb (outb3[1:0]), // Templated + .outc (outc3), // Templated + // Inputs + .index (index3[7:0])); // Templated t_case_huge_sub s4 (/*AUTOINST*/ - // Outputs - .outa (outa4[9:0]), // Templated - .outb (outb4[1:0]), // Templated - .outc (outc4), // Templated - // Inputs - .index (index4[7:0])); // Templated + // Outputs + .outa (outa4[9:0]), // Templated + .outb (outb4[1:0]), // Templated + .outc (outc4), // Templated + // Inputs + .index (index4[7:0])); // Templated t_case_huge_sub s5 (/*AUTOINST*/ - // Outputs - .outa (outa5[9:0]), // Templated - .outb (outb5[1:0]), // Templated - .outc (outc5), // Templated - // Inputs - .index (index5[7:0])); // Templated + // Outputs + .outa (outa5[9:0]), // Templated + .outb (outb5[1:0]), // Templated + .outc (outc5), // Templated + // Inputs + .index (index5[7:0])); // Templated t_case_huge_sub s6 (/*AUTOINST*/ - // Outputs - .outa (outa6[9:0]), // Templated - .outb (outb6[1:0]), // Templated - .outc (outc6), // Templated - // Inputs - .index (index6[7:0])); // Templated + // Outputs + .outa (outa6[9:0]), // Templated + .outb (outb6[1:0]), // Templated + .outc (outc6), // Templated + // Inputs + .index (index6[7:0])); // Templated t_case_huge_sub s7 (/*AUTOINST*/ - // Outputs - .outa (outa7[9:0]), // Templated - .outb (outb7[1:0]), // Templated - .outc (outc7), // Templated - // Inputs - .index (index7[7:0])); // Templated + // Outputs + .outa (outa7[9:0]), // Templated + .outb (outb7[1:0]), // Templated + .outc (outc7), // Templated + // Inputs + .index (index7[7:0])); // Templated t_case_huge_sub4 q (/*AUTOINST*/ - // Outputs - .outq (outq[9:0]), - // Inputs - .index (index[7:0])); + // Outputs + .outq (outq[9:0]), + // Inputs + .index (index[7:0])); integer cyc; initial cyc=1; @@ -142,69 +142,69 @@ module t (/*AUTOARG*/ always @ (posedge clk) begin if (cyc!=0) begin - cyc <= cyc + 1; - //$write("%x: %x\n",cyc,outr); - //$write("%x: %x %x %x %x\n", cyc, outa1,outb1,outc1,index1); - if (cyc==1) begin - index <= 10'h236; - end - if (cyc==2) begin - index <= 10'h022; - if (outsmall != 10'h282) $stop; - if (outr != 4'b0) $stop; - if ({outa0,outb0,outc0}!={10'h282,2'd3,1'b0}) $stop; - if ({outa1,outb1,outc1}!={10'h21c,2'd3,1'b1}) $stop; - if ({outa2,outb2,outc2}!={10'h148,2'd0,1'b1}) $stop; - if ({outa3,outb3,outc3}!={10'h3c0,2'd2,1'b0}) $stop; - if ({outa4,outb4,outc4}!={10'h176,2'd1,1'b1}) $stop; - if ({outa5,outb5,outc5}!={10'h3fc,2'd2,1'b1}) $stop; - if ({outa6,outb6,outc6}!={10'h295,2'd3,1'b1}) $stop; - if ({outa7,outb7,outc7}!={10'h113,2'd2,1'b1}) $stop; - if (outq != 10'h001) $stop; - end - if (cyc==3) begin - index <= 10'h165; - if (outsmall != 10'h191) $stop; - if (outr != 4'h5) $stop; - if ({outa1,outb1,outc1}!={10'h379,2'd1,1'b0}) $stop; - if ({outa2,outb2,outc2}!={10'h073,2'd0,1'b0}) $stop; - if ({outa3,outb3,outc3}!={10'h2fd,2'd3,1'b1}) $stop; - if ({outa4,outb4,outc4}!={10'h2e0,2'd3,1'b1}) $stop; - if ({outa5,outb5,outc5}!={10'h337,2'd1,1'b1}) $stop; - if ({outa6,outb6,outc6}!={10'h2c7,2'd3,1'b1}) $stop; - if ({outa7,outb7,outc7}!={10'h19e,2'd3,1'b0}) $stop; - if (outq != 10'h001) $stop; - end - if (cyc==4) begin - index <= 10'h201; - if (outsmall != 10'h268) $stop; - if (outr != 4'h2) $stop; - if ({outa1,outb1,outc1}!={10'h111,2'd1,1'b0}) $stop; - if ({outa2,outb2,outc2}!={10'h1f9,2'd0,1'b0}) $stop; - if ({outa3,outb3,outc3}!={10'h232,2'd0,1'b1}) $stop; - if ({outa4,outb4,outc4}!={10'h255,2'd3,1'b0}) $stop; - if ({outa5,outb5,outc5}!={10'h34c,2'd1,1'b1}) $stop; - if ({outa6,outb6,outc6}!={10'h049,2'd1,1'b1}) $stop; - if ({outa7,outb7,outc7}!={10'h197,2'd3,1'b0}) $stop; - if (outq != 10'h001) $stop; - end - if (cyc==5) begin - index <= 10'h3ff; - if (outr != 4'hd) $stop; - if (outq != 10'h001) $stop; - end - if (cyc==6) begin - index <= 10'h0; - if (outr != 4'hd) $stop; - if (outq != 10'h114) $stop; - end - if (cyc==7) begin - if (outr != 4'h4) $stop; - end - if (cyc==9) begin - $write("*-* All Finished *-*\n"); - $finish; - end + cyc <= cyc + 1; + //$write("%x: %x\n",cyc,outr); + //$write("%x: %x %x %x %x\n", cyc, outa1,outb1,outc1,index1); + if (cyc==1) begin + index <= 10'h236; + end + if (cyc==2) begin + index <= 10'h022; + if (outsmall != 10'h282) $stop; + if (outr != 4'b0) $stop; + if ({outa0,outb0,outc0}!={10'h282,2'd3,1'b0}) $stop; + if ({outa1,outb1,outc1}!={10'h21c,2'd3,1'b1}) $stop; + if ({outa2,outb2,outc2}!={10'h148,2'd0,1'b1}) $stop; + if ({outa3,outb3,outc3}!={10'h3c0,2'd2,1'b0}) $stop; + if ({outa4,outb4,outc4}!={10'h176,2'd1,1'b1}) $stop; + if ({outa5,outb5,outc5}!={10'h3fc,2'd2,1'b1}) $stop; + if ({outa6,outb6,outc6}!={10'h295,2'd3,1'b1}) $stop; + if ({outa7,outb7,outc7}!={10'h113,2'd2,1'b1}) $stop; + if (outq != 10'h001) $stop; + end + if (cyc==3) begin + index <= 10'h165; + if (outsmall != 10'h191) $stop; + if (outr != 4'h5) $stop; + if ({outa1,outb1,outc1}!={10'h379,2'd1,1'b0}) $stop; + if ({outa2,outb2,outc2}!={10'h073,2'd0,1'b0}) $stop; + if ({outa3,outb3,outc3}!={10'h2fd,2'd3,1'b1}) $stop; + if ({outa4,outb4,outc4}!={10'h2e0,2'd3,1'b1}) $stop; + if ({outa5,outb5,outc5}!={10'h337,2'd1,1'b1}) $stop; + if ({outa6,outb6,outc6}!={10'h2c7,2'd3,1'b1}) $stop; + if ({outa7,outb7,outc7}!={10'h19e,2'd3,1'b0}) $stop; + if (outq != 10'h001) $stop; + end + if (cyc==4) begin + index <= 10'h201; + if (outsmall != 10'h268) $stop; + if (outr != 4'h2) $stop; + if ({outa1,outb1,outc1}!={10'h111,2'd1,1'b0}) $stop; + if ({outa2,outb2,outc2}!={10'h1f9,2'd0,1'b0}) $stop; + if ({outa3,outb3,outc3}!={10'h232,2'd0,1'b1}) $stop; + if ({outa4,outb4,outc4}!={10'h255,2'd3,1'b0}) $stop; + if ({outa5,outb5,outc5}!={10'h34c,2'd1,1'b1}) $stop; + if ({outa6,outb6,outc6}!={10'h049,2'd1,1'b1}) $stop; + if ({outa7,outb7,outc7}!={10'h197,2'd3,1'b0}) $stop; + if (outq != 10'h001) $stop; + end + if (cyc==5) begin + index <= 10'h3ff; + if (outr != 4'hd) $stop; + if (outq != 10'h001) $stop; + end + if (cyc==6) begin + index <= 10'h0; + if (outr != 4'hd) $stop; + if (outq != 10'h114) $stop; + end + if (cyc==7) begin + if (outr != 4'h4) $stop; + end + if (cyc==9) begin + $write("*-* All Finished *-*\n"); + $finish; + end end end endmodule diff --git a/test_regress/t/t_case_huge_sub.v b/test_regress/t/t_case_huge_sub.v index c40ed7f32..b593c05fa 100644 --- a/test_regress/t/t_case_huge_sub.v +++ b/test_regress/t/t_case_huge_sub.v @@ -14,14 +14,14 @@ module t_case_huge_sub (/*AUTOARG*/ input [7:0] index; output [9:0] outa; output [1:0] outb; - output outc; + output outc; // ============================= /*AUTOREG*/ // Beginning of automatic regs (for this module's undeclared outputs) - reg [9:0] outa; - reg [1:0] outb; - reg outc; + reg [9:0] outa; + reg [1:0] outb; + reg outc; // End of automatics // ============================= @@ -30,262 +30,262 @@ module t_case_huge_sub (/*AUTOARG*/ always @(/*AS*/index) begin case (index) - 8'h00: begin outa = 10'h152; outb = 2'b00; outc = 1'b1; end - 8'h01: begin outa = 10'h318; outb = 2'b11; outc = 1'b1; end - 8'h02: begin outa = 10'h29f; outb = 2'b11; outc = 1'b0; end - 8'h03: begin outa = 10'h392; outb = 2'b01; outc = 1'b1; end - 8'h04: begin outa = 10'h1ef; outb = 2'b00; outc = 1'b0; end - 8'h05: begin outa = 10'h06c; outb = 2'b10; outc = 1'b1; end - 8'h06: begin outa = 10'h29f; outb = 2'b11; outc = 1'b0; end - 8'h07: begin outa = 10'h29a; outb = 2'b10; outc = 1'b0; end - 8'h08: begin outa = 10'h3ce; outb = 2'b01; outc = 1'b0; end - 8'h09: begin outa = 10'h37c; outb = 2'b01; outc = 1'b0; end - 8'h0a: begin outa = 10'h058; outb = 2'b10; outc = 1'b0; end - 8'h0b: begin outa = 10'h3b2; outb = 2'b01; outc = 1'b1; end - 8'h0c: begin outa = 10'h36f; outb = 2'b11; outc = 1'b0; end - 8'h0d: begin outa = 10'h2c5; outb = 2'b11; outc = 1'b0; end - 8'h0e: begin outa = 10'h23a; outb = 2'b00; outc = 1'b0; end - 8'h0f: begin outa = 10'h222; outb = 2'b01; outc = 1'b1; end - 8'h10: begin outa = 10'h328; outb = 2'b00; outc = 1'b1; end - 8'h11: begin outa = 10'h3c3; outb = 2'b00; outc = 1'b1; end - 8'h12: begin outa = 10'h12c; outb = 2'b01; outc = 1'b0; end - 8'h13: begin outa = 10'h1d0; outb = 2'b00; outc = 1'b1; end - 8'h14: begin outa = 10'h3ff; outb = 2'b01; outc = 1'b1; end - 8'h15: begin outa = 10'h115; outb = 2'b11; outc = 1'b1; end - 8'h16: begin outa = 10'h3ba; outb = 2'b10; outc = 1'b0; end - 8'h17: begin outa = 10'h3ba; outb = 2'b00; outc = 1'b0; end - 8'h18: begin outa = 10'h10d; outb = 2'b00; outc = 1'b1; end - 8'h19: begin outa = 10'h13b; outb = 2'b01; outc = 1'b1; end - 8'h1a: begin outa = 10'h0a0; outb = 2'b10; outc = 1'b1; end - 8'h1b: begin outa = 10'h264; outb = 2'b11; outc = 1'b0; end - 8'h1c: begin outa = 10'h3a2; outb = 2'b10; outc = 1'b0; end - 8'h1d: begin outa = 10'h07c; outb = 2'b00; outc = 1'b1; end - 8'h1e: begin outa = 10'h291; outb = 2'b00; outc = 1'b0; end - 8'h1f: begin outa = 10'h1d1; outb = 2'b10; outc = 1'b0; end - 8'h20: begin outa = 10'h354; outb = 2'b11; outc = 1'b1; end - 8'h21: begin outa = 10'h0c0; outb = 2'b00; outc = 1'b1; end - 8'h22: begin outa = 10'h191; outb = 2'b00; outc = 1'b0; end - 8'h23: begin outa = 10'h379; outb = 2'b01; outc = 1'b0; end - 8'h24: begin outa = 10'h073; outb = 2'b00; outc = 1'b0; end - 8'h25: begin outa = 10'h2fd; outb = 2'b11; outc = 1'b1; end - 8'h26: begin outa = 10'h2e0; outb = 2'b11; outc = 1'b1; end - 8'h27: begin outa = 10'h337; outb = 2'b01; outc = 1'b1; end - 8'h28: begin outa = 10'h2c7; outb = 2'b11; outc = 1'b1; end - 8'h29: begin outa = 10'h19e; outb = 2'b11; outc = 1'b0; end - 8'h2a: begin outa = 10'h107; outb = 2'b10; outc = 1'b0; end - 8'h2b: begin outa = 10'h06a; outb = 2'b01; outc = 1'b1; end - 8'h2c: begin outa = 10'h1c7; outb = 2'b01; outc = 1'b1; end - 8'h2d: begin outa = 10'h107; outb = 2'b10; outc = 1'b0; end - 8'h2e: begin outa = 10'h0cf; outb = 2'b01; outc = 1'b1; end - 8'h2f: begin outa = 10'h009; outb = 2'b11; outc = 1'b1; end - 8'h30: begin outa = 10'h09d; outb = 2'b00; outc = 1'b1; end - 8'h31: begin outa = 10'h28e; outb = 2'b00; outc = 1'b0; end - 8'h32: begin outa = 10'h010; outb = 2'b01; outc = 1'b0; end - 8'h33: begin outa = 10'h1e0; outb = 2'b10; outc = 1'b0; end - 8'h34: begin outa = 10'h079; outb = 2'b01; outc = 1'b1; end - 8'h35: begin outa = 10'h13e; outb = 2'b10; outc = 1'b1; end - 8'h36: begin outa = 10'h282; outb = 2'b11; outc = 1'b0; end - 8'h37: begin outa = 10'h21c; outb = 2'b11; outc = 1'b1; end - 8'h38: begin outa = 10'h148; outb = 2'b00; outc = 1'b1; end - 8'h39: begin outa = 10'h3c0; outb = 2'b10; outc = 1'b0; end - 8'h3a: begin outa = 10'h176; outb = 2'b01; outc = 1'b1; end - 8'h3b: begin outa = 10'h3fc; outb = 2'b10; outc = 1'b1; end - 8'h3c: begin outa = 10'h295; outb = 2'b11; outc = 1'b1; end - 8'h3d: begin outa = 10'h113; outb = 2'b10; outc = 1'b1; end - 8'h3e: begin outa = 10'h354; outb = 2'b01; outc = 1'b1; end - 8'h3f: begin outa = 10'h0db; outb = 2'b11; outc = 1'b0; end - 8'h40: begin outa = 10'h238; outb = 2'b01; outc = 1'b0; end - 8'h41: begin outa = 10'h12b; outb = 2'b01; outc = 1'b1; end - 8'h42: begin outa = 10'h1dc; outb = 2'b10; outc = 1'b0; end - 8'h43: begin outa = 10'h137; outb = 2'b01; outc = 1'b1; end - 8'h44: begin outa = 10'h1e2; outb = 2'b01; outc = 1'b1; end - 8'h45: begin outa = 10'h3d5; outb = 2'b11; outc = 1'b1; end - 8'h46: begin outa = 10'h30c; outb = 2'b11; outc = 1'b0; end - 8'h47: begin outa = 10'h298; outb = 2'b11; outc = 1'b0; end - 8'h48: begin outa = 10'h080; outb = 2'b00; outc = 1'b1; end - 8'h49: begin outa = 10'h35a; outb = 2'b11; outc = 1'b1; end - 8'h4a: begin outa = 10'h01b; outb = 2'b00; outc = 1'b0; end - 8'h4b: begin outa = 10'h0a3; outb = 2'b11; outc = 1'b0; end - 8'h4c: begin outa = 10'h0b3; outb = 2'b11; outc = 1'b1; end - 8'h4d: begin outa = 10'h17a; outb = 2'b00; outc = 1'b0; end - 8'h4e: begin outa = 10'h3ae; outb = 2'b11; outc = 1'b0; end - 8'h4f: begin outa = 10'h078; outb = 2'b11; outc = 1'b0; end - 8'h50: begin outa = 10'h322; outb = 2'b00; outc = 1'b1; end - 8'h51: begin outa = 10'h213; outb = 2'b11; outc = 1'b0; end - 8'h52: begin outa = 10'h11a; outb = 2'b11; outc = 1'b0; end - 8'h53: begin outa = 10'h1a7; outb = 2'b00; outc = 1'b0; end - 8'h54: begin outa = 10'h35a; outb = 2'b00; outc = 1'b1; end - 8'h55: begin outa = 10'h233; outb = 2'b00; outc = 1'b0; end - 8'h56: begin outa = 10'h01d; outb = 2'b01; outc = 1'b1; end - 8'h57: begin outa = 10'h2d5; outb = 2'b00; outc = 1'b0; end - 8'h58: begin outa = 10'h1a0; outb = 2'b00; outc = 1'b1; end - 8'h59: begin outa = 10'h3d0; outb = 2'b00; outc = 1'b1; end - 8'h5a: begin outa = 10'h181; outb = 2'b01; outc = 1'b1; end - 8'h5b: begin outa = 10'h219; outb = 2'b01; outc = 1'b1; end - 8'h5c: begin outa = 10'h26a; outb = 2'b01; outc = 1'b1; end - 8'h5d: begin outa = 10'h050; outb = 2'b10; outc = 1'b0; end - 8'h5e: begin outa = 10'h189; outb = 2'b10; outc = 1'b0; end - 8'h5f: begin outa = 10'h1eb; outb = 2'b01; outc = 1'b1; end - 8'h60: begin outa = 10'h224; outb = 2'b00; outc = 1'b1; end - 8'h61: begin outa = 10'h2fe; outb = 2'b00; outc = 1'b0; end - 8'h62: begin outa = 10'h0ae; outb = 2'b00; outc = 1'b1; end - 8'h63: begin outa = 10'h1cd; outb = 2'b00; outc = 1'b0; end - 8'h64: begin outa = 10'h273; outb = 2'b10; outc = 1'b1; end - 8'h65: begin outa = 10'h268; outb = 2'b10; outc = 1'b0; end - 8'h66: begin outa = 10'h111; outb = 2'b01; outc = 1'b0; end - 8'h67: begin outa = 10'h1f9; outb = 2'b00; outc = 1'b0; end - 8'h68: begin outa = 10'h232; outb = 2'b00; outc = 1'b1; end - 8'h69: begin outa = 10'h255; outb = 2'b11; outc = 1'b0; end - 8'h6a: begin outa = 10'h34c; outb = 2'b01; outc = 1'b1; end - 8'h6b: begin outa = 10'h049; outb = 2'b01; outc = 1'b1; end - 8'h6c: begin outa = 10'h197; outb = 2'b11; outc = 1'b0; end - 8'h6d: begin outa = 10'h0fe; outb = 2'b11; outc = 1'b0; end - 8'h6e: begin outa = 10'h253; outb = 2'b01; outc = 1'b1; end - 8'h6f: begin outa = 10'h2de; outb = 2'b11; outc = 1'b0; end - 8'h70: begin outa = 10'h13b; outb = 2'b10; outc = 1'b1; end - 8'h71: begin outa = 10'h040; outb = 2'b10; outc = 1'b0; end - 8'h72: begin outa = 10'h0b4; outb = 2'b00; outc = 1'b1; end - 8'h73: begin outa = 10'h233; outb = 2'b11; outc = 1'b1; end - 8'h74: begin outa = 10'h198; outb = 2'b00; outc = 1'b1; end - 8'h75: begin outa = 10'h018; outb = 2'b00; outc = 1'b1; end - 8'h76: begin outa = 10'h2f7; outb = 2'b00; outc = 1'b1; end - 8'h77: begin outa = 10'h134; outb = 2'b11; outc = 1'b0; end - 8'h78: begin outa = 10'h1ca; outb = 2'b10; outc = 1'b0; end - 8'h79: begin outa = 10'h286; outb = 2'b10; outc = 1'b1; end - 8'h7a: begin outa = 10'h0e6; outb = 2'b11; outc = 1'b1; end - 8'h7b: begin outa = 10'h064; outb = 2'b10; outc = 1'b1; end - 8'h7c: begin outa = 10'h257; outb = 2'b00; outc = 1'b1; end - 8'h7d: begin outa = 10'h31a; outb = 2'b10; outc = 1'b1; end - 8'h7e: begin outa = 10'h247; outb = 2'b01; outc = 1'b0; end - 8'h7f: begin outa = 10'h299; outb = 2'b00; outc = 1'b0; end - 8'h80: begin outa = 10'h02c; outb = 2'b00; outc = 1'b0; end - 8'h81: begin outa = 10'h2bb; outb = 2'b11; outc = 1'b0; end - 8'h82: begin outa = 10'h180; outb = 2'b10; outc = 1'b0; end - 8'h83: begin outa = 10'h245; outb = 2'b01; outc = 1'b1; end - 8'h84: begin outa = 10'h0da; outb = 2'b10; outc = 1'b0; end - 8'h85: begin outa = 10'h367; outb = 2'b10; outc = 1'b0; end - 8'h86: begin outa = 10'h304; outb = 2'b01; outc = 1'b0; end - 8'h87: begin outa = 10'h38b; outb = 2'b11; outc = 1'b0; end - 8'h88: begin outa = 10'h09f; outb = 2'b01; outc = 1'b0; end - 8'h89: begin outa = 10'h1f0; outb = 2'b10; outc = 1'b1; end - 8'h8a: begin outa = 10'h281; outb = 2'b10; outc = 1'b1; end - 8'h8b: begin outa = 10'h019; outb = 2'b00; outc = 1'b0; end - 8'h8c: begin outa = 10'h1f2; outb = 2'b10; outc = 1'b0; end - 8'h8d: begin outa = 10'h0b1; outb = 2'b01; outc = 1'b1; end - 8'h8e: begin outa = 10'h058; outb = 2'b01; outc = 1'b1; end - 8'h8f: begin outa = 10'h39b; outb = 2'b00; outc = 1'b1; end - 8'h90: begin outa = 10'h2ec; outb = 2'b10; outc = 1'b1; end - 8'h91: begin outa = 10'h250; outb = 2'b00; outc = 1'b1; end - 8'h92: begin outa = 10'h3f4; outb = 2'b10; outc = 1'b1; end - 8'h93: begin outa = 10'h057; outb = 2'b10; outc = 1'b1; end - 8'h94: begin outa = 10'h18f; outb = 2'b01; outc = 1'b1; end - 8'h95: begin outa = 10'h105; outb = 2'b01; outc = 1'b1; end - 8'h96: begin outa = 10'h1ae; outb = 2'b00; outc = 1'b1; end - 8'h97: begin outa = 10'h04e; outb = 2'b10; outc = 1'b0; end - 8'h98: begin outa = 10'h240; outb = 2'b11; outc = 1'b0; end - 8'h99: begin outa = 10'h3e4; outb = 2'b01; outc = 1'b0; end - 8'h9a: begin outa = 10'h3c6; outb = 2'b01; outc = 1'b0; end - 8'h9b: begin outa = 10'h109; outb = 2'b00; outc = 1'b1; end - 8'h9c: begin outa = 10'h073; outb = 2'b10; outc = 1'b1; end - 8'h9d: begin outa = 10'h19f; outb = 2'b01; outc = 1'b0; end - 8'h9e: begin outa = 10'h3b8; outb = 2'b01; outc = 1'b0; end - 8'h9f: begin outa = 10'h00e; outb = 2'b00; outc = 1'b1; end - 8'ha0: begin outa = 10'h1b3; outb = 2'b11; outc = 1'b1; end - 8'ha1: begin outa = 10'h2bd; outb = 2'b11; outc = 1'b0; end - 8'ha2: begin outa = 10'h324; outb = 2'b00; outc = 1'b1; end - 8'ha3: begin outa = 10'h343; outb = 2'b10; outc = 1'b0; end - 8'ha4: begin outa = 10'h1c9; outb = 2'b01; outc = 1'b0; end - 8'ha5: begin outa = 10'h185; outb = 2'b00; outc = 1'b1; end - 8'ha6: begin outa = 10'h37a; outb = 2'b00; outc = 1'b1; end - 8'ha7: begin outa = 10'h0e0; outb = 2'b01; outc = 1'b1; end - 8'ha8: begin outa = 10'h0a3; outb = 2'b10; outc = 1'b0; end - 8'ha9: begin outa = 10'h019; outb = 2'b11; outc = 1'b0; end - 8'haa: begin outa = 10'h099; outb = 2'b00; outc = 1'b1; end - 8'hab: begin outa = 10'h376; outb = 2'b01; outc = 1'b1; end - 8'hac: begin outa = 10'h077; outb = 2'b00; outc = 1'b1; end - 8'had: begin outa = 10'h2b1; outb = 2'b11; outc = 1'b1; end - 8'hae: begin outa = 10'h27f; outb = 2'b00; outc = 1'b0; end - 8'haf: begin outa = 10'h265; outb = 2'b11; outc = 1'b0; end - 8'hb0: begin outa = 10'h156; outb = 2'b10; outc = 1'b1; end - 8'hb1: begin outa = 10'h1ce; outb = 2'b00; outc = 1'b0; end - 8'hb2: begin outa = 10'h008; outb = 2'b01; outc = 1'b0; end - 8'hb3: begin outa = 10'h12e; outb = 2'b11; outc = 1'b1; end - 8'hb4: begin outa = 10'h199; outb = 2'b11; outc = 1'b0; end - 8'hb5: begin outa = 10'h330; outb = 2'b10; outc = 1'b0; end - 8'hb6: begin outa = 10'h1ab; outb = 2'b01; outc = 1'b1; end - 8'hb7: begin outa = 10'h3bd; outb = 2'b00; outc = 1'b0; end - 8'hb8: begin outa = 10'h0ca; outb = 2'b10; outc = 1'b0; end - 8'hb9: begin outa = 10'h367; outb = 2'b00; outc = 1'b0; end - 8'hba: begin outa = 10'h334; outb = 2'b00; outc = 1'b0; end - 8'hbb: begin outa = 10'h040; outb = 2'b00; outc = 1'b1; end - 8'hbc: begin outa = 10'h1a7; outb = 2'b10; outc = 1'b1; end - 8'hbd: begin outa = 10'h036; outb = 2'b11; outc = 1'b1; end - 8'hbe: begin outa = 10'h223; outb = 2'b11; outc = 1'b1; end - 8'hbf: begin outa = 10'h075; outb = 2'b01; outc = 1'b0; end - 8'hc0: begin outa = 10'h3c4; outb = 2'b00; outc = 1'b1; end - 8'hc1: begin outa = 10'h2cc; outb = 2'b01; outc = 1'b0; end - 8'hc2: begin outa = 10'h123; outb = 2'b01; outc = 1'b0; end - 8'hc3: begin outa = 10'h3fd; outb = 2'b01; outc = 1'b1; end - 8'hc4: begin outa = 10'h11e; outb = 2'b00; outc = 1'b0; end - 8'hc5: begin outa = 10'h27c; outb = 2'b11; outc = 1'b1; end - 8'hc6: begin outa = 10'h1e2; outb = 2'b11; outc = 1'b0; end - 8'hc7: begin outa = 10'h377; outb = 2'b11; outc = 1'b0; end - 8'hc8: begin outa = 10'h33a; outb = 2'b11; outc = 1'b0; end - 8'hc9: begin outa = 10'h32d; outb = 2'b11; outc = 1'b1; end - 8'hca: begin outa = 10'h014; outb = 2'b11; outc = 1'b0; end - 8'hcb: begin outa = 10'h332; outb = 2'b10; outc = 1'b0; end - 8'hcc: begin outa = 10'h359; outb = 2'b00; outc = 1'b0; end - 8'hcd: begin outa = 10'h0a4; outb = 2'b10; outc = 1'b1; end - 8'hce: begin outa = 10'h348; outb = 2'b00; outc = 1'b1; end - 8'hcf: begin outa = 10'h04b; outb = 2'b11; outc = 1'b1; end - 8'hd0: begin outa = 10'h147; outb = 2'b10; outc = 1'b1; end - 8'hd1: begin outa = 10'h026; outb = 2'b00; outc = 1'b1; end - 8'hd2: begin outa = 10'h103; outb = 2'b00; outc = 1'b0; end - 8'hd3: begin outa = 10'h106; outb = 2'b00; outc = 1'b1; end - 8'hd4: begin outa = 10'h35a; outb = 2'b00; outc = 1'b0; end - 8'hd5: begin outa = 10'h254; outb = 2'b01; outc = 1'b0; end - 8'hd6: begin outa = 10'h0cd; outb = 2'b01; outc = 1'b0; end - 8'hd7: begin outa = 10'h17c; outb = 2'b11; outc = 1'b1; end - 8'hd8: begin outa = 10'h37e; outb = 2'b10; outc = 1'b1; end - 8'hd9: begin outa = 10'h0a9; outb = 2'b11; outc = 1'b1; end - 8'hda: begin outa = 10'h0fe; outb = 2'b01; outc = 1'b0; end - 8'hdb: begin outa = 10'h3c0; outb = 2'b11; outc = 1'b1; end - 8'hdc: begin outa = 10'h1d9; outb = 2'b10; outc = 1'b1; end - 8'hdd: begin outa = 10'h10e; outb = 2'b00; outc = 1'b1; end - 8'hde: begin outa = 10'h394; outb = 2'b01; outc = 1'b0; end - 8'hdf: begin outa = 10'h316; outb = 2'b01; outc = 1'b0; end - 8'he0: begin outa = 10'h05b; outb = 2'b11; outc = 1'b0; end - 8'he1: begin outa = 10'h126; outb = 2'b01; outc = 1'b1; end - 8'he2: begin outa = 10'h369; outb = 2'b11; outc = 1'b0; end - 8'he3: begin outa = 10'h291; outb = 2'b10; outc = 1'b1; end - 8'he4: begin outa = 10'h2ca; outb = 2'b00; outc = 1'b1; end - 8'he5: begin outa = 10'h25b; outb = 2'b01; outc = 1'b1; end - 8'he6: begin outa = 10'h106; outb = 2'b00; outc = 1'b0; end - 8'he7: begin outa = 10'h172; outb = 2'b11; outc = 1'b1; end - 8'he8: begin outa = 10'h2f7; outb = 2'b00; outc = 1'b1; end - 8'he9: begin outa = 10'h2d3; outb = 2'b11; outc = 1'b1; end - 8'hea: begin outa = 10'h182; outb = 2'b00; outc = 1'b0; end - 8'heb: begin outa = 10'h327; outb = 2'b00; outc = 1'b1; end - 8'hec: begin outa = 10'h1d0; outb = 2'b10; outc = 1'b0; end - 8'hed: begin outa = 10'h204; outb = 2'b00; outc = 1'b1; end - 8'hee: begin outa = 10'h11f; outb = 2'b00; outc = 1'b1; end - 8'hef: begin outa = 10'h365; outb = 2'b11; outc = 1'b1; end - 8'hf0: begin outa = 10'h2c2; outb = 2'b01; outc = 1'b1; end - 8'hf1: begin outa = 10'h2b5; outb = 2'b10; outc = 1'b0; end - 8'hf2: begin outa = 10'h1f8; outb = 2'b10; outc = 1'b1; end - 8'hf3: begin outa = 10'h2a7; outb = 2'b01; outc = 1'b1; end - 8'hf4: begin outa = 10'h1be; outb = 2'b10; outc = 1'b1; end - 8'hf5: begin outa = 10'h25e; outb = 2'b10; outc = 1'b1; end - 8'hf6: begin outa = 10'h032; outb = 2'b10; outc = 1'b0; end - 8'hf7: begin outa = 10'h2ef; outb = 2'b00; outc = 1'b0; end - 8'hf8: begin outa = 10'h02f; outb = 2'b00; outc = 1'b1; end - 8'hf9: begin outa = 10'h201; outb = 2'b10; outc = 1'b0; end - 8'hfa: begin outa = 10'h054; outb = 2'b01; outc = 1'b1; end - 8'hfb: begin outa = 10'h013; outb = 2'b10; outc = 1'b0; end - 8'hfc: begin outa = 10'h249; outb = 2'b01; outc = 1'b0; end - 8'hfd: begin outa = 10'h09a; outb = 2'b10; outc = 1'b0; end - 8'hfe: begin outa = 10'h012; outb = 2'b00; outc = 1'b0; end - 8'hff: begin outa = 10'h114; outb = 2'b10; outc = 1'b1; end + 8'h00: begin outa = 10'h152; outb = 2'b00; outc = 1'b1; end + 8'h01: begin outa = 10'h318; outb = 2'b11; outc = 1'b1; end + 8'h02: begin outa = 10'h29f; outb = 2'b11; outc = 1'b0; end + 8'h03: begin outa = 10'h392; outb = 2'b01; outc = 1'b1; end + 8'h04: begin outa = 10'h1ef; outb = 2'b00; outc = 1'b0; end + 8'h05: begin outa = 10'h06c; outb = 2'b10; outc = 1'b1; end + 8'h06: begin outa = 10'h29f; outb = 2'b11; outc = 1'b0; end + 8'h07: begin outa = 10'h29a; outb = 2'b10; outc = 1'b0; end + 8'h08: begin outa = 10'h3ce; outb = 2'b01; outc = 1'b0; end + 8'h09: begin outa = 10'h37c; outb = 2'b01; outc = 1'b0; end + 8'h0a: begin outa = 10'h058; outb = 2'b10; outc = 1'b0; end + 8'h0b: begin outa = 10'h3b2; outb = 2'b01; outc = 1'b1; end + 8'h0c: begin outa = 10'h36f; outb = 2'b11; outc = 1'b0; end + 8'h0d: begin outa = 10'h2c5; outb = 2'b11; outc = 1'b0; end + 8'h0e: begin outa = 10'h23a; outb = 2'b00; outc = 1'b0; end + 8'h0f: begin outa = 10'h222; outb = 2'b01; outc = 1'b1; end + 8'h10: begin outa = 10'h328; outb = 2'b00; outc = 1'b1; end + 8'h11: begin outa = 10'h3c3; outb = 2'b00; outc = 1'b1; end + 8'h12: begin outa = 10'h12c; outb = 2'b01; outc = 1'b0; end + 8'h13: begin outa = 10'h1d0; outb = 2'b00; outc = 1'b1; end + 8'h14: begin outa = 10'h3ff; outb = 2'b01; outc = 1'b1; end + 8'h15: begin outa = 10'h115; outb = 2'b11; outc = 1'b1; end + 8'h16: begin outa = 10'h3ba; outb = 2'b10; outc = 1'b0; end + 8'h17: begin outa = 10'h3ba; outb = 2'b00; outc = 1'b0; end + 8'h18: begin outa = 10'h10d; outb = 2'b00; outc = 1'b1; end + 8'h19: begin outa = 10'h13b; outb = 2'b01; outc = 1'b1; end + 8'h1a: begin outa = 10'h0a0; outb = 2'b10; outc = 1'b1; end + 8'h1b: begin outa = 10'h264; outb = 2'b11; outc = 1'b0; end + 8'h1c: begin outa = 10'h3a2; outb = 2'b10; outc = 1'b0; end + 8'h1d: begin outa = 10'h07c; outb = 2'b00; outc = 1'b1; end + 8'h1e: begin outa = 10'h291; outb = 2'b00; outc = 1'b0; end + 8'h1f: begin outa = 10'h1d1; outb = 2'b10; outc = 1'b0; end + 8'h20: begin outa = 10'h354; outb = 2'b11; outc = 1'b1; end + 8'h21: begin outa = 10'h0c0; outb = 2'b00; outc = 1'b1; end + 8'h22: begin outa = 10'h191; outb = 2'b00; outc = 1'b0; end + 8'h23: begin outa = 10'h379; outb = 2'b01; outc = 1'b0; end + 8'h24: begin outa = 10'h073; outb = 2'b00; outc = 1'b0; end + 8'h25: begin outa = 10'h2fd; outb = 2'b11; outc = 1'b1; end + 8'h26: begin outa = 10'h2e0; outb = 2'b11; outc = 1'b1; end + 8'h27: begin outa = 10'h337; outb = 2'b01; outc = 1'b1; end + 8'h28: begin outa = 10'h2c7; outb = 2'b11; outc = 1'b1; end + 8'h29: begin outa = 10'h19e; outb = 2'b11; outc = 1'b0; end + 8'h2a: begin outa = 10'h107; outb = 2'b10; outc = 1'b0; end + 8'h2b: begin outa = 10'h06a; outb = 2'b01; outc = 1'b1; end + 8'h2c: begin outa = 10'h1c7; outb = 2'b01; outc = 1'b1; end + 8'h2d: begin outa = 10'h107; outb = 2'b10; outc = 1'b0; end + 8'h2e: begin outa = 10'h0cf; outb = 2'b01; outc = 1'b1; end + 8'h2f: begin outa = 10'h009; outb = 2'b11; outc = 1'b1; end + 8'h30: begin outa = 10'h09d; outb = 2'b00; outc = 1'b1; end + 8'h31: begin outa = 10'h28e; outb = 2'b00; outc = 1'b0; end + 8'h32: begin outa = 10'h010; outb = 2'b01; outc = 1'b0; end + 8'h33: begin outa = 10'h1e0; outb = 2'b10; outc = 1'b0; end + 8'h34: begin outa = 10'h079; outb = 2'b01; outc = 1'b1; end + 8'h35: begin outa = 10'h13e; outb = 2'b10; outc = 1'b1; end + 8'h36: begin outa = 10'h282; outb = 2'b11; outc = 1'b0; end + 8'h37: begin outa = 10'h21c; outb = 2'b11; outc = 1'b1; end + 8'h38: begin outa = 10'h148; outb = 2'b00; outc = 1'b1; end + 8'h39: begin outa = 10'h3c0; outb = 2'b10; outc = 1'b0; end + 8'h3a: begin outa = 10'h176; outb = 2'b01; outc = 1'b1; end + 8'h3b: begin outa = 10'h3fc; outb = 2'b10; outc = 1'b1; end + 8'h3c: begin outa = 10'h295; outb = 2'b11; outc = 1'b1; end + 8'h3d: begin outa = 10'h113; outb = 2'b10; outc = 1'b1; end + 8'h3e: begin outa = 10'h354; outb = 2'b01; outc = 1'b1; end + 8'h3f: begin outa = 10'h0db; outb = 2'b11; outc = 1'b0; end + 8'h40: begin outa = 10'h238; outb = 2'b01; outc = 1'b0; end + 8'h41: begin outa = 10'h12b; outb = 2'b01; outc = 1'b1; end + 8'h42: begin outa = 10'h1dc; outb = 2'b10; outc = 1'b0; end + 8'h43: begin outa = 10'h137; outb = 2'b01; outc = 1'b1; end + 8'h44: begin outa = 10'h1e2; outb = 2'b01; outc = 1'b1; end + 8'h45: begin outa = 10'h3d5; outb = 2'b11; outc = 1'b1; end + 8'h46: begin outa = 10'h30c; outb = 2'b11; outc = 1'b0; end + 8'h47: begin outa = 10'h298; outb = 2'b11; outc = 1'b0; end + 8'h48: begin outa = 10'h080; outb = 2'b00; outc = 1'b1; end + 8'h49: begin outa = 10'h35a; outb = 2'b11; outc = 1'b1; end + 8'h4a: begin outa = 10'h01b; outb = 2'b00; outc = 1'b0; end + 8'h4b: begin outa = 10'h0a3; outb = 2'b11; outc = 1'b0; end + 8'h4c: begin outa = 10'h0b3; outb = 2'b11; outc = 1'b1; end + 8'h4d: begin outa = 10'h17a; outb = 2'b00; outc = 1'b0; end + 8'h4e: begin outa = 10'h3ae; outb = 2'b11; outc = 1'b0; end + 8'h4f: begin outa = 10'h078; outb = 2'b11; outc = 1'b0; end + 8'h50: begin outa = 10'h322; outb = 2'b00; outc = 1'b1; end + 8'h51: begin outa = 10'h213; outb = 2'b11; outc = 1'b0; end + 8'h52: begin outa = 10'h11a; outb = 2'b11; outc = 1'b0; end + 8'h53: begin outa = 10'h1a7; outb = 2'b00; outc = 1'b0; end + 8'h54: begin outa = 10'h35a; outb = 2'b00; outc = 1'b1; end + 8'h55: begin outa = 10'h233; outb = 2'b00; outc = 1'b0; end + 8'h56: begin outa = 10'h01d; outb = 2'b01; outc = 1'b1; end + 8'h57: begin outa = 10'h2d5; outb = 2'b00; outc = 1'b0; end + 8'h58: begin outa = 10'h1a0; outb = 2'b00; outc = 1'b1; end + 8'h59: begin outa = 10'h3d0; outb = 2'b00; outc = 1'b1; end + 8'h5a: begin outa = 10'h181; outb = 2'b01; outc = 1'b1; end + 8'h5b: begin outa = 10'h219; outb = 2'b01; outc = 1'b1; end + 8'h5c: begin outa = 10'h26a; outb = 2'b01; outc = 1'b1; end + 8'h5d: begin outa = 10'h050; outb = 2'b10; outc = 1'b0; end + 8'h5e: begin outa = 10'h189; outb = 2'b10; outc = 1'b0; end + 8'h5f: begin outa = 10'h1eb; outb = 2'b01; outc = 1'b1; end + 8'h60: begin outa = 10'h224; outb = 2'b00; outc = 1'b1; end + 8'h61: begin outa = 10'h2fe; outb = 2'b00; outc = 1'b0; end + 8'h62: begin outa = 10'h0ae; outb = 2'b00; outc = 1'b1; end + 8'h63: begin outa = 10'h1cd; outb = 2'b00; outc = 1'b0; end + 8'h64: begin outa = 10'h273; outb = 2'b10; outc = 1'b1; end + 8'h65: begin outa = 10'h268; outb = 2'b10; outc = 1'b0; end + 8'h66: begin outa = 10'h111; outb = 2'b01; outc = 1'b0; end + 8'h67: begin outa = 10'h1f9; outb = 2'b00; outc = 1'b0; end + 8'h68: begin outa = 10'h232; outb = 2'b00; outc = 1'b1; end + 8'h69: begin outa = 10'h255; outb = 2'b11; outc = 1'b0; end + 8'h6a: begin outa = 10'h34c; outb = 2'b01; outc = 1'b1; end + 8'h6b: begin outa = 10'h049; outb = 2'b01; outc = 1'b1; end + 8'h6c: begin outa = 10'h197; outb = 2'b11; outc = 1'b0; end + 8'h6d: begin outa = 10'h0fe; outb = 2'b11; outc = 1'b0; end + 8'h6e: begin outa = 10'h253; outb = 2'b01; outc = 1'b1; end + 8'h6f: begin outa = 10'h2de; outb = 2'b11; outc = 1'b0; end + 8'h70: begin outa = 10'h13b; outb = 2'b10; outc = 1'b1; end + 8'h71: begin outa = 10'h040; outb = 2'b10; outc = 1'b0; end + 8'h72: begin outa = 10'h0b4; outb = 2'b00; outc = 1'b1; end + 8'h73: begin outa = 10'h233; outb = 2'b11; outc = 1'b1; end + 8'h74: begin outa = 10'h198; outb = 2'b00; outc = 1'b1; end + 8'h75: begin outa = 10'h018; outb = 2'b00; outc = 1'b1; end + 8'h76: begin outa = 10'h2f7; outb = 2'b00; outc = 1'b1; end + 8'h77: begin outa = 10'h134; outb = 2'b11; outc = 1'b0; end + 8'h78: begin outa = 10'h1ca; outb = 2'b10; outc = 1'b0; end + 8'h79: begin outa = 10'h286; outb = 2'b10; outc = 1'b1; end + 8'h7a: begin outa = 10'h0e6; outb = 2'b11; outc = 1'b1; end + 8'h7b: begin outa = 10'h064; outb = 2'b10; outc = 1'b1; end + 8'h7c: begin outa = 10'h257; outb = 2'b00; outc = 1'b1; end + 8'h7d: begin outa = 10'h31a; outb = 2'b10; outc = 1'b1; end + 8'h7e: begin outa = 10'h247; outb = 2'b01; outc = 1'b0; end + 8'h7f: begin outa = 10'h299; outb = 2'b00; outc = 1'b0; end + 8'h80: begin outa = 10'h02c; outb = 2'b00; outc = 1'b0; end + 8'h81: begin outa = 10'h2bb; outb = 2'b11; outc = 1'b0; end + 8'h82: begin outa = 10'h180; outb = 2'b10; outc = 1'b0; end + 8'h83: begin outa = 10'h245; outb = 2'b01; outc = 1'b1; end + 8'h84: begin outa = 10'h0da; outb = 2'b10; outc = 1'b0; end + 8'h85: begin outa = 10'h367; outb = 2'b10; outc = 1'b0; end + 8'h86: begin outa = 10'h304; outb = 2'b01; outc = 1'b0; end + 8'h87: begin outa = 10'h38b; outb = 2'b11; outc = 1'b0; end + 8'h88: begin outa = 10'h09f; outb = 2'b01; outc = 1'b0; end + 8'h89: begin outa = 10'h1f0; outb = 2'b10; outc = 1'b1; end + 8'h8a: begin outa = 10'h281; outb = 2'b10; outc = 1'b1; end + 8'h8b: begin outa = 10'h019; outb = 2'b00; outc = 1'b0; end + 8'h8c: begin outa = 10'h1f2; outb = 2'b10; outc = 1'b0; end + 8'h8d: begin outa = 10'h0b1; outb = 2'b01; outc = 1'b1; end + 8'h8e: begin outa = 10'h058; outb = 2'b01; outc = 1'b1; end + 8'h8f: begin outa = 10'h39b; outb = 2'b00; outc = 1'b1; end + 8'h90: begin outa = 10'h2ec; outb = 2'b10; outc = 1'b1; end + 8'h91: begin outa = 10'h250; outb = 2'b00; outc = 1'b1; end + 8'h92: begin outa = 10'h3f4; outb = 2'b10; outc = 1'b1; end + 8'h93: begin outa = 10'h057; outb = 2'b10; outc = 1'b1; end + 8'h94: begin outa = 10'h18f; outb = 2'b01; outc = 1'b1; end + 8'h95: begin outa = 10'h105; outb = 2'b01; outc = 1'b1; end + 8'h96: begin outa = 10'h1ae; outb = 2'b00; outc = 1'b1; end + 8'h97: begin outa = 10'h04e; outb = 2'b10; outc = 1'b0; end + 8'h98: begin outa = 10'h240; outb = 2'b11; outc = 1'b0; end + 8'h99: begin outa = 10'h3e4; outb = 2'b01; outc = 1'b0; end + 8'h9a: begin outa = 10'h3c6; outb = 2'b01; outc = 1'b0; end + 8'h9b: begin outa = 10'h109; outb = 2'b00; outc = 1'b1; end + 8'h9c: begin outa = 10'h073; outb = 2'b10; outc = 1'b1; end + 8'h9d: begin outa = 10'h19f; outb = 2'b01; outc = 1'b0; end + 8'h9e: begin outa = 10'h3b8; outb = 2'b01; outc = 1'b0; end + 8'h9f: begin outa = 10'h00e; outb = 2'b00; outc = 1'b1; end + 8'ha0: begin outa = 10'h1b3; outb = 2'b11; outc = 1'b1; end + 8'ha1: begin outa = 10'h2bd; outb = 2'b11; outc = 1'b0; end + 8'ha2: begin outa = 10'h324; outb = 2'b00; outc = 1'b1; end + 8'ha3: begin outa = 10'h343; outb = 2'b10; outc = 1'b0; end + 8'ha4: begin outa = 10'h1c9; outb = 2'b01; outc = 1'b0; end + 8'ha5: begin outa = 10'h185; outb = 2'b00; outc = 1'b1; end + 8'ha6: begin outa = 10'h37a; outb = 2'b00; outc = 1'b1; end + 8'ha7: begin outa = 10'h0e0; outb = 2'b01; outc = 1'b1; end + 8'ha8: begin outa = 10'h0a3; outb = 2'b10; outc = 1'b0; end + 8'ha9: begin outa = 10'h019; outb = 2'b11; outc = 1'b0; end + 8'haa: begin outa = 10'h099; outb = 2'b00; outc = 1'b1; end + 8'hab: begin outa = 10'h376; outb = 2'b01; outc = 1'b1; end + 8'hac: begin outa = 10'h077; outb = 2'b00; outc = 1'b1; end + 8'had: begin outa = 10'h2b1; outb = 2'b11; outc = 1'b1; end + 8'hae: begin outa = 10'h27f; outb = 2'b00; outc = 1'b0; end + 8'haf: begin outa = 10'h265; outb = 2'b11; outc = 1'b0; end + 8'hb0: begin outa = 10'h156; outb = 2'b10; outc = 1'b1; end + 8'hb1: begin outa = 10'h1ce; outb = 2'b00; outc = 1'b0; end + 8'hb2: begin outa = 10'h008; outb = 2'b01; outc = 1'b0; end + 8'hb3: begin outa = 10'h12e; outb = 2'b11; outc = 1'b1; end + 8'hb4: begin outa = 10'h199; outb = 2'b11; outc = 1'b0; end + 8'hb5: begin outa = 10'h330; outb = 2'b10; outc = 1'b0; end + 8'hb6: begin outa = 10'h1ab; outb = 2'b01; outc = 1'b1; end + 8'hb7: begin outa = 10'h3bd; outb = 2'b00; outc = 1'b0; end + 8'hb8: begin outa = 10'h0ca; outb = 2'b10; outc = 1'b0; end + 8'hb9: begin outa = 10'h367; outb = 2'b00; outc = 1'b0; end + 8'hba: begin outa = 10'h334; outb = 2'b00; outc = 1'b0; end + 8'hbb: begin outa = 10'h040; outb = 2'b00; outc = 1'b1; end + 8'hbc: begin outa = 10'h1a7; outb = 2'b10; outc = 1'b1; end + 8'hbd: begin outa = 10'h036; outb = 2'b11; outc = 1'b1; end + 8'hbe: begin outa = 10'h223; outb = 2'b11; outc = 1'b1; end + 8'hbf: begin outa = 10'h075; outb = 2'b01; outc = 1'b0; end + 8'hc0: begin outa = 10'h3c4; outb = 2'b00; outc = 1'b1; end + 8'hc1: begin outa = 10'h2cc; outb = 2'b01; outc = 1'b0; end + 8'hc2: begin outa = 10'h123; outb = 2'b01; outc = 1'b0; end + 8'hc3: begin outa = 10'h3fd; outb = 2'b01; outc = 1'b1; end + 8'hc4: begin outa = 10'h11e; outb = 2'b00; outc = 1'b0; end + 8'hc5: begin outa = 10'h27c; outb = 2'b11; outc = 1'b1; end + 8'hc6: begin outa = 10'h1e2; outb = 2'b11; outc = 1'b0; end + 8'hc7: begin outa = 10'h377; outb = 2'b11; outc = 1'b0; end + 8'hc8: begin outa = 10'h33a; outb = 2'b11; outc = 1'b0; end + 8'hc9: begin outa = 10'h32d; outb = 2'b11; outc = 1'b1; end + 8'hca: begin outa = 10'h014; outb = 2'b11; outc = 1'b0; end + 8'hcb: begin outa = 10'h332; outb = 2'b10; outc = 1'b0; end + 8'hcc: begin outa = 10'h359; outb = 2'b00; outc = 1'b0; end + 8'hcd: begin outa = 10'h0a4; outb = 2'b10; outc = 1'b1; end + 8'hce: begin outa = 10'h348; outb = 2'b00; outc = 1'b1; end + 8'hcf: begin outa = 10'h04b; outb = 2'b11; outc = 1'b1; end + 8'hd0: begin outa = 10'h147; outb = 2'b10; outc = 1'b1; end + 8'hd1: begin outa = 10'h026; outb = 2'b00; outc = 1'b1; end + 8'hd2: begin outa = 10'h103; outb = 2'b00; outc = 1'b0; end + 8'hd3: begin outa = 10'h106; outb = 2'b00; outc = 1'b1; end + 8'hd4: begin outa = 10'h35a; outb = 2'b00; outc = 1'b0; end + 8'hd5: begin outa = 10'h254; outb = 2'b01; outc = 1'b0; end + 8'hd6: begin outa = 10'h0cd; outb = 2'b01; outc = 1'b0; end + 8'hd7: begin outa = 10'h17c; outb = 2'b11; outc = 1'b1; end + 8'hd8: begin outa = 10'h37e; outb = 2'b10; outc = 1'b1; end + 8'hd9: begin outa = 10'h0a9; outb = 2'b11; outc = 1'b1; end + 8'hda: begin outa = 10'h0fe; outb = 2'b01; outc = 1'b0; end + 8'hdb: begin outa = 10'h3c0; outb = 2'b11; outc = 1'b1; end + 8'hdc: begin outa = 10'h1d9; outb = 2'b10; outc = 1'b1; end + 8'hdd: begin outa = 10'h10e; outb = 2'b00; outc = 1'b1; end + 8'hde: begin outa = 10'h394; outb = 2'b01; outc = 1'b0; end + 8'hdf: begin outa = 10'h316; outb = 2'b01; outc = 1'b0; end + 8'he0: begin outa = 10'h05b; outb = 2'b11; outc = 1'b0; end + 8'he1: begin outa = 10'h126; outb = 2'b01; outc = 1'b1; end + 8'he2: begin outa = 10'h369; outb = 2'b11; outc = 1'b0; end + 8'he3: begin outa = 10'h291; outb = 2'b10; outc = 1'b1; end + 8'he4: begin outa = 10'h2ca; outb = 2'b00; outc = 1'b1; end + 8'he5: begin outa = 10'h25b; outb = 2'b01; outc = 1'b1; end + 8'he6: begin outa = 10'h106; outb = 2'b00; outc = 1'b0; end + 8'he7: begin outa = 10'h172; outb = 2'b11; outc = 1'b1; end + 8'he8: begin outa = 10'h2f7; outb = 2'b00; outc = 1'b1; end + 8'he9: begin outa = 10'h2d3; outb = 2'b11; outc = 1'b1; end + 8'hea: begin outa = 10'h182; outb = 2'b00; outc = 1'b0; end + 8'heb: begin outa = 10'h327; outb = 2'b00; outc = 1'b1; end + 8'hec: begin outa = 10'h1d0; outb = 2'b10; outc = 1'b0; end + 8'hed: begin outa = 10'h204; outb = 2'b00; outc = 1'b1; end + 8'hee: begin outa = 10'h11f; outb = 2'b00; outc = 1'b1; end + 8'hef: begin outa = 10'h365; outb = 2'b11; outc = 1'b1; end + 8'hf0: begin outa = 10'h2c2; outb = 2'b01; outc = 1'b1; end + 8'hf1: begin outa = 10'h2b5; outb = 2'b10; outc = 1'b0; end + 8'hf2: begin outa = 10'h1f8; outb = 2'b10; outc = 1'b1; end + 8'hf3: begin outa = 10'h2a7; outb = 2'b01; outc = 1'b1; end + 8'hf4: begin outa = 10'h1be; outb = 2'b10; outc = 1'b1; end + 8'hf5: begin outa = 10'h25e; outb = 2'b10; outc = 1'b1; end + 8'hf6: begin outa = 10'h032; outb = 2'b10; outc = 1'b0; end + 8'hf7: begin outa = 10'h2ef; outb = 2'b00; outc = 1'b0; end + 8'hf8: begin outa = 10'h02f; outb = 2'b00; outc = 1'b1; end + 8'hf9: begin outa = 10'h201; outb = 2'b10; outc = 1'b0; end + 8'hfa: begin outa = 10'h054; outb = 2'b01; outc = 1'b1; end + 8'hfb: begin outa = 10'h013; outb = 2'b10; outc = 1'b0; end + 8'hfc: begin outa = 10'h249; outb = 2'b01; outc = 1'b0; end + 8'hfd: begin outa = 10'h09a; outb = 2'b10; outc = 1'b0; end + 8'hfe: begin outa = 10'h012; outb = 2'b00; outc = 1'b0; end + 8'hff: begin outa = 10'h114; outb = 2'b10; outc = 1'b1; end endcase end endmodule diff --git a/test_regress/t/t_case_huge_sub2.v b/test_regress/t/t_case_huge_sub2.v index d753dff22..20d8422ca 100644 --- a/test_regress/t/t_case_huge_sub2.v +++ b/test_regress/t/t_case_huge_sub2.v @@ -17,7 +17,7 @@ module t_case_huge_sub2 (/*AUTOARG*/ // ============================= /*AUTOREG*/ // Beginning of automatic regs (for this module's undeclared outputs) - reg [9:0] outa; + reg [9:0] outa; // End of automatics // ============================= @@ -27,265 +27,265 @@ module t_case_huge_sub2 (/*AUTOARG*/ always @(/*AS*/index) begin case (index[7:0]) `ifdef VERILATOR // Harder test - 8'h00: begin outa = $c("0"); end // Makes whole table non-optimizable + 8'h00: begin outa = $c("0"); end // Makes whole table non-optimizable `else - 8'h00: begin outa = 10'h0; end + 8'h00: begin outa = 10'h0; end `endif - 8'h01: begin outa = 10'h318; end - 8'h02: begin outa = 10'h29f; end - 8'h03: begin outa = 10'h392; end - 8'h04: begin outa = 10'h1ef; end - 8'h05: begin outa = 10'h06c; end - 8'h06: begin outa = 10'h29f; end - 8'h07: begin outa = 10'h29a; end - 8'h08: begin outa = 10'h3ce; end - 8'h09: begin outa = 10'h37c; end - 8'h0a: begin outa = 10'h058; end - 8'h0b: begin outa = 10'h3b2; end - 8'h0c: begin outa = 10'h36f; end - 8'h0d: begin outa = 10'h2c5; end - 8'h0e: begin outa = 10'h23a; end - 8'h0f: begin outa = 10'h222; end - 8'h10: begin outa = 10'h328; end - 8'h11: begin outa = 10'h3c3; end - 8'h12: begin outa = 10'h12c; end - 8'h13: begin outa = 10'h1d0; end - 8'h14: begin outa = 10'h3ff; end - 8'h15: begin outa = 10'h115; end - 8'h16: begin outa = 10'h3ba; end - 8'h17: begin outa = 10'h3ba; end - 8'h18: begin outa = 10'h10d; end - 8'h19: begin outa = 10'h13b; end - 8'h1a: begin outa = 10'h0a0; end - 8'h1b: begin outa = 10'h264; end - 8'h1c: begin outa = 10'h3a2; end - 8'h1d: begin outa = 10'h07c; end - 8'h1e: begin outa = 10'h291; end - 8'h1f: begin outa = 10'h1d1; end - 8'h20: begin outa = 10'h354; end - 8'h21: begin outa = 10'h0c0; end - 8'h22: begin outa = 10'h191; end - 8'h23: begin outa = 10'h379; end - 8'h24: begin outa = 10'h073; end - 8'h25: begin outa = 10'h2fd; end - 8'h26: begin outa = 10'h2e0; end - 8'h27: begin outa = 10'h337; end - 8'h28: begin outa = 10'h2c7; end - 8'h29: begin outa = 10'h19e; end - 8'h2a: begin outa = 10'h107; end - 8'h2b: begin outa = 10'h06a; end - 8'h2c: begin outa = 10'h1c7; end - 8'h2d: begin outa = 10'h107; end - 8'h2e: begin outa = 10'h0cf; end - 8'h2f: begin outa = 10'h009; end - 8'h30: begin outa = 10'h09d; end - 8'h31: begin outa = 10'h28e; end - 8'h32: begin outa = 10'h010; end - 8'h33: begin outa = 10'h1e0; end - 8'h34: begin outa = 10'h079; end - 8'h35: begin outa = 10'h13e; end - 8'h36: begin outa = 10'h282; end - 8'h37: begin outa = 10'h21c; end - 8'h38: begin outa = 10'h148; end - 8'h39: begin outa = 10'h3c0; end - 8'h3a: begin outa = 10'h176; end - 8'h3b: begin outa = 10'h3fc; end - 8'h3c: begin outa = 10'h295; end - 8'h3d: begin outa = 10'h113; end - 8'h3e: begin outa = 10'h354; end - 8'h3f: begin outa = 10'h0db; end - 8'h40: begin outa = 10'h238; end - 8'h41: begin outa = 10'h12b; end - 8'h42: begin outa = 10'h1dc; end - 8'h43: begin outa = 10'h137; end - 8'h44: begin outa = 10'h1e2; end - 8'h45: begin outa = 10'h3d5; end - 8'h46: begin outa = 10'h30c; end - 8'h47: begin outa = 10'h298; end - 8'h48: begin outa = 10'h080; end - 8'h49: begin outa = 10'h35a; end - 8'h4a: begin outa = 10'h01b; end - 8'h4b: begin outa = 10'h0a3; end - 8'h4c: begin outa = 10'h0b3; end - 8'h4d: begin outa = 10'h17a; end - 8'h4e: begin outa = 10'h3ae; end - 8'h4f: begin outa = 10'h078; end - 8'h50: begin outa = 10'h322; end - 8'h51: begin outa = 10'h213; end - 8'h52: begin outa = 10'h11a; end - 8'h53: begin outa = 10'h1a7; end - 8'h54: begin outa = 10'h35a; end - 8'h55: begin outa = 10'h233; end - 8'h56: begin outa = 10'h01d; end - 8'h57: begin outa = 10'h2d5; end - 8'h58: begin outa = 10'h1a0; end - 8'h59: begin outa = 10'h3d0; end - 8'h5a: begin outa = 10'h181; end - 8'h5b: begin outa = 10'h219; end - 8'h5c: begin outa = 10'h26a; end - 8'h5d: begin outa = 10'h050; end - 8'h5e: begin outa = 10'h189; end - 8'h5f: begin outa = 10'h1eb; end - 8'h60: begin outa = 10'h224; end - 8'h61: begin outa = 10'h2fe; end - 8'h62: begin outa = 10'h0ae; end - 8'h63: begin outa = 10'h1cd; end - 8'h64: begin outa = 10'h273; end - 8'h65: begin outa = 10'h268; end - 8'h66: begin outa = 10'h111; end - 8'h67: begin outa = 10'h1f9; end - 8'h68: begin outa = 10'h232; end - 8'h69: begin outa = 10'h255; end - 8'h6a: begin outa = 10'h34c; end - 8'h6b: begin outa = 10'h049; end - 8'h6c: begin outa = 10'h197; end - 8'h6d: begin outa = 10'h0fe; end - 8'h6e: begin outa = 10'h253; end - 8'h6f: begin outa = 10'h2de; end - 8'h70: begin outa = 10'h13b; end - 8'h71: begin outa = 10'h040; end - 8'h72: begin outa = 10'h0b4; end - 8'h73: begin outa = 10'h233; end - 8'h74: begin outa = 10'h198; end - 8'h75: begin outa = 10'h018; end - 8'h76: begin outa = 10'h2f7; end - 8'h77: begin outa = 10'h134; end - 8'h78: begin outa = 10'h1ca; end - 8'h79: begin outa = 10'h286; end - 8'h7a: begin outa = 10'h0e6; end - 8'h7b: begin outa = 10'h064; end - 8'h7c: begin outa = 10'h257; end - 8'h7d: begin outa = 10'h31a; end - 8'h7e: begin outa = 10'h247; end - 8'h7f: begin outa = 10'h299; end - 8'h80: begin outa = 10'h02c; end - 8'h81: begin outa = 10'h2bb; end - 8'h82: begin outa = 10'h180; end - 8'h83: begin outa = 10'h245; end - 8'h84: begin outa = 10'h0da; end - 8'h85: begin outa = 10'h367; end - 8'h86: begin outa = 10'h304; end - 8'h87: begin outa = 10'h38b; end - 8'h88: begin outa = 10'h09f; end - 8'h89: begin outa = 10'h1f0; end - 8'h8a: begin outa = 10'h281; end - 8'h8b: begin outa = 10'h019; end - 8'h8c: begin outa = 10'h1f2; end - 8'h8d: begin outa = 10'h0b1; end - 8'h8e: begin outa = 10'h058; end - 8'h8f: begin outa = 10'h39b; end - 8'h90: begin outa = 10'h2ec; end - 8'h91: begin outa = 10'h250; end - 8'h92: begin outa = 10'h3f4; end - 8'h93: begin outa = 10'h057; end - 8'h94: begin outa = 10'h18f; end - 8'h95: begin outa = 10'h105; end - 8'h96: begin outa = 10'h1ae; end - 8'h97: begin outa = 10'h04e; end - 8'h98: begin outa = 10'h240; end - 8'h99: begin outa = 10'h3e4; end - 8'h9a: begin outa = 10'h3c6; end - 8'h9b: begin outa = 10'h109; end - 8'h9c: begin outa = 10'h073; end - 8'h9d: begin outa = 10'h19f; end - 8'h9e: begin outa = 10'h3b8; end - 8'h9f: begin outa = 10'h00e; end - 8'ha0: begin outa = 10'h1b3; end - 8'ha1: begin outa = 10'h2bd; end - 8'ha2: begin outa = 10'h324; end - 8'ha3: begin outa = 10'h343; end - 8'ha4: begin outa = 10'h1c9; end - 8'ha5: begin outa = 10'h185; end - 8'ha6: begin outa = 10'h37a; end - 8'ha7: begin outa = 10'h0e0; end - 8'ha8: begin outa = 10'h0a3; end - 8'ha9: begin outa = 10'h019; end - 8'haa: begin outa = 10'h099; end - 8'hab: begin outa = 10'h376; end - 8'hac: begin outa = 10'h077; end - 8'had: begin outa = 10'h2b1; end - 8'hae: begin outa = 10'h27f; end - 8'haf: begin outa = 10'h265; end - 8'hb0: begin outa = 10'h156; end - 8'hb1: begin outa = 10'h1ce; end - 8'hb2: begin outa = 10'h008; end - 8'hb3: begin outa = 10'h12e; end - 8'hb4: begin outa = 10'h199; end - 8'hb5: begin outa = 10'h330; end - 8'hb6: begin outa = 10'h1ab; end - 8'hb7: begin outa = 10'h3bd; end - 8'hb8: begin outa = 10'h0ca; end - 8'hb9: begin outa = 10'h367; end - 8'hba: begin outa = 10'h334; end - 8'hbb: begin outa = 10'h040; end - 8'hbc: begin outa = 10'h1a7; end - 8'hbd: begin outa = 10'h036; end - 8'hbe: begin outa = 10'h223; end - 8'hbf: begin outa = 10'h075; end - 8'hc0: begin outa = 10'h3c4; end - 8'hc1: begin outa = 10'h2cc; end - 8'hc2: begin outa = 10'h123; end - 8'hc3: begin outa = 10'h3fd; end - 8'hc4: begin outa = 10'h11e; end - 8'hc5: begin outa = 10'h27c; end - 8'hc6: begin outa = 10'h1e2; end - 8'hc7: begin outa = 10'h377; end - 8'hc8: begin outa = 10'h33a; end - 8'hc9: begin outa = 10'h32d; end - 8'hca: begin outa = 10'h014; end - 8'hcb: begin outa = 10'h332; end - 8'hcc: begin outa = 10'h359; end - 8'hcd: begin outa = 10'h0a4; end - 8'hce: begin outa = 10'h348; end - 8'hcf: begin outa = 10'h04b; end - 8'hd0: begin outa = 10'h147; end - 8'hd1: begin outa = 10'h026; end - 8'hd2: begin outa = 10'h103; end - 8'hd3: begin outa = 10'h106; end - 8'hd4: begin outa = 10'h35a; end - 8'hd5: begin outa = 10'h254; end - 8'hd6: begin outa = 10'h0cd; end - 8'hd7: begin outa = 10'h17c; end - 8'hd8: begin outa = 10'h37e; end - 8'hd9: begin outa = 10'h0a9; end - 8'hda: begin outa = 10'h0fe; end - 8'hdb: begin outa = 10'h3c0; end - 8'hdc: begin outa = 10'h1d9; end - 8'hdd: begin outa = 10'h10e; end - 8'hde: begin outa = 10'h394; end - 8'hdf: begin outa = 10'h316; end - 8'he0: begin outa = 10'h05b; end - 8'he1: begin outa = 10'h126; end - 8'he2: begin outa = 10'h369; end - 8'he3: begin outa = 10'h291; end - 8'he4: begin outa = 10'h2ca; end - 8'he5: begin outa = 10'h25b; end - 8'he6: begin outa = 10'h106; end - 8'he7: begin outa = 10'h172; end - 8'he8: begin outa = 10'h2f7; end - 8'he9: begin outa = 10'h2d3; end - 8'hea: begin outa = 10'h182; end - 8'heb: begin outa = 10'h327; end - 8'hec: begin outa = 10'h1d0; end - 8'hed: begin outa = 10'h204; end - 8'hee: begin outa = 10'h11f; end - 8'hef: begin outa = 10'h365; end - 8'hf0: begin outa = 10'h2c2; end - 8'hf1: begin outa = 10'h2b5; end - 8'hf2: begin outa = 10'h1f8; end - 8'hf3: begin outa = 10'h2a7; end - 8'hf4: begin outa = 10'h1be; end - 8'hf5: begin outa = 10'h25e; end - 8'hf6: begin outa = 10'h032; end - 8'hf7: begin outa = 10'h2ef; end - 8'hf8: begin outa = 10'h02f; end - 8'hf9: begin outa = 10'h201; end - 8'hfa: begin outa = 10'h054; end - 8'hfb: begin outa = 10'h013; end - 8'hfc: begin outa = 10'h249; end - 8'hfd: begin outa = 10'h09a; end - 8'hfe: begin outa = 10'h012; end - 8'hff: begin outa = 10'h114; end + 8'h01: begin outa = 10'h318; end + 8'h02: begin outa = 10'h29f; end + 8'h03: begin outa = 10'h392; end + 8'h04: begin outa = 10'h1ef; end + 8'h05: begin outa = 10'h06c; end + 8'h06: begin outa = 10'h29f; end + 8'h07: begin outa = 10'h29a; end + 8'h08: begin outa = 10'h3ce; end + 8'h09: begin outa = 10'h37c; end + 8'h0a: begin outa = 10'h058; end + 8'h0b: begin outa = 10'h3b2; end + 8'h0c: begin outa = 10'h36f; end + 8'h0d: begin outa = 10'h2c5; end + 8'h0e: begin outa = 10'h23a; end + 8'h0f: begin outa = 10'h222; end + 8'h10: begin outa = 10'h328; end + 8'h11: begin outa = 10'h3c3; end + 8'h12: begin outa = 10'h12c; end + 8'h13: begin outa = 10'h1d0; end + 8'h14: begin outa = 10'h3ff; end + 8'h15: begin outa = 10'h115; end + 8'h16: begin outa = 10'h3ba; end + 8'h17: begin outa = 10'h3ba; end + 8'h18: begin outa = 10'h10d; end + 8'h19: begin outa = 10'h13b; end + 8'h1a: begin outa = 10'h0a0; end + 8'h1b: begin outa = 10'h264; end + 8'h1c: begin outa = 10'h3a2; end + 8'h1d: begin outa = 10'h07c; end + 8'h1e: begin outa = 10'h291; end + 8'h1f: begin outa = 10'h1d1; end + 8'h20: begin outa = 10'h354; end + 8'h21: begin outa = 10'h0c0; end + 8'h22: begin outa = 10'h191; end + 8'h23: begin outa = 10'h379; end + 8'h24: begin outa = 10'h073; end + 8'h25: begin outa = 10'h2fd; end + 8'h26: begin outa = 10'h2e0; end + 8'h27: begin outa = 10'h337; end + 8'h28: begin outa = 10'h2c7; end + 8'h29: begin outa = 10'h19e; end + 8'h2a: begin outa = 10'h107; end + 8'h2b: begin outa = 10'h06a; end + 8'h2c: begin outa = 10'h1c7; end + 8'h2d: begin outa = 10'h107; end + 8'h2e: begin outa = 10'h0cf; end + 8'h2f: begin outa = 10'h009; end + 8'h30: begin outa = 10'h09d; end + 8'h31: begin outa = 10'h28e; end + 8'h32: begin outa = 10'h010; end + 8'h33: begin outa = 10'h1e0; end + 8'h34: begin outa = 10'h079; end + 8'h35: begin outa = 10'h13e; end + 8'h36: begin outa = 10'h282; end + 8'h37: begin outa = 10'h21c; end + 8'h38: begin outa = 10'h148; end + 8'h39: begin outa = 10'h3c0; end + 8'h3a: begin outa = 10'h176; end + 8'h3b: begin outa = 10'h3fc; end + 8'h3c: begin outa = 10'h295; end + 8'h3d: begin outa = 10'h113; end + 8'h3e: begin outa = 10'h354; end + 8'h3f: begin outa = 10'h0db; end + 8'h40: begin outa = 10'h238; end + 8'h41: begin outa = 10'h12b; end + 8'h42: begin outa = 10'h1dc; end + 8'h43: begin outa = 10'h137; end + 8'h44: begin outa = 10'h1e2; end + 8'h45: begin outa = 10'h3d5; end + 8'h46: begin outa = 10'h30c; end + 8'h47: begin outa = 10'h298; end + 8'h48: begin outa = 10'h080; end + 8'h49: begin outa = 10'h35a; end + 8'h4a: begin outa = 10'h01b; end + 8'h4b: begin outa = 10'h0a3; end + 8'h4c: begin outa = 10'h0b3; end + 8'h4d: begin outa = 10'h17a; end + 8'h4e: begin outa = 10'h3ae; end + 8'h4f: begin outa = 10'h078; end + 8'h50: begin outa = 10'h322; end + 8'h51: begin outa = 10'h213; end + 8'h52: begin outa = 10'h11a; end + 8'h53: begin outa = 10'h1a7; end + 8'h54: begin outa = 10'h35a; end + 8'h55: begin outa = 10'h233; end + 8'h56: begin outa = 10'h01d; end + 8'h57: begin outa = 10'h2d5; end + 8'h58: begin outa = 10'h1a0; end + 8'h59: begin outa = 10'h3d0; end + 8'h5a: begin outa = 10'h181; end + 8'h5b: begin outa = 10'h219; end + 8'h5c: begin outa = 10'h26a; end + 8'h5d: begin outa = 10'h050; end + 8'h5e: begin outa = 10'h189; end + 8'h5f: begin outa = 10'h1eb; end + 8'h60: begin outa = 10'h224; end + 8'h61: begin outa = 10'h2fe; end + 8'h62: begin outa = 10'h0ae; end + 8'h63: begin outa = 10'h1cd; end + 8'h64: begin outa = 10'h273; end + 8'h65: begin outa = 10'h268; end + 8'h66: begin outa = 10'h111; end + 8'h67: begin outa = 10'h1f9; end + 8'h68: begin outa = 10'h232; end + 8'h69: begin outa = 10'h255; end + 8'h6a: begin outa = 10'h34c; end + 8'h6b: begin outa = 10'h049; end + 8'h6c: begin outa = 10'h197; end + 8'h6d: begin outa = 10'h0fe; end + 8'h6e: begin outa = 10'h253; end + 8'h6f: begin outa = 10'h2de; end + 8'h70: begin outa = 10'h13b; end + 8'h71: begin outa = 10'h040; end + 8'h72: begin outa = 10'h0b4; end + 8'h73: begin outa = 10'h233; end + 8'h74: begin outa = 10'h198; end + 8'h75: begin outa = 10'h018; end + 8'h76: begin outa = 10'h2f7; end + 8'h77: begin outa = 10'h134; end + 8'h78: begin outa = 10'h1ca; end + 8'h79: begin outa = 10'h286; end + 8'h7a: begin outa = 10'h0e6; end + 8'h7b: begin outa = 10'h064; end + 8'h7c: begin outa = 10'h257; end + 8'h7d: begin outa = 10'h31a; end + 8'h7e: begin outa = 10'h247; end + 8'h7f: begin outa = 10'h299; end + 8'h80: begin outa = 10'h02c; end + 8'h81: begin outa = 10'h2bb; end + 8'h82: begin outa = 10'h180; end + 8'h83: begin outa = 10'h245; end + 8'h84: begin outa = 10'h0da; end + 8'h85: begin outa = 10'h367; end + 8'h86: begin outa = 10'h304; end + 8'h87: begin outa = 10'h38b; end + 8'h88: begin outa = 10'h09f; end + 8'h89: begin outa = 10'h1f0; end + 8'h8a: begin outa = 10'h281; end + 8'h8b: begin outa = 10'h019; end + 8'h8c: begin outa = 10'h1f2; end + 8'h8d: begin outa = 10'h0b1; end + 8'h8e: begin outa = 10'h058; end + 8'h8f: begin outa = 10'h39b; end + 8'h90: begin outa = 10'h2ec; end + 8'h91: begin outa = 10'h250; end + 8'h92: begin outa = 10'h3f4; end + 8'h93: begin outa = 10'h057; end + 8'h94: begin outa = 10'h18f; end + 8'h95: begin outa = 10'h105; end + 8'h96: begin outa = 10'h1ae; end + 8'h97: begin outa = 10'h04e; end + 8'h98: begin outa = 10'h240; end + 8'h99: begin outa = 10'h3e4; end + 8'h9a: begin outa = 10'h3c6; end + 8'h9b: begin outa = 10'h109; end + 8'h9c: begin outa = 10'h073; end + 8'h9d: begin outa = 10'h19f; end + 8'h9e: begin outa = 10'h3b8; end + 8'h9f: begin outa = 10'h00e; end + 8'ha0: begin outa = 10'h1b3; end + 8'ha1: begin outa = 10'h2bd; end + 8'ha2: begin outa = 10'h324; end + 8'ha3: begin outa = 10'h343; end + 8'ha4: begin outa = 10'h1c9; end + 8'ha5: begin outa = 10'h185; end + 8'ha6: begin outa = 10'h37a; end + 8'ha7: begin outa = 10'h0e0; end + 8'ha8: begin outa = 10'h0a3; end + 8'ha9: begin outa = 10'h019; end + 8'haa: begin outa = 10'h099; end + 8'hab: begin outa = 10'h376; end + 8'hac: begin outa = 10'h077; end + 8'had: begin outa = 10'h2b1; end + 8'hae: begin outa = 10'h27f; end + 8'haf: begin outa = 10'h265; end + 8'hb0: begin outa = 10'h156; end + 8'hb1: begin outa = 10'h1ce; end + 8'hb2: begin outa = 10'h008; end + 8'hb3: begin outa = 10'h12e; end + 8'hb4: begin outa = 10'h199; end + 8'hb5: begin outa = 10'h330; end + 8'hb6: begin outa = 10'h1ab; end + 8'hb7: begin outa = 10'h3bd; end + 8'hb8: begin outa = 10'h0ca; end + 8'hb9: begin outa = 10'h367; end + 8'hba: begin outa = 10'h334; end + 8'hbb: begin outa = 10'h040; end + 8'hbc: begin outa = 10'h1a7; end + 8'hbd: begin outa = 10'h036; end + 8'hbe: begin outa = 10'h223; end + 8'hbf: begin outa = 10'h075; end + 8'hc0: begin outa = 10'h3c4; end + 8'hc1: begin outa = 10'h2cc; end + 8'hc2: begin outa = 10'h123; end + 8'hc3: begin outa = 10'h3fd; end + 8'hc4: begin outa = 10'h11e; end + 8'hc5: begin outa = 10'h27c; end + 8'hc6: begin outa = 10'h1e2; end + 8'hc7: begin outa = 10'h377; end + 8'hc8: begin outa = 10'h33a; end + 8'hc9: begin outa = 10'h32d; end + 8'hca: begin outa = 10'h014; end + 8'hcb: begin outa = 10'h332; end + 8'hcc: begin outa = 10'h359; end + 8'hcd: begin outa = 10'h0a4; end + 8'hce: begin outa = 10'h348; end + 8'hcf: begin outa = 10'h04b; end + 8'hd0: begin outa = 10'h147; end + 8'hd1: begin outa = 10'h026; end + 8'hd2: begin outa = 10'h103; end + 8'hd3: begin outa = 10'h106; end + 8'hd4: begin outa = 10'h35a; end + 8'hd5: begin outa = 10'h254; end + 8'hd6: begin outa = 10'h0cd; end + 8'hd7: begin outa = 10'h17c; end + 8'hd8: begin outa = 10'h37e; end + 8'hd9: begin outa = 10'h0a9; end + 8'hda: begin outa = 10'h0fe; end + 8'hdb: begin outa = 10'h3c0; end + 8'hdc: begin outa = 10'h1d9; end + 8'hdd: begin outa = 10'h10e; end + 8'hde: begin outa = 10'h394; end + 8'hdf: begin outa = 10'h316; end + 8'he0: begin outa = 10'h05b; end + 8'he1: begin outa = 10'h126; end + 8'he2: begin outa = 10'h369; end + 8'he3: begin outa = 10'h291; end + 8'he4: begin outa = 10'h2ca; end + 8'he5: begin outa = 10'h25b; end + 8'he6: begin outa = 10'h106; end + 8'he7: begin outa = 10'h172; end + 8'he8: begin outa = 10'h2f7; end + 8'he9: begin outa = 10'h2d3; end + 8'hea: begin outa = 10'h182; end + 8'heb: begin outa = 10'h327; end + 8'hec: begin outa = 10'h1d0; end + 8'hed: begin outa = 10'h204; end + 8'hee: begin outa = 10'h11f; end + 8'hef: begin outa = 10'h365; end + 8'hf0: begin outa = 10'h2c2; end + 8'hf1: begin outa = 10'h2b5; end + 8'hf2: begin outa = 10'h1f8; end + 8'hf3: begin outa = 10'h2a7; end + 8'hf4: begin outa = 10'h1be; end + 8'hf5: begin outa = 10'h25e; end + 8'hf6: begin outa = 10'h032; end + 8'hf7: begin outa = 10'h2ef; end + 8'hf8: begin outa = 10'h02f; end + 8'hf9: begin outa = 10'h201; end + 8'hfa: begin outa = 10'h054; end + 8'hfb: begin outa = 10'h013; end + 8'hfc: begin outa = 10'h249; end + 8'hfd: begin outa = 10'h09a; end + 8'hfe: begin outa = 10'h012; end + 8'hff: begin outa = 10'h114; end endcase end endmodule diff --git a/test_regress/t/t_case_huge_sub3.v b/test_regress/t/t_case_huge_sub3.v index 8174c9100..82f100177 100644 --- a/test_regress/t/t_case_huge_sub3.v +++ b/test_regress/t/t_case_huge_sub3.v @@ -18,7 +18,7 @@ module t_case_huge_sub3 (/*AUTOARG*/ // ============================= /*AUTOREG*/ // Beginning of automatic regs (for this module's undeclared outputs) - reg [3:0] outr; + reg [3:0] outr; // End of automatics // ============================= @@ -31,262 +31,262 @@ module t_case_huge_sub3 (/*AUTOARG*/ always @(posedge clk) begin case (index[7:0]) - 8'h00: begin outr <= 4'h0; end - 8'h01: begin /*No Change*/ end - 8'h02: begin outr <= outr^index[8:5]^4'ha; end - 8'h03: begin outr <= outr^index[8:5]^4'h4; end - 8'h04: begin outr <= outr^index[8:5]^4'hd; end - 8'h05: begin outr <= outr^index[8:5]^4'h1; end - 8'h06: begin outr <= outr^index[8:5]^4'hf; end - 8'h07: begin outr <= outr^index[8:5]^4'he; end - 8'h08: begin outr <= outr^index[8:5]^4'h0; end - 8'h09: begin outr <= outr^index[8:5]^4'h4; end - 8'h0a: begin outr <= outr^index[8:5]^4'h5; end - 8'h0b: begin outr <= outr^index[8:5]^4'ha; end - 8'h0c: begin outr <= outr^index[8:5]^4'h2; end - 8'h0d: begin outr <= outr^index[8:5]^4'hf; end - 8'h0e: begin outr <= outr^index[8:5]^4'h5; end - 8'h0f: begin outr <= outr^index[8:5]^4'h0; end - 8'h10: begin outr <= outr^index[8:5]^4'h3; end - 8'h11: begin outr <= outr^index[8:5]^4'hb; end - 8'h12: begin outr <= outr^index[8:5]^4'h0; end - 8'h13: begin outr <= outr^index[8:5]^4'hf; end - 8'h14: begin outr <= outr^index[8:5]^4'h3; end - 8'h15: begin outr <= outr^index[8:5]^4'h5; end - 8'h16: begin outr <= outr^index[8:5]^4'h7; end - 8'h17: begin outr <= outr^index[8:5]^4'h2; end - 8'h18: begin outr <= outr^index[8:5]^4'h3; end - 8'h19: begin outr <= outr^index[8:5]^4'hb; end - 8'h1a: begin outr <= outr^index[8:5]^4'h5; end - 8'h1b: begin outr <= outr^index[8:5]^4'h4; end - 8'h1c: begin outr <= outr^index[8:5]^4'h2; end - 8'h1d: begin outr <= outr^index[8:5]^4'hf; end - 8'h1e: begin outr <= outr^index[8:5]^4'h0; end - 8'h1f: begin outr <= outr^index[8:5]^4'h4; end - 8'h20: begin outr <= outr^index[8:5]^4'h6; end - 8'h21: begin outr <= outr^index[8:5]^4'ha; end - 8'h22: begin outr <= outr^index[8:5]^4'h6; end - 8'h23: begin outr <= outr^index[8:5]^4'hb; end - 8'h24: begin outr <= outr^index[8:5]^4'ha; end - 8'h25: begin outr <= outr^index[8:5]^4'he; end - 8'h26: begin outr <= outr^index[8:5]^4'h7; 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end + 8'he1: begin outr <= outr^index[8:5]^4'h0; end + 8'he2: begin outr <= outr^index[8:5]^4'h9; end + 8'he3: begin outr <= outr^index[8:5]^4'h3; end + 8'he4: begin outr <= outr^index[8:5]^4'h2; end + 8'he5: begin outr <= outr^index[8:5]^4'h4; end + 8'he6: begin outr <= outr^index[8:5]^4'h5; end + 8'he7: begin outr <= outr^index[8:5]^4'h5; end + 8'he8: begin outr <= outr^index[8:5]^4'hf; end + 8'he9: begin outr <= outr^index[8:5]^4'ha; end + 8'hea: begin outr <= outr^index[8:5]^4'hc; end + 8'heb: begin outr <= outr^index[8:5]^4'hd; end + 8'hec: begin outr <= outr^index[8:5]^4'h1; end + 8'hed: begin outr <= outr^index[8:5]^4'h5; end + 8'hee: begin outr <= outr^index[8:5]^4'h9; end + 8'hef: begin outr <= outr^index[8:5]^4'h0; end + 8'hf0: begin outr <= outr^index[8:5]^4'hd; end + 8'hf1: begin outr <= outr^index[8:5]^4'hf; end + 8'hf2: begin outr <= outr^index[8:5]^4'h4; end + 8'hf3: begin outr <= outr^index[8:5]^4'ha; end + 8'hf4: begin outr <= outr^index[8:5]^4'h8; end + 8'hf5: begin outr <= outr^index[8:5]^4'he; end + 8'hf6: begin outr <= outr^index[8:5]^4'he; end + 8'hf7: begin outr <= outr^index[8:5]^4'h1; end + 8'hf8: begin outr <= outr^index[8:5]^4'h6; end + 8'hf9: begin outr <= outr^index[8:5]^4'h0; end + 8'hfa: begin outr <= outr^index[8:5]^4'h5; end + 8'hfb: begin outr <= outr^index[8:5]^4'h1; end + 8'hfc: begin outr <= outr^index[8:5]^4'h8; end + 8'hfd: begin outr <= outr^index[8:5]^4'h6; end + 8'hfe: begin outr <= outr^index[8:5]^4'h1; end + default: begin outr <= outr^index[8:5]^4'h6; end endcase end endmodule diff --git a/test_regress/t/t_case_huge_sub4.v b/test_regress/t/t_case_huge_sub4.v index 221dafcc8..c642bc65e 100644 --- a/test_regress/t/t_case_huge_sub4.v +++ b/test_regress/t/t_case_huge_sub4.v @@ -19,47 +19,47 @@ module t_case_huge_sub4 (/*AUTOARG*/ // ============================= /*AUTOREG*/ // Beginning of automatic regs (for this module's undeclared outputs) - reg [9:0] outq; + reg [9:0] outq; // End of automatics // ============================= always @(/*AS*/index) begin case (index) - // default below: no change - 8'h00: begin outq = 10'h001; end - 8'he0: begin outq = 10'h05b; end - 8'he1: begin outq = 10'h126; end - 8'he2: begin outq = 10'h369; end - 8'he3: begin outq = 10'h291; end - 8'he4: begin outq = 10'h2ca; end - 8'he5: begin outq = 10'h25b; end - 8'he6: begin outq = 10'h106; end - 8'he7: begin outq = 10'h172; end - 8'he8: begin outq = 10'h2f7; end - 8'he9: begin outq = 10'h2d3; end - 8'hea: begin outq = 10'h182; end - 8'heb: begin outq = 10'h327; end - 8'hec: begin outq = 10'h1d0; end - 8'hed: begin outq = 10'h204; end - 8'hee: begin outq = 10'h11f; end - 8'hef: begin outq = 10'h365; end - 8'hf0: begin outq = 10'h2c2; end - 8'hf1: begin outq = 10'h2b5; end - 8'hf2: begin outq = 10'h1f8; end - 8'hf3: begin outq = 10'h2a7; end - 8'hf4: begin outq = 10'h1be; end - 8'hf5: begin outq = 10'h25e; end - 8'hf6: begin outq = 10'h032; end - 8'hf7: begin outq = 10'h2ef; end - 8'hf8: begin outq = 10'h02f; end - 8'hf9: begin outq = 10'h201; end - 8'hfa: begin outq = 10'h054; end - 8'hfb: begin outq = 10'h013; end - 8'hfc: begin outq = 10'h249; end - 8'hfd: begin outq = 10'h09a; end - 8'hfe: begin outq = 10'h012; end - 8'hff: begin outq = 10'h114; end - default: ; // No change + // default below: no change + 8'h00: begin outq = 10'h001; end + 8'he0: begin outq = 10'h05b; end + 8'he1: begin outq = 10'h126; end + 8'he2: begin outq = 10'h369; end + 8'he3: begin outq = 10'h291; end + 8'he4: begin outq = 10'h2ca; end + 8'he5: begin outq = 10'h25b; end + 8'he6: begin outq = 10'h106; end + 8'he7: begin outq = 10'h172; end + 8'he8: begin outq = 10'h2f7; end + 8'he9: begin outq = 10'h2d3; end + 8'hea: begin outq = 10'h182; end + 8'heb: begin outq = 10'h327; end + 8'hec: begin outq = 10'h1d0; end + 8'hed: begin outq = 10'h204; end + 8'hee: begin outq = 10'h11f; end + 8'hef: begin outq = 10'h365; end + 8'hf0: begin outq = 10'h2c2; end + 8'hf1: begin outq = 10'h2b5; end + 8'hf2: begin outq = 10'h1f8; end + 8'hf3: begin outq = 10'h2a7; end + 8'hf4: begin outq = 10'h1be; end + 8'hf5: begin outq = 10'h25e; end + 8'hf6: begin outq = 10'h032; end + 8'hf7: begin outq = 10'h2ef; end + 8'hf8: begin outq = 10'h02f; end + 8'hf9: begin outq = 10'h201; end + 8'hfa: begin outq = 10'h054; end + 8'hfb: begin outq = 10'h013; end + 8'hfc: begin outq = 10'h249; end + 8'hfd: begin outq = 10'h09a; end + 8'hfe: begin outq = 10'h012; end + 8'hff: begin outq = 10'h114; end + default: ; // No change endcase end endmodule diff --git a/test_regress/t/t_case_inside.v b/test_regress/t/t_case_inside.v index 49a70997b..f33993e3c 100644 --- a/test_regress/t/t_case_inside.v +++ b/test_regress/t/t_case_inside.v @@ -15,7 +15,7 @@ module t (/*AUTOARG*/ reg [63:0] crc; reg [63:0] sum; - reg out1; + reg out1; reg [4:0] out2; sub sub (.in(crc[23:0]), .out1(out1), .out2(out2)); @@ -27,16 +27,16 @@ module t (/*AUTOARG*/ crc <= {crc[62:0], crc[63] ^ crc[2] ^ crc[0]}; sum <= {sum[62:0], sum[63]^sum[2]^sum[0]} ^ {58'h0,out1,out2}; if (cyc==0) begin - // Setup - crc <= 64'h00000000_00000097; - sum <= 64'h0; + // Setup + crc <= 64'h00000000_00000097; + sum <= 64'h0; end else if (cyc==99) begin - $write("[%0t] cyc==%0d crc=%x sum=%x\n", $time, cyc, crc, sum); + $write("[%0t] cyc==%0d crc=%x sum=%x\n", $time, cyc, crc, sum); `define EXPECTED_SUM 64'h10204fa5567c8a4b - if (sum !== `EXPECTED_SUM) $stop; - $write("*-* All Finished *-*\n"); - $finish; + if (sum !== `EXPECTED_SUM) $stop; + $write("*-* All Finished *-*\n"); + $finish; end end @@ -50,17 +50,17 @@ module sub (/*AUTOARG*/ ); input [23:0] in; - output reg out1; + output reg out1; output reg [4:0] out2; always @* begin case (in[3:0]) inside - default: {out1,out2} = {1'b0,5'h0F}; // Note not last item - 4'h1, 4'h2, 4'h3: {out1,out2} = {1'b1,5'h01}; - 4'h4: {out1,out2} = {1'b1,5'h04}; - [4'h6:4'h5]: {out1,out2} = {1'b1,5'h05}; // order backwards, will not match - 4'b100?:/*8,9*/ {out1,out2} = {1'b1,5'h08}; - [4'hc:4'hf]: {out1,out2} = {1'b1,5'h0C}; + default: {out1,out2} = {1'b0,5'h0F}; // Note not last item + 4'h1, 4'h2, 4'h3: {out1,out2} = {1'b1,5'h01}; + 4'h4: {out1,out2} = {1'b1,5'h04}; + [4'h6:4'h5]: {out1,out2} = {1'b1,5'h05}; // order backwards, will not match + 4'b100?:/*8,9*/ {out1,out2} = {1'b1,5'h08}; + [4'hc:4'hf]: {out1,out2} = {1'b1,5'h0C}; endcase end diff --git a/test_regress/t/t_case_itemwidth.v b/test_regress/t/t_case_itemwidth.v index 67385ac9a..921a7bb51 100644 --- a/test_regress/t/t_case_itemwidth.v +++ b/test_regress/t/t_case_itemwidth.v @@ -22,66 +22,66 @@ module t (/*AUTOARG*/ reg [2:0] wrapcheck_b; test test (/*AUTOINST*/ - // Outputs - .data (data[7:0]), - // Inputs - .addr (addr[6:0]), - .e0 (e0[6:0]), - .e1 (e1[5:0]), - .e2 (e2[5:0])); + // Outputs + .data (data[7:0]), + // Inputs + .addr (addr[6:0]), + .e0 (e0[6:0]), + .e1 (e1[5:0]), + .e2 (e2[5:0])); always @(/*AS*/addr) begin case(addr[2:0]) - 3'd0+3'd0: wrapcheck_a = 3'h0; - 3'd0+3'd1: wrapcheck_a = 3'h1; - 3'd0+3'd2: wrapcheck_a = 3'h2; - 3'd0+3'd3: wrapcheck_a = 3'h3; - default: wrapcheck_a = 3'h4; + 3'd0+3'd0: wrapcheck_a = 3'h0; + 3'd0+3'd1: wrapcheck_a = 3'h1; + 3'd0+3'd2: wrapcheck_a = 3'h2; + 3'd0+3'd3: wrapcheck_a = 3'h3; + default: wrapcheck_a = 3'h4; endcase case(addr[2:0]) - 3'd0+0: wrapcheck_b = 3'h0; - 3'd1+1: wrapcheck_b = 3'h1; - 3'd2+2: wrapcheck_b = 3'h2; - 3'd3+3: wrapcheck_b = 3'h3; - default: wrapcheck_b = 3'h4; + 3'd0+0: wrapcheck_b = 3'h0; + 3'd1+1: wrapcheck_b = 3'h1; + 3'd2+2: wrapcheck_b = 3'h2; + 3'd3+3: wrapcheck_b = 3'h3; + default: wrapcheck_b = 3'h4; endcase end integer cyc; initial cyc=1; always @ (posedge clk) begin if (cyc!=0) begin - cyc <= cyc + 1; - //$write("%d %x %x %x\n", cyc, data, wrapcheck_a, wrapcheck_b); - if (cyc==1) begin - addr <= 7'h28; - e0 <= 7'h11; - e1 <= 6'h02; - e2 <= 6'h03; - end - if (cyc==2) begin - addr <= 7'h2b; - if (data != 8'h11) $stop; - end - if (cyc==3) begin - addr <= 7'h2c; - if (data != 8'h03) $stop; - if (wrapcheck_a != 3'h3) $stop; - if (wrapcheck_b != 3'h4) $stop; - end - if (cyc==4) begin - addr <= 7'h0; - if (data != 8'h00) $stop; - if (wrapcheck_a != 3'h4) $stop; - if (wrapcheck_b != 3'h2) $stop; - end - if (cyc==5) begin - if (data != 8'h00) $stop; - end - if (cyc==9) begin - $write("*-* All Finished *-*\n"); - $finish; - end + cyc <= cyc + 1; + //$write("%d %x %x %x\n", cyc, data, wrapcheck_a, wrapcheck_b); + if (cyc==1) begin + addr <= 7'h28; + e0 <= 7'h11; + e1 <= 6'h02; + e2 <= 6'h03; + end + if (cyc==2) begin + addr <= 7'h2b; + if (data != 8'h11) $stop; + end + if (cyc==3) begin + addr <= 7'h2c; + if (data != 8'h03) $stop; + if (wrapcheck_a != 3'h3) $stop; + if (wrapcheck_b != 3'h4) $stop; + end + if (cyc==4) begin + addr <= 7'h0; + if (data != 8'h00) $stop; + if (wrapcheck_a != 3'h4) $stop; + if (wrapcheck_b != 3'h2) $stop; + end + if (cyc==5) begin + if (data != 8'h00) $stop; + end + if (cyc==9) begin + $write("*-* All Finished *-*\n"); + $finish; + end end end @@ -97,23 +97,23 @@ module test (/*AUTOARG*/ addr, e0, e1, e2 ); - output [7:0] data; + output [7:0] data; - input [6:0] addr; - input [6:0] e0; - input [5:0] e1, e2; + input [6:0] addr; + input [6:0] e0; + input [5:0] e1, e2; - reg [7:0] data; + reg [7:0] data; always @(/*AS*/addr or e0 or e1 or e2) begin - case (addr) - `AI: data = {e0[6], 1'b0, e0[5:0]}; - `AI+1: data = e1; - `AI+2, - `AI+3: data = e2; - default: data = 0; - endcase + case (addr) + `AI: data = {e0[6], 1'b0, e0[5:0]}; + `AI+1: data = e1; + `AI+2, + `AI+3: data = e2; + default: data = 0; + endcase end endmodule diff --git a/test_regress/t/t_case_nest.v b/test_regress/t/t_case_nest.v index 024d1ebca..55be130de 100644 --- a/test_regress/t/t_case_nest.v +++ b/test_regress/t/t_case_nest.v @@ -15,7 +15,7 @@ module t (/*AUTOARG*/ reg [63:0] crc; reg [63:0] sum; - reg out1; + reg out1; sub sub (.in(crc[23:0]), .out1(out1)); always @ (posedge clk) begin @@ -26,12 +26,12 @@ module t (/*AUTOARG*/ crc <= {crc[62:0], crc[63] ^ crc[2] ^ crc[0]}; sum <= {sum[62:0], sum[63]^sum[2]^sum[0]} ^ {63'h0,out1}; if (cyc==1) begin - // Setup - crc <= 64'h00000000_00000097; - sum <= 64'h0; + // Setup + crc <= 64'h00000000_00000097; + sum <= 64'h0; end else if (cyc==90) begin - if (sum !== 64'h2e5cb972eb02b8a0) $stop; + if (sum !== 64'h2e5cb972eb02b8a0) $stop; end else if (cyc==91) begin end @@ -42,8 +42,8 @@ module t (/*AUTOARG*/ else if (cyc==94) begin end else if (cyc==99) begin - $write("*-* All Finished *-*\n"); - $finish; + $write("*-* All Finished *-*\n"); + $finish; end end @@ -63,48 +63,48 @@ module sub (/*AUTOARG*/ always @* begin casez (in[17:16]) - 2'b00: casez (in[2:0]) - 3'h0: out1[0] = in[0]^RANDOM[0]; - 3'h1: out1[0] = in[0]^RANDOM[1]; - 3'h2: out1[0] = in[0]^RANDOM[2]; - 3'h3: out1[0] = in[0]^RANDOM[3]; - 3'h4: out1[0] = in[0]^RANDOM[4]; - 3'h5: out1[0] = in[0]^RANDOM[5]; - 3'h6: out1[0] = in[0]^RANDOM[6]; - 3'h7: out1[0] = in[0]^RANDOM[7]; - endcase - 2'b01: casez (in[2:0]) - 3'h0: out1[0] = RANDOM[10]; - 3'h1: out1[0] = RANDOM[11]; - 3'h2: out1[0] = RANDOM[12]; - 3'h3: out1[0] = RANDOM[13]; - 3'h4: out1[0] = RANDOM[14]; - 3'h5: out1[0] = RANDOM[15]; - 3'h6: out1[0] = RANDOM[16]; - 3'h7: out1[0] = RANDOM[17]; - endcase - 2'b1?: casez (in[4]) - 1'b1: casez (in[2:0]) - 3'h0: out1[0] = RANDOM[20]; - 3'h1: out1[0] = RANDOM[21]; - 3'h2: out1[0] = RANDOM[22]; - 3'h3: out1[0] = RANDOM[23]; - 3'h4: out1[0] = RANDOM[24]; - 3'h5: out1[0] = RANDOM[25]; - 3'h6: out1[0] = RANDOM[26]; - 3'h7: out1[0] = RANDOM[27]; - endcase - 1'b0: casez (in[2:0]) - 3'h0: out1[0] = RANDOM[30]; - 3'h1: out1[0] = RANDOM[31]; - 3'h2: out1[0] = RANDOM[32]; - 3'h3: out1[0] = RANDOM[33]; - 3'h4: out1[0] = RANDOM[34]; - 3'h5: out1[0] = RANDOM[35]; - 3'h6: out1[0] = RANDOM[36]; - 3'h7: out1[0] = RANDOM[37]; - endcase - endcase + 2'b00: casez (in[2:0]) + 3'h0: out1[0] = in[0]^RANDOM[0]; + 3'h1: out1[0] = in[0]^RANDOM[1]; + 3'h2: out1[0] = in[0]^RANDOM[2]; + 3'h3: out1[0] = in[0]^RANDOM[3]; + 3'h4: out1[0] = in[0]^RANDOM[4]; + 3'h5: out1[0] = in[0]^RANDOM[5]; + 3'h6: out1[0] = in[0]^RANDOM[6]; + 3'h7: out1[0] = in[0]^RANDOM[7]; + endcase + 2'b01: casez (in[2:0]) + 3'h0: out1[0] = RANDOM[10]; + 3'h1: out1[0] = RANDOM[11]; + 3'h2: out1[0] = RANDOM[12]; + 3'h3: out1[0] = RANDOM[13]; + 3'h4: out1[0] = RANDOM[14]; + 3'h5: out1[0] = RANDOM[15]; + 3'h6: out1[0] = RANDOM[16]; + 3'h7: out1[0] = RANDOM[17]; + endcase + 2'b1?: casez (in[4]) + 1'b1: casez (in[2:0]) + 3'h0: out1[0] = RANDOM[20]; + 3'h1: out1[0] = RANDOM[21]; + 3'h2: out1[0] = RANDOM[22]; + 3'h3: out1[0] = RANDOM[23]; + 3'h4: out1[0] = RANDOM[24]; + 3'h5: out1[0] = RANDOM[25]; + 3'h6: out1[0] = RANDOM[26]; + 3'h7: out1[0] = RANDOM[27]; + endcase + 1'b0: casez (in[2:0]) + 3'h0: out1[0] = RANDOM[30]; + 3'h1: out1[0] = RANDOM[31]; + 3'h2: out1[0] = RANDOM[32]; + 3'h3: out1[0] = RANDOM[33]; + 3'h4: out1[0] = RANDOM[34]; + 3'h5: out1[0] = RANDOM[35]; + 3'h6: out1[0] = RANDOM[36]; + 3'h7: out1[0] = RANDOM[37]; + endcase + endcase endcase end diff --git a/test_regress/t/t_case_onehot.v b/test_regress/t/t_case_onehot.v index 35288267a..f555945d4 100644 --- a/test_regress/t/t_case_onehot.v +++ b/test_regress/t/t_case_onehot.v @@ -10,26 +10,26 @@ module t (/*AUTOARG*/ ); input clk; - integer cyc = 0; - reg [63:0] crc; - reg [63:0] sum; + integer cyc = 0; + reg [63:0] crc; + reg [63:0] sum; // Take CRC data and apply to testblock inputs wire [2:0] in = (crc[1:0]==0 ? 3'd0 - : crc[1:0]==0 ? 3'd1 - : crc[1:0]==0 ? 3'd2 : 3'd4); + : crc[1:0]==0 ? 3'd1 + : crc[1:0]==0 ? 3'd2 : 3'd4); /*AUTOWIRE*/ // Beginning of automatic wires (for undeclared instantiated-module outputs) - wire [31:0] out; // From test of Test.v + wire [31:0] out; // From test of Test.v // End of automatics Test test (/*AUTOINST*/ - // Outputs - .out (out[31:0]), - // Inputs - .clk (clk), - .in (in[2:0])); + // Outputs + .out (out[31:0]), + // Inputs + .clk (clk), + .in (in[2:0])); // Aggregate outputs into a single result vector wire [63:0] result = {32'h0, out}; @@ -43,23 +43,23 @@ module t (/*AUTOARG*/ crc <= {crc[62:0], crc[63] ^ crc[2] ^ crc[0]}; sum <= result ^ {sum[62:0], sum[63] ^ sum[2] ^ sum[0]}; if (cyc==0) begin - // Setup - crc <= 64'h5aef0c8d_d70a4497; - sum <= 64'h0; + // Setup + crc <= 64'h5aef0c8d_d70a4497; + sum <= 64'h0; end else if (cyc<10) begin - sum <= 64'h0; + sum <= 64'h0; end else if (cyc<90) begin end else if (cyc==99) begin - $write("[%0t] cyc==%0d crc=%x sum=%x\n", $time, cyc, crc, sum); - if (crc !== 64'hc77bb9b3784ea091) $stop; - // What checksum will we end up with (above print should match) + $write("[%0t] cyc==%0d crc=%x sum=%x\n", $time, cyc, crc, sum); + if (crc !== 64'hc77bb9b3784ea091) $stop; + // What checksum will we end up with (above print should match) `define EXPECTED_SUM 64'h704ca23e2a83e1c5 - if (sum !== `EXPECTED_SUM) $stop; - $write("*-* All Finished *-*\n"); - $finish; + if (sum !== `EXPECTED_SUM) $stop; + $write("*-* All Finished *-*\n"); + $finish; end end @@ -87,10 +87,10 @@ module Test (/*AUTOARG*/ always @(posedge clk) begin case (1'b1) // synopsys parallel_case - in[ST_0]: out <= 32'h1234; - in[ST_1]: out <= 32'h4356; - in[ST_2]: out <= 32'h9874; - default: out <= 32'h1; + in[ST_0]: out <= 32'h1234; + in[ST_1]: out <= 32'h4356; + in[ST_2]: out <= 32'h9874; + default: out <= 32'h1; endcase end endmodule diff --git a/test_regress/t/t_case_orig.v b/test_regress/t/t_case_orig.v index eb40b783b..cd0ca49f1 100644 --- a/test_regress/t/t_case_orig.v +++ b/test_regress/t/t_case_orig.v @@ -10,9 +10,9 @@ module t (/*AUTOARG*/ ); input clk; - reg _ranit; + reg _ranit; - reg rnd; + reg rnd; reg [2:0] a; reg [2:0] b; reg [31:0] wide; @@ -22,108 +22,108 @@ module t (/*AUTOARG*/ wire sigone1 = 1'b1; wire sigone2 = 1'b1; - reg ok; + reg ok; parameter [1:0] twounkn = 2'b?; // This gets extended to 2'b?? // Large case statements should be well optimizable. - reg [2:0] anot; + reg [2:0] anot; always @ (/*AS*/a) begin casez (a) - default: anot = 3'b001; - 3'd0: anot = 3'b111; - 3'd1: anot = 3'b110; - 3'd2: anot = 3'b101; - 3'd3: anot = 3'b101; - 3'd4: anot = 3'b011; - 3'd5: anot = 3'b010; - 3'd6: anot = 3'b001; // Same so folds with 7 + default: anot = 3'b001; + 3'd0: anot = 3'b111; + 3'd1: anot = 3'b110; + 3'd2: anot = 3'b101; + 3'd3: anot = 3'b101; + 3'd4: anot = 3'b011; + 3'd5: anot = 3'b010; + 3'd6: anot = 3'b001; // Same so folds with 7 endcase end always @ (posedge clk) begin if (!_ranit) begin - _ranit <= 1; - rnd <= 1; - $write("[%0t] t_case: Running\n", $time); - // - a = 3'b101; - b = 3'b111; - // verilator lint_off CASEX - casex (a) - default: $stop; - 3'bx1x: $stop; - 3'b100: $stop; - 3'bx01: ; - endcase - casez (a) - default: $stop; - 3'b?1?: $stop; - 3'b100: $stop; - 3'b?01: ; - endcase - casez (a) - default: $stop; - {1'b0, twounkn}: $stop; - {1'b1, twounkn}: ; - endcase - casez (b) - default: $stop; - {1'b0, twounkn}: $stop; - {1'b1, twounkn}: ; -// {1'b0, 2'b??}: $stop; -// {1'b1, 2'b??}: ; - endcase - case(a[0]) - default: ; - endcase - casex(a) - default: ; - 3'b?0?: ; - endcase - // verilator lint_off CASEX - //This is illegal, the default occurs before the statements. - //case(a[0]) - // default: $stop; - // 1'b1: ; - //endcase - // - wide = 32'h12345678; - casez (wide) - default: $stop; - 32'h12345677, - 32'h12345678, - 32'h12345679: ; - endcase - // - ok = 0; - casez ({sigone1,sigone2}) - //2'b10, 2'b01, 2'bXX: ; // verilator bails at this since in 2 state it can be true... - 2'b10, 2'b01: ; - 2'b00: ; - default: ok=1'b1; - endcase + _ranit <= 1; + rnd <= 1; + $write("[%0t] t_case: Running\n", $time); + // + a = 3'b101; + b = 3'b111; + // verilator lint_off CASEX + casex (a) + default: $stop; + 3'bx1x: $stop; + 3'b100: $stop; + 3'bx01: ; + endcase + casez (a) + default: $stop; + 3'b?1?: $stop; + 3'b100: $stop; + 3'b?01: ; + endcase + casez (a) + default: $stop; + {1'b0, twounkn}: $stop; + {1'b1, twounkn}: ; + endcase + casez (b) + default: $stop; + {1'b0, twounkn}: $stop; + {1'b1, twounkn}: ; +// {1'b0, 2'b??}: $stop; +// {1'b1, 2'b??}: ; + endcase + case(a[0]) + default: ; + endcase + casex(a) + default: ; + 3'b?0?: ; + endcase + // verilator lint_off CASEX + //This is illegal, the default occurs before the statements. + //case(a[0]) + // default: $stop; + // 1'b1: ; + //endcase + // + wide = 32'h12345678; + casez (wide) + default: $stop; + 32'h12345677, + 32'h12345678, + 32'h12345679: ; + endcase + // + ok = 0; + casez ({sigone1,sigone2}) + //2'b10, 2'b01, 2'bXX: ; // verilator bails at this since in 2 state it can be true... + 2'b10, 2'b01: ; + 2'b00: ; + default: ok=1'b1; + endcase if (ok !== 1'b1) $stop; - // + // - if (rnd) begin - $write(""); - end - // - $write("*-* All Finished *-*\n"); - $finish; + if (rnd) begin + $write(""); + end + // + $write("*-* All Finished *-*\n"); + $finish; end end // Check parameters in case statements - parameter ALU_DO_REGISTER = 3'h1; // input selected by reg addr. - parameter DSP_REGISTER_V = 6'h03; + parameter ALU_DO_REGISTER = 3'h1; // input selected by reg addr. + parameter DSP_REGISTER_V = 6'h03; - reg [2:0] alu_ctl_2s; // Delayed version of alu_ctl - reg [5:0] reg_addr_2s; // Delayed version of reg_addr - reg [7:0] ir_slave_2s; // Instruction Register delayed 2 phases - reg [15:10] f_tmp_2s; // Delayed copy of F - reg p00_2s; + reg [2:0] alu_ctl_2s; // Delayed version of alu_ctl + reg [5:0] reg_addr_2s; // Delayed version of reg_addr + reg [7:0] ir_slave_2s; // Instruction Register delayed 2 phases + reg [15:10] f_tmp_2s; // Delayed copy of F + reg p00_2s; initial begin alu_ctl_2s = 3'h1; @@ -131,16 +131,16 @@ module t (/*AUTOARG*/ ir_slave_2s= 0; f_tmp_2s= 0; casex ({alu_ctl_2s,reg_addr_2s, - ir_slave_2s[7],ir_slave_2s[5:4],ir_slave_2s[1:0], - f_tmp_2s[11:10]}) - default: p00_2s = 1'b0; - {ALU_DO_REGISTER,DSP_REGISTER_V,1'bx,2'bx,2'bx,2'bx}: p00_2s = 1'b1; + ir_slave_2s[7],ir_slave_2s[5:4],ir_slave_2s[1:0], + f_tmp_2s[11:10]}) + default: p00_2s = 1'b0; + {ALU_DO_REGISTER,DSP_REGISTER_V,1'bx,2'bx,2'bx,2'bx}: p00_2s = 1'b1; endcase if (1'b0) $display ("%x %x %x %x", alu_ctl_2s, ir_slave_2s, f_tmp_2s, p00_2s); //Prevent unused // case ({1'b1, 1'b1}) - default: $stop; - {1'b1, p00_2s}: ; + default: $stop; + {1'b1, p00_2s}: ; endcase end @@ -151,24 +151,24 @@ module t (/*AUTOARG*/ initial begin foo = {1'b0,1'b0,1'b0,1'b0,1'b0,7'h04,8'b0}; casez (foo) - default: $stop; - {1'b1,1'b?,1'b?,1'b?,1'b?,ANY_STATE,8'b?}: $stop; - {1'b?,1'b1,1'b?,1'b?,1'b?,7'h00,8'b?}: $stop; - {1'b?,1'b?,1'b1,1'b?,1'b?,7'h00,8'b?}: $stop; - {1'b?,1'b?,1'b?,1'b1,1'b?,7'h00,8'b?}: $stop; - {1'b?,1'b?,1'b?,1'b?,1'b?,7'h04,8'b?}: ; - {1'b?,1'b?,1'b?,1'b?,1'b?,7'h06,8'hdf}: $stop; - {1'b?,1'b?,1'b?,1'b?,1'b?,7'h06,8'h00}: $stop; + default: $stop; + {1'b1,1'b?,1'b?,1'b?,1'b?,ANY_STATE,8'b?}: $stop; + {1'b?,1'b1,1'b?,1'b?,1'b?,7'h00,8'b?}: $stop; + {1'b?,1'b?,1'b1,1'b?,1'b?,7'h00,8'b?}: $stop; + {1'b?,1'b?,1'b?,1'b1,1'b?,7'h00,8'b?}: $stop; + {1'b?,1'b?,1'b?,1'b?,1'b?,7'h04,8'b?}: ; + {1'b?,1'b?,1'b?,1'b?,1'b?,7'h06,8'hdf}: $stop; + {1'b?,1'b?,1'b?,1'b?,1'b?,7'h06,8'h00}: $stop; endcase end initial begin foo = 20'b1010; casex (foo[3:0]) - default: $stop; - 4'b0xxx, - 4'b100x, - 4'b11xx: $stop; - 4'b1010: ; + default: $stop; + 4'b0xxx, + 4'b100x, + 4'b11xx: $stop; + 4'b1010: ; endcase end initial begin @@ -176,10 +176,10 @@ module t (/*AUTOARG*/ ok = 1'b0; // Test of RANGE(CONCAT reductions... casex ({foo[3:2],foo[1:0],foo[3]}) - 5'bxx10x: begin ok=1'b0; foo=20'd1; ok=1'b1; end // Check multiple expressions - 5'bxx00x: $stop; - 5'bxx01x: $stop; - 5'bxx11x: $stop; + 5'bxx10x: begin ok=1'b0; foo=20'd1; ok=1'b1; end // Check multiple expressions + 5'bxx00x: $stop; + 5'bxx01x: $stop; + 5'bxx11x: $stop; endcase if (!ok) $stop; end diff --git a/test_regress/t/t_case_reducer.v b/test_regress/t/t_case_reducer.v index ab8f6eabe..bf55f5d2f 100644 --- a/test_regress/t/t_case_reducer.v +++ b/test_regress/t/t_case_reducer.v @@ -10,9 +10,9 @@ module t (/*AUTOARG*/ ); input clk; - integer cyc = 0; - reg [63:0] crc; - reg [63:0] sum; + integer cyc = 0; + reg [63:0] crc; + reg [63:0] sum; // Take CRC data and apply to testblock inputs wire [7:0] operand_a = crc[7:0]; @@ -20,16 +20,16 @@ module t (/*AUTOARG*/ /*AUTOWIRE*/ // Beginning of automatic wires (for undeclared instantiated-module outputs) - wire [6:0] out; // From test of Test.v + wire [6:0] out; // From test of Test.v // End of automatics Test test (/*AUTOINST*/ - // Outputs - .out (out[6:0]), - // Inputs - .clk (clk), - .operand_a (operand_a[7:0]), - .operand_b (operand_b[7:0])); + // Outputs + .out (out[6:0]), + // Inputs + .clk (clk), + .operand_a (operand_a[7:0]), + .operand_b (operand_b[7:0])); // Aggregate outputs into a single result vector wire [63:0] result = {57'h0, out}; @@ -43,23 +43,23 @@ module t (/*AUTOARG*/ crc <= {crc[62:0], crc[63] ^ crc[2] ^ crc[0]}; sum <= result ^ {sum[62:0], sum[63] ^ sum[2] ^ sum[0]}; if (cyc==0) begin - // Setup - crc <= 64'h5aef0c8d_d70a4497; - sum <= 64'h0; + // Setup + crc <= 64'h5aef0c8d_d70a4497; + sum <= 64'h0; end else if (cyc<10) begin - sum <= 64'h0; + sum <= 64'h0; end else if (cyc<90) begin end else if (cyc==99) begin - $write("[%0t] cyc==%0d crc=%x sum=%x\n", $time, cyc, crc, sum); - if (crc !== 64'hc77bb9b3784ea091) $stop; - // What checksum will we end up with (above print should match) + $write("[%0t] cyc==%0d crc=%x sum=%x\n", $time, cyc, crc, sum); + if (crc !== 64'hc77bb9b3784ea091) $stop; + // What checksum will we end up with (above print should match) `define EXPECTED_SUM 64'h8a78c2ec4946ac38 - if (sum !== `EXPECTED_SUM) $stop; - $write("*-* All Finished *-*\n"); - $finish; + if (sum !== `EXPECTED_SUM) $stop; + $write("*-* All Finished *-*\n"); + $finish; end end @@ -68,15 +68,15 @@ endmodule module Test ( // Inputs - input wire clk, + input wire clk, input wire [7:0] operand_a, // operand a input wire [7:0] operand_b, // operand b - // Outputs + // Outputs output wire [6:0] out ); - wire [6:0] clz_a; - wire [6:0] clz_b; + wire [6:0] clz_a; + wire [6:0] clz_b; clz u_clz_a ( diff --git a/test_regress/t/t_case_wild.v b/test_regress/t/t_case_wild.v index 171236ad5..ac8db4014 100644 --- a/test_regress/t/t_case_wild.v +++ b/test_regress/t/t_case_wild.v @@ -15,7 +15,7 @@ module t (/*AUTOARG*/ reg [63:0] crc; reg [63:0] sum; - reg out1; + reg out1; reg [4:0] out2; sub sub (.in(crc[23:0]), .out1(out1), .out2(out2)); @@ -25,12 +25,12 @@ module t (/*AUTOARG*/ crc <= {crc[62:0], crc[63] ^ crc[2] ^ crc[0]}; sum <= {sum[62:0], sum[63]^sum[2]^sum[0]} ^ {58'h0,out1,out2}; if (cyc==0) begin - // Setup - crc <= 64'h00000000_00000097; - sum <= 64'h0; + // Setup + crc <= 64'h00000000_00000097; + sum <= 64'h0; end else if (cyc==90) begin - if (sum !== 64'hf0afc2bfa78277c5) $stop; + if (sum !== 64'hf0afc2bfa78277c5) $stop; end else if (cyc==91) begin end @@ -41,8 +41,8 @@ module t (/*AUTOARG*/ else if (cyc==94) begin end else if (cyc==99) begin - $write("*-* All Finished *-*\n"); - $finish; + $write("*-* All Finished *-*\n"); + $finish; end end @@ -56,7 +56,7 @@ module sub (/*AUTOARG*/ ); input [23:0] in; - output reg out1; + output reg out1; output reg [4:0] out2; always @* begin @@ -64,32 +64,32 @@ module sub (/*AUTOARG*/ casez (in[0]) endcase casez (in) - 24'b0000_0000_0000_0000_0000_0000 : {out1,out2} = {1'b0,5'h00}; - 24'b????_????_????_????_????_???1 : {out1,out2} = {1'b1,5'h00}; - 24'b????_????_????_????_????_??10 : {out1,out2} = {1'b1,5'h01}; - 24'b????_????_????_????_????_?100 : {out1,out2} = {1'b1,5'h02}; - 24'b????_????_????_????_????_1000 : {out1,out2} = {1'b1,5'h03}; - 24'b????_????_????_????_???1_0000 : {out1,out2} = {1'b1,5'h04}; - 24'b????_????_????_????_??10_0000 : {out1,out2} = {1'b1,5'h05}; - 24'b????_????_????_????_?100_0000 : {out1,out2} = {1'b1,5'h06}; - 24'b????_????_????_????_1000_0000 : {out1,out2} = {1'b1,5'h07}; - // Same pattern, but reversed to test we work OK. - 24'b1000_0000_0000_0000_0000_0000 : {out1,out2} = {1'b1,5'h17}; - 24'b?100_0000_0000_0000_0000_0000 : {out1,out2} = {1'b1,5'h16}; - 24'b??10_0000_0000_0000_0000_0000 : {out1,out2} = {1'b1,5'h15}; - 24'b???1_0000_0000_0000_0000_0000 : {out1,out2} = {1'b1,5'h14}; - 24'b????_1000_0000_0000_0000_0000 : {out1,out2} = {1'b1,5'h13}; - 24'b????_?100_0000_0000_0000_0000 : {out1,out2} = {1'b1,5'h12}; - 24'b????_??10_0000_0000_0000_0000 : {out1,out2} = {1'b1,5'h11}; - 24'b????_???1_0000_0000_0000_0000 : {out1,out2} = {1'b1,5'h10}; - 24'b????_????_1000_0000_0000_0000 : {out1,out2} = {1'b1,5'h0f}; - 24'b????_????_?100_0000_0000_0000 : {out1,out2} = {1'b1,5'h0e}; - 24'b????_????_??10_0000_0000_0000 : {out1,out2} = {1'b1,5'h0d}; - 24'b????_????_???1_0000_0000_0000 : {out1,out2} = {1'b1,5'h0c}; - 24'b????_????_????_1000_0000_0000 : {out1,out2} = {1'b1,5'h0b}; - 24'b????_????_????_?100_0000_0000 : {out1,out2} = {1'b1,5'h0a}; - 24'b????_????_????_??10_0000_0000 : {out1,out2} = {1'b1,5'h09}; - 24'b????_????_????_???1_0000_0000 : {out1,out2} = {1'b1,5'h08}; + 24'b0000_0000_0000_0000_0000_0000 : {out1,out2} = {1'b0,5'h00}; + 24'b????_????_????_????_????_???1 : {out1,out2} = {1'b1,5'h00}; + 24'b????_????_????_????_????_??10 : {out1,out2} = {1'b1,5'h01}; + 24'b????_????_????_????_????_?100 : {out1,out2} = {1'b1,5'h02}; + 24'b????_????_????_????_????_1000 : {out1,out2} = {1'b1,5'h03}; + 24'b????_????_????_????_???1_0000 : {out1,out2} = {1'b1,5'h04}; + 24'b????_????_????_????_??10_0000 : {out1,out2} = {1'b1,5'h05}; + 24'b????_????_????_????_?100_0000 : {out1,out2} = {1'b1,5'h06}; + 24'b????_????_????_????_1000_0000 : {out1,out2} = {1'b1,5'h07}; + // Same pattern, but reversed to test we work OK. + 24'b1000_0000_0000_0000_0000_0000 : {out1,out2} = {1'b1,5'h17}; + 24'b?100_0000_0000_0000_0000_0000 : {out1,out2} = {1'b1,5'h16}; + 24'b??10_0000_0000_0000_0000_0000 : {out1,out2} = {1'b1,5'h15}; + 24'b???1_0000_0000_0000_0000_0000 : {out1,out2} = {1'b1,5'h14}; + 24'b????_1000_0000_0000_0000_0000 : {out1,out2} = {1'b1,5'h13}; + 24'b????_?100_0000_0000_0000_0000 : {out1,out2} = {1'b1,5'h12}; + 24'b????_??10_0000_0000_0000_0000 : {out1,out2} = {1'b1,5'h11}; + 24'b????_???1_0000_0000_0000_0000 : {out1,out2} = {1'b1,5'h10}; + 24'b????_????_1000_0000_0000_0000 : {out1,out2} = {1'b1,5'h0f}; + 24'b????_????_?100_0000_0000_0000 : {out1,out2} = {1'b1,5'h0e}; + 24'b????_????_??10_0000_0000_0000 : {out1,out2} = {1'b1,5'h0d}; + 24'b????_????_???1_0000_0000_0000 : {out1,out2} = {1'b1,5'h0c}; + 24'b????_????_????_1000_0000_0000 : {out1,out2} = {1'b1,5'h0b}; + 24'b????_????_????_?100_0000_0000 : {out1,out2} = {1'b1,5'h0a}; + 24'b????_????_????_??10_0000_0000 : {out1,out2} = {1'b1,5'h09}; + 24'b????_????_????_???1_0000_0000 : {out1,out2} = {1'b1,5'h08}; endcase end diff --git a/test_regress/t/t_case_write1_tasks.v b/test_regress/t/t_case_write1_tasks.v index 9a1a46669..be868734c 100644 --- a/test_regress/t/t_case_write1_tasks.v +++ b/test_regress/t/t_case_write1_tasks.v @@ -17,137 +17,137 @@ module t_case_write1_tasks (); inout [STRLEN*8:1] foobar; // verilator no_inline_task begin - case (rab[6:0]) - 7'h00 : foobar = {foobar, " 0"}; - 7'h01 : foobar = {foobar, " 1"}; - 7'h02 : foobar = {foobar, " 2"}; - 7'h03 : foobar = {foobar, " 3"}; - 7'h04 : foobar = {foobar, " 4"}; - 7'h05 : foobar = {foobar, " 5"}; - 7'h06 : foobar = {foobar, " 6"}; - 7'h07 : foobar = {foobar, " 7"}; - 7'h08 : foobar = {foobar, " 8"}; - 7'h09 : foobar = {foobar, " 9"}; - 7'h0a : foobar = {foobar, " 10"}; - 7'h0b : foobar = {foobar, " 11"}; - 7'h0c : foobar = {foobar, " 12"}; - 7'h0d : foobar = {foobar, " 13"}; - 7'h0e : foobar = {foobar, " 14"}; - 7'h0f : foobar = {foobar, " 15"}; - 7'h10 : foobar = {foobar, " 16"}; - 7'h11 : foobar = {foobar, " 17"}; - 7'h12 : foobar = {foobar, " 18"}; - 7'h13 : foobar = {foobar, " 19"}; - 7'h14 : foobar = {foobar, " 20"}; - 7'h15 : foobar = {foobar, " 21"}; - 7'h16 : foobar = {foobar, " 22"}; - 7'h17 : foobar = {foobar, " 23"}; - 7'h18 : foobar = {foobar, " 24"}; - 7'h19 : foobar = {foobar, " 25"}; - 7'h1a : foobar = {foobar, " 26"}; - 7'h1b : foobar = {foobar, " 27"}; - 7'h1c : foobar = {foobar, " 28"}; - 7'h1d : foobar = {foobar, " 29"}; - 7'h1e : foobar = {foobar, " 30"}; - 7'h1f : foobar = {foobar, " 31"}; - 7'h20 : foobar = {foobar, " 32"}; - 7'h21 : foobar = {foobar, " 33"}; - 7'h22 : foobar = {foobar, " 34"}; - 7'h23 : foobar = {foobar, " 35"}; - 7'h24 : foobar = {foobar, " 36"}; - 7'h25 : foobar = {foobar, " 37"}; - 7'h26 : foobar = {foobar, " 38"}; - 7'h27 : foobar = {foobar, " 39"}; - 7'h28 : foobar = {foobar, " 40"}; - 7'h29 : foobar = {foobar, " 41"}; - 7'h2a : foobar = {foobar, " 42"}; - 7'h2b : foobar = {foobar, " 43"}; - 7'h2c : foobar = {foobar, " 44"}; - 7'h2d : foobar = {foobar, " 45"}; - 7'h2e : foobar = {foobar, " 46"}; - 7'h2f : foobar = {foobar, " 47"}; - 7'h30 : foobar = {foobar, " 48"}; - 7'h31 : foobar = {foobar, " 49"}; - 7'h32 : foobar = {foobar, " 50"}; - 7'h33 : foobar = {foobar, " 51"}; - 7'h34 : foobar = {foobar, " 52"}; - 7'h35 : foobar = {foobar, " 53"}; - 7'h36 : foobar = {foobar, " 54"}; - 7'h37 : foobar = {foobar, " 55"}; - 7'h38 : foobar = {foobar, " 56"}; - 7'h39 : foobar = {foobar, " 57"}; - 7'h3a : foobar = {foobar, " 58"}; - 7'h3b : foobar = {foobar, " 59"}; - 7'h3c : foobar = {foobar, " 60"}; - 7'h3d : foobar = {foobar, " 61"}; - 7'h3e : foobar = {foobar, " 62"}; - 7'h3f : foobar = {foobar, " 63"}; - 7'h40 : foobar = {foobar, " 64"}; - 7'h41 : foobar = {foobar, " 65"}; - 7'h42 : foobar = {foobar, " 66"}; - 7'h43 : foobar = {foobar, " 67"}; - 7'h44 : foobar = {foobar, " 68"}; - 7'h45 : foobar = {foobar, " 69"}; - 7'h46 : foobar = {foobar, " 70"}; - 7'h47 : foobar = {foobar, " 71"}; - 7'h48 : foobar = {foobar, " 72"}; - 7'h49 : foobar = {foobar, " 73"}; - 7'h4a : foobar = {foobar, " 74"}; - 7'h4b : foobar = {foobar, " 75"}; - 7'h4c : foobar = {foobar, " 76"}; - 7'h4d : foobar = {foobar, " 77"}; - 7'h4e : foobar = {foobar, " 78"}; - 7'h4f : foobar = {foobar, " 79"}; - 7'h50 : foobar = {foobar, " 80"}; - 7'h51 : foobar = {foobar, " 81"}; - 7'h52 : foobar = {foobar, " 82"}; - 7'h53 : foobar = {foobar, " 83"}; - 7'h54 : foobar = {foobar, " 84"}; - 7'h55 : foobar = {foobar, " 85"}; - 7'h56 : foobar = {foobar, " 86"}; - 7'h57 : foobar = {foobar, " 87"}; - 7'h58 : foobar = {foobar, " 88"}; - 7'h59 : foobar = {foobar, " 89"}; - 7'h5a : foobar = {foobar, " 90"}; - 7'h5b : foobar = {foobar, " 91"}; - 7'h5c : foobar = {foobar, " 92"}; - 7'h5d : foobar = {foobar, " 93"}; - 7'h5e : foobar = {foobar, " 94"}; - 7'h5f : foobar = {foobar, " 95"}; - 7'h60 : foobar = {foobar, " 96"}; - 7'h61 : foobar = {foobar, " 97"}; - 7'h62 : foobar = {foobar, " 98"}; - 7'h63 : foobar = {foobar, " 99"}; - 7'h64 : foobar = {foobar, " 100"}; - 7'h65 : foobar = {foobar, " 101"}; - 7'h66 : foobar = {foobar, " 102"}; - 7'h67 : foobar = {foobar, " 103"}; - 7'h68 : foobar = {foobar, " 104"}; - 7'h69 : foobar = {foobar, " 105"}; - 7'h6a : foobar = {foobar, " 106"}; - 7'h6b : foobar = {foobar, " 107"}; - 7'h6c : foobar = {foobar, " 108"}; - 7'h6d : foobar = {foobar, " 109"}; - 7'h6e : foobar = {foobar, " 110"}; - 7'h6f : foobar = {foobar, " 111"}; - 7'h70 : foobar = {foobar, " 112"}; - 7'h71 : foobar = {foobar, " 113"}; - 7'h72 : foobar = {foobar, " 114"}; - 7'h73 : foobar = {foobar, " 115"}; - 7'h74 : foobar = {foobar, " 116"}; - 7'h75 : foobar = {foobar, " 117"}; - 7'h76 : foobar = {foobar, " 118"}; - 7'h77 : foobar = {foobar, " 119"}; - 7'h78 : foobar = {foobar, " 120"}; - 7'h79 : foobar = {foobar, " 121"}; - 7'h7a : foobar = {foobar, " 122"}; - 7'h7b : foobar = {foobar, " 123"}; - 7'h7c : foobar = {foobar, " 124"}; - 7'h7d : foobar = {foobar, " 125"}; - 7'h7e : foobar = {foobar, " 126"}; - 7'h7f : foobar = {foobar, " 127"}; - default:foobar = {foobar, " 128"}; - endcase + case (rab[6:0]) + 7'h00 : foobar = {foobar, " 0"}; + 7'h01 : foobar = {foobar, " 1"}; + 7'h02 : foobar = {foobar, " 2"}; + 7'h03 : foobar = {foobar, " 3"}; + 7'h04 : foobar = {foobar, " 4"}; + 7'h05 : foobar = {foobar, " 5"}; + 7'h06 : foobar = {foobar, " 6"}; + 7'h07 : foobar = {foobar, " 7"}; + 7'h08 : foobar = {foobar, " 8"}; + 7'h09 : foobar = {foobar, " 9"}; + 7'h0a : foobar = {foobar, " 10"}; + 7'h0b : foobar = {foobar, " 11"}; + 7'h0c : foobar = {foobar, " 12"}; + 7'h0d : foobar = {foobar, " 13"}; + 7'h0e : foobar = {foobar, " 14"}; + 7'h0f : foobar = {foobar, " 15"}; + 7'h10 : foobar = {foobar, " 16"}; + 7'h11 : foobar = {foobar, " 17"}; + 7'h12 : foobar = {foobar, " 18"}; + 7'h13 : foobar = {foobar, " 19"}; + 7'h14 : foobar = {foobar, " 20"}; + 7'h15 : foobar = {foobar, " 21"}; + 7'h16 : foobar = {foobar, " 22"}; + 7'h17 : foobar = {foobar, " 23"}; + 7'h18 : foobar = {foobar, " 24"}; + 7'h19 : foobar = {foobar, " 25"}; + 7'h1a : foobar = {foobar, " 26"}; + 7'h1b : foobar = {foobar, " 27"}; + 7'h1c : foobar = {foobar, " 28"}; + 7'h1d : foobar = {foobar, " 29"}; + 7'h1e : foobar = {foobar, " 30"}; + 7'h1f : foobar = {foobar, " 31"}; + 7'h20 : foobar = {foobar, " 32"}; + 7'h21 : foobar = {foobar, " 33"}; + 7'h22 : foobar = {foobar, " 34"}; + 7'h23 : foobar = {foobar, " 35"}; + 7'h24 : foobar = {foobar, " 36"}; + 7'h25 : foobar = {foobar, " 37"}; + 7'h26 : foobar = {foobar, " 38"}; + 7'h27 : foobar = {foobar, " 39"}; + 7'h28 : foobar = {foobar, " 40"}; + 7'h29 : foobar = {foobar, " 41"}; + 7'h2a : foobar = {foobar, " 42"}; + 7'h2b : foobar = {foobar, " 43"}; + 7'h2c : foobar = {foobar, " 44"}; + 7'h2d : foobar = {foobar, " 45"}; + 7'h2e : foobar = {foobar, " 46"}; + 7'h2f : foobar = {foobar, " 47"}; + 7'h30 : foobar = {foobar, " 48"}; + 7'h31 : foobar = {foobar, " 49"}; + 7'h32 : foobar = {foobar, " 50"}; + 7'h33 : foobar = {foobar, " 51"}; + 7'h34 : foobar = {foobar, " 52"}; + 7'h35 : foobar = {foobar, " 53"}; + 7'h36 : foobar = {foobar, " 54"}; + 7'h37 : foobar = {foobar, " 55"}; + 7'h38 : foobar = {foobar, " 56"}; + 7'h39 : foobar = {foobar, " 57"}; + 7'h3a : foobar = {foobar, " 58"}; + 7'h3b : foobar = {foobar, " 59"}; + 7'h3c : foobar = {foobar, " 60"}; + 7'h3d : foobar = {foobar, " 61"}; + 7'h3e : foobar = {foobar, " 62"}; + 7'h3f : foobar = {foobar, " 63"}; + 7'h40 : foobar = {foobar, " 64"}; + 7'h41 : foobar = {foobar, " 65"}; + 7'h42 : foobar = {foobar, " 66"}; + 7'h43 : foobar = {foobar, " 67"}; + 7'h44 : foobar = {foobar, " 68"}; + 7'h45 : foobar = {foobar, " 69"}; + 7'h46 : foobar = {foobar, " 70"}; + 7'h47 : foobar = {foobar, " 71"}; + 7'h48 : foobar = {foobar, " 72"}; + 7'h49 : foobar = {foobar, " 73"}; + 7'h4a : foobar = {foobar, " 74"}; + 7'h4b : foobar = {foobar, " 75"}; + 7'h4c : foobar = {foobar, " 76"}; + 7'h4d : foobar = {foobar, " 77"}; + 7'h4e : foobar = {foobar, " 78"}; + 7'h4f : foobar = {foobar, " 79"}; + 7'h50 : foobar = {foobar, " 80"}; + 7'h51 : foobar = {foobar, " 81"}; + 7'h52 : foobar = {foobar, " 82"}; + 7'h53 : foobar = {foobar, " 83"}; + 7'h54 : foobar = {foobar, " 84"}; + 7'h55 : foobar = {foobar, " 85"}; + 7'h56 : foobar = {foobar, " 86"}; + 7'h57 : foobar = {foobar, " 87"}; + 7'h58 : foobar = {foobar, " 88"}; + 7'h59 : foobar = {foobar, " 89"}; + 7'h5a : foobar = {foobar, " 90"}; + 7'h5b : foobar = {foobar, " 91"}; + 7'h5c : foobar = {foobar, " 92"}; + 7'h5d : foobar = {foobar, " 93"}; + 7'h5e : foobar = {foobar, " 94"}; + 7'h5f : foobar = {foobar, " 95"}; + 7'h60 : foobar = {foobar, " 96"}; + 7'h61 : foobar = {foobar, " 97"}; + 7'h62 : foobar = {foobar, " 98"}; + 7'h63 : foobar = {foobar, " 99"}; + 7'h64 : foobar = {foobar, " 100"}; + 7'h65 : foobar = {foobar, " 101"}; + 7'h66 : foobar = {foobar, " 102"}; + 7'h67 : foobar = {foobar, " 103"}; + 7'h68 : foobar = {foobar, " 104"}; + 7'h69 : foobar = {foobar, " 105"}; + 7'h6a : foobar = {foobar, " 106"}; + 7'h6b : foobar = {foobar, " 107"}; + 7'h6c : foobar = {foobar, " 108"}; + 7'h6d : foobar = {foobar, " 109"}; + 7'h6e : foobar = {foobar, " 110"}; + 7'h6f : foobar = {foobar, " 111"}; + 7'h70 : foobar = {foobar, " 112"}; + 7'h71 : foobar = {foobar, " 113"}; + 7'h72 : foobar = {foobar, " 114"}; + 7'h73 : foobar = {foobar, " 115"}; + 7'h74 : foobar = {foobar, " 116"}; + 7'h75 : foobar = {foobar, " 117"}; + 7'h76 : foobar = {foobar, " 118"}; + 7'h77 : foobar = {foobar, " 119"}; + 7'h78 : foobar = {foobar, " 120"}; + 7'h79 : foobar = {foobar, " 121"}; + 7'h7a : foobar = {foobar, " 122"}; + 7'h7b : foobar = {foobar, " 123"}; + 7'h7c : foobar = {foobar, " 124"}; + 7'h7d : foobar = {foobar, " 125"}; + 7'h7e : foobar = {foobar, " 126"}; + 7'h7f : foobar = {foobar, " 127"}; + default:foobar = {foobar, " 128"}; + endcase end endtask @@ -157,13 +157,13 @@ module t_case_write1_tasks (); inout [STRLEN*8: 1] foobar; // verilator no_inline_task begin - case (rb[5:0]) - 6'h10, - 6'h17, - 6'h1e, - 6'h1f: foobar = {foobar, " 129"}; - default: ozonerab({1'b1, rb}, foobar); - endcase + case (rb[5:0]) + 6'h10, + 6'h17, + 6'h1e, + 6'h1f: foobar = {foobar, " 129"}; + default: ozonerab({1'b1, rb}, foobar); + endcase end endtask @@ -173,44 +173,44 @@ module t_case_write1_tasks (); inout [STRLEN*8: 1] foobar; // verilator no_inline_task begin - case (foo) - 2'h0 : + case (foo) + 2'h0 : begin - skyway({4{im16[15]}}, foobar); - skyway({4{im16[15]}}, foobar); - skyway(im16[15:12], foobar); - skyway(im16[11: 8], foobar); - skyway(im16[ 7: 4], foobar); - skyway(im16[ 3:0], foobar); - foobar = {foobar, " 130"}; + skyway({4{im16[15]}}, foobar); + skyway({4{im16[15]}}, foobar); + skyway(im16[15:12], foobar); + skyway(im16[11: 8], foobar); + skyway(im16[ 7: 4], foobar); + skyway(im16[ 3:0], foobar); + foobar = {foobar, " 130"}; end - 2'h1 : + 2'h1 : begin - foobar = {foobar, " 131"}; - skyway(im16[15:12], foobar); - skyway(im16[11: 8], foobar); - skyway(im16[ 7: 4], foobar); - skyway(im16[ 3:0], foobar); + foobar = {foobar, " 131"}; + skyway(im16[15:12], foobar); + skyway(im16[11: 8], foobar); + skyway(im16[ 7: 4], foobar); + skyway(im16[ 3:0], foobar); end - 2'h2 : + 2'h2 : begin - skyway({4{im16[15]}}, foobar); - skyway({4{im16[15]}}, foobar); - skyway(im16[15:12], foobar); - skyway(im16[11: 8], foobar); - skyway(im16[ 7: 4], foobar); - skyway(im16[ 3:0], foobar); - foobar = {foobar, " 132"}; + skyway({4{im16[15]}}, foobar); + skyway({4{im16[15]}}, foobar); + skyway(im16[15:12], foobar); + skyway(im16[11: 8], foobar); + skyway(im16[ 7: 4], foobar); + skyway(im16[ 3:0], foobar); + foobar = {foobar, " 132"}; end - 2'h3 : + 2'h3 : begin - foobar = {foobar, " 133"}; - skyway(im16[15:12], foobar); - skyway(im16[11: 8], foobar); - skyway(im16[ 7: 4], foobar); - skyway(im16[ 3:0], foobar); + foobar = {foobar, " 133"}; + skyway(im16[15:12], foobar); + skyway(im16[11: 8], foobar); + skyway(im16[ 7: 4], foobar); + skyway(im16[ 3:0], foobar); end - endcase + endcase end endtask @@ -219,24 +219,24 @@ module t_case_write1_tasks (); inout [STRLEN*8: 1] foobar; // verilator no_inline_task begin - case (hex) - 4'h0 : foobar = {foobar, " 134"}; - 4'h1 : foobar = {foobar, " 135"}; - 4'h2 : foobar = {foobar, " 136"}; - 4'h3 : foobar = {foobar, " 137"}; - 4'h4 : foobar = {foobar, " 138"}; - 4'h5 : foobar = {foobar, " 139"}; - 4'h6 : foobar = {foobar, " 140"}; - 4'h7 : foobar = {foobar, " 141"}; - 4'h8 : foobar = {foobar, " 142"}; - 4'h9 : foobar = {foobar, " 143"}; - 4'ha : foobar = {foobar, " 144"}; - 4'hb : foobar = {foobar, " 145"}; - 4'hc : foobar = {foobar, " 146"}; - 4'hd : foobar = {foobar, " 147"}; - 4'he : foobar = {foobar, " 148"}; - 4'hf : foobar = {foobar, " 149"}; - endcase + case (hex) + 4'h0 : foobar = {foobar, " 134"}; + 4'h1 : foobar = {foobar, " 135"}; + 4'h2 : foobar = {foobar, " 136"}; + 4'h3 : foobar = {foobar, " 137"}; + 4'h4 : foobar = {foobar, " 138"}; + 4'h5 : foobar = {foobar, " 139"}; + 4'h6 : foobar = {foobar, " 140"}; + 4'h7 : foobar = {foobar, " 141"}; + 4'h8 : foobar = {foobar, " 142"}; + 4'h9 : foobar = {foobar, " 143"}; + 4'ha : foobar = {foobar, " 144"}; + 4'hb : foobar = {foobar, " 145"}; + 4'hc : foobar = {foobar, " 146"}; + 4'hd : foobar = {foobar, " 147"}; + 4'he : foobar = {foobar, " 148"}; + 4'hf : foobar = {foobar, " 149"}; + endcase end endtask @@ -245,16 +245,16 @@ module t_case_write1_tasks (); inout [STRLEN*8: 1] foobar; // verilator no_inline_task begin - case (foo[11: 9]) - 3'h0 : foobar = {foobar, " 158"}; - 3'h1 : foobar = {foobar, " 159"}; - 3'h2 : foobar = {foobar, " 160"}; - 3'h3 : foobar = {foobar, " 161"}; - 3'h4 : foobar = {foobar, " 162"}; - 3'h5 : foobar = {foobar, " 163"}; - 3'h6 : foobar = {foobar, " 164"}; - 3'h7 : foobar = {foobar, " 165"}; - endcase + case (foo[11: 9]) + 3'h0 : foobar = {foobar, " 158"}; + 3'h1 : foobar = {foobar, " 159"}; + 3'h2 : foobar = {foobar, " 160"}; + 3'h3 : foobar = {foobar, " 161"}; + 3'h4 : foobar = {foobar, " 162"}; + 3'h5 : foobar = {foobar, " 163"}; + 3'h6 : foobar = {foobar, " 164"}; + 3'h7 : foobar = {foobar, " 165"}; + endcase end endtask @@ -263,10 +263,10 @@ module t_case_write1_tasks (); inout [STRLEN*8: 1] foobar; // verilator no_inline_task begin - if (k) - foobar = {foobar, " 166"}; - else - foobar = {foobar, " 167"}; + if (k) + foobar = {foobar, " 166"}; + else + foobar = {foobar, " 167"}; end endtask @@ -275,16 +275,16 @@ module t_case_write1_tasks (); inout [STRLEN*8: 1] foobar; // verilator no_inline_task begin - case (ae) - 3'b000 : foobar = {foobar, " 168"}; - 3'b001 : foobar = {foobar, " 169"}; - 3'b010 : foobar = {foobar, " 170"}; - 3'b011 : foobar = {foobar, " 171"}; - 3'b100 : foobar = {foobar, " 172"}; - 3'b101 : foobar = {foobar, " 173"}; - 3'b110 : foobar = {foobar, " 174"}; - 3'b111 : foobar = {foobar, " 175"}; - endcase + case (ae) + 3'b000 : foobar = {foobar, " 168"}; + 3'b001 : foobar = {foobar, " 169"}; + 3'b010 : foobar = {foobar, " 170"}; + 3'b011 : foobar = {foobar, " 171"}; + 3'b100 : foobar = {foobar, " 172"}; + 3'b101 : foobar = {foobar, " 173"}; + 3'b110 : foobar = {foobar, " 174"}; + 3'b111 : foobar = {foobar, " 175"}; + endcase end endtask @@ -293,16 +293,16 @@ module t_case_write1_tasks (); inout [STRLEN*8: 1] foobar; // verilator no_inline_task begin - case (aee) - 3'b001, - 3'b011, - 3'b101, - 3'b111 : foobar = {foobar, " 176"}; - 3'b000 : foobar = {foobar, " 177"}; - 3'b010 : foobar = {foobar, " 178"}; - 3'b100 : foobar = {foobar, " 179"}; - 3'b110 : foobar = {foobar, " 180"}; - endcase + case (aee) + 3'b001, + 3'b011, + 3'b101, + 3'b111 : foobar = {foobar, " 176"}; + 3'b000 : foobar = {foobar, " 177"}; + 3'b010 : foobar = {foobar, " 178"}; + 3'b100 : foobar = {foobar, " 179"}; + 3'b110 : foobar = {foobar, " 180"}; + endcase end endtask @@ -311,16 +311,16 @@ module t_case_write1_tasks (); inout [STRLEN*8: 1] foobar; // verilator no_inline_task begin - case (ape) - 3'b001, - 3'b011, - 3'b101, - 3'b111 : foobar = {foobar, " 181"}; - 3'b000 : foobar = {foobar, " 182"}; - 3'b010 : foobar = {foobar, " 183"}; - 3'b100 : foobar = {foobar, " 184"}; - 3'b110 : foobar = {foobar, " 185"}; - endcase + case (ape) + 3'b001, + 3'b011, + 3'b101, + 3'b111 : foobar = {foobar, " 181"}; + 3'b000 : foobar = {foobar, " 182"}; + 3'b010 : foobar = {foobar, " 183"}; + 3'b100 : foobar = {foobar, " 184"}; + 3'b110 : foobar = {foobar, " 185"}; + endcase end endtask @@ -329,98 +329,98 @@ module t_case_write1_tasks (); inout [STRLEN*8: 1] foobar; // verilator no_inline_task begin - case (foo[24:21]) - 4'h0 : + case (foo[24:21]) + 4'h0 : if (foo[26]) foobar = {foobar, " 186"}; else foobar = {foobar, " 187"}; - 4'h1 : + 4'h1 : case (foo[26:25]) 2'b00 : foobar = {foobar, " 188"}; 2'b01 : foobar = {foobar, " 189"}; 2'b10 : foobar = {foobar, " 190"}; 2'b11 : foobar = {foobar, " 191"}; endcase - 4'h2 : foobar = {foobar, " 192"}; - 4'h3 : + 4'h2 : foobar = {foobar, " 192"}; + 4'h3 : case (foo[26:25]) 2'b00 : foobar = {foobar, " 193"}; 2'b01 : foobar = {foobar, " 194"}; 2'b10 : foobar = {foobar, " 195"}; 2'b11 : foobar = {foobar, " 196"}; endcase - 4'h4 : + 4'h4 : if (foo[26]) foobar = {foobar, " 197"}; else foobar = {foobar, " 198"}; - 4'h5 : + 4'h5 : case (foo[26:25]) 2'b00 : foobar = {foobar, " 199"}; 2'b01 : foobar = {foobar, " 200"}; 2'b10 : foobar = {foobar, " 201"}; 2'b11 : foobar = {foobar, " 202"}; endcase - 4'h6 : foobar = {foobar, " 203"}; - 4'h7 : + 4'h6 : foobar = {foobar, " 203"}; + 4'h7 : case (foo[26:25]) 2'b00 : foobar = {foobar, " 204"}; 2'b01 : foobar = {foobar, " 205"}; 2'b10 : foobar = {foobar, " 206"}; 2'b11 : foobar = {foobar, " 207"}; endcase - 4'h8 : + 4'h8 : case (foo[26:25]) 2'b00 : foobar = {foobar, " 208"}; 2'b01 : foobar = {foobar, " 209"}; 2'b10 : foobar = {foobar, " 210"}; 2'b11 : foobar = {foobar, " 211"}; endcase - 4'h9 : + 4'h9 : case (foo[26:25]) 2'b00 : foobar = {foobar, " 212"}; 2'b01 : foobar = {foobar, " 213"}; 2'b10 : foobar = {foobar, " 214"}; 2'b11 : foobar = {foobar, " 215"}; endcase - 4'ha : + 4'ha : if (foo[25]) foobar = {foobar, " 216"}; else foobar = {foobar, " 217"}; - 4'hb : + 4'hb : if (foo[25]) foobar = {foobar, " 218"}; else foobar = {foobar, " 219"}; - 4'hc : + 4'hc : if (foo[26]) foobar = {foobar, " 220"}; else foobar = {foobar, " 221"}; - 4'hd : + 4'hd : case (foo[26:25]) 2'b00 : foobar = {foobar, " 222"}; 2'b01 : foobar = {foobar, " 223"}; 2'b10 : foobar = {foobar, " 224"}; 2'b11 : foobar = {foobar, " 225"}; endcase - 4'he : + 4'he : case (foo[26:25]) 2'b00 : foobar = {foobar, " 226"}; 2'b01 : foobar = {foobar, " 227"}; 2'b10 : foobar = {foobar, " 228"}; 2'b11 : foobar = {foobar, " 229"}; endcase - 4'hf : + 4'hf : case (foo[26:25]) 2'b00 : foobar = {foobar, " 230"}; 2'b01 : foobar = {foobar, " 231"}; 2'b10 : foobar = {foobar, " 232"}; 2'b11 : foobar = {foobar, " 233"}; endcase - endcase + endcase end endtask @@ -429,1131 +429,1131 @@ module t_case_write1_tasks (); inout [STRLEN*8: 1] foobar; // verilator no_inline_task begin - case (foo[27:21]) - 7'h00: - begin - ozoneae(foo[20:18], foobar); - foobar = {foobar," 234"}; - foobar = {foobar, " 235"}; - end - 7'h01: - begin - ozoneae(foo[20:18], foobar); - foobar = {foobar," 236"}; - ozoneae(foo[17:15], foobar); - foobar = {foobar," 237"}; - foobar = {foobar, " 238"}; - end - 7'h02: - foobar = {foobar, " 239"}; - 7'h03: - begin - ozoneae(foo[20:18], foobar); - foobar = {foobar," 240"}; - ozoneae(foo[17:15], foobar); - foobar = {foobar," 241"}; - foobar = {foobar, " 242"}; - end - 7'h04: - begin - ozoneae(foo[20:18], foobar); - foobar = {foobar," 243"}; - foobar = {foobar," 244"}; - end - 7'h05: - begin - ozoneae(foo[20:18], foobar); - foobar = {foobar," 245"}; - ozoneae(foo[17:15], foobar); - foobar = {foobar," 246"}; - end - 7'h06: - foobar = {foobar, " 247"}; - 7'h07: - begin - ozoneae(foo[20:18], foobar); - foobar = {foobar," 248"}; - ozoneae(foo[17:15], foobar); - foobar = {foobar," 249"}; - end - 7'h08: - begin - ozoneae(foo[20:18], foobar); - foobar = {foobar," 250"}; - ozoneae(foo[17:15], foobar); - foobar = {foobar," 251"}; - end - 7'h09: - begin - ozoneae(foo[20:18], foobar); - foobar = {foobar," 252"}; - ozoneae(foo[17:15], foobar); - foobar = {foobar," 253"}; - end - 7'h0a: - begin - ozoneae(foo[17:15], foobar); - foobar = {foobar," 254"}; - end - 7'h0b: - begin - ozoneae(foo[17:15], foobar); - foobar = {foobar," 255"}; - end - 7'h0c: - begin - ozoneae(foo[20:18], foobar); - foobar = {foobar," 256"}; - end - 7'h0d: - begin - ozoneae(foo[20:18], foobar); - foobar = {foobar," 257"}; - ozoneae(foo[17:15], foobar); - foobar = {foobar," 258"}; - end - 7'h0e: - begin - ozoneae(foo[20:18], foobar); - foobar = {foobar," 259"}; - ozoneae(foo[17:15], foobar); - foobar = {foobar," 260"}; - end - 7'h0f: - begin - ozoneae(foo[20:18], foobar); - foobar = {foobar," 261"}; - ozoneae(foo[17:15], foobar); - foobar = {foobar," 262"}; - end - 7'h10: - begin - ozoneae(foo[20:18], foobar); - foobar = {foobar," 263"}; - ozoneae(foo[17:15], foobar); - foobar = {foobar," 264"}; - foobar = {foobar, " 265"}; - foobar = {foobar, " 266"}; - end - 7'h11: - begin - ozoneae(foo[20:18], foobar); - foobar = {foobar," 267"}; - ozoneae(foo[17:15], foobar); - foobar = {foobar," 268"}; - foobar = {foobar, " 269"}; - foobar = {foobar, " 270"}; - end - 7'h12: - begin - ozoneae(foo[20:18], foobar); - foobar = {foobar," 271"}; - ozoneae(foo[17:15], foobar); - foobar = {foobar," 272"}; - foobar = {foobar, " 273"}; - foobar = {foobar, " 274"}; - end - 7'h13: - begin - ozoneae(foo[20:18], foobar); - foobar = {foobar," 275"}; - ozoneae(foo[17:15], foobar); - foobar = {foobar," 276"}; - foobar = {foobar, " 277"}; - foobar = {foobar, " 278"}; - end - 7'h14: - begin - ozoneaee(foo[20:18], foobar); - foobar = {foobar," 279"}; - ozoneaee(foo[17:15], foobar); - foobar = {foobar," 280"}; - ozoneape(foo[20:18], foobar); - foobar = {foobar," 281"}; - ozoneape(foo[17:15], foobar); - foobar = {foobar," 282"}; - foobar = {foobar, " 283"}; - foobar = {foobar, " 284"}; - end - 7'h15: - begin - ozoneaee(foo[20:18], foobar); - foobar = {foobar," 285"}; - ozoneaee(foo[17:15], foobar); - foobar = {foobar," 286"}; - ozoneape(foo[20:18], foobar); - foobar = {foobar," 287"}; - ozoneape(foo[17:15], foobar); - foobar = {foobar," 288"}; - foobar = {foobar, " 289"}; - foobar = {foobar, " 290"}; - end - 7'h16: - begin - ozoneaee(foo[20:18], foobar); - foobar = {foobar," 291"}; - ozoneaee(foo[17:15], foobar); - foobar = {foobar," 292"}; - ozoneape(foo[20:18], foobar); - foobar = {foobar," 293"}; - ozoneape(foo[17:15], foobar); - foobar = {foobar," 294"}; - foobar = {foobar, " 295"}; - foobar = {foobar, " 296"}; - end - 7'h17: - begin - ozoneaee(foo[20:18], foobar); - foobar = {foobar," 297"}; - ozoneaee(foo[17:15], foobar); - foobar = {foobar," 298"}; - ozoneape(foo[20:18], foobar); - foobar = {foobar," 299"}; - ozoneape(foo[17:15], foobar); - foobar = {foobar," 300"}; - foobar = {foobar, " 301"}; - foobar = {foobar, " 302"}; - end - 7'h18: - begin - ozoneae(foo[20:18], foobar); - foobar = {foobar," 303"}; - ozoneae(foo[17:15], foobar); - foobar = {foobar," 304"}; - foobar = {foobar, " 305"}; - foobar = {foobar, " 306"}; - end - 7'h19: - begin - ozoneae(foo[20:18], foobar); - foobar = {foobar," 307"}; - ozoneae(foo[17:15], foobar); - foobar = {foobar," 308"}; - foobar = {foobar, " 309"}; - foobar = {foobar, " 310"}; - end - 7'h1a: - begin - ozoneae(foo[20:18], foobar); - foobar = {foobar," 311"}; - ozoneae(foo[17:15], foobar); - foobar = {foobar," 312"}; - foobar = {foobar, " 313"}; - foobar = {foobar, " 314"}; - end - 7'h1b: - begin - ozoneae(foo[20:18], foobar); - foobar = {foobar," 315"}; - ozoneae(foo[17:15], foobar); - foobar = {foobar," 316"}; - foobar = {foobar, " 317"}; - foobar = {foobar, " 318"}; - end - 7'h1c: - begin - ozoneae(foo[20:18], foobar); - foobar = {foobar," 319"}; - ozoneae(foo[17:15], foobar); - foobar = {foobar," 320"}; - foobar = {foobar, " 321"}; - foobar = {foobar, " 322"}; - end - 7'h1d: - begin - ozoneae(foo[20:18], foobar); - foobar = {foobar," 323"}; - ozoneae(foo[17:15], foobar); - foobar = {foobar," 324"}; - foobar = {foobar, " 325"}; - foobar = {foobar, " 326"}; - end - 7'h1e: - begin - ozoneaee(foo[20:18], foobar); - foobar = {foobar," 327"}; - ozoneaee(foo[17:15], foobar); - foobar = {foobar," 328"}; - ozoneape(foo[20:18], foobar); - foobar = {foobar," 329"}; - ozoneape(foo[17:15], foobar); - foobar = {foobar," 330"}; - foobar = {foobar, " 331"}; - foobar = {foobar, " 332"}; - end - 7'h1f: - begin - ozoneaee(foo[20:18], foobar); - foobar = {foobar," 333"}; - ozoneaee(foo[17:15], foobar); - foobar = {foobar," 334"}; - ozoneape(foo[20:18], foobar); - foobar = {foobar," 335"}; - ozoneape(foo[17:15], foobar); - foobar = {foobar," 336"}; - foobar = {foobar, " 337"}; - foobar = {foobar, " 338"}; - end - 7'h20: - begin - ozoneaee(foo[20:18], foobar); - foobar = {foobar," 339"}; - ozoneaee(foo[17:15], foobar); - foobar = {foobar," 340"}; - ozoneape(foo[20:18], foobar); - foobar = {foobar," 341"}; - ozoneape(foo[17:15], foobar); - foobar = {foobar," 342"}; - foobar = {foobar, " 343"}; - foobar = {foobar, " 344"}; - end - 7'h21: - begin - ozoneaee(foo[20:18], foobar); - foobar = {foobar," 345"}; - ozoneaee(foo[17:15], foobar); - foobar = {foobar," 346"}; - ozoneape(foo[20:18], foobar); - foobar = {foobar," 347"}; - ozoneape(foo[17:15], foobar); - foobar = {foobar," 348"}; - foobar = {foobar, " 349"}; - foobar = {foobar, " 350"}; - end - 7'h22: - begin - ozoneae(foo[20:18], foobar); - foobar = {foobar," 351"}; - ozoneae(foo[17:15], foobar); - foobar = {foobar," 352"}; - foobar = {foobar, " 353"}; - foobar = {foobar, " 354"}; - end - 7'h23: - begin - ozoneae(foo[20:18], foobar); - foobar = {foobar," 355"}; - ozoneae(foo[17:15], foobar); - foobar = {foobar," 356"}; - foobar = {foobar, " 357"}; - foobar = {foobar, " 358"}; - end - 7'h24: - begin - ozoneae(foo[20:18], foobar); - foobar = {foobar," 359"}; - ozoneae(foo[17:15], foobar); - foobar = {foobar," 360"}; - foobar = {foobar, " 361"}; - foobar = {foobar, " 362"}; - end - 7'h25: - begin - ozoneae(foo[20:18], foobar); - foobar = {foobar," 363"}; - ozoneae(foo[17:15], foobar); - foobar = {foobar," 364"}; - foobar = {foobar, " 365"}; - foobar = {foobar, " 366"}; - end - 7'h26: - begin - ozoneae(foo[20:18], foobar); - foobar = {foobar," 367"}; - ozoneae(foo[17:15], foobar); - foobar = {foobar," 368"}; - foobar = {foobar, " 369"}; - foobar = {foobar, " 370"}; - end - 7'h27: - begin - ozoneae(foo[20:18], foobar); - foobar = {foobar," 371"}; - ozoneae(foo[17:15], foobar); - foobar = {foobar," 372"}; - foobar = {foobar, " 373"}; - foobar = {foobar, " 374"}; - end - 7'h28: - begin - ozoneaee(foo[20:18], foobar); - foobar = {foobar," 375"}; - ozoneaee(foo[17:15], foobar); - foobar = {foobar," 376"}; - ozoneape(foo[20:18], foobar); - foobar = {foobar," 377"}; - ozoneape(foo[17:15], foobar); - foobar = {foobar," 378"}; - foobar = {foobar, " 379"}; - foobar = {foobar, " 380"}; - end - 7'h29: - begin - ozoneaee(foo[20:18], foobar); - foobar = {foobar," 381"}; - ozoneaee(foo[17:15], foobar); - foobar = {foobar," 382"}; - ozoneape(foo[20:18], foobar); - foobar = {foobar," 383"}; - ozoneape(foo[17:15], foobar); - foobar = {foobar," 384"}; - foobar = {foobar, " 385"}; - foobar = {foobar, " 386"}; - end - 7'h2a: - begin - ozoneaee(foo[20:18], foobar); - foobar = {foobar," 387"}; - ozoneaee(foo[17:15], foobar); - foobar = {foobar," 388"}; - ozoneape(foo[20:18], foobar); - foobar = {foobar," 389"}; - ozoneape(foo[17:15], foobar); - foobar = {foobar," 390"}; - foobar = {foobar, " 391"}; - foobar = {foobar, " 392"}; - end - 7'h2b: - begin - ozoneaee(foo[20:18], foobar); - foobar = {foobar," 393"}; - ozoneaee(foo[17:15], foobar); - foobar = {foobar," 394"}; - ozoneape(foo[20:18], foobar); - foobar = {foobar," 395"}; - ozoneape(foo[17:15], foobar); - foobar = {foobar," 396"}; - foobar = {foobar, " 397"}; - foobar = {foobar, " 398"}; - end - 7'h2c: - begin - ozoneae(foo[20:18], foobar); - foobar = {foobar," 399"}; - ozoneae(foo[17:15], foobar); - foobar = {foobar," 400"}; - foobar = {foobar, " 401"}; - foobar = {foobar, " 402"}; - end - 7'h2d: - begin - ozoneae(foo[20:18], foobar); - foobar = {foobar," 403"}; - ozoneae(foo[17:15], foobar); - foobar = {foobar," 404"}; - foobar = {foobar, " 405"}; - foobar = {foobar, " 406"}; - end - 7'h2e: - begin - ozoneae(foo[20:18], foobar); - foobar = {foobar," 407"}; - ozoneae(foo[17:15], foobar); - foobar = {foobar," 408"}; - foobar = {foobar, " 409"}; - foobar = {foobar, " 410"}; - end - 7'h2f: - begin - ozoneae(foo[20:18], foobar); - foobar = {foobar," 411"}; - ozoneae(foo[17:15], foobar); - foobar = {foobar," 412"}; - foobar = {foobar, " 413"}; - foobar = {foobar, " 414"}; - end - 7'h30: - begin - ozoneae(foo[20:18], foobar); - foobar = {foobar," 415"}; - ozoneae(foo[17:15], foobar); - foobar = {foobar," 416"}; - foobar = {foobar, " 417"}; - foobar = {foobar, " 418"}; - end - 7'h31: - begin - ozoneae(foo[20:18], foobar); - foobar = {foobar," 419"}; - ozoneae(foo[17:15], foobar); - foobar = {foobar," 420"}; - foobar = {foobar, " 421"}; - foobar = {foobar, " 422"}; - end - 7'h32: - begin - ozoneaee(foo[20:18], foobar); - foobar = {foobar," 423"}; - ozoneaee(foo[17:15], foobar); - foobar = {foobar," 424"}; - ozoneape(foo[20:18], foobar); - foobar = {foobar," 425"}; - ozoneape(foo[17:15], foobar); - foobar = {foobar," 426"}; - foobar = {foobar, " 427"}; - foobar = {foobar, " 428"}; - end - 7'h33: - begin - ozoneaee(foo[20:18], foobar); - foobar = {foobar," 429"}; - ozoneaee(foo[17:15], foobar); - foobar = {foobar," 430"}; - ozoneape(foo[20:18], foobar); - foobar = {foobar," 431"}; - ozoneape(foo[17:15], foobar); - foobar = {foobar," 432"}; - foobar = {foobar, " 433"}; - foobar = {foobar, " 434"}; - end - 7'h34: - begin - ozoneaee(foo[20:18], foobar); - foobar = {foobar," 435"}; - ozoneaee(foo[17:15], foobar); - foobar = {foobar," 436"}; - ozoneape(foo[20:18], foobar); - foobar = {foobar," 437"}; - ozoneape(foo[17:15], foobar); - foobar = {foobar," 438"}; - foobar = {foobar, " 439"}; - foobar = {foobar, " 440"}; - end - 7'h35: - begin - ozoneaee(foo[20:18], foobar); - foobar = {foobar," 441"}; - ozoneaee(foo[17:15], foobar); - foobar = {foobar," 442"}; - ozoneape(foo[20:18], foobar); - foobar = {foobar," 443"}; - ozoneape(foo[17:15], foobar); - foobar = {foobar," 444"}; - foobar = {foobar, " 445"}; - foobar = {foobar, " 446"}; - end - 7'h36: - begin - ozoneae(foo[20:18], foobar); - foobar = {foobar," 447"}; - ozoneae(foo[17:15], foobar); - foobar = {foobar," 448"}; - foobar = {foobar, " 449"}; - foobar = {foobar, " 450"}; - end - 7'h37: - begin - ozoneae(foo[20:18], foobar); - foobar = {foobar," 451"}; - ozoneae(foo[17:15], foobar); - foobar = {foobar," 452"}; - foobar = {foobar, " 453"}; - foobar = {foobar, " 454"}; - end - 7'h38: - begin - ozoneae(foo[20:18], foobar); - foobar = {foobar," 455"}; - ozoneae(foo[17:15], foobar); - foobar = {foobar," 456"}; - foobar = {foobar, " 457"}; - end - 7'h39: - begin - ozoneae(foo[20:18], foobar); - foobar = {foobar," 458"}; - ozoneae(foo[17:15], foobar); - foobar = {foobar," 459"}; - foobar = {foobar, " 460"}; - end - 7'h3a: - begin - ozoneae(foo[20:18], foobar); - foobar = {foobar," 461"}; - ozoneae(foo[17:15], foobar); - foobar = {foobar," 462"}; - foobar = {foobar, " 463"}; - end - 7'h3b: - begin - ozoneae(foo[20:18], foobar); - foobar = {foobar," 464"}; - ozoneae(foo[17:15], foobar); - foobar = {foobar," 465"}; - foobar = {foobar, " 466"}; - end - 7'h3c: - begin - ozoneaee(foo[20:18], foobar); - foobar = {foobar," 467"}; - ozoneaee(foo[17:15], foobar); - foobar = {foobar," 468"}; - ozoneape(foo[20:18], foobar); - foobar = {foobar," 469"}; - ozoneape(foo[17:15], foobar); - foobar = {foobar," 470"}; - foobar = {foobar, " 471"}; - end - 7'h3d: - begin - ozoneaee(foo[20:18], foobar); - foobar = {foobar," 472"}; - ozoneaee(foo[17:15], foobar); - foobar = {foobar," 473"}; - ozoneape(foo[20:18], foobar); - foobar = {foobar," 474"}; - ozoneape(foo[17:15], foobar); - foobar = {foobar," 475"}; - foobar = {foobar, " 476"}; - end - 7'h3e: - begin - ozoneaee(foo[20:18], foobar); - foobar = {foobar," 477"}; - ozoneaee(foo[17:15], foobar); - foobar = {foobar," 478"}; - ozoneape(foo[20:18], foobar); - foobar = {foobar," 479"}; - ozoneape(foo[17:15], foobar); - foobar = {foobar," 480"}; - foobar = {foobar, " 481"}; - end - 7'h3f: - begin - ozoneaee(foo[20:18], foobar); - foobar = {foobar," 482"}; - ozoneaee(foo[17:15], foobar); - foobar = {foobar," 483"}; - ozoneape(foo[20:18], foobar); - foobar = {foobar," 484"}; - ozoneape(foo[17:15], foobar); - foobar = {foobar," 485"}; - foobar = {foobar, " 486"}; - end - 7'h40: - begin - ozoneae(foo[20:18], foobar); - foobar = {foobar," 487"}; - ozoneae(foo[17:15], foobar); - foobar = {foobar," 488"}; - foobar = {foobar, " 489"}; - foobar = {foobar, " 490"}; - end - 7'h41: - begin - foobar = {foobar, " 491"}; - foobar = {foobar, " 492"}; - end - 7'h42: - begin - foobar = {foobar, " 493"}; - foobar = {foobar, " 494"}; - end - 7'h43: - begin - foobar = {foobar, " 495"}; - foobar = {foobar, " 496"}; - end - 7'h44: - begin - foobar = {foobar, " 497"}; - foobar = {foobar, " 498"}; - end - 7'h45: - foobar = {foobar, " 499"}; - 7'h46: - begin - ozoneae(foo[20:18], foobar); - foobar = {foobar," 500"}; - foobar = {foobar, " 501"}; - foobar = {foobar, " 502"}; - end - 7'h47: - begin - ozoneaee(foo[20:18], foobar); - foobar = {foobar," 503"}; - ozoneae(foo[17:15], foobar); - foobar = {foobar," 504"}; - ozoneape(foo[20:18], foobar); - foobar = {foobar," 505"}; - ozoneape(foo[20:18], foobar); - foobar = {foobar," 506"}; - foobar = {foobar, " 507"}; - foobar = {foobar, " 508"}; - end - 7'h48: - begin - ozoneaee(foo[20:18], foobar); - foobar = {foobar," 509"}; - ozoneape(foo[20:18], foobar); - foobar = {foobar," 510"}; - ozoneape(foo[20:18], foobar); - foobar = {foobar," 511"}; - ozoneaee(foo[17:15], foobar); - foobar = {foobar," 512"}; - ozoneape(foo[17:15], foobar); - foobar = {foobar," 513"}; - end - 7'h49: - begin - ozoneae(foo[20:18], foobar); - foobar = {foobar," 514"}; - ozoneaee(foo[17:15], foobar); - foobar = {foobar," 515"}; - ozoneape(foo[17:15], foobar); - foobar = {foobar," 516"}; - end - 7'h4a: + case (foo[27:21]) + 7'h00: + begin + ozoneae(foo[20:18], foobar); + foobar = {foobar," 234"}; + foobar = {foobar, " 235"}; + end + 7'h01: + begin + ozoneae(foo[20:18], foobar); + foobar = {foobar," 236"}; + ozoneae(foo[17:15], foobar); + foobar = {foobar," 237"}; + foobar = {foobar, " 238"}; + end + 7'h02: + foobar = {foobar, " 239"}; + 7'h03: + begin + ozoneae(foo[20:18], foobar); + foobar = {foobar," 240"}; + ozoneae(foo[17:15], foobar); + foobar = {foobar," 241"}; + foobar = {foobar, " 242"}; + end + 7'h04: + begin + ozoneae(foo[20:18], foobar); + foobar = {foobar," 243"}; + foobar = {foobar," 244"}; + end + 7'h05: + begin + ozoneae(foo[20:18], foobar); + foobar = {foobar," 245"}; + ozoneae(foo[17:15], foobar); + foobar = {foobar," 246"}; + end + 7'h06: + foobar = {foobar, " 247"}; + 7'h07: + begin + ozoneae(foo[20:18], foobar); + foobar = {foobar," 248"}; + ozoneae(foo[17:15], foobar); + foobar = {foobar," 249"}; + end + 7'h08: + begin + ozoneae(foo[20:18], foobar); + foobar = {foobar," 250"}; + ozoneae(foo[17:15], foobar); + foobar = {foobar," 251"}; + end + 7'h09: + begin + ozoneae(foo[20:18], foobar); + foobar = {foobar," 252"}; + ozoneae(foo[17:15], foobar); + foobar = {foobar," 253"}; + end + 7'h0a: + begin + ozoneae(foo[17:15], foobar); + foobar = {foobar," 254"}; + end + 7'h0b: + begin + ozoneae(foo[17:15], foobar); + foobar = {foobar," 255"}; + end + 7'h0c: + begin + ozoneae(foo[20:18], foobar); + foobar = {foobar," 256"}; + end + 7'h0d: + begin + ozoneae(foo[20:18], foobar); + foobar = {foobar," 257"}; + ozoneae(foo[17:15], foobar); + foobar = {foobar," 258"}; + end + 7'h0e: + begin + ozoneae(foo[20:18], foobar); + foobar = {foobar," 259"}; + ozoneae(foo[17:15], foobar); + foobar = {foobar," 260"}; + end + 7'h0f: + begin + ozoneae(foo[20:18], foobar); + foobar = {foobar," 261"}; + ozoneae(foo[17:15], foobar); + foobar = {foobar," 262"}; + end + 7'h10: + begin + ozoneae(foo[20:18], foobar); + foobar = {foobar," 263"}; + ozoneae(foo[17:15], foobar); + foobar = {foobar," 264"}; + foobar = {foobar, " 265"}; + foobar = {foobar, " 266"}; + end + 7'h11: + begin + ozoneae(foo[20:18], foobar); + foobar = {foobar," 267"}; + ozoneae(foo[17:15], foobar); + foobar = {foobar," 268"}; + foobar = {foobar, " 269"}; + foobar = {foobar, " 270"}; + end + 7'h12: + begin + ozoneae(foo[20:18], foobar); + foobar = {foobar," 271"}; + ozoneae(foo[17:15], foobar); + foobar = {foobar," 272"}; + foobar = {foobar, " 273"}; + foobar = {foobar, " 274"}; + end + 7'h13: + begin + ozoneae(foo[20:18], foobar); + foobar = {foobar," 275"}; + ozoneae(foo[17:15], foobar); + foobar = {foobar," 276"}; + foobar = {foobar, " 277"}; + foobar = {foobar, " 278"}; + end + 7'h14: + begin + ozoneaee(foo[20:18], foobar); + foobar = {foobar," 279"}; + ozoneaee(foo[17:15], foobar); + foobar = {foobar," 280"}; + ozoneape(foo[20:18], foobar); + foobar = {foobar," 281"}; + ozoneape(foo[17:15], foobar); + foobar = {foobar," 282"}; + foobar = {foobar, " 283"}; + foobar = {foobar, " 284"}; + end + 7'h15: + begin + ozoneaee(foo[20:18], foobar); + foobar = {foobar," 285"}; + ozoneaee(foo[17:15], foobar); + foobar = {foobar," 286"}; + ozoneape(foo[20:18], foobar); + foobar = {foobar," 287"}; + ozoneape(foo[17:15], foobar); + foobar = {foobar," 288"}; + foobar = {foobar, " 289"}; + foobar = {foobar, " 290"}; + end + 7'h16: + begin + ozoneaee(foo[20:18], foobar); + foobar = {foobar," 291"}; + ozoneaee(foo[17:15], foobar); + foobar = {foobar," 292"}; + ozoneape(foo[20:18], foobar); + foobar = {foobar," 293"}; + ozoneape(foo[17:15], foobar); + foobar = {foobar," 294"}; + foobar = {foobar, " 295"}; + foobar = {foobar, " 296"}; + end + 7'h17: + begin + ozoneaee(foo[20:18], foobar); + foobar = {foobar," 297"}; + ozoneaee(foo[17:15], foobar); + foobar = {foobar," 298"}; + ozoneape(foo[20:18], foobar); + foobar = {foobar," 299"}; + ozoneape(foo[17:15], foobar); + foobar = {foobar," 300"}; + foobar = {foobar, " 301"}; + foobar = {foobar, " 302"}; + end + 7'h18: + begin + ozoneae(foo[20:18], foobar); + foobar = {foobar," 303"}; + ozoneae(foo[17:15], foobar); + foobar = {foobar," 304"}; + foobar = {foobar, " 305"}; + foobar = {foobar, " 306"}; + end + 7'h19: + begin + ozoneae(foo[20:18], foobar); + foobar = {foobar," 307"}; + ozoneae(foo[17:15], foobar); + foobar = {foobar," 308"}; + foobar = {foobar, " 309"}; + foobar = {foobar, " 310"}; + end + 7'h1a: + begin + ozoneae(foo[20:18], foobar); + foobar = {foobar," 311"}; + ozoneae(foo[17:15], foobar); + foobar = {foobar," 312"}; + foobar = {foobar, " 313"}; + foobar = {foobar, " 314"}; + end + 7'h1b: + begin + ozoneae(foo[20:18], foobar); + foobar = {foobar," 315"}; + ozoneae(foo[17:15], foobar); + foobar = {foobar," 316"}; + foobar = {foobar, " 317"}; + foobar = {foobar, " 318"}; + end + 7'h1c: + begin + ozoneae(foo[20:18], foobar); + foobar = {foobar," 319"}; + ozoneae(foo[17:15], foobar); + foobar = {foobar," 320"}; + foobar = {foobar, " 321"}; + foobar = {foobar, " 322"}; + end + 7'h1d: + begin + ozoneae(foo[20:18], foobar); + foobar = {foobar," 323"}; + ozoneae(foo[17:15], foobar); + foobar = {foobar," 324"}; + foobar = {foobar, " 325"}; + foobar = {foobar, " 326"}; + end + 7'h1e: + begin + ozoneaee(foo[20:18], foobar); + foobar = {foobar," 327"}; + ozoneaee(foo[17:15], foobar); + foobar = {foobar," 328"}; + ozoneape(foo[20:18], foobar); + foobar = {foobar," 329"}; + ozoneape(foo[17:15], foobar); + foobar = {foobar," 330"}; + foobar = {foobar, " 331"}; + foobar = {foobar, " 332"}; + end + 7'h1f: + begin + ozoneaee(foo[20:18], foobar); + foobar = {foobar," 333"}; + ozoneaee(foo[17:15], foobar); + foobar = {foobar," 334"}; + ozoneape(foo[20:18], foobar); + foobar = {foobar," 335"}; + ozoneape(foo[17:15], foobar); + foobar = {foobar," 336"}; + foobar = {foobar, " 337"}; + foobar = {foobar, " 338"}; + end + 7'h20: + begin + ozoneaee(foo[20:18], foobar); + foobar = {foobar," 339"}; + ozoneaee(foo[17:15], foobar); + foobar = {foobar," 340"}; + ozoneape(foo[20:18], foobar); + foobar = {foobar," 341"}; + ozoneape(foo[17:15], foobar); + foobar = {foobar," 342"}; + foobar = {foobar, " 343"}; + foobar = {foobar, " 344"}; + end + 7'h21: + begin + ozoneaee(foo[20:18], foobar); + foobar = {foobar," 345"}; + ozoneaee(foo[17:15], foobar); + foobar = {foobar," 346"}; + ozoneape(foo[20:18], foobar); + foobar = {foobar," 347"}; + ozoneape(foo[17:15], foobar); + foobar = {foobar," 348"}; + foobar = {foobar, " 349"}; + foobar = {foobar, " 350"}; + end + 7'h22: + begin + ozoneae(foo[20:18], foobar); + foobar = {foobar," 351"}; + ozoneae(foo[17:15], foobar); + foobar = {foobar," 352"}; + foobar = {foobar, " 353"}; + foobar = {foobar, " 354"}; + end + 7'h23: + begin + ozoneae(foo[20:18], foobar); + foobar = {foobar," 355"}; + ozoneae(foo[17:15], foobar); + foobar = {foobar," 356"}; + foobar = {foobar, " 357"}; + foobar = {foobar, " 358"}; + end + 7'h24: + begin + ozoneae(foo[20:18], foobar); + foobar = {foobar," 359"}; + ozoneae(foo[17:15], foobar); + foobar = {foobar," 360"}; + foobar = {foobar, " 361"}; + foobar = {foobar, " 362"}; + end + 7'h25: + begin + ozoneae(foo[20:18], foobar); + foobar = {foobar," 363"}; + ozoneae(foo[17:15], foobar); + foobar = {foobar," 364"}; + foobar = {foobar, " 365"}; + foobar = {foobar, " 366"}; + end + 7'h26: + begin + ozoneae(foo[20:18], foobar); + foobar = {foobar," 367"}; + ozoneae(foo[17:15], foobar); + foobar = {foobar," 368"}; + foobar = {foobar, " 369"}; + foobar = {foobar, " 370"}; + end + 7'h27: + begin + ozoneae(foo[20:18], foobar); + foobar = {foobar," 371"}; + ozoneae(foo[17:15], foobar); + foobar = {foobar," 372"}; + foobar = {foobar, " 373"}; + foobar = {foobar, " 374"}; + end + 7'h28: + begin + ozoneaee(foo[20:18], foobar); + foobar = {foobar," 375"}; + ozoneaee(foo[17:15], foobar); + foobar = {foobar," 376"}; + ozoneape(foo[20:18], foobar); + foobar = {foobar," 377"}; + ozoneape(foo[17:15], foobar); + foobar = {foobar," 378"}; + foobar = {foobar, " 379"}; + foobar = {foobar, " 380"}; + end + 7'h29: + begin + ozoneaee(foo[20:18], foobar); + foobar = {foobar," 381"}; + ozoneaee(foo[17:15], foobar); + foobar = {foobar," 382"}; + ozoneape(foo[20:18], foobar); + foobar = {foobar," 383"}; + ozoneape(foo[17:15], foobar); + foobar = {foobar," 384"}; + foobar = {foobar, " 385"}; + foobar = {foobar, " 386"}; + end + 7'h2a: + begin + ozoneaee(foo[20:18], foobar); + foobar = {foobar," 387"}; + ozoneaee(foo[17:15], foobar); + foobar = {foobar," 388"}; + ozoneape(foo[20:18], foobar); + foobar = {foobar," 389"}; + ozoneape(foo[17:15], foobar); + foobar = {foobar," 390"}; + foobar = {foobar, " 391"}; + foobar = {foobar, " 392"}; + end + 7'h2b: + begin + ozoneaee(foo[20:18], foobar); + foobar = {foobar," 393"}; + ozoneaee(foo[17:15], foobar); + foobar = {foobar," 394"}; + ozoneape(foo[20:18], foobar); + foobar = {foobar," 395"}; + ozoneape(foo[17:15], foobar); + foobar = {foobar," 396"}; + foobar = {foobar, " 397"}; + foobar = {foobar, " 398"}; + end + 7'h2c: + begin + ozoneae(foo[20:18], foobar); + foobar = {foobar," 399"}; + ozoneae(foo[17:15], foobar); + foobar = {foobar," 400"}; + foobar = {foobar, " 401"}; + foobar = {foobar, " 402"}; + end + 7'h2d: + begin + ozoneae(foo[20:18], foobar); + foobar = {foobar," 403"}; + ozoneae(foo[17:15], foobar); + foobar = {foobar," 404"}; + foobar = {foobar, " 405"}; + foobar = {foobar, " 406"}; + end + 7'h2e: + begin + ozoneae(foo[20:18], foobar); + foobar = {foobar," 407"}; + ozoneae(foo[17:15], foobar); + foobar = {foobar," 408"}; + foobar = {foobar, " 409"}; + foobar = {foobar, " 410"}; + end + 7'h2f: + begin + ozoneae(foo[20:18], foobar); + foobar = {foobar," 411"}; + ozoneae(foo[17:15], foobar); + foobar = {foobar," 412"}; + foobar = {foobar, " 413"}; + foobar = {foobar, " 414"}; + end + 7'h30: + begin + ozoneae(foo[20:18], foobar); + foobar = {foobar," 415"}; + ozoneae(foo[17:15], foobar); + foobar = {foobar," 416"}; + foobar = {foobar, " 417"}; + foobar = {foobar, " 418"}; + end + 7'h31: + begin + ozoneae(foo[20:18], foobar); + foobar = {foobar," 419"}; + ozoneae(foo[17:15], foobar); + foobar = {foobar," 420"}; + foobar = {foobar, " 421"}; + foobar = {foobar, " 422"}; + end + 7'h32: + begin + ozoneaee(foo[20:18], foobar); + foobar = {foobar," 423"}; + ozoneaee(foo[17:15], foobar); + foobar = {foobar," 424"}; + ozoneape(foo[20:18], foobar); + foobar = {foobar," 425"}; + ozoneape(foo[17:15], foobar); + foobar = {foobar," 426"}; + foobar = {foobar, " 427"}; + foobar = {foobar, " 428"}; + end + 7'h33: + begin + ozoneaee(foo[20:18], foobar); + foobar = {foobar," 429"}; + ozoneaee(foo[17:15], foobar); + foobar = {foobar," 430"}; + ozoneape(foo[20:18], foobar); + foobar = {foobar," 431"}; + ozoneape(foo[17:15], foobar); + foobar = {foobar," 432"}; + foobar = {foobar, " 433"}; + foobar = {foobar, " 434"}; + end + 7'h34: + begin + ozoneaee(foo[20:18], foobar); + foobar = {foobar," 435"}; + ozoneaee(foo[17:15], foobar); + foobar = {foobar," 436"}; + ozoneape(foo[20:18], foobar); + foobar = {foobar," 437"}; + ozoneape(foo[17:15], foobar); + foobar = {foobar," 438"}; + foobar = {foobar, " 439"}; + foobar = {foobar, " 440"}; + end + 7'h35: + begin + ozoneaee(foo[20:18], foobar); + foobar = {foobar," 441"}; + ozoneaee(foo[17:15], foobar); + foobar = {foobar," 442"}; + ozoneape(foo[20:18], foobar); + foobar = {foobar," 443"}; + ozoneape(foo[17:15], foobar); + foobar = {foobar," 444"}; + foobar = {foobar, " 445"}; + foobar = {foobar, " 446"}; + end + 7'h36: + begin + ozoneae(foo[20:18], foobar); + foobar = {foobar," 447"}; + ozoneae(foo[17:15], foobar); + foobar = {foobar," 448"}; + foobar = {foobar, " 449"}; + foobar = {foobar, " 450"}; + end + 7'h37: + begin + ozoneae(foo[20:18], foobar); + foobar = {foobar," 451"}; + ozoneae(foo[17:15], foobar); + foobar = {foobar," 452"}; + foobar = {foobar, " 453"}; + foobar = {foobar, " 454"}; + end + 7'h38: + begin + ozoneae(foo[20:18], foobar); + foobar = {foobar," 455"}; + ozoneae(foo[17:15], foobar); + foobar = {foobar," 456"}; + foobar = {foobar, " 457"}; + end + 7'h39: + begin + ozoneae(foo[20:18], foobar); + foobar = {foobar," 458"}; + ozoneae(foo[17:15], foobar); + foobar = {foobar," 459"}; + foobar = {foobar, " 460"}; + end + 7'h3a: + begin + ozoneae(foo[20:18], foobar); + foobar = {foobar," 461"}; + ozoneae(foo[17:15], foobar); + foobar = {foobar," 462"}; + foobar = {foobar, " 463"}; + end + 7'h3b: + begin + ozoneae(foo[20:18], foobar); + foobar = {foobar," 464"}; + ozoneae(foo[17:15], foobar); + foobar = {foobar," 465"}; + foobar = {foobar, " 466"}; + end + 7'h3c: + begin + ozoneaee(foo[20:18], foobar); + foobar = {foobar," 467"}; + ozoneaee(foo[17:15], foobar); + foobar = {foobar," 468"}; + ozoneape(foo[20:18], foobar); + foobar = {foobar," 469"}; + ozoneape(foo[17:15], foobar); + foobar = {foobar," 470"}; + foobar = {foobar, " 471"}; + end + 7'h3d: + begin + ozoneaee(foo[20:18], foobar); + foobar = {foobar," 472"}; + ozoneaee(foo[17:15], foobar); + foobar = {foobar," 473"}; + ozoneape(foo[20:18], foobar); + foobar = {foobar," 474"}; + ozoneape(foo[17:15], foobar); + foobar = {foobar," 475"}; + foobar = {foobar, " 476"}; + end + 7'h3e: + begin + ozoneaee(foo[20:18], foobar); + foobar = {foobar," 477"}; + ozoneaee(foo[17:15], foobar); + foobar = {foobar," 478"}; + ozoneape(foo[20:18], foobar); + foobar = {foobar," 479"}; + ozoneape(foo[17:15], foobar); + foobar = {foobar," 480"}; + foobar = {foobar, " 481"}; + end + 7'h3f: + begin + ozoneaee(foo[20:18], foobar); + foobar = {foobar," 482"}; + ozoneaee(foo[17:15], foobar); + foobar = {foobar," 483"}; + ozoneape(foo[20:18], foobar); + foobar = {foobar," 484"}; + ozoneape(foo[17:15], foobar); + foobar = {foobar," 485"}; + foobar = {foobar, " 486"}; + end + 7'h40: + begin + ozoneae(foo[20:18], foobar); + foobar = {foobar," 487"}; + ozoneae(foo[17:15], foobar); + foobar = {foobar," 488"}; + foobar = {foobar, " 489"}; + foobar = {foobar, " 490"}; + end + 7'h41: + begin + foobar = {foobar, " 491"}; + foobar = {foobar, " 492"}; + end + 7'h42: + begin + foobar = {foobar, " 493"}; + foobar = {foobar, " 494"}; + end + 7'h43: + begin + foobar = {foobar, " 495"}; + foobar = {foobar, " 496"}; + end + 7'h44: + begin + foobar = {foobar, " 497"}; + foobar = {foobar, " 498"}; + end + 7'h45: + foobar = {foobar, " 499"}; + 7'h46: + begin + ozoneae(foo[20:18], foobar); + foobar = {foobar," 500"}; + foobar = {foobar, " 501"}; + foobar = {foobar, " 502"}; + end + 7'h47: + begin + ozoneaee(foo[20:18], foobar); + foobar = {foobar," 503"}; + ozoneae(foo[17:15], foobar); + foobar = {foobar," 504"}; + ozoneape(foo[20:18], foobar); + foobar = {foobar," 505"}; + ozoneape(foo[20:18], foobar); + foobar = {foobar," 506"}; + foobar = {foobar, " 507"}; + foobar = {foobar, " 508"}; + end + 7'h48: + begin + ozoneaee(foo[20:18], foobar); + foobar = {foobar," 509"}; + ozoneape(foo[20:18], foobar); + foobar = {foobar," 510"}; + ozoneape(foo[20:18], foobar); + foobar = {foobar," 511"}; + ozoneaee(foo[17:15], foobar); + foobar = {foobar," 512"}; + ozoneape(foo[17:15], foobar); + foobar = {foobar," 513"}; + end + 7'h49: + begin + ozoneae(foo[20:18], foobar); + foobar = {foobar," 514"}; + ozoneaee(foo[17:15], foobar); + foobar = {foobar," 515"}; + ozoneape(foo[17:15], foobar); + foobar = {foobar," 516"}; + end + 7'h4a: foobar = {foobar," 517"}; - 7'h4b: + 7'h4b: foobar = {foobar, " 518"}; - 7'h4c: - begin - ozoneae(foo[20:18], foobar); - foobar = {foobar," 519"}; - foobar = {foobar, " 520"}; - foobar = {foobar, " 521"}; - end - 7'h4d: - begin - ozoneaee(foo[20:18], foobar); - foobar = {foobar," 522"}; - ozoneae(foo[17:15], foobar); - foobar = {foobar," 523"}; - ozoneape(foo[20:18], foobar); - foobar = {foobar," 524"}; - ozoneape(foo[20:18], foobar); - foobar = {foobar," 525"}; - foobar = {foobar, " 526"}; - foobar = {foobar, " 527"}; - end - 7'h4e: - begin - ozoneaee(foo[20:18], foobar); - foobar = {foobar," 528"}; - ozoneae(foo[17:15], foobar); - foobar = {foobar," 529"}; - ozoneape(foo[20:18], foobar); - foobar = {foobar," 530"}; - ozoneape(foo[20:18], foobar); - foobar = {foobar," 531"}; - end - 7'h4f: - begin - ozoneae(foo[20:18], foobar); - foobar = {foobar," 532"}; - end - 7'h50: - begin - ozoneaee(foo[20:18], foobar); - foobar = {foobar," 533"}; - ozoneae(foo[17:15], foobar); - foobar = {foobar," 534"}; - ozoneaee(foo[20:18], foobar); - foobar = {foobar," 535"}; - ozoneae(foo[17:15], foobar); - foobar = {foobar," 536"}; - ozoneape(foo[20:18], foobar); - foobar = {foobar," 537"}; - ozoneae(foo[17:15], foobar); - foobar = {foobar," 538"}; - ozoneape(foo[20:18], foobar); - foobar = {foobar," 539"}; - ozoneae(foo[17:15], foobar); - foobar = {foobar," 540"}; - end - 7'h51: - begin - ozoneaee(foo[20:18], foobar); - foobar = {foobar," 541"}; - ozoneape(foo[20:18], foobar); - foobar = {foobar," 542"}; - ozoneaee(foo[20:18], foobar); - foobar = {foobar," 543"}; - ozoneape(foo[20:18], foobar); - foobar = {foobar," 544"}; - ozoneae(foo[17:15], foobar); - foobar = {foobar," 545"}; - end - 7'h52: - foobar = {foobar, " 546"}; - 7'h53: - begin - ozoneae(foo[20:18], foobar); - foobar = {foobar, " 547"}; - end - 7'h54: - begin - ozoneae(foo[20:18], foobar); - foobar = {foobar," 548"}; - ozoneae(foo[17:15], foobar); - foobar = {foobar," 549"}; - end - 7'h55: - begin - ozoneae(foo[20:18], foobar); - foobar = {foobar," 550"}; - ozoneae(foo[17:15], foobar); - foobar = {foobar," 551"}; - end - 7'h56: - begin - ozoneae(foo[20:18], foobar); - foobar = {foobar," 552"}; - ozoneae(foo[17:15], foobar); - foobar = {foobar," 553"}; - foobar = {foobar, " 554"}; - end - 7'h57: - begin - ozoneaee(foo[20:18], foobar); - foobar = {foobar," 555"}; - ozoneae(foo[17:15], foobar); - foobar = {foobar," 556"}; - ozoneape(foo[20:18], foobar); - foobar = {foobar," 557"}; - ozoneape(foo[20:18], foobar); - foobar = {foobar," 558"}; - end - 7'h58: - begin - ozoneae(foo[20:18], foobar); - foobar = {foobar, " 559"}; - end - 7'h59: - begin - ozoneaee(foo[20:18], foobar); - foobar = {foobar," 560"}; - ozoneae(foo[17:15], foobar); - foobar = {foobar," 561"}; - ozoneape(foo[20:18], foobar); - foobar = {foobar," 562"}; - ozoneape(foo[20:18], foobar); - foobar = {foobar," 563"}; - end - 7'h5a: - begin - ozoneae(foo[20:18], foobar); - foobar = {foobar," 564"}; - ozoneae(foo[17:15], foobar); - foobar = {foobar, " 565"}; - end - 7'h5b: - begin - ozoneae(foo[20:18], foobar); - foobar = {foobar," 566"}; - ozoneae(foo[17:15], foobar); - foobar = {foobar, " 567"}; - end - 7'h5c: - begin - foobar = {foobar," 568"}; - ozoneape(foo[17:15], foobar); - foobar = {foobar," 569"}; - foobar = {foobar," 570"}; - ozoneape(foo[17:15], foobar); - foobar = {foobar," 571"}; - ozoneae(foo[20:18], foobar); - foobar = {foobar," 572"}; - ozoneaee(foo[17:15], foobar); - foobar = {foobar, " 573"}; - end - 7'h5d: - begin - foobar = {foobar," 574"}; - ozoneape(foo[17:15], foobar); - foobar = {foobar," 575"}; - foobar = {foobar," 576"}; - ozoneape(foo[17:15], foobar); - foobar = {foobar," 577"}; - ozoneae(foo[20:18], foobar); - foobar = {foobar," 578"}; - ozoneaee(foo[17:15], foobar); - foobar = {foobar, " 579"}; - end - 7'h5e: - begin - ozoneae(foo[20:18], foobar); - foobar = {foobar," 580"}; - ozoneae(foo[17:15], foobar); - foobar = {foobar, " 581"}; - end - 7'h5f: - begin - ozoneaee(foo[20:18], foobar); - foobar = {foobar," 582"}; - ozoneae(foo[17:15], foobar); - foobar = {foobar," 583"}; - ozoneaee(foo[20:18], foobar); - foobar = {foobar," 584"}; - ozoneae(foo[17:15], foobar); - foobar = {foobar," 585"}; - ozoneape(foo[20:18], foobar); - foobar = {foobar," 586"}; - ozoneae(foo[17:15], foobar); - foobar = {foobar," 587"}; - ozoneape(foo[20:18], foobar); - foobar = {foobar," 588"}; - ozoneae(foo[17:15], foobar); - foobar = {foobar," 589"}; - end - 7'h60: - begin - ozoneae(foo[20:18], foobar); - foobar = {foobar," 590"}; - ozoneae(foo[17:15], foobar); - foobar = {foobar," 591"}; - end - 7'h61: - begin - ozoneae(foo[20:18], foobar); - foobar = {foobar," 592"}; - ozoneae(foo[17:15], foobar); - foobar = {foobar," 593"}; - end - 7'h62: - begin - ozoneae(foo[20:18], foobar); - foobar = {foobar," 594"}; - ozoneae(foo[17:15], foobar); - foobar = {foobar," 595"}; - end - 7'h63: - begin - ozoneae(foo[20:18], foobar); - foobar = {foobar," 596"}; - ozoneae(foo[17:15], foobar); - foobar = {foobar," 597"}; - end - 7'h64: - begin - ozoneaee(foo[20:18], foobar); - foobar = {foobar," 598"}; - ozoneaee(foo[17:15], foobar); - foobar = {foobar," 599"}; - ozoneape(foo[20:18], foobar); - foobar = {foobar," 600"}; - ozoneape(foo[17:15], foobar); - foobar = {foobar," 601"}; - end - 7'h65: - begin - ozoneaee(foo[20:18], foobar); - foobar = {foobar," 602"}; - ozoneaee(foo[17:15], foobar); - foobar = {foobar," 603"}; - ozoneape(foo[20:18], foobar); - foobar = {foobar," 604"}; - ozoneape(foo[17:15], foobar); - foobar = {foobar," 605"}; - end - 7'h66: - begin - ozoneaee(foo[20:18], foobar); - foobar = {foobar," 606"}; - ozoneaee(foo[17:15], foobar); - foobar = {foobar," 607"}; - ozoneape(foo[20:18], foobar); - foobar = {foobar," 608"}; - ozoneape(foo[17:15], foobar); - foobar = {foobar," 609"}; - end - 7'h67: - begin - ozoneaee(foo[20:18], foobar); - foobar = {foobar," 610"}; - ozoneaee(foo[17:15], foobar); - foobar = {foobar," 611"}; - ozoneape(foo[20:18], foobar); - foobar = {foobar," 612"}; - ozoneape(foo[17:15], foobar); - foobar = {foobar," 613"}; - end - 7'h68: - begin - ozoneaee(foo[20:18], foobar); - foobar = {foobar," 614"}; - ozoneaee(foo[17:15], foobar); - foobar = {foobar," 615"}; - ozoneaee(foo[20:18], foobar); - foobar = {foobar," 616"}; - ozoneape(foo[20:18], foobar); - foobar = {foobar," 617"}; - ozoneape(foo[20:18], foobar); - foobar = {foobar," 618"}; - ozoneape(foo[17:15], foobar); - end - 7'h69: - begin - ozoneae(foo[20:18], foobar); - foobar = {foobar," 619"}; - ozoneae(foo[17:15], foobar); - foobar = {foobar," 620"}; - ozoneae(foo[20:18], foobar); - foobar = {foobar," 621"}; - end - 7'h6a: - begin - ozoneaee(foo[20:18], foobar); - foobar = {foobar," 622"}; - ozoneae(foo[17:15], foobar); - foobar = {foobar," 623"}; - ozoneaee(foo[20:18], foobar); - foobar = {foobar," 624"}; - ozoneape(foo[20:18], foobar); - foobar = {foobar," 625"}; - ozoneaee(foo[20:18], foobar); - foobar = {foobar," 626"}; - ozoneae(foo[17:15], foobar); - end - 7'h6b: - begin - ozoneae(foo[20:18], foobar); - foobar = {foobar," 627"}; - ozoneae(foo[17:15], foobar); - foobar = {foobar," 628"}; - ozoneae(foo[20:18], foobar); - foobar = {foobar," 629"}; - end - 7'h6c: - begin - ozoneaee(foo[20:18], foobar); - foobar = {foobar," 630"}; - ozoneae(foo[17:15], foobar); - foobar = {foobar," 631"}; - ozoneaee(foo[20:18], foobar); - foobar = {foobar," 632"}; - ozoneape(foo[20:18], foobar); - foobar = {foobar," 633"}; - ozoneaee(foo[20:18], foobar); - foobar = {foobar," 634"}; - ozoneae(foo[17:15], foobar); - end - 7'h6d: - begin - ozoneae(foo[20:18], foobar); - foobar = {foobar," 635"}; - ozoneae(foo[17:15], foobar); - foobar = {foobar," 636"}; - ozoneae(foo[20:18], foobar); - foobar = {foobar," 637"}; - end - 7'h6e: - begin - ozoneaee(foo[20:18], foobar); - foobar = {foobar," 638"}; - ozoneaee(foo[17:15], foobar); - foobar = {foobar," 639"}; - ozoneape(foo[20:18], foobar); - foobar = {foobar," 640"}; - ozoneape(foo[17:15], foobar); - foobar = {foobar," 641"}; - end - 7'h6f: - begin - ozoneaee(foo[20:18], foobar); - foobar = {foobar," 642"}; - ozoneaee(foo[17:15], foobar); - foobar = {foobar," 643"}; - ozoneape(foo[20:18], foobar); - foobar = {foobar," 644"}; - ozoneape(foo[17:15], foobar); - foobar = {foobar," 645"}; - end - 7'h70: - begin - ozoneae(foo[20:18], foobar); - foobar = {foobar," 646"}; - ozoneae(foo[20:18], foobar); - foobar = {foobar," 647"}; - ozoneae(foo[17:15], foobar); - foobar = {foobar," 648"}; - ozoneae(foo[17:15], foobar); - foobar = {foobar, " 649"}; - end - 7'h71: - begin - ozoneae(foo[20:18], foobar); - foobar = {foobar," 650"}; - ozoneae(foo[17:15], foobar); - foobar = {foobar, " 651"}; - end - 7'h72: - begin - ozoneae(foo[20:18], foobar); - foobar = {foobar," 652"}; - ozoneae(foo[17:15], foobar); - foobar = {foobar, " 653"}; - end - 7'h73: - begin - ozoneae(foo[20:18], foobar); - foobar = {foobar," 654"}; - ozoneae(foo[20:18], foobar); - foobar = {foobar," 655"}; - ozoneae(foo[17:15], foobar); - end - 7'h74: - begin - ozoneae(foo[20:18], foobar); - foobar = {foobar," 656"}; - ozoneae(foo[20:18], foobar); - foobar = {foobar," 657"}; - ozoneae(foo[17:15], foobar); - end - 7'h75: - begin - ozoneaee(foo[20:18], foobar); - foobar = {foobar," 658"}; - ozoneaee(foo[17:15], foobar); - foobar = {foobar," 659"}; - ozoneape(foo[20:18], foobar); - foobar = {foobar," 660"}; - ozoneape(foo[17:15], foobar); - foobar = {foobar," 661"}; - foobar = {foobar, " 662"}; - foobar = {foobar, " 663"}; - end - 7'h76: - begin - ozoneaee(foo[20:18], foobar); - foobar = {foobar," 664"}; - ozoneaee(foo[17:15], foobar); - foobar = {foobar," 665"}; - ozoneaee(foo[20:18], foobar); - foobar = {foobar," 666"}; - ozoneape(foo[20:18], foobar); - foobar = {foobar," 667"}; - ozoneape(foo[17:15], foobar); - foobar = {foobar," 668"}; - ozoneape(foo[20:18], foobar); - foobar = {foobar," 669"}; - end - 7'h77: - begin - ozoneaee(foo[20:18], foobar); - foobar = {foobar," 670"}; - ozoneaee(foo[17:15], foobar); - foobar = {foobar," 671"}; - ozoneaee(foo[17:15], foobar); - foobar = {foobar," 672"}; - ozoneape(foo[20:18], foobar); - foobar = {foobar," 673"}; - ozoneape(foo[17:15], foobar); - foobar = {foobar," 674"}; - ozoneape(foo[17:15], foobar); - foobar = {foobar," 675"}; - end - 7'h78, - 7'h79, - 7'h7a, - 7'h7b, - 7'h7c, - 7'h7d, - 7'h7e, - 7'h7f: + 7'h4c: + begin + ozoneae(foo[20:18], foobar); + foobar = {foobar," 519"}; + foobar = {foobar, " 520"}; + foobar = {foobar, " 521"}; + end + 7'h4d: + begin + ozoneaee(foo[20:18], foobar); + foobar = {foobar," 522"}; + ozoneae(foo[17:15], foobar); + foobar = {foobar," 523"}; + ozoneape(foo[20:18], foobar); + foobar = {foobar," 524"}; + ozoneape(foo[20:18], foobar); + foobar = {foobar," 525"}; + foobar = {foobar, " 526"}; + foobar = {foobar, " 527"}; + end + 7'h4e: + begin + ozoneaee(foo[20:18], foobar); + foobar = {foobar," 528"}; + ozoneae(foo[17:15], foobar); + foobar = {foobar," 529"}; + ozoneape(foo[20:18], foobar); + foobar = {foobar," 530"}; + ozoneape(foo[20:18], foobar); + foobar = {foobar," 531"}; + end + 7'h4f: + begin + ozoneae(foo[20:18], foobar); + foobar = {foobar," 532"}; + end + 7'h50: + begin + ozoneaee(foo[20:18], foobar); + foobar = {foobar," 533"}; + ozoneae(foo[17:15], foobar); + foobar = {foobar," 534"}; + ozoneaee(foo[20:18], foobar); + foobar = {foobar," 535"}; + ozoneae(foo[17:15], foobar); + foobar = {foobar," 536"}; + ozoneape(foo[20:18], foobar); + foobar = {foobar," 537"}; + ozoneae(foo[17:15], foobar); + foobar = {foobar," 538"}; + ozoneape(foo[20:18], foobar); + foobar = {foobar," 539"}; + ozoneae(foo[17:15], foobar); + foobar = {foobar," 540"}; + end + 7'h51: + begin + ozoneaee(foo[20:18], foobar); + foobar = {foobar," 541"}; + ozoneape(foo[20:18], foobar); + foobar = {foobar," 542"}; + ozoneaee(foo[20:18], foobar); + foobar = {foobar," 543"}; + ozoneape(foo[20:18], foobar); + foobar = {foobar," 544"}; + ozoneae(foo[17:15], foobar); + foobar = {foobar," 545"}; + end + 7'h52: + foobar = {foobar, " 546"}; + 7'h53: + begin + ozoneae(foo[20:18], foobar); + foobar = {foobar, " 547"}; + end + 7'h54: + begin + ozoneae(foo[20:18], foobar); + foobar = {foobar," 548"}; + ozoneae(foo[17:15], foobar); + foobar = {foobar," 549"}; + end + 7'h55: + begin + ozoneae(foo[20:18], foobar); + foobar = {foobar," 550"}; + ozoneae(foo[17:15], foobar); + foobar = {foobar," 551"}; + end + 7'h56: + begin + ozoneae(foo[20:18], foobar); + foobar = {foobar," 552"}; + ozoneae(foo[17:15], foobar); + foobar = {foobar," 553"}; + foobar = {foobar, " 554"}; + end + 7'h57: + begin + ozoneaee(foo[20:18], foobar); + foobar = {foobar," 555"}; + ozoneae(foo[17:15], foobar); + foobar = {foobar," 556"}; + ozoneape(foo[20:18], foobar); + foobar = {foobar," 557"}; + ozoneape(foo[20:18], foobar); + foobar = {foobar," 558"}; + end + 7'h58: + begin + ozoneae(foo[20:18], foobar); + foobar = {foobar, " 559"}; + end + 7'h59: + begin + ozoneaee(foo[20:18], foobar); + foobar = {foobar," 560"}; + ozoneae(foo[17:15], foobar); + foobar = {foobar," 561"}; + ozoneape(foo[20:18], foobar); + foobar = {foobar," 562"}; + ozoneape(foo[20:18], foobar); + foobar = {foobar," 563"}; + end + 7'h5a: + begin + ozoneae(foo[20:18], foobar); + foobar = {foobar," 564"}; + ozoneae(foo[17:15], foobar); + foobar = {foobar, " 565"}; + end + 7'h5b: + begin + ozoneae(foo[20:18], foobar); + foobar = {foobar," 566"}; + ozoneae(foo[17:15], foobar); + foobar = {foobar, " 567"}; + end + 7'h5c: + begin + foobar = {foobar," 568"}; + ozoneape(foo[17:15], foobar); + foobar = {foobar," 569"}; + foobar = {foobar," 570"}; + ozoneape(foo[17:15], foobar); + foobar = {foobar," 571"}; + ozoneae(foo[20:18], foobar); + foobar = {foobar," 572"}; + ozoneaee(foo[17:15], foobar); + foobar = {foobar, " 573"}; + end + 7'h5d: + begin + foobar = {foobar," 574"}; + ozoneape(foo[17:15], foobar); + foobar = {foobar," 575"}; + foobar = {foobar," 576"}; + ozoneape(foo[17:15], foobar); + foobar = {foobar," 577"}; + ozoneae(foo[20:18], foobar); + foobar = {foobar," 578"}; + ozoneaee(foo[17:15], foobar); + foobar = {foobar, " 579"}; + end + 7'h5e: + begin + ozoneae(foo[20:18], foobar); + foobar = {foobar," 580"}; + ozoneae(foo[17:15], foobar); + foobar = {foobar, " 581"}; + end + 7'h5f: + begin + ozoneaee(foo[20:18], foobar); + foobar = {foobar," 582"}; + ozoneae(foo[17:15], foobar); + foobar = {foobar," 583"}; + ozoneaee(foo[20:18], foobar); + foobar = {foobar," 584"}; + ozoneae(foo[17:15], foobar); + foobar = {foobar," 585"}; + ozoneape(foo[20:18], foobar); + foobar = {foobar," 586"}; + ozoneae(foo[17:15], foobar); + foobar = {foobar," 587"}; + ozoneape(foo[20:18], foobar); + foobar = {foobar," 588"}; + ozoneae(foo[17:15], foobar); + foobar = {foobar," 589"}; + end + 7'h60: + begin + ozoneae(foo[20:18], foobar); + foobar = {foobar," 590"}; + ozoneae(foo[17:15], foobar); + foobar = {foobar," 591"}; + end + 7'h61: + begin + ozoneae(foo[20:18], foobar); + foobar = {foobar," 592"}; + ozoneae(foo[17:15], foobar); + foobar = {foobar," 593"}; + end + 7'h62: + begin + ozoneae(foo[20:18], foobar); + foobar = {foobar," 594"}; + ozoneae(foo[17:15], foobar); + foobar = {foobar," 595"}; + end + 7'h63: + begin + ozoneae(foo[20:18], foobar); + foobar = {foobar," 596"}; + ozoneae(foo[17:15], foobar); + foobar = {foobar," 597"}; + end + 7'h64: + begin + ozoneaee(foo[20:18], foobar); + foobar = {foobar," 598"}; + ozoneaee(foo[17:15], foobar); + foobar = {foobar," 599"}; + ozoneape(foo[20:18], foobar); + foobar = {foobar," 600"}; + ozoneape(foo[17:15], foobar); + foobar = {foobar," 601"}; + end + 7'h65: + begin + ozoneaee(foo[20:18], foobar); + foobar = {foobar," 602"}; + ozoneaee(foo[17:15], foobar); + foobar = {foobar," 603"}; + ozoneape(foo[20:18], foobar); + foobar = {foobar," 604"}; + ozoneape(foo[17:15], foobar); + foobar = {foobar," 605"}; + end + 7'h66: + begin + ozoneaee(foo[20:18], foobar); + foobar = {foobar," 606"}; + ozoneaee(foo[17:15], foobar); + foobar = {foobar," 607"}; + ozoneape(foo[20:18], foobar); + foobar = {foobar," 608"}; + ozoneape(foo[17:15], foobar); + foobar = {foobar," 609"}; + end + 7'h67: + begin + ozoneaee(foo[20:18], foobar); + foobar = {foobar," 610"}; + ozoneaee(foo[17:15], foobar); + foobar = {foobar," 611"}; + ozoneape(foo[20:18], foobar); + foobar = {foobar," 612"}; + ozoneape(foo[17:15], foobar); + foobar = {foobar," 613"}; + end + 7'h68: + begin + ozoneaee(foo[20:18], foobar); + foobar = {foobar," 614"}; + ozoneaee(foo[17:15], foobar); + foobar = {foobar," 615"}; + ozoneaee(foo[20:18], foobar); + foobar = {foobar," 616"}; + ozoneape(foo[20:18], foobar); + foobar = {foobar," 617"}; + ozoneape(foo[20:18], foobar); + foobar = {foobar," 618"}; + ozoneape(foo[17:15], foobar); + end + 7'h69: + begin + ozoneae(foo[20:18], foobar); + foobar = {foobar," 619"}; + ozoneae(foo[17:15], foobar); + foobar = {foobar," 620"}; + ozoneae(foo[20:18], foobar); + foobar = {foobar," 621"}; + end + 7'h6a: + begin + ozoneaee(foo[20:18], foobar); + foobar = {foobar," 622"}; + ozoneae(foo[17:15], foobar); + foobar = {foobar," 623"}; + ozoneaee(foo[20:18], foobar); + foobar = {foobar," 624"}; + ozoneape(foo[20:18], foobar); + foobar = {foobar," 625"}; + ozoneaee(foo[20:18], foobar); + foobar = {foobar," 626"}; + ozoneae(foo[17:15], foobar); + end + 7'h6b: + begin + ozoneae(foo[20:18], foobar); + foobar = {foobar," 627"}; + ozoneae(foo[17:15], foobar); + foobar = {foobar," 628"}; + ozoneae(foo[20:18], foobar); + foobar = {foobar," 629"}; + end + 7'h6c: + begin + ozoneaee(foo[20:18], foobar); + foobar = {foobar," 630"}; + ozoneae(foo[17:15], foobar); + foobar = {foobar," 631"}; + ozoneaee(foo[20:18], foobar); + foobar = {foobar," 632"}; + ozoneape(foo[20:18], foobar); + foobar = {foobar," 633"}; + ozoneaee(foo[20:18], foobar); + foobar = {foobar," 634"}; + ozoneae(foo[17:15], foobar); + end + 7'h6d: + begin + ozoneae(foo[20:18], foobar); + foobar = {foobar," 635"}; + ozoneae(foo[17:15], foobar); + foobar = {foobar," 636"}; + ozoneae(foo[20:18], foobar); + foobar = {foobar," 637"}; + end + 7'h6e: + begin + ozoneaee(foo[20:18], foobar); + foobar = {foobar," 638"}; + ozoneaee(foo[17:15], foobar); + foobar = {foobar," 639"}; + ozoneape(foo[20:18], foobar); + foobar = {foobar," 640"}; + ozoneape(foo[17:15], foobar); + foobar = {foobar," 641"}; + end + 7'h6f: + begin + ozoneaee(foo[20:18], foobar); + foobar = {foobar," 642"}; + ozoneaee(foo[17:15], foobar); + foobar = {foobar," 643"}; + ozoneape(foo[20:18], foobar); + foobar = {foobar," 644"}; + ozoneape(foo[17:15], foobar); + foobar = {foobar," 645"}; + end + 7'h70: + begin + ozoneae(foo[20:18], foobar); + foobar = {foobar," 646"}; + ozoneae(foo[20:18], foobar); + foobar = {foobar," 647"}; + ozoneae(foo[17:15], foobar); + foobar = {foobar," 648"}; + ozoneae(foo[17:15], foobar); + foobar = {foobar, " 649"}; + end + 7'h71: + begin + ozoneae(foo[20:18], foobar); + foobar = {foobar," 650"}; + ozoneae(foo[17:15], foobar); + foobar = {foobar, " 651"}; + end + 7'h72: + begin + ozoneae(foo[20:18], foobar); + foobar = {foobar," 652"}; + ozoneae(foo[17:15], foobar); + foobar = {foobar, " 653"}; + end + 7'h73: + begin + ozoneae(foo[20:18], foobar); + foobar = {foobar," 654"}; + ozoneae(foo[20:18], foobar); + foobar = {foobar," 655"}; + ozoneae(foo[17:15], foobar); + end + 7'h74: + begin + ozoneae(foo[20:18], foobar); + foobar = {foobar," 656"}; + ozoneae(foo[20:18], foobar); + foobar = {foobar," 657"}; + ozoneae(foo[17:15], foobar); + end + 7'h75: + begin + ozoneaee(foo[20:18], foobar); + foobar = {foobar," 658"}; + ozoneaee(foo[17:15], foobar); + foobar = {foobar," 659"}; + ozoneape(foo[20:18], foobar); + foobar = {foobar," 660"}; + ozoneape(foo[17:15], foobar); + foobar = {foobar," 661"}; + foobar = {foobar, " 662"}; + foobar = {foobar, " 663"}; + end + 7'h76: + begin + ozoneaee(foo[20:18], foobar); + foobar = {foobar," 664"}; + ozoneaee(foo[17:15], foobar); + foobar = {foobar," 665"}; + ozoneaee(foo[20:18], foobar); + foobar = {foobar," 666"}; + ozoneape(foo[20:18], foobar); + foobar = {foobar," 667"}; + ozoneape(foo[17:15], foobar); + foobar = {foobar," 668"}; + ozoneape(foo[20:18], foobar); + foobar = {foobar," 669"}; + end + 7'h77: + begin + ozoneaee(foo[20:18], foobar); + foobar = {foobar," 670"}; + ozoneaee(foo[17:15], foobar); + foobar = {foobar," 671"}; + ozoneaee(foo[17:15], foobar); + foobar = {foobar," 672"}; + ozoneape(foo[20:18], foobar); + foobar = {foobar," 673"}; + ozoneape(foo[17:15], foobar); + foobar = {foobar," 674"}; + ozoneape(foo[17:15], foobar); + foobar = {foobar," 675"}; + end + 7'h78, + 7'h79, + 7'h7a, + 7'h7b, + 7'h7c, + 7'h7d, + 7'h7e, + 7'h7f: foobar = {foobar," 676"}; - endcase + endcase end endtask @@ -1562,116 +1562,116 @@ module t_case_write1_tasks (); inout [STRLEN*8: 1] foobar; // verilator no_inline_task begin - case (foo[24:21]) - 4'h0 : + case (foo[24:21]) + 4'h0 : case (foo[26:25]) 2'b00 : foobar = {foobar," 677"}; 2'b01 : foobar = {foobar," 678"}; 2'b10 : foobar = {foobar," 679"}; 2'b11 : foobar = {foobar," 680"}; endcase - 4'h1 : + 4'h1 : case (foo[26:25]) 2'b00 : foobar = {foobar," 681"}; 2'b01 : foobar = {foobar," 682"}; 2'b10 : foobar = {foobar," 683"}; 2'b11 : foobar = {foobar," 684"}; endcase - 4'h2 : + 4'h2 : case (foo[26:25]) 2'b00 : foobar = {foobar," 685"}; 2'b01 : foobar = {foobar," 686"}; 2'b10 : foobar = {foobar," 687"}; 2'b11 : foobar = {foobar," 688"}; endcase - 4'h3 : + 4'h3 : case (foo[26:25]) 2'b00 : foobar = {foobar," 689"}; 2'b01 : foobar = {foobar," 690"}; 2'b10 : foobar = {foobar," 691"}; 2'b11 : foobar = {foobar," 692"}; endcase - 4'h4 : + 4'h4 : case (foo[26:25]) 2'b00 : foobar = {foobar," 693"}; 2'b01 : foobar = {foobar," 694"}; 2'b10 : foobar = {foobar," 695"}; 2'b11 : foobar = {foobar," 696"}; endcase - 4'h5 : + 4'h5 : case (foo[26:25]) 2'b00 : foobar = {foobar," 697"}; 2'b01 : foobar = {foobar," 698"}; 2'b10 : foobar = {foobar," 699"}; 2'b11 : foobar = {foobar," 700"}; endcase - 4'h6 : + 4'h6 : case (foo[26:25]) 2'b00 : foobar = {foobar," 701"}; 2'b01 : foobar = {foobar," 702"}; 2'b10 : foobar = {foobar," 703"}; 2'b11 : foobar = {foobar," 704"}; endcase - 4'h7 : + 4'h7 : case (foo[26:25]) 2'b00 : foobar = {foobar," 705"}; 2'b01 : foobar = {foobar," 706"}; 2'b10 : foobar = {foobar," 707"}; 2'b11 : foobar = {foobar," 708"}; endcase - 4'h8 : + 4'h8 : if (foo[26]) foobar = {foobar," 709"}; else foobar = {foobar," 710"}; - 4'h9 : + 4'h9 : case (foo[26:25]) 2'b00 : foobar = {foobar," 711"}; 2'b01 : foobar = {foobar," 712"}; 2'b10 : foobar = {foobar," 713"}; 2'b11 : foobar = {foobar," 714"}; endcase - 4'ha : + 4'ha : case (foo[26:25]) 2'b00 : foobar = {foobar," 715"}; 2'b01 : foobar = {foobar," 716"}; 2'b10 : foobar = {foobar," 717"}; 2'b11 : foobar = {foobar," 718"}; endcase - 4'hb : + 4'hb : case (foo[26:25]) 2'b00 : foobar = {foobar," 719"}; 2'b01 : foobar = {foobar," 720"}; 2'b10 : foobar = {foobar," 721"}; 2'b11 : foobar = {foobar," 722"}; endcase - 4'hc : + 4'hc : if (foo[26]) foobar = {foobar," 723"}; else foobar = {foobar," 724"}; - 4'hd : + 4'hd : case (foo[26:25]) 2'b00 : foobar = {foobar," 725"}; 2'b01 : foobar = {foobar," 726"}; 2'b10 : foobar = {foobar," 727"}; 2'b11 : foobar = {foobar," 728"}; endcase - 4'he : + 4'he : case (foo[26:25]) 2'b00 : foobar = {foobar," 729"}; 2'b01 : foobar = {foobar," 730"}; 2'b10 : foobar = {foobar," 731"}; 2'b11 : foobar = {foobar," 732"}; endcase - 4'hf : + 4'hf : case (foo[26:25]) 2'b00 : foobar = {foobar," 733"}; 2'b01 : foobar = {foobar," 734"}; 2'b10 : foobar = {foobar," 735"}; 2'b11 : foobar = {foobar," 736"}; endcase - endcase + endcase end endtask @@ -1680,198 +1680,198 @@ module t_case_write1_tasks (); inout [STRLEN*8: 1] foobar; // verilator no_inline_task begin - casez (foo[25:21]) - 5'h00 : - begin - ozoneae(foo[20:18], foobar); - foobar = {foobar," 737"}; - ozoneae(foo[17:15], foobar); - foobar = {foobar," 738"}; - end - 5'h01 : - begin - ozoneae(foo[20:18], foobar); - foobar = {foobar," 739"}; - ozoneae(foo[17:15], foobar); - foobar = {foobar," 740"}; - end - 5'h02 : - begin - ozoneae(foo[20:18], foobar); - foobar = {foobar," 741"}; - ozoneae(foo[17:15], foobar); - foobar = {foobar," 742"}; - end - 5'h03 : - begin - ozoneae(foo[20:18], foobar); - foobar = {foobar," 743"}; - ozoneae(foo[17:15], foobar); - foobar = {foobar," 744"}; - end - 5'h04 : - begin - ozoneae(foo[20:18], foobar); - foobar = {foobar," 745"}; - ozoneae(foo[17:15], foobar); - foobar = {foobar," 746"}; - end - 5'h05 : - begin - ozoneae(foo[20:18], foobar); - foobar = {foobar," 747"}; - ozoneae(foo[17:15], foobar); - foobar = {foobar," 748"}; - end - 5'h06 : - begin - ozoneae(foo[20:18], foobar); - foobar = {foobar," 749"}; - ozoneae(foo[17:15], foobar); - foobar = {foobar," 750"}; - end - 5'h07 : - begin - ozoneae(foo[20:18], foobar); - foobar = {foobar," 751"}; - ozoneae(foo[17:15], foobar); - foobar = {foobar," 752"}; - end - 5'h08 : - begin - ozoneae(foo[20:18], foobar); - foobar = {foobar," 753"}; - if (foo[ 6]) - foobar = {foobar," 754"}; - else - foobar = {foobar," 755"}; - end - 5'h09 : - begin - ozoneae(foo[20:18], foobar); - foobar = {foobar," 756"}; - ozoneae(foo[17:15], foobar); - foobar = {foobar," 757"}; - end - 5'h0a : - begin - ozoneae(foo[20:18], foobar); - foobar = {foobar," 758"}; - ozoneae(foo[17:15], foobar); - end - 5'h0b : - begin - ozoneae(foo[20:18], foobar); - foobar = {foobar," 759"}; - ozoneae(foo[17:15], foobar); - foobar = {foobar," 760"}; - end - 5'h0c : - begin - ozoneae(foo[20:18], foobar); - foobar = {foobar," 761"}; - end - 5'h0d : - begin - ozoneae(foo[20:18], foobar); - foobar = {foobar," 762"}; - ozoneae(foo[17:15], foobar); - foobar = {foobar," 763"}; - end - 5'h0e : - begin - ozoneae(foo[20:18], foobar); - foobar = {foobar," 764"}; - ozoneae(foo[17:15], foobar); - end - 5'h0f : - begin - ozoneae(foo[20:18], foobar); - foobar = {foobar," 765"}; - ozoneae(foo[17:15], foobar); - end - 5'h10 : - begin - ozoneae(foo[20:18], foobar); - foobar = {foobar," 766"}; - ozoneae(foo[17:15], foobar); - foobar = {foobar," 767"}; - end - 5'h11 : - begin - ozoneae(foo[20:18], foobar); - foobar = {foobar," 768"}; - ozoneae(foo[17:15], foobar); - foobar = {foobar," 769"}; - end - 5'h18 : - begin - ozoneae(foo[20:18], foobar); - foobar = {foobar," 770"}; - if (foo[ 6]) - foobar = {foobar," 771"}; - else - foobar = {foobar," 772"}; - end - 5'h1a : - begin - ozoneae(foo[20:18], foobar); - foobar = {foobar," 773"}; - ozoneae(foo[17:15], foobar); - foobar = {foobar," 774"}; - end - 5'h1b : - begin - ozoneae(foo[20:18], foobar); - foobar = {foobar," 775"}; - ozoneae(foo[17:15], foobar); - foobar = {foobar," 776"}; - if (foo[ 6]) - foobar = {foobar," 777"}; - else - foobar = {foobar," 778"}; - foobar = {foobar," 779"}; - end - 5'h1c : - begin - ozoneae(foo[20:18], foobar); - foobar = {foobar," 780"}; - end - 5'h1d : - begin - ozoneae(foo[20:18], foobar); - foobar = {foobar," 781"}; - if (foo[ 6]) - foobar = {foobar," 782"}; - else - foobar = {foobar," 783"}; - foobar = {foobar," 784"}; - end - 5'h1e : - begin - ozoneae(foo[20:18], foobar); - foobar = {foobar," 785"}; - if (foo[ 6]) - foobar = {foobar," 786"}; - else - foobar = {foobar," 787"}; - foobar = {foobar," 788"}; - end - 5'h1f : - begin - ozoneae(foo[20:18], foobar); - foobar = {foobar," 789"}; - ozoneae(foo[17:15], foobar); - foobar = {foobar," 790"}; - if (foo[ 6]) - foobar = {foobar," 791"}; - else - foobar = {foobar," 792"}; - foobar = {foobar," 793"}; - end - default : + casez (foo[25:21]) + 5'h00 : + begin + ozoneae(foo[20:18], foobar); + foobar = {foobar," 737"}; + ozoneae(foo[17:15], foobar); + foobar = {foobar," 738"}; + end + 5'h01 : + begin + ozoneae(foo[20:18], foobar); + foobar = {foobar," 739"}; + ozoneae(foo[17:15], foobar); + foobar = {foobar," 740"}; + end + 5'h02 : + begin + ozoneae(foo[20:18], foobar); + foobar = {foobar," 741"}; + ozoneae(foo[17:15], foobar); + foobar = {foobar," 742"}; + end + 5'h03 : + begin + ozoneae(foo[20:18], foobar); + foobar = {foobar," 743"}; + ozoneae(foo[17:15], foobar); + foobar = {foobar," 744"}; + end + 5'h04 : + begin + ozoneae(foo[20:18], foobar); + foobar = {foobar," 745"}; + ozoneae(foo[17:15], foobar); + foobar = {foobar," 746"}; + end + 5'h05 : + begin + ozoneae(foo[20:18], foobar); + foobar = {foobar," 747"}; + ozoneae(foo[17:15], foobar); + foobar = {foobar," 748"}; + end + 5'h06 : + begin + ozoneae(foo[20:18], foobar); + foobar = {foobar," 749"}; + ozoneae(foo[17:15], foobar); + foobar = {foobar," 750"}; + end + 5'h07 : + begin + ozoneae(foo[20:18], foobar); + foobar = {foobar," 751"}; + ozoneae(foo[17:15], foobar); + foobar = {foobar," 752"}; + end + 5'h08 : + begin + ozoneae(foo[20:18], foobar); + foobar = {foobar," 753"}; + if (foo[ 6]) + foobar = {foobar," 754"}; + else + foobar = {foobar," 755"}; + end + 5'h09 : + begin + ozoneae(foo[20:18], foobar); + foobar = {foobar," 756"}; + ozoneae(foo[17:15], foobar); + foobar = {foobar," 757"}; + end + 5'h0a : + begin + ozoneae(foo[20:18], foobar); + foobar = {foobar," 758"}; + ozoneae(foo[17:15], foobar); + end + 5'h0b : + begin + ozoneae(foo[20:18], foobar); + foobar = {foobar," 759"}; + ozoneae(foo[17:15], foobar); + foobar = {foobar," 760"}; + end + 5'h0c : + begin + ozoneae(foo[20:18], foobar); + foobar = {foobar," 761"}; + end + 5'h0d : + begin + ozoneae(foo[20:18], foobar); + foobar = {foobar," 762"}; + ozoneae(foo[17:15], foobar); + foobar = {foobar," 763"}; + end + 5'h0e : + begin + ozoneae(foo[20:18], foobar); + foobar = {foobar," 764"}; + ozoneae(foo[17:15], foobar); + end + 5'h0f : + begin + ozoneae(foo[20:18], foobar); + foobar = {foobar," 765"}; + ozoneae(foo[17:15], foobar); + end + 5'h10 : + begin + ozoneae(foo[20:18], foobar); + foobar = {foobar," 766"}; + ozoneae(foo[17:15], foobar); + foobar = {foobar," 767"}; + end + 5'h11 : + begin + ozoneae(foo[20:18], foobar); + foobar = {foobar," 768"}; + ozoneae(foo[17:15], foobar); + foobar = {foobar," 769"}; + end + 5'h18 : + begin + ozoneae(foo[20:18], foobar); + foobar = {foobar," 770"}; + if (foo[ 6]) + foobar = {foobar," 771"}; + else + foobar = {foobar," 772"}; + end + 5'h1a : + begin + ozoneae(foo[20:18], foobar); + foobar = {foobar," 773"}; + ozoneae(foo[17:15], foobar); + foobar = {foobar," 774"}; + end + 5'h1b : + begin + ozoneae(foo[20:18], foobar); + foobar = {foobar," 775"}; + ozoneae(foo[17:15], foobar); + foobar = {foobar," 776"}; + if (foo[ 6]) + foobar = {foobar," 777"}; + else + foobar = {foobar," 778"}; + foobar = {foobar," 779"}; + end + 5'h1c : + begin + ozoneae(foo[20:18], foobar); + foobar = {foobar," 780"}; + end + 5'h1d : + begin + ozoneae(foo[20:18], foobar); + foobar = {foobar," 781"}; + if (foo[ 6]) + foobar = {foobar," 782"}; + else + foobar = {foobar," 783"}; + foobar = {foobar," 784"}; + end + 5'h1e : + begin + ozoneae(foo[20:18], foobar); + foobar = {foobar," 785"}; + if (foo[ 6]) + foobar = {foobar," 786"}; + else + foobar = {foobar," 787"}; + foobar = {foobar," 788"}; + end + 5'h1f : + begin + ozoneae(foo[20:18], foobar); + foobar = {foobar," 789"}; + ozoneae(foo[17:15], foobar); + foobar = {foobar," 790"}; + if (foo[ 6]) + foobar = {foobar," 791"}; + else + foobar = {foobar," 792"}; + foobar = {foobar," 793"}; + end + default : foobar = {foobar," 794"}; - endcase + endcase end endtask @@ -1880,118 +1880,118 @@ module t_case_write1_tasks (); inout [STRLEN*8: 1] foobar; // verilator no_inline_task begin - case (foo[25:21]) - 5'h00, - 5'h01, - 5'h02: - begin - ozoneae(foo[20:18], foobar); - case (foo[22:21]) - 2'h0: foobar = {foobar," 795"}; - 2'h1: foobar = {foobar," 796"}; - 2'h2: foobar = {foobar," 797"}; - endcase - ozoneae(foo[17:15], foobar); - foobar = {foobar," 798"}; - if (foo[ 9]) - ozoneae(foo[ 8: 6], foobar); - else - ozonef3e_te(foo[ 8: 6], foobar); - foobar = {foobar," 799"}; - end - 5'h08, - 5'h09, - 5'h0d, - 5'h0e, - 5'h0f: - begin - ozoneae(foo[20:18], foobar); - foobar = {foobar," 800"}; - ozoneae(foo[17:15], foobar); - case (foo[23:21]) - 3'h0: foobar = {foobar," 801"}; - 3'h1: foobar = {foobar," 802"}; - 3'h5: foobar = {foobar," 803"}; - 3'h6: foobar = {foobar," 804"}; - 3'h7: foobar = {foobar," 805"}; - endcase - if (foo[ 9]) - ozoneae(foo[ 8: 6], foobar); - else - ozonef3e_te(foo[ 8: 6], foobar); - end - 5'h0a, - 5'h0b: - begin - ozoneae(foo[17:15], foobar); - if (foo[21]) - foobar = {foobar," 806"}; - else - foobar = {foobar," 807"}; - if (foo[ 9]) - ozoneae(foo[ 8: 6], foobar); - else - ozonef3e_te(foo[ 8: 6], foobar); - end - 5'h0c: - begin - ozoneae(foo[20:18], foobar); - foobar = {foobar," 808"}; - if (foo[ 9]) - ozoneae(foo[ 8: 6], foobar); - else - ozonef3e_te(foo[ 8: 6], foobar); - foobar = {foobar," 809"}; - ozoneae(foo[17:15], foobar); - end - 5'h10, - 5'h11, - 5'h12, - 5'h13: - begin - ozoneae(foo[20:18], foobar); - foobar = {foobar," 810"}; - ozoneae(foo[17:15], foobar); - case (foo[22:21]) - 2'h0, - 2'h2: - foobar = {foobar," 811"}; - 2'h1, - 2'h3: - foobar = {foobar," 812"}; - endcase - ozoneae(foo[ 8: 6], foobar); - foobar = {foobar," 813"}; - ozoneae((foo[20:18]+1), foobar); - foobar = {foobar," 814"}; - ozoneae((foo[17:15]+1), foobar); - case (foo[22:21]) - 2'h0, - 2'h3: - foobar = {foobar," 815"}; - 2'h1, - 2'h2: - foobar = {foobar," 816"}; - endcase - ozoneae((foo[ 8: 6]+1), foobar); - end - 5'h18: - begin - ozoneae(foo[20:18], foobar); - foobar = {foobar," 817"}; - ozoneae(foo[17:15], foobar); - foobar = {foobar," 818"}; - ozoneae(foo[ 8: 6], foobar); - foobar = {foobar," 819"}; - ozoneae(foo[20:18], foobar); - foobar = {foobar," 820"}; - ozoneae(foo[17:15], foobar); - foobar = {foobar," 821"}; - ozoneae(foo[ 8: 6], foobar); - end - default : + case (foo[25:21]) + 5'h00, + 5'h01, + 5'h02: + begin + ozoneae(foo[20:18], foobar); + case (foo[22:21]) + 2'h0: foobar = {foobar," 795"}; + 2'h1: foobar = {foobar," 796"}; + 2'h2: foobar = {foobar," 797"}; + endcase + ozoneae(foo[17:15], foobar); + foobar = {foobar," 798"}; + if (foo[ 9]) + ozoneae(foo[ 8: 6], foobar); + else + ozonef3e_te(foo[ 8: 6], foobar); + foobar = {foobar," 799"}; + end + 5'h08, + 5'h09, + 5'h0d, + 5'h0e, + 5'h0f: + begin + ozoneae(foo[20:18], foobar); + foobar = {foobar," 800"}; + ozoneae(foo[17:15], foobar); + case (foo[23:21]) + 3'h0: foobar = {foobar," 801"}; + 3'h1: foobar = {foobar," 802"}; + 3'h5: foobar = {foobar," 803"}; + 3'h6: foobar = {foobar," 804"}; + 3'h7: foobar = {foobar," 805"}; + endcase + if (foo[ 9]) + ozoneae(foo[ 8: 6], foobar); + else + ozonef3e_te(foo[ 8: 6], foobar); + end + 5'h0a, + 5'h0b: + begin + ozoneae(foo[17:15], foobar); + if (foo[21]) + foobar = {foobar," 806"}; + else + foobar = {foobar," 807"}; + if (foo[ 9]) + ozoneae(foo[ 8: 6], foobar); + else + ozonef3e_te(foo[ 8: 6], foobar); + end + 5'h0c: + begin + ozoneae(foo[20:18], foobar); + foobar = {foobar," 808"}; + if (foo[ 9]) + ozoneae(foo[ 8: 6], foobar); + else + ozonef3e_te(foo[ 8: 6], foobar); + foobar = {foobar," 809"}; + ozoneae(foo[17:15], foobar); + end + 5'h10, + 5'h11, + 5'h12, + 5'h13: + begin + ozoneae(foo[20:18], foobar); + foobar = {foobar," 810"}; + ozoneae(foo[17:15], foobar); + case (foo[22:21]) + 2'h0, + 2'h2: + foobar = {foobar," 811"}; + 2'h1, + 2'h3: + foobar = {foobar," 812"}; + endcase + ozoneae(foo[ 8: 6], foobar); + foobar = {foobar," 813"}; + ozoneae((foo[20:18]+1), foobar); + foobar = {foobar," 814"}; + ozoneae((foo[17:15]+1), foobar); + case (foo[22:21]) + 2'h0, + 2'h3: + foobar = {foobar," 815"}; + 2'h1, + 2'h2: + foobar = {foobar," 816"}; + endcase + ozoneae((foo[ 8: 6]+1), foobar); + end + 5'h18: + begin + ozoneae(foo[20:18], foobar); + foobar = {foobar," 817"}; + ozoneae(foo[17:15], foobar); + foobar = {foobar," 818"}; + ozoneae(foo[ 8: 6], foobar); + foobar = {foobar," 819"}; + ozoneae(foo[20:18], foobar); + foobar = {foobar," 820"}; + ozoneae(foo[17:15], foobar); + foobar = {foobar," 821"}; + ozoneae(foo[ 8: 6], foobar); + end + default : foobar = {foobar," 822"}; - endcase + endcase end endtask task ozonef3e_te; @@ -1999,12 +1999,12 @@ module t_case_write1_tasks (); inout [STRLEN*8: 1] foobar; // verilator no_inline_task begin - case (te) - 3'b100 : foobar = {foobar, " 823"}; - 3'b101 : foobar = {foobar, " 824"}; - 3'b110 : foobar = {foobar, " 825"}; - default: foobar = {foobar, " 826"}; - endcase + case (te) + 3'b100 : foobar = {foobar, " 823"}; + 3'b101 : foobar = {foobar, " 824"}; + 3'b110 : foobar = {foobar, " 825"}; + default: foobar = {foobar, " 826"}; + endcase end endtask task ozonearm; @@ -2012,16 +2012,16 @@ module t_case_write1_tasks (); inout [STRLEN*8: 1] foobar; // verilator no_inline_task begin - case (ate) - 3'b000 : foobar = {foobar, " 827"}; - 3'b001 : foobar = {foobar, " 828"}; - 3'b010 : foobar = {foobar, " 829"}; - 3'b011 : foobar = {foobar, " 830"}; - 3'b100 : foobar = {foobar, " 831"}; - 3'b101 : foobar = {foobar, " 832"}; - 3'b110 : foobar = {foobar, " 833"}; - 3'b111 : foobar = {foobar, " 834"}; - endcase + case (ate) + 3'b000 : foobar = {foobar, " 827"}; + 3'b001 : foobar = {foobar, " 828"}; + 3'b010 : foobar = {foobar, " 829"}; + 3'b011 : foobar = {foobar, " 830"}; + 3'b100 : foobar = {foobar, " 831"}; + 3'b101 : foobar = {foobar, " 832"}; + 3'b110 : foobar = {foobar, " 833"}; + 3'b111 : foobar = {foobar, " 834"}; + endcase end endtask task ozonebmuop; @@ -2029,136 +2029,136 @@ module t_case_write1_tasks (); inout [STRLEN*8: 1] foobar; // verilator no_inline_task begin - case (f4[ 4:0]) - 5'h00, - 5'h04 : + case (f4[ 4:0]) + 5'h00, + 5'h04 : foobar = {foobar, " 835"}; - 5'h01, - 5'h05 : + 5'h01, + 5'h05 : foobar = {foobar, " 836"}; - 5'h02, - 5'h06 : + 5'h02, + 5'h06 : foobar = {foobar, " 837"}; - 5'h03, - 5'h07 : + 5'h03, + 5'h07 : foobar = {foobar, " 838"}; - 5'h08, - 5'h18 : + 5'h08, + 5'h18 : foobar = {foobar, " 839"}; - 5'h09, - 5'h19 : + 5'h09, + 5'h19 : foobar = {foobar, " 840"}; - 5'h0a, - 5'h1a : + 5'h0a, + 5'h1a : foobar = {foobar, " 841"}; - 5'h0b : + 5'h0b : foobar = {foobar, " 842"}; - 5'h1b : + 5'h1b : foobar = {foobar, " 843"}; - 5'h0c, - 5'h1c : + 5'h0c, + 5'h1c : foobar = {foobar, " 844"}; - 5'h0d, - 5'h1d : + 5'h0d, + 5'h1d : foobar = {foobar, " 845"}; - 5'h1e : + 5'h1e : foobar = {foobar, " 846"}; - endcase + endcase end endtask task ozonef3; input [ 31:0] foo; inout [STRLEN*8: 1] foobar; - reg nacho; + reg nacho; // verilator no_inline_task begin : f3_body - nacho = 1'b0; - case (foo[24:21]) - 4'h0: + nacho = 1'b0; + case (foo[24:21]) + 4'h0: case (foo[26:25]) 2'b00 : foobar = {foobar, " 847"}; 2'b01 : foobar = {foobar, " 848"}; 2'b10 : foobar = {foobar, " 849"}; 2'b11 : foobar = {foobar, " 850"}; endcase - 4'h1: + 4'h1: case (foo[26:25]) 2'b00 : foobar = {foobar, " 851"}; 2'b01 : foobar = {foobar, " 852"}; 2'b10 : foobar = {foobar, " 853"}; 2'b11 : foobar = {foobar, " 854"}; endcase - 4'h2: + 4'h2: case (foo[26:25]) 2'b00 : foobar = {foobar, " 855"}; 2'b01 : foobar = {foobar, " 856"}; 2'b10 : foobar = {foobar, " 857"}; 2'b11 : foobar = {foobar, " 858"}; endcase - 4'h8, - 4'h9, - 4'hd, - 4'he, - 4'hf : + 4'h8, + 4'h9, + 4'hd, + 4'he, + 4'hf : case (foo[26:25]) - 2'b00 : foobar = {foobar, " 859"}; - 2'b01 : foobar = {foobar, " 860"}; - 2'b10 : foobar = {foobar, " 861"}; - 2'b11 : foobar = {foobar, " 862"}; + 2'b00 : foobar = {foobar, " 859"}; + 2'b01 : foobar = {foobar, " 860"}; + 2'b10 : foobar = {foobar, " 861"}; + 2'b11 : foobar = {foobar, " 862"}; endcase - 4'ha, - 4'hb : + 4'ha, + 4'hb : if (foo[25]) - foobar = {foobar, " 863"}; + foobar = {foobar, " 863"}; else - foobar = {foobar, " 864"}; - 4'hc : + foobar = {foobar, " 864"}; + 4'hc : if (foo[26]) foobar = {foobar, " 865"}; else foobar = {foobar, " 866"}; - default : - begin - foobar = {foobar, " 867"}; - nacho = 1'b1; - end - endcase - if (~nacho) - begin - case (foo[24:21]) - 4'h8 : - foobar = {foobar, " 868"}; - 4'h9 : - foobar = {foobar, " 869"}; - 4'ha, - 4'he : - foobar = {foobar, " 870"}; - 4'hb, - 4'hf : - foobar = {foobar, " 871"}; - 4'hd : - foobar = {foobar, " 872"}; - endcase - if (foo[20]) - case (foo[18:16]) - 3'b000 : foobar = {foobar, " 873"}; - 3'b100 : foobar = {foobar, " 874"}; - default: foobar = {foobar, " 875"}; - endcase - else - ozoneae(foo[18:16], foobar); - if (foo[24:21] === 4'hc) - if (foo[25]) - foobar = {foobar, " 876"}; - else - foobar = {foobar, " 877"}; - case (foo[24:21]) - 4'h0, - 4'h1, - 4'h2: - foobar = {foobar, " 878"}; - endcase - end + default : + begin + foobar = {foobar, " 867"}; + nacho = 1'b1; + end + endcase + if (~nacho) + begin + case (foo[24:21]) + 4'h8 : + foobar = {foobar, " 868"}; + 4'h9 : + foobar = {foobar, " 869"}; + 4'ha, + 4'he : + foobar = {foobar, " 870"}; + 4'hb, + 4'hf : + foobar = {foobar, " 871"}; + 4'hd : + foobar = {foobar, " 872"}; + endcase + if (foo[20]) + case (foo[18:16]) + 3'b000 : foobar = {foobar, " 873"}; + 3'b100 : foobar = {foobar, " 874"}; + default: foobar = {foobar, " 875"}; + endcase + else + ozoneae(foo[18:16], foobar); + if (foo[24:21] === 4'hc) + if (foo[25]) + foobar = {foobar, " 876"}; + else + foobar = {foobar, " 877"}; + case (foo[24:21]) + 4'h0, + 4'h1, + 4'h2: + foobar = {foobar, " 878"}; + endcase + end end endtask task ozonerx; @@ -2166,17 +2166,17 @@ module t_case_write1_tasks (); inout [STRLEN*8: 1] foobar; // verilator no_inline_task begin - case (foo[19:18]) - 2'h0 : foobar = {foobar, " 879"}; - 2'h1 : foobar = {foobar, " 880"}; - 2'h2 : foobar = {foobar, " 881"}; - 2'h3 : foobar = {foobar, " 882"}; - endcase - case (foo[17:16]) - 2'h1 : foobar = {foobar, " 883"}; - 2'h2 : foobar = {foobar, " 884"}; - 2'h3 : foobar = {foobar, " 885"}; - endcase + case (foo[19:18]) + 2'h0 : foobar = {foobar, " 879"}; + 2'h1 : foobar = {foobar, " 880"}; + 2'h2 : foobar = {foobar, " 881"}; + 2'h3 : foobar = {foobar, " 882"}; + endcase + case (foo[17:16]) + 2'h1 : foobar = {foobar, " 883"}; + 2'h2 : foobar = {foobar, " 884"}; + 2'h3 : foobar = {foobar, " 885"}; + endcase end endtask task ozonerme; @@ -2184,47 +2184,47 @@ module t_case_write1_tasks (); inout [STRLEN*8: 1] foobar; // verilator no_inline_task begin - case (rme) - 3'h0 : foobar = {foobar, " 886"}; - 3'h1 : foobar = {foobar, " 887"}; - 3'h2 : foobar = {foobar, " 888"}; - 3'h3 : foobar = {foobar, " 889"}; - 3'h4 : foobar = {foobar, " 890"}; - 3'h5 : foobar = {foobar, " 891"}; - 3'h6 : foobar = {foobar, " 892"}; - 3'h7 : foobar = {foobar, " 893"}; - endcase + case (rme) + 3'h0 : foobar = {foobar, " 886"}; + 3'h1 : foobar = {foobar, " 887"}; + 3'h2 : foobar = {foobar, " 888"}; + 3'h3 : foobar = {foobar, " 889"}; + 3'h4 : foobar = {foobar, " 890"}; + 3'h5 : foobar = {foobar, " 891"}; + 3'h6 : foobar = {foobar, " 892"}; + 3'h7 : foobar = {foobar, " 893"}; + endcase end endtask task ozoneye; input [5:0] ye; - input l; + input l; inout [STRLEN*8: 1] foobar; // verilator no_inline_task begin - foobar = {foobar, " 894"}; - ozonerme(ye[5:3],foobar); - case ({ye[ 2:0], l}) - 4'h2, - 4'ha: foobar = {foobar, " 895"}; - 4'h4, - 4'hb: foobar = {foobar, " 896"}; - 4'h6, - 4'he: foobar = {foobar, " 897"}; - 4'h8, - 4'hc: foobar = {foobar, " 898"}; - endcase + foobar = {foobar, " 894"}; + ozonerme(ye[5:3],foobar); + case ({ye[ 2:0], l}) + 4'h2, + 4'ha: foobar = {foobar, " 895"}; + 4'h4, + 4'hb: foobar = {foobar, " 896"}; + 4'h6, + 4'he: foobar = {foobar, " 897"}; + 4'h8, + 4'hc: foobar = {foobar, " 898"}; + endcase end endtask task ozonef1e_ye; input [5:0] ye; - input l; + input l; inout [STRLEN*8: 1] foobar; // verilator no_inline_task begin - foobar = {foobar, " 899"}; - ozonerme(ye[5:3],foobar); - ozonef1e_inc_dec(ye[5:0], l ,foobar); + foobar = {foobar, " 899"}; + ozonerme(ye[5:3],foobar); + ozonef1e_inc_dec(ye[5:0], l ,foobar); end endtask task ozonef1e_h; @@ -2232,31 +2232,31 @@ module t_case_write1_tasks (); inout [STRLEN*8: 1] foobar; // verilator no_inline_task begin - if (e[ 2:0] <= 3'h4) - foobar = {foobar, " 900"}; + if (e[ 2:0] <= 3'h4) + foobar = {foobar, " 900"}; end endtask task ozonef1e_inc_dec; input [5:0] ye; - input l; + input l; inout [STRLEN*8: 1] foobar; // verilator no_inline_task begin - case ({ye[ 2:0], l}) - 4'h2, - 4'h3, - 4'ha: foobar = {foobar, " 901"}; - 4'h4, - 4'h5, - 4'hb: foobar = {foobar, " 902"}; - 4'h6, - 4'h7, - 4'he: foobar = {foobar, " 903"}; - 4'h8, - 4'h9, - 4'hc: foobar = {foobar, " 904"}; - 4'hf: foobar = {foobar, " 905"}; - endcase + case ({ye[ 2:0], l}) + 4'h2, + 4'h3, + 4'ha: foobar = {foobar, " 901"}; + 4'h4, + 4'h5, + 4'hb: foobar = {foobar, " 902"}; + 4'h6, + 4'h7, + 4'he: foobar = {foobar, " 903"}; + 4'h8, + 4'h9, + 4'hc: foobar = {foobar, " 904"}; + 4'hf: foobar = {foobar, " 905"}; + endcase end endtask task ozonef1e_hl; @@ -2265,18 +2265,18 @@ module t_case_write1_tasks (); inout [STRLEN*8: 1] foobar; // verilator no_inline_task begin - case ({e[ 2:0], l}) - 4'h0, - 4'h2, - 4'h4, - 4'h6, - 4'h8: foobar = {foobar, " 906"}; - 4'h1, - 4'h3, - 4'h5, - 4'h7, - 4'h9: foobar = {foobar, " 907"}; - endcase + case ({e[ 2:0], l}) + 4'h0, + 4'h2, + 4'h4, + 4'h6, + 4'h8: foobar = {foobar, " 906"}; + 4'h1, + 4'h3, + 4'h5, + 4'h7, + 4'h9: foobar = {foobar, " 907"}; + endcase end endtask task ozonexe; @@ -2284,19 +2284,19 @@ module t_case_write1_tasks (); inout [STRLEN*8: 1] foobar; // verilator no_inline_task begin - case (xe[3]) - 1'b0 : foobar = {foobar, " 908"}; - 1'b1 : foobar = {foobar, " 909"}; - endcase - case (xe[ 2:0]) - 3'h1, - 3'h5: foobar = {foobar, " 910"}; - 3'h2, - 3'h6: foobar = {foobar, " 911"}; - 3'h3, - 3'h7: foobar = {foobar, " 912"}; - 3'h4: foobar = {foobar, " 913"}; - endcase + case (xe[3]) + 1'b0 : foobar = {foobar, " 908"}; + 1'b1 : foobar = {foobar, " 909"}; + endcase + case (xe[ 2:0]) + 3'h1, + 3'h5: foobar = {foobar, " 910"}; + 3'h2, + 3'h6: foobar = {foobar, " 911"}; + 3'h3, + 3'h7: foobar = {foobar, " 912"}; + 3'h4: foobar = {foobar, " 913"}; + endcase end endtask task ozonerp; @@ -2304,16 +2304,16 @@ module t_case_write1_tasks (); inout [STRLEN*8: 1] foobar; // verilator no_inline_task begin - case (rp) - 3'h0 : foobar = {foobar, " 914"}; - 3'h1 : foobar = {foobar, " 915"}; - 3'h2 : foobar = {foobar, " 916"}; - 3'h3 : foobar = {foobar, " 917"}; - 3'h4 : foobar = {foobar, " 918"}; - 3'h5 : foobar = {foobar, " 919"}; - 3'h6 : foobar = {foobar, " 920"}; - 3'h7 : foobar = {foobar, " 921"}; - endcase + case (rp) + 3'h0 : foobar = {foobar, " 914"}; + 3'h1 : foobar = {foobar, " 915"}; + 3'h2 : foobar = {foobar, " 916"}; + 3'h3 : foobar = {foobar, " 917"}; + 3'h4 : foobar = {foobar, " 918"}; + 3'h5 : foobar = {foobar, " 919"}; + 3'h6 : foobar = {foobar, " 920"}; + 3'h7 : foobar = {foobar, " 921"}; + endcase end endtask task ozonery; @@ -2321,24 +2321,24 @@ module t_case_write1_tasks (); inout [STRLEN*8: 1] foobar; // verilator no_inline_task begin - case (ry) - 4'h0 : foobar = {foobar, " 922"}; - 4'h1 : foobar = {foobar, " 923"}; - 4'h2 : foobar = {foobar, " 924"}; - 4'h3 : foobar = {foobar, " 925"}; - 4'h4 : foobar = {foobar, " 926"}; - 4'h5 : foobar = {foobar, " 927"}; - 4'h6 : foobar = {foobar, " 928"}; - 4'h7 : foobar = {foobar, " 929"}; - 4'h8 : foobar = {foobar, " 930"}; - 4'h9 : foobar = {foobar, " 931"}; - 4'ha : foobar = {foobar, " 932"}; - 4'hb : foobar = {foobar, " 933"}; - 4'hc : foobar = {foobar, " 934"}; - 4'hd : foobar = {foobar, " 935"}; - 4'he : foobar = {foobar, " 936"}; - 4'hf : foobar = {foobar, " 937"}; - endcase + case (ry) + 4'h0 : foobar = {foobar, " 922"}; + 4'h1 : foobar = {foobar, " 923"}; + 4'h2 : foobar = {foobar, " 924"}; + 4'h3 : foobar = {foobar, " 925"}; + 4'h4 : foobar = {foobar, " 926"}; + 4'h5 : foobar = {foobar, " 927"}; + 4'h6 : foobar = {foobar, " 928"}; + 4'h7 : foobar = {foobar, " 929"}; + 4'h8 : foobar = {foobar, " 930"}; + 4'h9 : foobar = {foobar, " 931"}; + 4'ha : foobar = {foobar, " 932"}; + 4'hb : foobar = {foobar, " 933"}; + 4'hc : foobar = {foobar, " 934"}; + 4'hd : foobar = {foobar, " 935"}; + 4'he : foobar = {foobar, " 936"}; + 4'hf : foobar = {foobar, " 937"}; + endcase end endtask task ozonearx; @@ -2346,12 +2346,12 @@ module t_case_write1_tasks (); inout [STRLEN*8: 1] foobar; // verilator no_inline_task begin - case (foo[1:0]) - 2'h0 : foobar = {foobar, " 938"}; - 2'h1 : foobar = {foobar, " 939"}; - 2'h2 : foobar = {foobar, " 940"}; - 2'h3 : foobar = {foobar, " 941"}; - endcase + case (foo[1:0]) + 2'h0 : foobar = {foobar, " 938"}; + 2'h1 : foobar = {foobar, " 939"}; + 2'h2 : foobar = {foobar, " 940"}; + 2'h3 : foobar = {foobar, " 941"}; + endcase end endtask task ozonef3f4imop; @@ -2359,19 +2359,19 @@ module t_case_write1_tasks (); inout [STRLEN*8: 1] foobar; // verilator no_inline_task begin - casez (f3f4iml) - 5'b000??: foobar = {foobar, " 942"}; - 5'b001??: foobar = {foobar, " 943"}; - 5'b?10??: foobar = {foobar, " 944"}; - 5'b0110?: foobar = {foobar, " 945"}; - 5'b01110: foobar = {foobar, " 946"}; - 5'b01111: foobar = {foobar, " 947"}; - 5'b10???: foobar = {foobar, " 948"}; - 5'b11100: foobar = {foobar, " 949"}; - 5'b11101: foobar = {foobar, " 950"}; - 5'b11110: foobar = {foobar, " 951"}; - 5'b11111: foobar = {foobar, " 952"}; - endcase + casez (f3f4iml) + 5'b000??: foobar = {foobar, " 942"}; + 5'b001??: foobar = {foobar, " 943"}; + 5'b?10??: foobar = {foobar, " 944"}; + 5'b0110?: foobar = {foobar, " 945"}; + 5'b01110: foobar = {foobar, " 946"}; + 5'b01111: foobar = {foobar, " 947"}; + 5'b10???: foobar = {foobar, " 948"}; + 5'b11100: foobar = {foobar, " 949"}; + 5'b11101: foobar = {foobar, " 950"}; + 5'b11110: foobar = {foobar, " 951"}; + 5'b11111: foobar = {foobar, " 952"}; + endcase end endtask task ozonecon; @@ -2379,40 +2379,40 @@ module t_case_write1_tasks (); inout [STRLEN*8: 1] foobar; // verilator no_inline_task begin - case (con) - 5'h00 : foobar = {foobar, " 953"}; - 5'h01 : foobar = {foobar, " 954"}; - 5'h02 : foobar = {foobar, " 955"}; - 5'h03 : foobar = {foobar, " 956"}; - 5'h04 : foobar = {foobar, " 957"}; - 5'h05 : foobar = {foobar, " 958"}; - 5'h06 : foobar = {foobar, " 959"}; - 5'h07 : foobar = {foobar, " 960"}; - 5'h08 : foobar = {foobar, " 961"}; - 5'h09 : foobar = {foobar, " 962"}; - 5'h0a : foobar = {foobar, " 963"}; - 5'h0b : foobar = {foobar, " 964"}; - 5'h0c : foobar = {foobar, " 965"}; - 5'h0d : foobar = {foobar, " 966"}; - 5'h0e : foobar = {foobar, " 967"}; - 5'h0f : foobar = {foobar, " 968"}; - 5'h10 : foobar = {foobar, " 969"}; - 5'h11 : foobar = {foobar, " 970"}; - 5'h12 : foobar = {foobar, " 971"}; - 5'h13 : foobar = {foobar, " 972"}; - 5'h14 : foobar = {foobar, " 973"}; - 5'h15 : foobar = {foobar, " 974"}; - 5'h16 : foobar = {foobar, " 975"}; - 5'h17 : foobar = {foobar, " 976"}; - 5'h18 : foobar = {foobar, " 977"}; - 5'h19 : foobar = {foobar, " 978"}; - 5'h1a : foobar = {foobar, " 979"}; - 5'h1b : foobar = {foobar, " 980"}; - 5'h1c : foobar = {foobar, " 981"}; - 5'h1d : foobar = {foobar, " 982"}; - 5'h1e : foobar = {foobar, " 983"}; - 5'h1f : foobar = {foobar, " 984"}; - endcase + case (con) + 5'h00 : foobar = {foobar, " 953"}; + 5'h01 : foobar = {foobar, " 954"}; + 5'h02 : foobar = {foobar, " 955"}; + 5'h03 : foobar = {foobar, " 956"}; + 5'h04 : foobar = {foobar, " 957"}; + 5'h05 : foobar = {foobar, " 958"}; + 5'h06 : foobar = {foobar, " 959"}; + 5'h07 : foobar = {foobar, " 960"}; + 5'h08 : foobar = {foobar, " 961"}; + 5'h09 : foobar = {foobar, " 962"}; + 5'h0a : foobar = {foobar, " 963"}; + 5'h0b : foobar = {foobar, " 964"}; + 5'h0c : foobar = {foobar, " 965"}; + 5'h0d : foobar = {foobar, " 966"}; + 5'h0e : foobar = {foobar, " 967"}; + 5'h0f : foobar = {foobar, " 968"}; + 5'h10 : foobar = {foobar, " 969"}; + 5'h11 : foobar = {foobar, " 970"}; + 5'h12 : foobar = {foobar, " 971"}; + 5'h13 : foobar = {foobar, " 972"}; + 5'h14 : foobar = {foobar, " 973"}; + 5'h15 : foobar = {foobar, " 974"}; + 5'h16 : foobar = {foobar, " 975"}; + 5'h17 : foobar = {foobar, " 976"}; + 5'h18 : foobar = {foobar, " 977"}; + 5'h19 : foobar = {foobar, " 978"}; + 5'h1a : foobar = {foobar, " 979"}; + 5'h1b : foobar = {foobar, " 980"}; + 5'h1c : foobar = {foobar, " 981"}; + 5'h1d : foobar = {foobar, " 982"}; + 5'h1e : foobar = {foobar, " 983"}; + 5'h1f : foobar = {foobar, " 984"}; + endcase end endtask task ozonedr; @@ -2420,24 +2420,24 @@ module t_case_write1_tasks (); inout [STRLEN*8: 1] foobar; // verilator no_inline_task begin - case (foo[ 9: 6]) - 4'h0 : foobar = {foobar, " 985"}; - 4'h1 : foobar = {foobar, " 986"}; - 4'h2 : foobar = {foobar, " 987"}; - 4'h3 : foobar = {foobar, " 988"}; - 4'h4 : foobar = {foobar, " 989"}; - 4'h5 : foobar = {foobar, " 990"}; - 4'h6 : foobar = {foobar, " 991"}; - 4'h7 : foobar = {foobar, " 992"}; - 4'h8 : foobar = {foobar, " 993"}; - 4'h9 : foobar = {foobar, " 994"}; - 4'ha : foobar = {foobar, " 995"}; - 4'hb : foobar = {foobar, " 996"}; - 4'hc : foobar = {foobar, " 997"}; - 4'hd : foobar = {foobar, " 998"}; - 4'he : foobar = {foobar, " 999"}; - 4'hf : foobar = {foobar, " 1000"}; - endcase + case (foo[ 9: 6]) + 4'h0 : foobar = {foobar, " 985"}; + 4'h1 : foobar = {foobar, " 986"}; + 4'h2 : foobar = {foobar, " 987"}; + 4'h3 : foobar = {foobar, " 988"}; + 4'h4 : foobar = {foobar, " 989"}; + 4'h5 : foobar = {foobar, " 990"}; + 4'h6 : foobar = {foobar, " 991"}; + 4'h7 : foobar = {foobar, " 992"}; + 4'h8 : foobar = {foobar, " 993"}; + 4'h9 : foobar = {foobar, " 994"}; + 4'ha : foobar = {foobar, " 995"}; + 4'hb : foobar = {foobar, " 996"}; + 4'hc : foobar = {foobar, " 997"}; + 4'hd : foobar = {foobar, " 998"}; + 4'he : foobar = {foobar, " 999"}; + 4'hf : foobar = {foobar, " 1000"}; + endcase end endtask task ozoneshift; @@ -2445,12 +2445,12 @@ module t_case_write1_tasks (); inout [STRLEN*8: 1] foobar; // verilator no_inline_task begin - case (foo[ 4: 3]) - 2'h0 : foobar = {foobar, " 1001"}; - 2'h1 : foobar = {foobar, " 1002"}; - 2'h2 : foobar = {foobar, " 1003"}; - 2'h3 : foobar = {foobar, " 1004"}; - endcase + case (foo[ 4: 3]) + 2'h0 : foobar = {foobar, " 1001"}; + 2'h1 : foobar = {foobar, " 1002"}; + 2'h2 : foobar = {foobar, " 1003"}; + 2'h3 : foobar = {foobar, " 1004"}; + endcase end endtask task ozoneacc; @@ -2458,10 +2458,10 @@ module t_case_write1_tasks (); inout [STRLEN*8: 1] foobar; // verilator no_inline_task begin - case (foo) - 2'h0 : foobar = {foobar, " 1005"}; - 2'h1 : foobar = {foobar, " 1006"}; - endcase + case (foo) + 2'h0 : foobar = {foobar, " 1005"}; + 2'h1 : foobar = {foobar, " 1006"}; + endcase end endtask task ozonehl; @@ -2469,31 +2469,31 @@ module t_case_write1_tasks (); inout [STRLEN*8: 1] foobar; // verilator no_inline_task begin - case (foo) - 2'h0 : foobar = {foobar, " 1007"}; - 2'h1 : foobar = {foobar, " 1008"}; - endcase + case (foo) + 2'h0 : foobar = {foobar, " 1007"}; + 2'h1 : foobar = {foobar, " 1008"}; + endcase end endtask task dude; inout [STRLEN*8: 1] foobar; - reg [ 7:0] temp; - integer i; - reg nacho; + reg [ 7:0] temp; + integer i; + reg nacho; // verilator no_inline_task begin : justify_block - nacho = 1'b0; - for (i=STRLEN-1; i>1; i=i-1) - begin - temp = foobar>>((STRLEN-1)*8); - if (temp || nacho) - nacho = 1'b1; - else - begin - foobar = foobar<<8; - foobar[8:1] = 32; - end - end + nacho = 1'b0; + for (i=STRLEN-1; i>1; i=i-1) + begin + temp = foobar>>((STRLEN-1)*8); + if (temp || nacho) + nacho = 1'b1; + else + begin + foobar = foobar<<8; + foobar[8:1] = 32; + end + end end endtask @@ -2503,1289 +2503,1289 @@ module t_case_write1_tasks (); reg [STRLEN*8: 1] foobar; // verilator no_inline_task begin - foobar = " 1009"; - if (&foo === 1'bx) - $fwrite(fd, " 1010"); - else - casez ( {foo[31:26], foo[19:15], foo[5:0]} ) + foobar = " 1009"; + if (&foo === 1'bx) + $fwrite(fd, " 1010"); + else + casez ( {foo[31:26], foo[19:15], foo[5:0]} ) 17'b00_111?_?_????_??_???? : begin - ozonef1(foo, foobar); - foobar = {foobar, " 1011"}; - ozoneacc(~foo[26], foobar); - ozonehl(foo[20], foobar); - foobar = {foobar, " 1012"}; - ozonerx(foo, foobar); - dude(foobar); - $fwrite (fd, " 1013:%s", foobar); + ozonef1(foo, foobar); + foobar = {foobar, " 1011"}; + ozoneacc(~foo[26], foobar); + ozonehl(foo[20], foobar); + foobar = {foobar, " 1012"}; + ozonerx(foo, foobar); + dude(foobar); + $fwrite (fd, " 1013:%s", foobar); end 17'b01_001?_?_????_??_???? : begin - ozonef1(foo, foobar); - foobar = {foobar, " 1014"}; - ozonerx(foo, foobar); - foobar = {foobar, " 1015"}; - foobar = {foobar, " 1016"}; - ozonehl(foo[20], foobar); - dude(foobar); - $fwrite (fd, " 1017:%s", foobar); + ozonef1(foo, foobar); + foobar = {foobar, " 1014"}; + ozonerx(foo, foobar); + foobar = {foobar, " 1015"}; + foobar = {foobar, " 1016"}; + ozonehl(foo[20], foobar); + dude(foobar); + $fwrite (fd, " 1017:%s", foobar); end 17'b10_100?_?_????_??_???? : begin - ozonef1(foo, foobar); - foobar = {foobar, " 1018"}; - ozonerx(foo, foobar); - foobar = {foobar, " 1019"}; - foobar = {foobar, " 1020"}; - ozonehl(foo[20], foobar); - dude(foobar); - $fwrite (fd, " 1021:%s", foobar); + ozonef1(foo, foobar); + foobar = {foobar, " 1018"}; + ozonerx(foo, foobar); + foobar = {foobar, " 1019"}; + foobar = {foobar, " 1020"}; + ozonehl(foo[20], foobar); + dude(foobar); + $fwrite (fd, " 1021:%s", foobar); end 17'b10_101?_?_????_??_???? : begin - ozonef1(foo, foobar); - foobar = {foobar, " 1022"}; - if (foo[20]) - begin - foobar = {foobar, " 1023"}; - ozoneacc(foo[18], foobar); - foobar = {foobar, " 1024"}; - foobar = {foobar, " 1025"}; - if (foo[19]) - foobar = {foobar, " 1026"}; - else - foobar = {foobar, " 1027"}; - end - else - ozonerx(foo, foobar); - dude(foobar); - $fwrite (fd, " 1028:%s", foobar); + ozonef1(foo, foobar); + foobar = {foobar, " 1022"}; + if (foo[20]) + begin + foobar = {foobar, " 1023"}; + ozoneacc(foo[18], foobar); + foobar = {foobar, " 1024"}; + foobar = {foobar, " 1025"}; + if (foo[19]) + foobar = {foobar, " 1026"}; + else + foobar = {foobar, " 1027"}; + end + else + ozonerx(foo, foobar); + dude(foobar); + $fwrite (fd, " 1028:%s", foobar); end 17'b10_110?_?_????_??_???? : begin - ozonef1(foo, foobar); - foobar = {foobar, " 1029"}; - foobar = {foobar, " 1030"}; - ozonehl(foo[20], foobar); - foobar = {foobar, " 1031"}; - ozonerx(foo, foobar); - dude(foobar); - $fwrite (fd, " 1032:%s", foobar); + ozonef1(foo, foobar); + foobar = {foobar, " 1029"}; + foobar = {foobar, " 1030"}; + ozonehl(foo[20], foobar); + foobar = {foobar, " 1031"}; + ozonerx(foo, foobar); + dude(foobar); + $fwrite (fd, " 1032:%s", foobar); end 17'b10_111?_?_????_??_???? : begin - ozonef1(foo, foobar); - foobar = {foobar, " 1033"}; - foobar = {foobar, " 1034"}; - ozonehl(foo[20], foobar); - foobar = {foobar, " 1035"}; - ozonerx(foo, foobar); - dude(foobar); - $fwrite (fd, " 1036:%s", foobar); + ozonef1(foo, foobar); + foobar = {foobar, " 1033"}; + foobar = {foobar, " 1034"}; + ozonehl(foo[20], foobar); + foobar = {foobar, " 1035"}; + ozonerx(foo, foobar); + dude(foobar); + $fwrite (fd, " 1036:%s", foobar); end 17'b11_001?_?_????_??_???? : begin - ozonef1(foo, foobar); - foobar = {foobar, " 1037"}; - ozonerx(foo, foobar); - foobar = {foobar, " 1038"}; - foobar = {foobar, " 1039"}; - ozonehl(foo[20], foobar); - dude(foobar); - $fwrite (fd, " 1040:%s", foobar); + ozonef1(foo, foobar); + foobar = {foobar, " 1037"}; + ozonerx(foo, foobar); + foobar = {foobar, " 1038"}; + foobar = {foobar, " 1039"}; + ozonehl(foo[20], foobar); + dude(foobar); + $fwrite (fd, " 1040:%s", foobar); end 17'b11_111?_?_????_??_???? : begin - ozonef1(foo, foobar); - foobar = {foobar, " 1041"}; - foobar = {foobar, " 1042"}; - ozonerx(foo, foobar); - foobar = {foobar, " 1043"}; - if (foo[20]) - foobar = {foobar, " 1044"}; - else - foobar = {foobar, " 1045"}; - dude(foobar); - $fwrite (fd, " 1046:%s", foobar); + ozonef1(foo, foobar); + foobar = {foobar, " 1041"}; + foobar = {foobar, " 1042"}; + ozonerx(foo, foobar); + foobar = {foobar, " 1043"}; + if (foo[20]) + foobar = {foobar, " 1044"}; + else + foobar = {foobar, " 1045"}; + dude(foobar); + $fwrite (fd, " 1046:%s", foobar); end 17'b00_10??_?_????_?1_1111 : casez (foo[11: 5]) - 7'b??_0_010_0: - begin - foobar = " 1047"; - ozonecon(foo[14:10], foobar); - foobar = {foobar, " 1048"}; - ozonef1e(foo, foobar); - dude(foobar); - $fwrite (fd, " 1049:%s", foobar); - end - 7'b00_?_110_?: - begin - ozonef1e(foo, foobar); - foobar = {foobar, " 1050"}; - case ({foo[ 9],foo[ 5]}) - 2'b00: - begin - foobar = {foobar, " 1051"}; - ozoneae(foo[14:12], foobar); - ozonehl(foo[ 5], foobar); - end - 2'b01: - begin - foobar = {foobar, " 1052"}; - ozoneae(foo[14:12], foobar); - ozonehl(foo[ 5], foobar); - end - 2'b10: - begin - foobar = {foobar, " 1053"}; - ozoneae(foo[14:12], foobar); - end - 2'b11: foobar = {foobar, " 1054"}; - endcase - dude(foobar); - $fwrite (fd, " 1055:%s", foobar); - end - 7'b01_?_110_?: - begin - ozonef1e(foo, foobar); - foobar = {foobar, " 1056"}; - case ({foo[ 9],foo[ 5]}) - 2'b00: - begin - ozoneae(foo[14:12], foobar); - ozonehl(foo[ 5], foobar); - foobar = {foobar, " 1057"}; - end - 2'b01: - begin - ozoneae(foo[14:12], foobar); - ozonehl(foo[ 5], foobar); - foobar = {foobar, " 1058"}; - end - 2'b10: - begin - ozoneae(foo[14:12], foobar); - foobar = {foobar, " 1059"}; - end - 2'b11: foobar = {foobar, " 1060"}; - endcase - dude(foobar); - $fwrite (fd, " 1061:%s", foobar); - end - 7'b10_0_110_0: - begin - ozonef1e(foo, foobar); - foobar = {foobar, " 1062"}; - foobar = {foobar, " 1063"}; - if (foo[12]) - foobar = {foobar, " 1064"}; - else - ozonerab({4'b1001, foo[14:12]}, foobar); - dude(foobar); - $fwrite (fd, " 1065:%s", foobar); - end - 7'b10_0_110_1: - begin - ozonef1e(foo, foobar); - foobar = {foobar, " 1066"}; - if (foo[12]) - foobar = {foobar, " 1067"}; - else - ozonerab({4'b1001, foo[14:12]}, foobar); - foobar = {foobar, " 1068"}; - dude(foobar); - $fwrite (fd, " 1069:%s", foobar); - end - 7'b??_?_000_?: - begin - ozonef1e(foo, foobar); - foobar = {foobar, " 1070"}; - foobar = {foobar, " 1071"}; - ozonef1e_hl(foo[11:9],foo[ 5],foobar); - foobar = {foobar, " 1072"}; - ozonef1e_ye(foo[14:9],foo[ 5],foobar); - dude(foobar); - $fwrite (fd, " 1073:%s", foobar); - end - 7'b??_?_100_?: - begin - ozonef1e(foo, foobar); - foobar = {foobar, " 1074"}; - foobar = {foobar, " 1075"}; - ozonef1e_hl(foo[11:9],foo[ 5],foobar); - foobar = {foobar, " 1076"}; - ozonef1e_ye(foo[14:9],foo[ 5],foobar); - dude(foobar); - $fwrite (fd, " 1077:%s", foobar); - end - 7'b??_?_001_?: - begin - ozonef1e(foo, foobar); - foobar = {foobar, " 1078"}; - ozonef1e_ye(foo[14:9],foo[ 5],foobar); - foobar = {foobar, " 1079"}; - foobar = {foobar, " 1080"}; - ozonef1e_hl(foo[11:9],foo[ 5],foobar); - dude(foobar); - $fwrite (fd, " 1081:%s", foobar); - end - 7'b??_?_011_?: - begin - ozonef1e(foo, foobar); - foobar = {foobar, " 1082"}; - ozonef1e_ye(foo[14:9],foo[ 5],foobar); - foobar = {foobar, " 1083"}; - foobar = {foobar, " 1084"}; - ozonef1e_hl(foo[11:9],foo[ 5],foobar); - dude(foobar); - $fwrite (fd, " 1085:%s", foobar); - end - 7'b??_?_101_?: - begin - ozonef1e(foo, foobar); - foobar = {foobar, " 1086"}; - ozonef1e_ye(foo[14:9],foo[ 5],foobar); - dude(foobar); - $fwrite (fd, " 1087:%s", foobar); - end + 7'b??_0_010_0: + begin + foobar = " 1047"; + ozonecon(foo[14:10], foobar); + foobar = {foobar, " 1048"}; + ozonef1e(foo, foobar); + dude(foobar); + $fwrite (fd, " 1049:%s", foobar); + end + 7'b00_?_110_?: + begin + ozonef1e(foo, foobar); + foobar = {foobar, " 1050"}; + case ({foo[ 9],foo[ 5]}) + 2'b00: + begin + foobar = {foobar, " 1051"}; + ozoneae(foo[14:12], foobar); + ozonehl(foo[ 5], foobar); + end + 2'b01: + begin + foobar = {foobar, " 1052"}; + ozoneae(foo[14:12], foobar); + ozonehl(foo[ 5], foobar); + end + 2'b10: + begin + foobar = {foobar, " 1053"}; + ozoneae(foo[14:12], foobar); + end + 2'b11: foobar = {foobar, " 1054"}; + endcase + dude(foobar); + $fwrite (fd, " 1055:%s", foobar); + end + 7'b01_?_110_?: + begin + ozonef1e(foo, foobar); + foobar = {foobar, " 1056"}; + case ({foo[ 9],foo[ 5]}) + 2'b00: + begin + ozoneae(foo[14:12], foobar); + ozonehl(foo[ 5], foobar); + foobar = {foobar, " 1057"}; + end + 2'b01: + begin + ozoneae(foo[14:12], foobar); + ozonehl(foo[ 5], foobar); + foobar = {foobar, " 1058"}; + end + 2'b10: + begin + ozoneae(foo[14:12], foobar); + foobar = {foobar, " 1059"}; + end + 2'b11: foobar = {foobar, " 1060"}; + endcase + dude(foobar); + $fwrite (fd, " 1061:%s", foobar); + end + 7'b10_0_110_0: + begin + ozonef1e(foo, foobar); + foobar = {foobar, " 1062"}; + foobar = {foobar, " 1063"}; + if (foo[12]) + foobar = {foobar, " 1064"}; + else + ozonerab({4'b1001, foo[14:12]}, foobar); + dude(foobar); + $fwrite (fd, " 1065:%s", foobar); + end + 7'b10_0_110_1: + begin + ozonef1e(foo, foobar); + foobar = {foobar, " 1066"}; + if (foo[12]) + foobar = {foobar, " 1067"}; + else + ozonerab({4'b1001, foo[14:12]}, foobar); + foobar = {foobar, " 1068"}; + dude(foobar); + $fwrite (fd, " 1069:%s", foobar); + end + 7'b??_?_000_?: + begin + ozonef1e(foo, foobar); + foobar = {foobar, " 1070"}; + foobar = {foobar, " 1071"}; + ozonef1e_hl(foo[11:9],foo[ 5],foobar); + foobar = {foobar, " 1072"}; + ozonef1e_ye(foo[14:9],foo[ 5],foobar); + dude(foobar); + $fwrite (fd, " 1073:%s", foobar); + end + 7'b??_?_100_?: + begin + ozonef1e(foo, foobar); + foobar = {foobar, " 1074"}; + foobar = {foobar, " 1075"}; + ozonef1e_hl(foo[11:9],foo[ 5],foobar); + foobar = {foobar, " 1076"}; + ozonef1e_ye(foo[14:9],foo[ 5],foobar); + dude(foobar); + $fwrite (fd, " 1077:%s", foobar); + end + 7'b??_?_001_?: + begin + ozonef1e(foo, foobar); + foobar = {foobar, " 1078"}; + ozonef1e_ye(foo[14:9],foo[ 5],foobar); + foobar = {foobar, " 1079"}; + foobar = {foobar, " 1080"}; + ozonef1e_hl(foo[11:9],foo[ 5],foobar); + dude(foobar); + $fwrite (fd, " 1081:%s", foobar); + end + 7'b??_?_011_?: + begin + ozonef1e(foo, foobar); + foobar = {foobar, " 1082"}; + ozonef1e_ye(foo[14:9],foo[ 5],foobar); + foobar = {foobar, " 1083"}; + foobar = {foobar, " 1084"}; + ozonef1e_hl(foo[11:9],foo[ 5],foobar); + dude(foobar); + $fwrite (fd, " 1085:%s", foobar); + end + 7'b??_?_101_?: + begin + ozonef1e(foo, foobar); + foobar = {foobar, " 1086"}; + ozonef1e_ye(foo[14:9],foo[ 5],foobar); + dude(foobar); + $fwrite (fd, " 1087:%s", foobar); + end endcase 17'b00_10??_?_????_?0_0110 : begin - ozonef1e(foo, foobar); - foobar = {foobar, " 1088"}; - ozoneae(foo[ 8: 6], foobar); - ozonef1e_hl(foo[11:9],foo[ 5],foobar); - foobar = {foobar, " 1089"}; - ozonef1e_ye(foo[14:9],foo[ 5],foobar); - dude(foobar); - $fwrite (fd, " 1090:%s", foobar); + ozonef1e(foo, foobar); + foobar = {foobar, " 1088"}; + ozoneae(foo[ 8: 6], foobar); + ozonef1e_hl(foo[11:9],foo[ 5],foobar); + foobar = {foobar, " 1089"}; + ozonef1e_ye(foo[14:9],foo[ 5],foobar); + dude(foobar); + $fwrite (fd, " 1090:%s", foobar); end 17'b00_10??_?_????_00_0111 : begin - ozonef1e(foo, foobar); - foobar = {foobar, " 1091"}; - if (foo[ 6]) - foobar = {foobar, " 1092"}; - else - ozonerab({4'b1001, foo[ 8: 6]}, foobar); - foobar = {foobar, " 1093"}; - foobar = {foobar, " 1094"}; - ozonerme(foo[14:12],foobar); - case (foo[11: 9]) - 3'h2, - 3'h5, - 3'h6, - 3'h7: - ozonef1e_inc_dec(foo[14:9],1'b0,foobar); - 3'h1, - 3'h3, - 3'h4: - foobar = {foobar, " 1095"}; - endcase - dude(foobar); - $fwrite (fd, " 1096:%s", foobar); + ozonef1e(foo, foobar); + foobar = {foobar, " 1091"}; + if (foo[ 6]) + foobar = {foobar, " 1092"}; + else + ozonerab({4'b1001, foo[ 8: 6]}, foobar); + foobar = {foobar, " 1093"}; + foobar = {foobar, " 1094"}; + ozonerme(foo[14:12],foobar); + case (foo[11: 9]) + 3'h2, + 3'h5, + 3'h6, + 3'h7: + ozonef1e_inc_dec(foo[14:9],1'b0,foobar); + 3'h1, + 3'h3, + 3'h4: + foobar = {foobar, " 1095"}; + endcase + dude(foobar); + $fwrite (fd, " 1096:%s", foobar); end 17'b00_10??_?_????_?0_0100 : begin - ozonef1e(foo, foobar); - foobar = {foobar, " 1097"}; - ozonef1e_ye(foo[14:9],foo[ 5],foobar); - foobar = {foobar, " 1098"}; - ozoneae(foo[ 8: 6], foobar); - ozonef1e_hl(foo[11:9],foo[ 5],foobar); - dude(foobar); - $fwrite (fd, " 1099:%s", foobar); + ozonef1e(foo, foobar); + foobar = {foobar, " 1097"}; + ozonef1e_ye(foo[14:9],foo[ 5],foobar); + foobar = {foobar, " 1098"}; + ozoneae(foo[ 8: 6], foobar); + ozonef1e_hl(foo[11:9],foo[ 5],foobar); + dude(foobar); + $fwrite (fd, " 1099:%s", foobar); end 17'b00_10??_?_????_10_0111 : begin - ozonef1e(foo, foobar); - foobar = {foobar, " 1100"}; - foobar = {foobar, " 1101"}; - ozonerme(foo[14:12],foobar); - case (foo[11: 9]) - 3'h2, - 3'h5, - 3'h6, - 3'h7: - ozonef1e_inc_dec(foo[14:9],1'b0,foobar); - 3'h1, - 3'h3, - 3'h4: - foobar = {foobar, " 1102"}; - endcase - foobar = {foobar, " 1103"}; - if (foo[ 6]) - foobar = {foobar, " 1104"}; - else - ozonerab({4'b1001, foo[ 8: 6]}, foobar); - dude(foobar); - $fwrite (fd, " 1105:%s", foobar); + ozonef1e(foo, foobar); + foobar = {foobar, " 1100"}; + foobar = {foobar, " 1101"}; + ozonerme(foo[14:12],foobar); + case (foo[11: 9]) + 3'h2, + 3'h5, + 3'h6, + 3'h7: + ozonef1e_inc_dec(foo[14:9],1'b0,foobar); + 3'h1, + 3'h3, + 3'h4: + foobar = {foobar, " 1102"}; + endcase + foobar = {foobar, " 1103"}; + if (foo[ 6]) + foobar = {foobar, " 1104"}; + else + ozonerab({4'b1001, foo[ 8: 6]}, foobar); + dude(foobar); + $fwrite (fd, " 1105:%s", foobar); end 17'b00_10??_?_????_?0_1110 : begin - ozonef1e(foo, foobar); - foobar = {foobar, " 1106"}; - case (foo[11:9]) - 3'h2: - begin - foobar = {foobar, " 1107"}; - if (foo[14:12] == 3'h0) - foobar = {foobar, " 1108"}; - else - ozonerme(foo[14:12],foobar); - foobar = {foobar, " 1109"}; - end - 3'h6: - begin - foobar = {foobar, " 1110"}; - if (foo[14:12] == 3'h0) - foobar = {foobar, " 1111"}; - else - ozonerme(foo[14:12],foobar); - foobar = {foobar, " 1112"}; - end - 3'h0: - begin - foobar = {foobar, " 1113"}; - if (foo[14:12] == 3'h0) - foobar = {foobar, " 1114"}; - else - ozonerme(foo[14:12],foobar); - foobar = {foobar, " 1115"}; - if (foo[ 7: 5] >= 3'h5) - foobar = {foobar, " 1116"}; - else - ozonexe(foo[ 8: 5], foobar); - end - 3'h1: - begin - foobar = {foobar, " 1117"}; - if (foo[14:12] == 3'h0) - foobar = {foobar, " 1118"}; - else - ozonerme(foo[14:12],foobar); - foobar = {foobar, " 1119"}; - if (foo[ 7: 5] >= 3'h5) - foobar = {foobar, " 1120"}; - else - ozonexe(foo[ 8: 5], foobar); - end - 3'h4: - begin - foobar = {foobar, " 1121"}; - if (foo[14:12] == 3'h0) - foobar = {foobar, " 1122"}; - else - ozonerme(foo[14:12],foobar); - foobar = {foobar, " 1123"}; - if (foo[ 7: 5] >= 3'h5) - foobar = {foobar, " 1124"}; - else - ozonexe(foo[ 8: 5], foobar); - end - 3'h5: - begin - foobar = {foobar, " 1125"}; - if (foo[14:12] == 3'h0) - foobar = {foobar, " 1126"}; - else - ozonerme(foo[14:12],foobar); - foobar = {foobar, " 1127"}; - if (foo[ 7: 5] >= 3'h5) - foobar = {foobar, " 1128"}; - else - ozonexe(foo[ 8: 5], foobar); - end - endcase - dude(foobar); - $fwrite (fd, " 1129:%s", foobar); + ozonef1e(foo, foobar); + foobar = {foobar, " 1106"}; + case (foo[11:9]) + 3'h2: + begin + foobar = {foobar, " 1107"}; + if (foo[14:12] == 3'h0) + foobar = {foobar, " 1108"}; + else + ozonerme(foo[14:12],foobar); + foobar = {foobar, " 1109"}; + end + 3'h6: + begin + foobar = {foobar, " 1110"}; + if (foo[14:12] == 3'h0) + foobar = {foobar, " 1111"}; + else + ozonerme(foo[14:12],foobar); + foobar = {foobar, " 1112"}; + end + 3'h0: + begin + foobar = {foobar, " 1113"}; + if (foo[14:12] == 3'h0) + foobar = {foobar, " 1114"}; + else + ozonerme(foo[14:12],foobar); + foobar = {foobar, " 1115"}; + if (foo[ 7: 5] >= 3'h5) + foobar = {foobar, " 1116"}; + else + ozonexe(foo[ 8: 5], foobar); + end + 3'h1: + begin + foobar = {foobar, " 1117"}; + if (foo[14:12] == 3'h0) + foobar = {foobar, " 1118"}; + else + ozonerme(foo[14:12],foobar); + foobar = {foobar, " 1119"}; + if (foo[ 7: 5] >= 3'h5) + foobar = {foobar, " 1120"}; + else + ozonexe(foo[ 8: 5], foobar); + end + 3'h4: + begin + foobar = {foobar, " 1121"}; + if (foo[14:12] == 3'h0) + foobar = {foobar, " 1122"}; + else + ozonerme(foo[14:12],foobar); + foobar = {foobar, " 1123"}; + if (foo[ 7: 5] >= 3'h5) + foobar = {foobar, " 1124"}; + else + ozonexe(foo[ 8: 5], foobar); + end + 3'h5: + begin + foobar = {foobar, " 1125"}; + if (foo[14:12] == 3'h0) + foobar = {foobar, " 1126"}; + else + ozonerme(foo[14:12],foobar); + foobar = {foobar, " 1127"}; + if (foo[ 7: 5] >= 3'h5) + foobar = {foobar, " 1128"}; + else + ozonexe(foo[ 8: 5], foobar); + end + endcase + dude(foobar); + $fwrite (fd, " 1129:%s", foobar); end 17'b00_10??_?_????_?0_1111 : casez (foo[14: 9]) - 6'b001_10_?: - begin - ozonef1e(foo, foobar); - foobar = {foobar, " 1130"}; - foobar = {foobar, " 1131"}; - ozonef1e_hl(foo[ 7: 5],foo[ 9],foobar); - foobar = {foobar, " 1132"}; - ozonexe(foo[ 8: 5], foobar); - dude(foobar); - $fwrite (fd, " 1133:%s", foobar); - end - 6'b???_11_?: - begin - ozonef1e(foo, foobar); - foobar = {foobar, " 1134"}; - ozoneae(foo[14:12], foobar); - ozonef1e_hl(foo[ 7: 5],foo[ 9],foobar); - foobar = {foobar, " 1135"}; - ozonexe(foo[ 8: 5], foobar); - dude(foobar); - $fwrite (fd, " 1136:%s", foobar); - end - 6'b000_10_1, - 6'b010_10_1, - 6'b100_10_1, - 6'b110_10_1: - begin - ozonef1e(foo, foobar); - foobar = {foobar, " 1137"}; - ozonerab({4'b1001, foo[14:12]}, foobar); - foobar = {foobar, " 1138"}; - if ((foo[ 7: 5] >= 3'h1) & (foo[ 7: 5] <= 3'h3)) - foobar = {foobar, " 1139"}; - else - ozonexe(foo[ 8: 5], foobar); - dude(foobar); - $fwrite (fd, " 1140:%s", foobar); - end - 6'b000_10_0, - 6'b010_10_0, - 6'b100_10_0, - 6'b110_10_0: - begin - ozonef1e(foo, foobar); - foobar = {foobar, " 1141"}; - foobar = {foobar, " 1142"}; - ozonerab({4'b1001, foo[14:12]}, foobar); - foobar = {foobar, " 1143"}; - foobar = {foobar, " 1144"}; - ozonef1e_h(foo[ 7: 5],foobar); - foobar = {foobar, " 1145"}; - ozonexe(foo[ 8: 5], foobar); - dude(foobar); - $fwrite (fd, " 1146:%s", foobar); - end - 6'b???_00_?: - begin - ozonef1e(foo, foobar); - foobar = {foobar, " 1147"}; - if (foo[ 9]) - begin - foobar = {foobar, " 1148"}; - ozoneae(foo[14:12], foobar); - end - else - begin - foobar = {foobar, " 1149"}; - ozoneae(foo[14:12], foobar); - foobar = {foobar, " 1150"}; - end - foobar = {foobar, " 1151"}; - foobar = {foobar, " 1152"}; - ozonef1e_h(foo[ 7: 5],foobar); - foobar = {foobar, " 1153"}; - ozonexe(foo[ 8: 5], foobar); - dude(foobar); - $fwrite (fd, " 1154:%s", foobar); - end - 6'b???_01_?: - begin - ozonef1e(foo, foobar); - foobar = {foobar, " 1155"}; - ozoneae(foo[14:12], foobar); - if (foo[ 9]) - foobar = {foobar, " 1156"}; - else - foobar = {foobar, " 1157"}; - foobar = {foobar, " 1158"}; - foobar = {foobar, " 1159"}; - ozonef1e_h(foo[ 7: 5],foobar); - foobar = {foobar, " 1160"}; - ozonexe(foo[ 8: 5], foobar); - dude(foobar); - $fwrite (fd, " 1161:%s", foobar); - end - 6'b011_10_0: - begin - ozonef1e(foo, foobar); - foobar = {foobar, " 1162"}; - case (foo[ 8: 5]) - 4'h0: foobar = {foobar, " 1163"}; - 4'h1: foobar = {foobar, " 1164"}; - 4'h2: foobar = {foobar, " 1165"}; - 4'h3: foobar = {foobar, " 1166"}; - 4'h4: foobar = {foobar, " 1167"}; - 4'h5: foobar = {foobar, " 1168"}; - 4'h8: foobar = {foobar, " 1169"}; - 4'h9: foobar = {foobar, " 1170"}; - 4'ha: foobar = {foobar, " 1171"}; - 4'hb: foobar = {foobar, " 1172"}; - 4'hc: foobar = {foobar, " 1173"}; - 4'hd: foobar = {foobar, " 1174"}; - default: foobar = {foobar, " 1175"}; - endcase - dude(foobar); - $fwrite (fd, " 1176:%s", foobar); - end - default: foobar = {foobar, " 1177"}; + 6'b001_10_?: + begin + ozonef1e(foo, foobar); + foobar = {foobar, " 1130"}; + foobar = {foobar, " 1131"}; + ozonef1e_hl(foo[ 7: 5],foo[ 9],foobar); + foobar = {foobar, " 1132"}; + ozonexe(foo[ 8: 5], foobar); + dude(foobar); + $fwrite (fd, " 1133:%s", foobar); + end + 6'b???_11_?: + begin + ozonef1e(foo, foobar); + foobar = {foobar, " 1134"}; + ozoneae(foo[14:12], foobar); + ozonef1e_hl(foo[ 7: 5],foo[ 9],foobar); + foobar = {foobar, " 1135"}; + ozonexe(foo[ 8: 5], foobar); + dude(foobar); + $fwrite (fd, " 1136:%s", foobar); + end + 6'b000_10_1, + 6'b010_10_1, + 6'b100_10_1, + 6'b110_10_1: + begin + ozonef1e(foo, foobar); + foobar = {foobar, " 1137"}; + ozonerab({4'b1001, foo[14:12]}, foobar); + foobar = {foobar, " 1138"}; + if ((foo[ 7: 5] >= 3'h1) & (foo[ 7: 5] <= 3'h3)) + foobar = {foobar, " 1139"}; + else + ozonexe(foo[ 8: 5], foobar); + dude(foobar); + $fwrite (fd, " 1140:%s", foobar); + end + 6'b000_10_0, + 6'b010_10_0, + 6'b100_10_0, + 6'b110_10_0: + begin + ozonef1e(foo, foobar); + foobar = {foobar, " 1141"}; + foobar = {foobar, " 1142"}; + ozonerab({4'b1001, foo[14:12]}, foobar); + foobar = {foobar, " 1143"}; + foobar = {foobar, " 1144"}; + ozonef1e_h(foo[ 7: 5],foobar); + foobar = {foobar, " 1145"}; + ozonexe(foo[ 8: 5], foobar); + dude(foobar); + $fwrite (fd, " 1146:%s", foobar); + end + 6'b???_00_?: + begin + ozonef1e(foo, foobar); + foobar = {foobar, " 1147"}; + if (foo[ 9]) + begin + foobar = {foobar, " 1148"}; + ozoneae(foo[14:12], foobar); + end + else + begin + foobar = {foobar, " 1149"}; + ozoneae(foo[14:12], foobar); + foobar = {foobar, " 1150"}; + end + foobar = {foobar, " 1151"}; + foobar = {foobar, " 1152"}; + ozonef1e_h(foo[ 7: 5],foobar); + foobar = {foobar, " 1153"}; + ozonexe(foo[ 8: 5], foobar); + dude(foobar); + $fwrite (fd, " 1154:%s", foobar); + end + 6'b???_01_?: + begin + ozonef1e(foo, foobar); + foobar = {foobar, " 1155"}; + ozoneae(foo[14:12], foobar); + if (foo[ 9]) + foobar = {foobar, " 1156"}; + else + foobar = {foobar, " 1157"}; + foobar = {foobar, " 1158"}; + foobar = {foobar, " 1159"}; + ozonef1e_h(foo[ 7: 5],foobar); + foobar = {foobar, " 1160"}; + ozonexe(foo[ 8: 5], foobar); + dude(foobar); + $fwrite (fd, " 1161:%s", foobar); + end + 6'b011_10_0: + begin + ozonef1e(foo, foobar); + foobar = {foobar, " 1162"}; + case (foo[ 8: 5]) + 4'h0: foobar = {foobar, " 1163"}; + 4'h1: foobar = {foobar, " 1164"}; + 4'h2: foobar = {foobar, " 1165"}; + 4'h3: foobar = {foobar, " 1166"}; + 4'h4: foobar = {foobar, " 1167"}; + 4'h5: foobar = {foobar, " 1168"}; + 4'h8: foobar = {foobar, " 1169"}; + 4'h9: foobar = {foobar, " 1170"}; + 4'ha: foobar = {foobar, " 1171"}; + 4'hb: foobar = {foobar, " 1172"}; + 4'hc: foobar = {foobar, " 1173"}; + 4'hd: foobar = {foobar, " 1174"}; + default: foobar = {foobar, " 1175"}; + endcase + dude(foobar); + $fwrite (fd, " 1176:%s", foobar); + end + default: foobar = {foobar, " 1177"}; endcase 17'b00_10??_?_????_?0_110? : begin - ozonef1e(foo, foobar); - foobar = {foobar, " 1178"}; - foobar = {foobar, " 1179"}; - ozonef1e_hl(foo[11:9], foo[0], foobar); - foobar = {foobar, " 1180"}; - ozonef1e_ye(foo[14:9],1'b0,foobar); - foobar = {foobar, " 1181"}; - ozonef1e_h(foo[ 7: 5],foobar); - foobar = {foobar, " 1182"}; - ozonexe(foo[ 8: 5], foobar); - dude(foobar); - $fwrite (fd, " 1183:%s", foobar); + ozonef1e(foo, foobar); + foobar = {foobar, " 1178"}; + foobar = {foobar, " 1179"}; + ozonef1e_hl(foo[11:9], foo[0], foobar); + foobar = {foobar, " 1180"}; + ozonef1e_ye(foo[14:9],1'b0,foobar); + foobar = {foobar, " 1181"}; + ozonef1e_h(foo[ 7: 5],foobar); + foobar = {foobar, " 1182"}; + ozonexe(foo[ 8: 5], foobar); + dude(foobar); + $fwrite (fd, " 1183:%s", foobar); end 17'b00_10??_?_????_?1_110? : begin - ozonef1e(foo, foobar); - foobar = {foobar, " 1184"}; - foobar = {foobar, " 1185"}; - ozonef1e_hl(foo[11:9],foo[0],foobar); - foobar = {foobar, " 1186"}; - ozonef1e_ye(foo[14:9],foo[ 0],foobar); - foobar = {foobar, " 1187"}; - foobar = {foobar, " 1188"}; - ozonef1e_h(foo[ 7: 5],foobar); - foobar = {foobar, " 1189"}; - ozonexe(foo[ 8: 5], foobar); - dude(foobar); - $fwrite (fd, " 1190:%s", foobar); + ozonef1e(foo, foobar); + foobar = {foobar, " 1184"}; + foobar = {foobar, " 1185"}; + ozonef1e_hl(foo[11:9],foo[0],foobar); + foobar = {foobar, " 1186"}; + ozonef1e_ye(foo[14:9],foo[ 0],foobar); + foobar = {foobar, " 1187"}; + foobar = {foobar, " 1188"}; + ozonef1e_h(foo[ 7: 5],foobar); + foobar = {foobar, " 1189"}; + ozonexe(foo[ 8: 5], foobar); + dude(foobar); + $fwrite (fd, " 1190:%s", foobar); end 17'b00_10??_?_????_?0_101? : begin - ozonef1e(foo, foobar); - foobar = {foobar, " 1191"}; - ozonef1e_ye(foo[14:9],foo[ 0],foobar); - foobar = {foobar, " 1192"}; - foobar = {foobar, " 1193"}; - ozonef1e_hl(foo[11:9],foo[0],foobar); - foobar = {foobar, " 1194"}; - foobar = {foobar, " 1195"}; - ozonef1e_h(foo[ 7: 5],foobar); - foobar = {foobar, " 1196"}; - ozonexe(foo[ 8: 5], foobar); - dude(foobar); - $fwrite (fd, " 1197:%s", foobar); + ozonef1e(foo, foobar); + foobar = {foobar, " 1191"}; + ozonef1e_ye(foo[14:9],foo[ 0],foobar); + foobar = {foobar, " 1192"}; + foobar = {foobar, " 1193"}; + ozonef1e_hl(foo[11:9],foo[0],foobar); + foobar = {foobar, " 1194"}; + foobar = {foobar, " 1195"}; + ozonef1e_h(foo[ 7: 5],foobar); + foobar = {foobar, " 1196"}; + ozonexe(foo[ 8: 5], foobar); + dude(foobar); + $fwrite (fd, " 1197:%s", foobar); end 17'b00_10??_?_????_?0_1001 : begin - ozonef1e(foo, foobar); - foobar = {foobar, " 1198"}; - foobar = {foobar, " 1199"}; - ozonef1e_h(foo[11:9],foobar); - foobar = {foobar, " 1200"}; - ozonef1e_ye(foo[14:9],1'b0,foobar); - foobar = {foobar, " 1201"}; - case (foo[ 7: 5]) - 3'h1, - 3'h2, - 3'h3: - foobar = {foobar, " 1202"}; - default: - begin - foobar = {foobar, " 1203"}; - foobar = {foobar, " 1204"}; - ozonexe(foo[ 8: 5], foobar); - end - endcase - dude(foobar); - $fwrite (fd, " 1205:%s", foobar); + ozonef1e(foo, foobar); + foobar = {foobar, " 1198"}; + foobar = {foobar, " 1199"}; + ozonef1e_h(foo[11:9],foobar); + foobar = {foobar, " 1200"}; + ozonef1e_ye(foo[14:9],1'b0,foobar); + foobar = {foobar, " 1201"}; + case (foo[ 7: 5]) + 3'h1, + 3'h2, + 3'h3: + foobar = {foobar, " 1202"}; + default: + begin + foobar = {foobar, " 1203"}; + foobar = {foobar, " 1204"}; + ozonexe(foo[ 8: 5], foobar); + end + endcase + dude(foobar); + $fwrite (fd, " 1205:%s", foobar); end 17'b00_10??_?_????_?0_0101 : begin - ozonef1e(foo, foobar); - foobar = {foobar, " 1206"}; - case (foo[11: 9]) - 3'h1, - 3'h3, - 3'h4: - foobar = {foobar, " 1207"}; - default: - begin - ozonef1e_ye(foo[14:9],1'b0,foobar); - foobar = {foobar, " 1208"}; - foobar = {foobar, " 1209"}; - end - endcase - foobar = {foobar, " 1210"}; - foobar = {foobar, " 1211"}; - ozonef1e_h(foo[ 7: 5],foobar); - foobar = {foobar, " 1212"}; - ozonexe(foo[ 8: 5], foobar); - dude(foobar); - $fwrite (fd, " 1213:%s", foobar); + ozonef1e(foo, foobar); + foobar = {foobar, " 1206"}; + case (foo[11: 9]) + 3'h1, + 3'h3, + 3'h4: + foobar = {foobar, " 1207"}; + default: + begin + ozonef1e_ye(foo[14:9],1'b0,foobar); + foobar = {foobar, " 1208"}; + foobar = {foobar, " 1209"}; + end + endcase + foobar = {foobar, " 1210"}; + foobar = {foobar, " 1211"}; + ozonef1e_h(foo[ 7: 5],foobar); + foobar = {foobar, " 1212"}; + ozonexe(foo[ 8: 5], foobar); + dude(foobar); + $fwrite (fd, " 1213:%s", foobar); end 17'b00_10??_?_????_?1_1110 : begin - ozonef1e(foo, foobar); - foobar = {foobar, " 1214"}; - ozonef1e_ye(foo[14:9],1'b0,foobar); - foobar = {foobar, " 1215"}; - foobar = {foobar, " 1216"}; - ozonef1e_h(foo[11: 9],foobar); - foobar = {foobar, " 1217"}; - foobar = {foobar, " 1218"}; - ozonef1e_h(foo[ 7: 5],foobar); - foobar = {foobar, " 1219"}; - ozonexe(foo[ 8: 5], foobar); - dude(foobar); - $fwrite (fd, " 1220:%s", foobar); + ozonef1e(foo, foobar); + foobar = {foobar, " 1214"}; + ozonef1e_ye(foo[14:9],1'b0,foobar); + foobar = {foobar, " 1215"}; + foobar = {foobar, " 1216"}; + ozonef1e_h(foo[11: 9],foobar); + foobar = {foobar, " 1217"}; + foobar = {foobar, " 1218"}; + ozonef1e_h(foo[ 7: 5],foobar); + foobar = {foobar, " 1219"}; + ozonexe(foo[ 8: 5], foobar); + dude(foobar); + $fwrite (fd, " 1220:%s", foobar); end 17'b00_10??_?_????_?0_1000 : begin - ozonef1e(foo, foobar); - foobar = {foobar, " 1221"}; - ozonef1e_ye(foo[14:9],1'b0,foobar); - foobar = {foobar, " 1222"}; - foobar = {foobar, " 1223"}; - ozonef1e_h(foo[11: 9],foobar); - foobar = {foobar, " 1224"}; - foobar = {foobar, " 1225"}; - ozonef1e_h(foo[ 7: 5],foobar); - foobar = {foobar, " 1226"}; - ozonexe(foo[ 8: 5], foobar); - dude(foobar); - $fwrite (fd, " 1227:%s", foobar); + ozonef1e(foo, foobar); + foobar = {foobar, " 1221"}; + ozonef1e_ye(foo[14:9],1'b0,foobar); + foobar = {foobar, " 1222"}; + foobar = {foobar, " 1223"}; + ozonef1e_h(foo[11: 9],foobar); + foobar = {foobar, " 1224"}; + foobar = {foobar, " 1225"}; + ozonef1e_h(foo[ 7: 5],foobar); + foobar = {foobar, " 1226"}; + ozonexe(foo[ 8: 5], foobar); + dude(foobar); + $fwrite (fd, " 1227:%s", foobar); end 17'b10_01??_?_????_??_???? : begin - if (foo[27]) - foobar = " 1228"; - else - foobar = " 1229"; - ozonecon(foo[20:16], foobar); - foobar = {foobar, " 1230"}; - ozonef2(foo[31:0], foobar); - dude(foobar); - $fwrite (fd, " 1231:%s", foobar); + if (foo[27]) + foobar = " 1228"; + else + foobar = " 1229"; + ozonecon(foo[20:16], foobar); + foobar = {foobar, " 1230"}; + ozonef2(foo[31:0], foobar); + dude(foobar); + $fwrite (fd, " 1231:%s", foobar); end 17'b00_1000_?_????_01_0011 : if (~|foo[ 9: 8]) - begin - if (foo[ 7]) - foobar = " 1232"; - else - foobar = " 1233"; - ozonecon(foo[14:10], foobar); - foobar = {foobar, " 1234"}; - ozonef2e(foo[31:0], foobar); - dude(foobar); - $fwrite (fd, " 1235:%s", foobar); - end + begin + if (foo[ 7]) + foobar = " 1232"; + else + foobar = " 1233"; + ozonecon(foo[14:10], foobar); + foobar = {foobar, " 1234"}; + ozonef2e(foo[31:0], foobar); + dude(foobar); + $fwrite (fd, " 1235:%s", foobar); + end else - begin - foobar = " 1236"; - ozonecon(foo[14:10], foobar); - foobar = {foobar, " 1237"}; - ozonef3e(foo[31:0], foobar); - dude(foobar); - $fwrite (fd, " 1238:%s", foobar); - end + begin + foobar = " 1236"; + ozonecon(foo[14:10], foobar); + foobar = {foobar, " 1237"}; + ozonef3e(foo[31:0], foobar); + dude(foobar); + $fwrite (fd, " 1238:%s", foobar); + end 17'b11_110?_1_????_??_???? : begin - ozonef3(foo[31:0], foobar); - dude(foobar); - $fwrite(fd, " 1239:%s", foobar); + ozonef3(foo[31:0], foobar); + dude(foobar); + $fwrite(fd, " 1239:%s", foobar); end 17'b11_110?_0_????_??_???? : begin : f4_body - casez (foo[24:20]) - 5'b0_1110, - 5'b1_0???, - 5'b1_1111: - begin - $fwrite (fd, " 1240"); - end - 5'b0_00??: - begin - ozoneacc(foo[26], foobar); - foobar = {foobar, " 1241"}; - ozoneacc(foo[25], foobar); - ozonebmuop(foo[24:20], foobar); - ozoneae(foo[18:16], foobar); - foobar = {foobar, " 1242"}; - dude(foobar); - $fwrite(fd, " 1243:%s", foobar); - end - 5'b0_01??: - begin - ozoneacc(foo[26], foobar); - foobar = {foobar, " 1244"}; - ozoneacc(foo[25], foobar); - ozonebmuop(foo[24:20], foobar); - ozonearm(foo[18:16], foobar); - dude(foobar); - $fwrite(fd, " 1245:%s", foobar); - end - 5'b0_1011: - begin - ozoneacc(foo[26], foobar); - foobar = {foobar, " 1246"}; - ozonebmuop(foo[24:20], foobar); - foobar = {foobar, " 1247"}; - ozoneae(foo[18:16], foobar); - foobar = {foobar, " 1248"}; - dude(foobar); - $fwrite(fd, " 1249:%s", foobar); - end - 5'b0_100?, - 5'b0_1010, - 5'b0_110? : - begin - ozoneacc(foo[26], foobar); - foobar = {foobar, " 1250"}; - ozonebmuop(foo[24:20], foobar); - foobar = {foobar, " 1251"}; - ozoneacc(foo[25], foobar); - foobar = {foobar, " 1252"}; - ozoneae(foo[18:16], foobar); - foobar = {foobar, " 1253"}; - dude(foobar); - $fwrite(fd, " 1254:%s", foobar); - end - 5'b0_1111 : - begin - ozoneacc(foo[26], foobar); - foobar = {foobar, " 1255"}; - ozoneacc(foo[25], foobar); - foobar = {foobar, " 1256"}; - ozoneae(foo[18:16], foobar); - dude(foobar); - $fwrite(fd, " 1257:%s", foobar); - end - 5'b1_10??, - 5'b1_110?, - 5'b1_1110 : - begin - ozoneacc(foo[26], foobar); - foobar = {foobar, " 1258"}; - ozonebmuop(foo[24:20], foobar); - foobar = {foobar, " 1259"}; - ozoneacc(foo[25], foobar); - foobar = {foobar, " 1260"}; - ozonearm(foo[18:16], foobar); - foobar = {foobar, " 1261"}; - dude(foobar); - $fwrite(fd, " 1262:%s", foobar); - end - endcase + casez (foo[24:20]) + 5'b0_1110, + 5'b1_0???, + 5'b1_1111: + begin + $fwrite (fd, " 1240"); + end + 5'b0_00??: + begin + ozoneacc(foo[26], foobar); + foobar = {foobar, " 1241"}; + ozoneacc(foo[25], foobar); + ozonebmuop(foo[24:20], foobar); + ozoneae(foo[18:16], foobar); + foobar = {foobar, " 1242"}; + dude(foobar); + $fwrite(fd, " 1243:%s", foobar); + end + 5'b0_01??: + begin + ozoneacc(foo[26], foobar); + foobar = {foobar, " 1244"}; + ozoneacc(foo[25], foobar); + ozonebmuop(foo[24:20], foobar); + ozonearm(foo[18:16], foobar); + dude(foobar); + $fwrite(fd, " 1245:%s", foobar); + end + 5'b0_1011: + begin + ozoneacc(foo[26], foobar); + foobar = {foobar, " 1246"}; + ozonebmuop(foo[24:20], foobar); + foobar = {foobar, " 1247"}; + ozoneae(foo[18:16], foobar); + foobar = {foobar, " 1248"}; + dude(foobar); + $fwrite(fd, " 1249:%s", foobar); + end + 5'b0_100?, + 5'b0_1010, + 5'b0_110? : + begin + ozoneacc(foo[26], foobar); + foobar = {foobar, " 1250"}; + ozonebmuop(foo[24:20], foobar); + foobar = {foobar, " 1251"}; + ozoneacc(foo[25], foobar); + foobar = {foobar, " 1252"}; + ozoneae(foo[18:16], foobar); + foobar = {foobar, " 1253"}; + dude(foobar); + $fwrite(fd, " 1254:%s", foobar); + end + 5'b0_1111 : + begin + ozoneacc(foo[26], foobar); + foobar = {foobar, " 1255"}; + ozoneacc(foo[25], foobar); + foobar = {foobar, " 1256"}; + ozoneae(foo[18:16], foobar); + dude(foobar); + $fwrite(fd, " 1257:%s", foobar); + end + 5'b1_10??, + 5'b1_110?, + 5'b1_1110 : + begin + ozoneacc(foo[26], foobar); + foobar = {foobar, " 1258"}; + ozonebmuop(foo[24:20], foobar); + foobar = {foobar, " 1259"}; + ozoneacc(foo[25], foobar); + foobar = {foobar, " 1260"}; + ozonearm(foo[18:16], foobar); + foobar = {foobar, " 1261"}; + dude(foobar); + $fwrite(fd, " 1262:%s", foobar); + end + endcase end 17'b11_100?_?_????_??_???? : casez (foo[23:19]) - 5'b111??, - 5'b0111?: - begin - ozoneae(foo[26:24], foobar); - foobar = {foobar, " 1263"}; - ozonef3f4imop(foo[23:19], foobar); - foobar = {foobar, " 1264"}; - ozoneae(foo[18:16], foobar); - foobar = {foobar, " 1265"}; - skyway(foo[15:12], foobar); - skyway(foo[11: 8], foobar); - skyway(foo[ 7: 4], foobar); - skyway(foo[ 3:0], foobar); - foobar = {foobar, " 1266"}; - dude(foobar); - $fwrite(fd, " 1267:%s", foobar); - end - 5'b?0???, - 5'b110??: - begin - ozoneae(foo[26:24], foobar); - foobar = {foobar, " 1268"}; - if (foo[23:21] == 3'b100) - foobar = {foobar, " 1269"}; - ozoneae(foo[18:16], foobar); - if (foo[19]) - foobar = {foobar, " 1270"}; - else - foobar = {foobar, " 1271"}; - ozonef3f4imop(foo[23:19], foobar); - foobar = {foobar, " 1272"}; - ozonef3f4_iext(foo[20:19], foo[15:0], foobar); - dude(foobar); - $fwrite(fd, " 1273:%s", foobar); - end - 5'b010??, - 5'b0110?: - begin - ozoneae(foo[18:16], foobar); - if (foo[19]) - foobar = {foobar, " 1274"}; - else - foobar = {foobar, " 1275"}; - ozonef3f4imop(foo[23:19], foobar); - foobar = {foobar, " 1276"}; - ozonef3f4_iext(foo[20:19], foo[15:0], foobar); - dude(foobar); - $fwrite(fd, " 1277:%s", foobar); - end + 5'b111??, + 5'b0111?: + begin + ozoneae(foo[26:24], foobar); + foobar = {foobar, " 1263"}; + ozonef3f4imop(foo[23:19], foobar); + foobar = {foobar, " 1264"}; + ozoneae(foo[18:16], foobar); + foobar = {foobar, " 1265"}; + skyway(foo[15:12], foobar); + skyway(foo[11: 8], foobar); + skyway(foo[ 7: 4], foobar); + skyway(foo[ 3:0], foobar); + foobar = {foobar, " 1266"}; + dude(foobar); + $fwrite(fd, " 1267:%s", foobar); + end + 5'b?0???, + 5'b110??: + begin + ozoneae(foo[26:24], foobar); + foobar = {foobar, " 1268"}; + if (foo[23:21] == 3'b100) + foobar = {foobar, " 1269"}; + ozoneae(foo[18:16], foobar); + if (foo[19]) + foobar = {foobar, " 1270"}; + else + foobar = {foobar, " 1271"}; + ozonef3f4imop(foo[23:19], foobar); + foobar = {foobar, " 1272"}; + ozonef3f4_iext(foo[20:19], foo[15:0], foobar); + dude(foobar); + $fwrite(fd, " 1273:%s", foobar); + end + 5'b010??, + 5'b0110?: + begin + ozoneae(foo[18:16], foobar); + if (foo[19]) + foobar = {foobar, " 1274"}; + else + foobar = {foobar, " 1275"}; + ozonef3f4imop(foo[23:19], foobar); + foobar = {foobar, " 1276"}; + ozonef3f4_iext(foo[20:19], foo[15:0], foobar); + dude(foobar); + $fwrite(fd, " 1277:%s", foobar); + end endcase 17'b00_1000_?_????_11_0011 : begin - foobar = " 1278"; - ozonecon(foo[14:10], foobar); - foobar = {foobar, " 1279"}; - casez (foo[25:21]) - 5'b0_1110, - 5'b1_0???, - 5'b1_1111: - begin - $fwrite(fd, " 1280"); - end - 5'b0_00??: - begin - ozoneae(foo[20:18], foobar); - foobar = {foobar, " 1281"}; - ozoneae(foo[17:15], foobar); - ozonebmuop(foo[25:21], foobar); - ozoneae(foo[ 8: 6], foobar); - foobar = {foobar, " 1282"}; - dude(foobar); - $fwrite(fd, " 1283:%s", foobar); - end - 5'b0_01??: - begin - ozoneae(foo[20:18], foobar); - foobar = {foobar, " 1284"}; - ozoneae(foo[17:15], foobar); - ozonebmuop(foo[25:21], foobar); - ozonearm(foo[ 8: 6], foobar); - dude(foobar); - $fwrite(fd, " 1285:%s", foobar); - end - 5'b0_1011: - begin - ozoneae(foo[20:18], foobar); - foobar = {foobar, " 1286"}; - ozonebmuop(foo[25:21], foobar); - foobar = {foobar, " 1287"}; - ozoneae(foo[ 8: 6], foobar); - foobar = {foobar, " 1288"}; - dude(foobar); - $fwrite(fd, " 1289:%s", foobar); - end - 5'b0_100?, - 5'b0_1010, - 5'b0_110? : - begin - ozoneae(foo[20:18], foobar); - foobar = {foobar, " 1290"}; - ozonebmuop(foo[25:21], foobar); - foobar = {foobar, " 1291"}; - ozoneae(foo[17:15], foobar); - foobar = {foobar, " 1292"}; - ozoneae(foo[ 8: 6], foobar); - foobar = {foobar, " 1293"}; - dude(foobar); - $fwrite(fd, " 1294:%s", foobar); - end - 5'b0_1111 : - begin - ozoneae(foo[20:18], foobar); - foobar = {foobar, " 1295"}; - ozoneae(foo[17:15], foobar); - foobar = {foobar, " 1296"}; - ozoneae(foo[ 8: 6], foobar); - dude(foobar); - $fwrite(fd, " 1297:%s", foobar); - end - 5'b1_10??, - 5'b1_110?, - 5'b1_1110 : - begin - ozoneae(foo[20:18], foobar); - foobar = {foobar, " 1298"}; - ozonebmuop(foo[25:21], foobar); - foobar = {foobar, " 1299"}; - ozoneae(foo[17:15], foobar); - foobar = {foobar, " 1300"}; - ozonearm(foo[ 8: 6], foobar); - foobar = {foobar, " 1301"}; - dude(foobar); - $fwrite(fd, " 1302:%s", foobar); - end - endcase + foobar = " 1278"; + ozonecon(foo[14:10], foobar); + foobar = {foobar, " 1279"}; + casez (foo[25:21]) + 5'b0_1110, + 5'b1_0???, + 5'b1_1111: + begin + $fwrite(fd, " 1280"); + end + 5'b0_00??: + begin + ozoneae(foo[20:18], foobar); + foobar = {foobar, " 1281"}; + ozoneae(foo[17:15], foobar); + ozonebmuop(foo[25:21], foobar); + ozoneae(foo[ 8: 6], foobar); + foobar = {foobar, " 1282"}; + dude(foobar); + $fwrite(fd, " 1283:%s", foobar); + end + 5'b0_01??: + begin + ozoneae(foo[20:18], foobar); + foobar = {foobar, " 1284"}; + ozoneae(foo[17:15], foobar); + ozonebmuop(foo[25:21], foobar); + ozonearm(foo[ 8: 6], foobar); + dude(foobar); + $fwrite(fd, " 1285:%s", foobar); + end + 5'b0_1011: + begin + ozoneae(foo[20:18], foobar); + foobar = {foobar, " 1286"}; + ozonebmuop(foo[25:21], foobar); + foobar = {foobar, " 1287"}; + ozoneae(foo[ 8: 6], foobar); + foobar = {foobar, " 1288"}; + dude(foobar); + $fwrite(fd, " 1289:%s", foobar); + end + 5'b0_100?, + 5'b0_1010, + 5'b0_110? : + begin + ozoneae(foo[20:18], foobar); + foobar = {foobar, " 1290"}; + ozonebmuop(foo[25:21], foobar); + foobar = {foobar, " 1291"}; + ozoneae(foo[17:15], foobar); + foobar = {foobar, " 1292"}; + ozoneae(foo[ 8: 6], foobar); + foobar = {foobar, " 1293"}; + dude(foobar); + $fwrite(fd, " 1294:%s", foobar); + end + 5'b0_1111 : + begin + ozoneae(foo[20:18], foobar); + foobar = {foobar, " 1295"}; + ozoneae(foo[17:15], foobar); + foobar = {foobar, " 1296"}; + ozoneae(foo[ 8: 6], foobar); + dude(foobar); + $fwrite(fd, " 1297:%s", foobar); + end + 5'b1_10??, + 5'b1_110?, + 5'b1_1110 : + begin + ozoneae(foo[20:18], foobar); + foobar = {foobar, " 1298"}; + ozonebmuop(foo[25:21], foobar); + foobar = {foobar, " 1299"}; + ozoneae(foo[17:15], foobar); + foobar = {foobar, " 1300"}; + ozonearm(foo[ 8: 6], foobar); + foobar = {foobar, " 1301"}; + dude(foobar); + $fwrite(fd, " 1302:%s", foobar); + end + endcase end 17'b00_0010_?_????_??_???? : begin - $fwrite(fd, " 1304a:%x;%x", foobar, foo[25:20]); - ozonerab({1'b0, foo[25:20]}, foobar); - $fwrite(fd, " 1304b:%x", foobar); - foobar = {foobar, " 1303"}; - $fwrite(fd, " 1304c:%x;%x", foobar, foo[19:16]); - skyway(foo[19:16], foobar); - $fwrite(fd, " 1304d:%x", foobar); - dude(foobar); - $fwrite(fd, " 1304e:%x", foobar); - $fwrite(fd, " 1304:%s", foobar); + $fwrite(fd, " 1304a:%x;%x", foobar, foo[25:20]); + ozonerab({1'b0, foo[25:20]}, foobar); + $fwrite(fd, " 1304b:%x", foobar); + foobar = {foobar, " 1303"}; + $fwrite(fd, " 1304c:%x;%x", foobar, foo[19:16]); + skyway(foo[19:16], foobar); + $fwrite(fd, " 1304d:%x", foobar); + dude(foobar); + $fwrite(fd, " 1304e:%x", foobar); + $fwrite(fd, " 1304:%s", foobar); end 17'b00_01??_?_????_??_???? : begin - if (foo[27]) - begin - foobar = {foobar, " 1305"}; - if (foo[26]) - foobar = {foobar, " 1306"}; - else - foobar = {foobar, " 1307"}; - skyway(foo[19:16], foobar); - foobar = {foobar, " 1308"}; - ozonerab({1'b0, foo[25:20]}, foobar); - end - else - begin - ozonerab({1'b0, foo[25:20]}, foobar); - foobar = {foobar, " 1309"}; - if (foo[26]) - foobar = {foobar, " 1310"}; - else - foobar = {foobar, " 1311"}; - skyway(foo[19:16], foobar); - foobar = {foobar, " 1312"}; - end - dude(foobar); - $fwrite(fd, " 1313:%s", foobar); + if (foo[27]) + begin + foobar = {foobar, " 1305"}; + if (foo[26]) + foobar = {foobar, " 1306"}; + else + foobar = {foobar, " 1307"}; + skyway(foo[19:16], foobar); + foobar = {foobar, " 1308"}; + ozonerab({1'b0, foo[25:20]}, foobar); + end + else + begin + ozonerab({1'b0, foo[25:20]}, foobar); + foobar = {foobar, " 1309"}; + if (foo[26]) + foobar = {foobar, " 1310"}; + else + foobar = {foobar, " 1311"}; + skyway(foo[19:16], foobar); + foobar = {foobar, " 1312"}; + end + dude(foobar); + $fwrite(fd, " 1313:%s", foobar); end 17'b01_000?_?_????_??_???? : begin - if (foo[26]) - begin - ozonerb(foo[25:20], foobar); - foobar = {foobar, " 1314"}; - ozoneae(foo[18:16], foobar); - ozonehl(foo[19], foobar); - end - else - begin - ozoneae(foo[18:16], foobar); - ozonehl(foo[19], foobar); - foobar = {foobar, " 1315"}; - ozonerb(foo[25:20], foobar); - end - dude(foobar); - $fwrite(fd, " 1316:%s", foobar); + if (foo[26]) + begin + ozonerb(foo[25:20], foobar); + foobar = {foobar, " 1314"}; + ozoneae(foo[18:16], foobar); + ozonehl(foo[19], foobar); + end + else + begin + ozoneae(foo[18:16], foobar); + ozonehl(foo[19], foobar); + foobar = {foobar, " 1315"}; + ozonerb(foo[25:20], foobar); + end + dude(foobar); + $fwrite(fd, " 1316:%s", foobar); end 17'b01_10??_?_????_??_???? : begin - if (foo[27]) - begin - ozonerab({1'b0, foo[25:20]}, foobar); - foobar = {foobar, " 1317"}; - ozonerx(foo, foobar); - end - else - begin - ozonerx(foo, foobar); - foobar = {foobar, " 1318"}; - ozonerab({1'b0, foo[25:20]}, foobar); - end - dude(foobar); - $fwrite(fd, " 1319:%s", foobar); + if (foo[27]) + begin + ozonerab({1'b0, foo[25:20]}, foobar); + foobar = {foobar, " 1317"}; + ozonerx(foo, foobar); + end + else + begin + ozonerx(foo, foobar); + foobar = {foobar, " 1318"}; + ozonerab({1'b0, foo[25:20]}, foobar); + end + dude(foobar); + $fwrite(fd, " 1319:%s", foobar); end 17'b11_101?_?_????_??_???? : begin - ozonerab (foo[26:20], foobar); - foobar = {foobar, " 1320"}; - skyway(foo[19:16], foobar); - skyway(foo[15:12], foobar); - skyway(foo[11: 8], foobar); - skyway(foo[ 7: 4], foobar); - skyway(foo[ 3: 0], foobar); - dude(foobar); - $fwrite(fd, " 1321:%s", foobar); + ozonerab (foo[26:20], foobar); + foobar = {foobar, " 1320"}; + skyway(foo[19:16], foobar); + skyway(foo[15:12], foobar); + skyway(foo[11: 8], foobar); + skyway(foo[ 7: 4], foobar); + skyway(foo[ 3: 0], foobar); + dude(foobar); + $fwrite(fd, " 1321:%s", foobar); end 17'b11_0000_?_????_??_???? : begin - casez (foo[25:23]) - 3'b00?: - begin - ozonerab(foo[22:16], foobar); - foobar = {foobar, " 1322"}; - end - 3'b01?: - begin - foobar = {foobar, " 1323"}; - if (foo[22:16]>=7'h60) - foobar = {foobar, " 1324"}; - else - ozonerab(foo[22:16], foobar); - end - 3'b110: - foobar = {foobar, " 1325"}; - 3'b10?: - begin - foobar = {foobar, " 1326"}; - if (foo[22:16]>=7'h60) - foobar = {foobar, " 1327"}; - else - ozonerab(foo[22:16], foobar); - end - 3'b111: - begin - foobar = {foobar, " 1328"}; - ozonerab(foo[22:16], foobar); - foobar = {foobar, " 1329"}; - end - endcase - dude(foobar); - $fwrite(fd, " 1330:%s", foobar); + casez (foo[25:23]) + 3'b00?: + begin + ozonerab(foo[22:16], foobar); + foobar = {foobar, " 1322"}; + end + 3'b01?: + begin + foobar = {foobar, " 1323"}; + if (foo[22:16]>=7'h60) + foobar = {foobar, " 1324"}; + else + ozonerab(foo[22:16], foobar); + end + 3'b110: + foobar = {foobar, " 1325"}; + 3'b10?: + begin + foobar = {foobar, " 1326"}; + if (foo[22:16]>=7'h60) + foobar = {foobar, " 1327"}; + else + ozonerab(foo[22:16], foobar); + end + 3'b111: + begin + foobar = {foobar, " 1328"}; + ozonerab(foo[22:16], foobar); + foobar = {foobar, " 1329"}; + end + endcase + dude(foobar); + $fwrite(fd, " 1330:%s", foobar); end 17'b00_10??_?_????_?1_0000 : begin - if (foo[27]) - begin - foobar = {foobar, " 1331"}; - ozonerp(foo[14:12], foobar); - foobar = {foobar, " 1332"}; - skyway(foo[19:16], foobar); - skyway({foo[15],foo[11: 9]}, foobar); - skyway(foo[ 8: 5], foobar); - foobar = {foobar, " 1333"}; - if (foo[26:20]>=7'h60) - foobar = {foobar, " 1334"}; - else - ozonerab(foo[26:20], foobar); - end - else - begin - ozonerab(foo[26:20], foobar); - foobar = {foobar, " 1335"}; - foobar = {foobar, " 1336"}; - ozonerp(foo[14:12], foobar); - foobar = {foobar, " 1337"}; - skyway(foo[19:16], foobar); - skyway({foo[15],foo[11: 9]}, foobar); - skyway(foo[ 8: 5], foobar); - foobar = {foobar, " 1338"}; - end - dude(foobar); - $fwrite(fd, " 1339:%s", foobar); + if (foo[27]) + begin + foobar = {foobar, " 1331"}; + ozonerp(foo[14:12], foobar); + foobar = {foobar, " 1332"}; + skyway(foo[19:16], foobar); + skyway({foo[15],foo[11: 9]}, foobar); + skyway(foo[ 8: 5], foobar); + foobar = {foobar, " 1333"}; + if (foo[26:20]>=7'h60) + foobar = {foobar, " 1334"}; + else + ozonerab(foo[26:20], foobar); + end + else + begin + ozonerab(foo[26:20], foobar); + foobar = {foobar, " 1335"}; + foobar = {foobar, " 1336"}; + ozonerp(foo[14:12], foobar); + foobar = {foobar, " 1337"}; + skyway(foo[19:16], foobar); + skyway({foo[15],foo[11: 9]}, foobar); + skyway(foo[ 8: 5], foobar); + foobar = {foobar, " 1338"}; + end + dude(foobar); + $fwrite(fd, " 1339:%s", foobar); end 17'b00_101?_1_0000_?1_0010 : if (~|foo[11: 7]) - begin - if (foo[ 6]) - begin - foobar = {foobar, " 1340"}; - ozonerp(foo[14:12], foobar); - foobar = {foobar, " 1341"}; - ozonejk(foo[ 5], foobar); - foobar = {foobar, " 1342"}; - if (foo[26:20]>=7'h60) - foobar = {foobar, " 1343"}; - else - ozonerab(foo[26:20], foobar); - end - else - begin - ozonerab(foo[26:20], foobar); - foobar = {foobar, " 1344"}; - foobar = {foobar, " 1345"}; - ozonerp(foo[14:12], foobar); - foobar = {foobar, " 1346"}; - ozonejk(foo[ 5], foobar); - foobar = {foobar, " 1347"}; - end - dude(foobar); - $fwrite(fd, " 1348:%s", foobar); - end + begin + if (foo[ 6]) + begin + foobar = {foobar, " 1340"}; + ozonerp(foo[14:12], foobar); + foobar = {foobar, " 1341"}; + ozonejk(foo[ 5], foobar); + foobar = {foobar, " 1342"}; + if (foo[26:20]>=7'h60) + foobar = {foobar, " 1343"}; + else + ozonerab(foo[26:20], foobar); + end + else + begin + ozonerab(foo[26:20], foobar); + foobar = {foobar, " 1344"}; + foobar = {foobar, " 1345"}; + ozonerp(foo[14:12], foobar); + foobar = {foobar, " 1346"}; + ozonejk(foo[ 5], foobar); + foobar = {foobar, " 1347"}; + end + dude(foobar); + $fwrite(fd, " 1348:%s", foobar); + end else - $fwrite(fd, " 1349"); + $fwrite(fd, " 1349"); 17'b00_100?_0_0011_?1_0101 : if (~|foo[ 8: 7]) - begin - if (foo[6]) - begin - ozonerab(foo[26:20], foobar); - foobar = {foobar, " 1350"}; - ozoneye(foo[14: 9],foo[ 5], foobar); - end - else - begin - ozoneye(foo[14: 9],foo[ 5], foobar); - foobar = {foobar, " 1351"}; - if (foo[26:20]>=7'h60) - foobar = {foobar, " 1352"}; - else - ozonerab(foo[26:20], foobar); - end - dude(foobar); - $fwrite(fd, " 1353:%s", foobar); - end + begin + if (foo[6]) + begin + ozonerab(foo[26:20], foobar); + foobar = {foobar, " 1350"}; + ozoneye(foo[14: 9],foo[ 5], foobar); + end + else + begin + ozoneye(foo[14: 9],foo[ 5], foobar); + foobar = {foobar, " 1351"}; + if (foo[26:20]>=7'h60) + foobar = {foobar, " 1352"}; + else + ozonerab(foo[26:20], foobar); + end + dude(foobar); + $fwrite(fd, " 1353:%s", foobar); + end else - $fwrite(fd, " 1354"); + $fwrite(fd, " 1354"); 17'b00_1001_0_0000_?1_0010 : if (~|foo[25:20]) - begin - ozoneye(foo[14: 9],1'b0, foobar); - foobar = {foobar, " 1355"}; - ozonef1e_h(foo[11: 9],foobar); - foobar = {foobar, " 1356"}; - ozonef1e_h(foo[ 7: 5],foobar); - foobar = {foobar, " 1357"}; - ozonexe(foo[ 8: 5], foobar); - dude(foobar); - $fwrite(fd, " 1358:%s", foobar); - end + begin + ozoneye(foo[14: 9],1'b0, foobar); + foobar = {foobar, " 1355"}; + ozonef1e_h(foo[11: 9],foobar); + foobar = {foobar, " 1356"}; + ozonef1e_h(foo[ 7: 5],foobar); + foobar = {foobar, " 1357"}; + ozonexe(foo[ 8: 5], foobar); + dude(foobar); + $fwrite(fd, " 1358:%s", foobar); + end else - $fwrite(fd, " 1359"); + $fwrite(fd, " 1359"); 17'b00_101?_0_????_?1_0010 : if (~foo[13]) - begin - if (foo[12]) - begin - foobar = {foobar, " 1360"}; - if (foo[26:20]>=7'h60) - foobar = {foobar, " 1361"}; - else - ozonerab(foo[26:20], foobar); - foobar = {foobar, " 1362"}; - foobar = {foobar, " 1363"}; - skyway({1'b0,foo[18:16]}, foobar); - skyway({foo[15],foo[11: 9]}, foobar); - skyway(foo[ 8: 5], foobar); - dude(foobar); - $fwrite(fd, " 1364:%s", foobar); - end - else - begin - ozonerab(foo[26:20], foobar); - foobar = {foobar, " 1365"}; - foobar = {foobar, " 1366"}; - skyway({1'b0,foo[18:16]}, foobar); - skyway({foo[15],foo[11: 9]}, foobar); - skyway(foo[ 8: 5], foobar); - dude(foobar); - $fwrite(fd, " 1367:%s", foobar); - end - end + begin + if (foo[12]) + begin + foobar = {foobar, " 1360"}; + if (foo[26:20]>=7'h60) + foobar = {foobar, " 1361"}; + else + ozonerab(foo[26:20], foobar); + foobar = {foobar, " 1362"}; + foobar = {foobar, " 1363"}; + skyway({1'b0,foo[18:16]}, foobar); + skyway({foo[15],foo[11: 9]}, foobar); + skyway(foo[ 8: 5], foobar); + dude(foobar); + $fwrite(fd, " 1364:%s", foobar); + end + else + begin + ozonerab(foo[26:20], foobar); + foobar = {foobar, " 1365"}; + foobar = {foobar, " 1366"}; + skyway({1'b0,foo[18:16]}, foobar); + skyway({foo[15],foo[11: 9]}, foobar); + skyway(foo[ 8: 5], foobar); + dude(foobar); + $fwrite(fd, " 1367:%s", foobar); + end + end else - $fwrite(fd, " 1368"); + $fwrite(fd, " 1368"); 17'b01_01??_?_????_??_???? : begin - ozonerab({1'b0,foo[27:26],foo[19:16]}, foobar); - foobar = {foobar, " 1369"}; - ozonerab({1'b0,foo[25:20]}, foobar); - dude(foobar); - $fwrite(fd, " 1370:%s", foobar); + ozonerab({1'b0,foo[27:26],foo[19:16]}, foobar); + foobar = {foobar, " 1369"}; + ozonerab({1'b0,foo[25:20]}, foobar); + dude(foobar); + $fwrite(fd, " 1370:%s", foobar); end 17'b00_100?_?_???0_11_0101 : if (~foo[6]) - begin - foobar = " 1371"; - ozonecon(foo[14:10], foobar); - foobar = {foobar, " 1372"}; - ozonerab({foo[ 9: 7],foo[19:16]}, foobar); - foobar = {foobar, " 1373"}; - ozonerab({foo[26:20]}, foobar); - dude(foobar); - $fwrite(fd, " 1374:%s", foobar); - end + begin + foobar = " 1371"; + ozonecon(foo[14:10], foobar); + foobar = {foobar, " 1372"}; + ozonerab({foo[ 9: 7],foo[19:16]}, foobar); + foobar = {foobar, " 1373"}; + ozonerab({foo[26:20]}, foobar); + dude(foobar); + $fwrite(fd, " 1374:%s", foobar); + end else - $fwrite(fd, " 1375"); + $fwrite(fd, " 1375"); 17'b00_1000_?_????_?1_0010 : if (~|foo[25:24]) - begin - ozonery(foo[23:20], foobar); - foobar = {foobar, " 1376"}; - ozonerp(foo[14:12], foobar); - foobar = {foobar, " 1377"}; - skyway(foo[19:16], foobar); - skyway({foo[15],foo[11: 9]}, foobar); - skyway(foo[ 8: 5], foobar); - dude(foobar); - $fwrite(fd, " 1378:%s", foobar); - end + begin + ozonery(foo[23:20], foobar); + foobar = {foobar, " 1376"}; + ozonerp(foo[14:12], foobar); + foobar = {foobar, " 1377"}; + skyway(foo[19:16], foobar); + skyway({foo[15],foo[11: 9]}, foobar); + skyway(foo[ 8: 5], foobar); + dude(foobar); + $fwrite(fd, " 1378:%s", foobar); + end else if ((foo[25:24] == 2'b10) & ~|foo[19:15] & ~|foo[11: 6]) - begin - ozonery(foo[23:20], foobar); - foobar = {foobar, " 1379"}; - ozonerp(foo[14:12], foobar); - foobar = {foobar, " 1380"}; - ozonejk(foo[ 5], foobar); - dude(foobar); - $fwrite(fd, " 1381:%s", foobar); - end + begin + ozonery(foo[23:20], foobar); + foobar = {foobar, " 1379"}; + ozonerp(foo[14:12], foobar); + foobar = {foobar, " 1380"}; + ozonejk(foo[ 5], foobar); + dude(foobar); + $fwrite(fd, " 1381:%s", foobar); + end else - $fwrite(fd, " 1382"); + $fwrite(fd, " 1382"); 17'b11_01??_?_????_??_????, 17'b10_00??_?_????_??_???? : - if (foo[30]) - $fwrite(fd, " 1383:%s", foo[27:16]); - else - $fwrite(fd, " 1384:%s", foo[27:16]); + if (foo[30]) + $fwrite(fd, " 1383:%s", foo[27:16]); + else + $fwrite(fd, " 1384:%s", foo[27:16]); 17'b00_10??_?_????_01_1000 : if (~foo[6]) - begin - if (foo[7]) - $fwrite(fd, " 1385:%s", foo[27: 8]); - else - $fwrite(fd, " 1386:%s", foo[27: 8]); - end + begin + if (foo[7]) + $fwrite(fd, " 1385:%s", foo[27: 8]); + else + $fwrite(fd, " 1386:%s", foo[27: 8]); + end else - $fwrite(fd, " 1387"); + $fwrite(fd, " 1387"); 17'b00_10??_?_????_11_1000 : begin - foobar = " 1388"; - ozonecon(foo[14:10], foobar); - foobar = {foobar, " 1389"}; - if (foo[15]) - foobar = {foobar, " 1390"}; - else - foobar = {foobar, " 1391"}; - skyway(foo[27:24], foobar); - skyway(foo[23:20], foobar); - skyway(foo[19:16], foobar); - skyway(foo[ 9: 6], foobar); - dude(foobar); - $fwrite(fd, " 1392:%s", foobar); + foobar = " 1388"; + ozonecon(foo[14:10], foobar); + foobar = {foobar, " 1389"}; + if (foo[15]) + foobar = {foobar, " 1390"}; + else + foobar = {foobar, " 1391"}; + skyway(foo[27:24], foobar); + skyway(foo[23:20], foobar); + skyway(foo[19:16], foobar); + skyway(foo[ 9: 6], foobar); + dude(foobar); + $fwrite(fd, " 1392:%s", foobar); end 17'b11_0001_?_????_??_???? : casez (foo[25:22]) - 4'b01?? : - begin - foobar = " 1393"; - ozonecon(foo[20:16], foobar); - case (foo[23:21]) - 3'h0 : foobar = {foobar, " 1394"}; - 3'h1 : foobar = {foobar, " 1395"}; - 3'h2 : foobar = {foobar, " 1396"}; - 3'h3 : foobar = {foobar, " 1397"}; - 3'h4 : foobar = {foobar, " 1398"}; - 3'h5 : foobar = {foobar, " 1399"}; - 3'h6 : foobar = {foobar, " 1400"}; - 3'h7 : foobar = {foobar, " 1401"}; - endcase - dude(foobar); - $fwrite(fd, " 1402:%s", foobar); - end - 4'b0000 : - $fwrite(fd, " 1403:%s", foo[21:16]); - 4'b0010 : - if (~|foo[21:16]) + 4'b01?? : + begin + foobar = " 1393"; + ozonecon(foo[20:16], foobar); + case (foo[23:21]) + 3'h0 : foobar = {foobar, " 1394"}; + 3'h1 : foobar = {foobar, " 1395"}; + 3'h2 : foobar = {foobar, " 1396"}; + 3'h3 : foobar = {foobar, " 1397"}; + 3'h4 : foobar = {foobar, " 1398"}; + 3'h5 : foobar = {foobar, " 1399"}; + 3'h6 : foobar = {foobar, " 1400"}; + 3'h7 : foobar = {foobar, " 1401"}; + endcase + dude(foobar); + $fwrite(fd, " 1402:%s", foobar); + end + 4'b0000 : + $fwrite(fd, " 1403:%s", foo[21:16]); + 4'b0010 : + if (~|foo[21:16]) $fwrite(fd, " 1404"); - 4'b1010 : - if (~|foo[21:17]) - begin - if (foo[16]) - $fwrite(fd, " 1405"); - else - $fwrite(fd, " 1406"); - end - default : - $fwrite(fd, " 1407"); + 4'b1010 : + if (~|foo[21:17]) + begin + if (foo[16]) + $fwrite(fd, " 1405"); + else + $fwrite(fd, " 1406"); + end + default : + $fwrite(fd, " 1407"); endcase 17'b01_11??_?_????_??_???? : if (foo[27:23] === 5'h00) - $fwrite(fd, " 1408:%s", foo[22:16]); + $fwrite(fd, " 1408:%s", foo[22:16]); else - $fwrite(fd, " 1409:%s", foo[22:16]); + $fwrite(fd, " 1409:%s", foo[22:16]); default: $fwrite(fd, " 1410"); - endcase + endcase end endtask diff --git a/test_regress/t/t_case_write2_tasks.v b/test_regress/t/t_case_write2_tasks.v index eb0298ae1..cae09726e 100644 --- a/test_regress/t/t_case_write2_tasks.v +++ b/test_regress/t/t_case_write2_tasks.v @@ -19,137 +19,137 @@ module t_case_write2_tasks (); input [`FD_BITS] fd; // verilator no_inline_task begin - case (rab[6:0]) - 7'h00 : $fwrite (fd, " 0"); - 7'h01 : $fwrite (fd, " 1"); - 7'h02 : $fwrite (fd, " 2"); - 7'h03 : $fwrite (fd, " 3"); - 7'h04 : $fwrite (fd, " 4"); - 7'h05 : $fwrite (fd, " 5"); - 7'h06 : $fwrite (fd, " 6"); - 7'h07 : $fwrite (fd, " 7"); - 7'h08 : $fwrite (fd, " 8"); - 7'h09 : $fwrite (fd, " 9"); - 7'h0a : $fwrite (fd, " 10"); - 7'h0b : $fwrite (fd, " 11"); - 7'h0c : $fwrite (fd, " 12"); - 7'h0d : $fwrite (fd, " 13"); - 7'h0e : $fwrite (fd, " 14"); - 7'h0f : $fwrite (fd, " 15"); - 7'h10 : $fwrite (fd, " 16"); - 7'h11 : $fwrite (fd, " 17"); - 7'h12 : $fwrite (fd, " 18"); - 7'h13 : $fwrite (fd, " 19"); - 7'h14 : $fwrite (fd, " 20"); - 7'h15 : $fwrite (fd, " 21"); - 7'h16 : $fwrite (fd, " 22"); - 7'h17 : $fwrite (fd, " 23"); - 7'h18 : $fwrite (fd, " 24"); - 7'h19 : $fwrite (fd, " 25"); - 7'h1a : $fwrite (fd, " 26"); - 7'h1b : $fwrite (fd, " 27"); - 7'h1c : $fwrite (fd, " 28"); - 7'h1d : $fwrite (fd, " 29"); - 7'h1e : $fwrite (fd, " 30"); - 7'h1f : $fwrite (fd, " 31"); - 7'h20 : $fwrite (fd, " 32"); - 7'h21 : $fwrite (fd, " 33"); - 7'h22 : $fwrite (fd, " 34"); - 7'h23 : $fwrite (fd, " 35"); - 7'h24 : $fwrite (fd, " 36"); - 7'h25 : $fwrite (fd, " 37"); - 7'h26 : $fwrite (fd, " 38"); - 7'h27 : $fwrite (fd, " 39"); - 7'h28 : $fwrite (fd, " 40"); - 7'h29 : $fwrite (fd, " 41"); - 7'h2a : $fwrite (fd, " 42"); - 7'h2b : $fwrite (fd, " 43"); - 7'h2c : $fwrite (fd, " 44"); - 7'h2d : $fwrite (fd, " 45"); - 7'h2e : $fwrite (fd, " 46"); - 7'h2f : $fwrite (fd, " 47"); - 7'h30 : $fwrite (fd, " 48"); - 7'h31 : $fwrite (fd, " 49"); - 7'h32 : $fwrite (fd, " 50"); - 7'h33 : $fwrite (fd, " 51"); - 7'h34 : $fwrite (fd, " 52"); - 7'h35 : $fwrite (fd, " 53"); - 7'h36 : $fwrite (fd, " 54"); - 7'h37 : $fwrite (fd, " 55"); - 7'h38 : $fwrite (fd, " 56"); - 7'h39 : $fwrite (fd, " 57"); - 7'h3a : $fwrite (fd, " 58"); - 7'h3b : $fwrite (fd, " 59"); - 7'h3c : $fwrite (fd, " 60"); - 7'h3d : $fwrite (fd, " 61"); - 7'h3e : $fwrite (fd, " 62"); - 7'h3f : $fwrite (fd, " 63"); - 7'h40 : $fwrite (fd, " 64"); - 7'h41 : $fwrite (fd, " 65"); - 7'h42 : $fwrite (fd, " 66"); - 7'h43 : $fwrite (fd, " 67"); - 7'h44 : $fwrite (fd, " 68"); - 7'h45 : $fwrite (fd, " 69"); - 7'h46 : $fwrite (fd, " 70"); - 7'h47 : $fwrite (fd, " 71"); - 7'h48 : $fwrite (fd, " 72"); - 7'h49 : $fwrite (fd, " 73"); - 7'h4a : $fwrite (fd, " 74"); - 7'h4b : $fwrite (fd, " 75"); - 7'h4c : $fwrite (fd, " 76"); - 7'h4d : $fwrite (fd, " 77"); - 7'h4e : $fwrite (fd, " 78"); - 7'h4f : $fwrite (fd, " 79"); - 7'h50 : $fwrite (fd, " 80"); - 7'h51 : $fwrite (fd, " 81"); - 7'h52 : $fwrite (fd, " 82"); - 7'h53 : $fwrite (fd, " 83"); - 7'h54 : $fwrite (fd, " 84"); - 7'h55 : $fwrite (fd, " 85"); - 7'h56 : $fwrite (fd, " 86"); - 7'h57 : $fwrite (fd, " 87"); - 7'h58 : $fwrite (fd, " 88"); - 7'h59 : $fwrite (fd, " 89"); - 7'h5a : $fwrite (fd, " 90"); - 7'h5b : $fwrite (fd, " 91"); - 7'h5c : $fwrite (fd, " 92"); - 7'h5d : $fwrite (fd, " 93"); - 7'h5e : $fwrite (fd, " 94"); - 7'h5f : $fwrite (fd, " 95"); - 7'h60 : $fwrite (fd, " 96"); - 7'h61 : $fwrite (fd, " 97"); - 7'h62 : $fwrite (fd, " 98"); - 7'h63 : $fwrite (fd, " 99"); - 7'h64 : $fwrite (fd, " 100"); - 7'h65 : $fwrite (fd, " 101"); - 7'h66 : $fwrite (fd, " 102"); - 7'h67 : $fwrite (fd, " 103"); - 7'h68 : $fwrite (fd, " 104"); - 7'h69 : $fwrite (fd, " 105"); - 7'h6a : $fwrite (fd, " 106"); - 7'h6b : $fwrite (fd, " 107"); - 7'h6c : $fwrite (fd, " 108"); - 7'h6d : $fwrite (fd, " 109"); - 7'h6e : $fwrite (fd, " 110"); - 7'h6f : $fwrite (fd, " 111"); - 7'h70 : $fwrite (fd, " 112"); - 7'h71 : $fwrite (fd, " 113"); - 7'h72 : $fwrite (fd, " 114"); - 7'h73 : $fwrite (fd, " 115"); - 7'h74 : $fwrite (fd, " 116"); - 7'h75 : $fwrite (fd, " 117"); - 7'h76 : $fwrite (fd, " 118"); - 7'h77 : $fwrite (fd, " 119"); - 7'h78 : $fwrite (fd, " 120"); - 7'h79 : $fwrite (fd, " 121"); - 7'h7a : $fwrite (fd, " 122"); - 7'h7b : $fwrite (fd, " 123"); - 7'h7c : $fwrite (fd, " 124"); - 7'h7d : $fwrite (fd, " 125"); - 7'h7e : $fwrite (fd, " 126"); - 7'h7f : $fwrite (fd, " 127"); - default:$fwrite (fd, " 128"); - endcase + case (rab[6:0]) + 7'h00 : $fwrite (fd, " 0"); + 7'h01 : $fwrite (fd, " 1"); + 7'h02 : $fwrite (fd, " 2"); + 7'h03 : $fwrite (fd, " 3"); + 7'h04 : $fwrite (fd, " 4"); + 7'h05 : $fwrite (fd, " 5"); + 7'h06 : $fwrite (fd, " 6"); + 7'h07 : $fwrite (fd, " 7"); + 7'h08 : $fwrite (fd, " 8"); + 7'h09 : $fwrite (fd, " 9"); + 7'h0a : $fwrite (fd, " 10"); + 7'h0b : $fwrite (fd, " 11"); + 7'h0c : $fwrite (fd, " 12"); + 7'h0d : $fwrite (fd, " 13"); + 7'h0e : $fwrite (fd, " 14"); + 7'h0f : $fwrite (fd, " 15"); + 7'h10 : $fwrite (fd, " 16"); + 7'h11 : $fwrite (fd, " 17"); + 7'h12 : $fwrite (fd, " 18"); + 7'h13 : $fwrite (fd, " 19"); + 7'h14 : $fwrite (fd, " 20"); + 7'h15 : $fwrite (fd, " 21"); + 7'h16 : $fwrite (fd, " 22"); + 7'h17 : $fwrite (fd, " 23"); + 7'h18 : $fwrite (fd, " 24"); + 7'h19 : $fwrite (fd, " 25"); + 7'h1a : $fwrite (fd, " 26"); + 7'h1b : $fwrite (fd, " 27"); + 7'h1c : $fwrite (fd, " 28"); + 7'h1d : $fwrite (fd, " 29"); + 7'h1e : $fwrite (fd, " 30"); + 7'h1f : $fwrite (fd, " 31"); + 7'h20 : $fwrite (fd, " 32"); + 7'h21 : $fwrite (fd, " 33"); + 7'h22 : $fwrite (fd, " 34"); + 7'h23 : $fwrite (fd, " 35"); + 7'h24 : $fwrite (fd, " 36"); + 7'h25 : $fwrite (fd, " 37"); + 7'h26 : $fwrite (fd, " 38"); + 7'h27 : $fwrite (fd, " 39"); + 7'h28 : $fwrite (fd, " 40"); + 7'h29 : $fwrite (fd, " 41"); + 7'h2a : $fwrite (fd, " 42"); + 7'h2b : $fwrite (fd, " 43"); + 7'h2c : $fwrite (fd, " 44"); + 7'h2d : $fwrite (fd, " 45"); + 7'h2e : $fwrite (fd, " 46"); + 7'h2f : $fwrite (fd, " 47"); + 7'h30 : $fwrite (fd, " 48"); + 7'h31 : $fwrite (fd, " 49"); + 7'h32 : $fwrite (fd, " 50"); + 7'h33 : $fwrite (fd, " 51"); + 7'h34 : $fwrite (fd, " 52"); + 7'h35 : $fwrite (fd, " 53"); + 7'h36 : $fwrite (fd, " 54"); + 7'h37 : $fwrite (fd, " 55"); + 7'h38 : $fwrite (fd, " 56"); + 7'h39 : $fwrite (fd, " 57"); + 7'h3a : $fwrite (fd, " 58"); + 7'h3b : $fwrite (fd, " 59"); + 7'h3c : $fwrite (fd, " 60"); + 7'h3d : $fwrite (fd, " 61"); + 7'h3e : $fwrite (fd, " 62"); + 7'h3f : $fwrite (fd, " 63"); + 7'h40 : $fwrite (fd, " 64"); + 7'h41 : $fwrite (fd, " 65"); + 7'h42 : $fwrite (fd, " 66"); + 7'h43 : $fwrite (fd, " 67"); + 7'h44 : $fwrite (fd, " 68"); + 7'h45 : $fwrite (fd, " 69"); + 7'h46 : $fwrite (fd, " 70"); + 7'h47 : $fwrite (fd, " 71"); + 7'h48 : $fwrite (fd, " 72"); + 7'h49 : $fwrite (fd, " 73"); + 7'h4a : $fwrite (fd, " 74"); + 7'h4b : $fwrite (fd, " 75"); + 7'h4c : $fwrite (fd, " 76"); + 7'h4d : $fwrite (fd, " 77"); + 7'h4e : $fwrite (fd, " 78"); + 7'h4f : $fwrite (fd, " 79"); + 7'h50 : $fwrite (fd, " 80"); + 7'h51 : $fwrite (fd, " 81"); + 7'h52 : $fwrite (fd, " 82"); + 7'h53 : $fwrite (fd, " 83"); + 7'h54 : $fwrite (fd, " 84"); + 7'h55 : $fwrite (fd, " 85"); + 7'h56 : $fwrite (fd, " 86"); + 7'h57 : $fwrite (fd, " 87"); + 7'h58 : $fwrite (fd, " 88"); + 7'h59 : $fwrite (fd, " 89"); + 7'h5a : $fwrite (fd, " 90"); + 7'h5b : $fwrite (fd, " 91"); + 7'h5c : $fwrite (fd, " 92"); + 7'h5d : $fwrite (fd, " 93"); + 7'h5e : $fwrite (fd, " 94"); + 7'h5f : $fwrite (fd, " 95"); + 7'h60 : $fwrite (fd, " 96"); + 7'h61 : $fwrite (fd, " 97"); + 7'h62 : $fwrite (fd, " 98"); + 7'h63 : $fwrite (fd, " 99"); + 7'h64 : $fwrite (fd, " 100"); + 7'h65 : $fwrite (fd, " 101"); + 7'h66 : $fwrite (fd, " 102"); + 7'h67 : $fwrite (fd, " 103"); + 7'h68 : $fwrite (fd, " 104"); + 7'h69 : $fwrite (fd, " 105"); + 7'h6a : $fwrite (fd, " 106"); + 7'h6b : $fwrite (fd, " 107"); + 7'h6c : $fwrite (fd, " 108"); + 7'h6d : $fwrite (fd, " 109"); + 7'h6e : $fwrite (fd, " 110"); + 7'h6f : $fwrite (fd, " 111"); + 7'h70 : $fwrite (fd, " 112"); + 7'h71 : $fwrite (fd, " 113"); + 7'h72 : $fwrite (fd, " 114"); + 7'h73 : $fwrite (fd, " 115"); + 7'h74 : $fwrite (fd, " 116"); + 7'h75 : $fwrite (fd, " 117"); + 7'h76 : $fwrite (fd, " 118"); + 7'h77 : $fwrite (fd, " 119"); + 7'h78 : $fwrite (fd, " 120"); + 7'h79 : $fwrite (fd, " 121"); + 7'h7a : $fwrite (fd, " 122"); + 7'h7b : $fwrite (fd, " 123"); + 7'h7c : $fwrite (fd, " 124"); + 7'h7d : $fwrite (fd, " 125"); + 7'h7e : $fwrite (fd, " 126"); + 7'h7f : $fwrite (fd, " 127"); + default:$fwrite (fd, " 128"); + endcase end endtask @@ -158,13 +158,13 @@ module t_case_write2_tasks (); input [`FD_BITS] fd; // verilator no_inline_task begin - case (rb[5:0]) - 6'h10, - 6'h17, - 6'h1e, - 6'h1f: $fwrite (fd, " 129"); - default: ozonerab({1'b1, rb}, fd); - endcase + case (rb[5:0]) + 6'h10, + 6'h17, + 6'h1e, + 6'h1f: $fwrite (fd, " 129"); + default: ozonerab({1'b1, rb}, fd); + endcase end endtask @@ -174,44 +174,44 @@ module t_case_write2_tasks (); input [`FD_BITS] fd; // verilator no_inline_task begin - case (foo) - 2'h0 : + case (foo) + 2'h0 : begin - skyway({4{im16[15]}}, fd); - skyway({4{im16[15]}}, fd); - skyway(im16[15:12], fd); - skyway(im16[11: 8], fd); - skyway(im16[ 7: 4], fd); - skyway(im16[ 3:0], fd); - $fwrite (fd, " 130"); + skyway({4{im16[15]}}, fd); + skyway({4{im16[15]}}, fd); + skyway(im16[15:12], fd); + skyway(im16[11: 8], fd); + skyway(im16[ 7: 4], fd); + skyway(im16[ 3:0], fd); + $fwrite (fd, " 130"); end - 2'h1 : + 2'h1 : begin - $fwrite (fd, " 131"); - skyway(im16[15:12], fd); - skyway(im16[11: 8], fd); - skyway(im16[ 7: 4], fd); - skyway(im16[ 3:0], fd); + $fwrite (fd, " 131"); + skyway(im16[15:12], fd); + skyway(im16[11: 8], fd); + skyway(im16[ 7: 4], fd); + skyway(im16[ 3:0], fd); end - 2'h2 : + 2'h2 : begin - skyway({4{im16[15]}}, fd); - skyway({4{im16[15]}}, fd); - skyway(im16[15:12], fd); - skyway(im16[11: 8], fd); - skyway(im16[ 7: 4], fd); - skyway(im16[ 3:0], fd); - $fwrite (fd, " 132"); + skyway({4{im16[15]}}, fd); + skyway({4{im16[15]}}, fd); + skyway(im16[15:12], fd); + skyway(im16[11: 8], fd); + skyway(im16[ 7: 4], fd); + skyway(im16[ 3:0], fd); + $fwrite (fd, " 132"); end - 2'h3 : + 2'h3 : begin - $fwrite (fd, " 133"); - skyway(im16[15:12], fd); - skyway(im16[11: 8], fd); - skyway(im16[ 7: 4], fd); - skyway(im16[ 3:0], fd); + $fwrite (fd, " 133"); + skyway(im16[15:12], fd); + skyway(im16[11: 8], fd); + skyway(im16[ 7: 4], fd); + skyway(im16[ 3:0], fd); end - endcase + endcase end endtask @@ -220,24 +220,24 @@ module t_case_write2_tasks (); input [`FD_BITS] fd; // verilator no_inline_task begin - case (hex) - 4'h0 : $fwrite (fd, " 134"); - 4'h1 : $fwrite (fd, " 135"); - 4'h2 : $fwrite (fd, " 136"); - 4'h3 : $fwrite (fd, " 137"); - 4'h4 : $fwrite (fd, " 138"); - 4'h5 : $fwrite (fd, " 139"); - 4'h6 : $fwrite (fd, " 140"); - 4'h7 : $fwrite (fd, " 141"); - 4'h8 : $fwrite (fd, " 142"); - 4'h9 : $fwrite (fd, " 143"); - 4'ha : $fwrite (fd, " 144"); - 4'hb : $fwrite (fd, " 145"); - 4'hc : $fwrite (fd, " 146"); - 4'hd : $fwrite (fd, " 147"); - 4'he : $fwrite (fd, " 148"); - 4'hf : $fwrite (fd, " 149"); - endcase + case (hex) + 4'h0 : $fwrite (fd, " 134"); + 4'h1 : $fwrite (fd, " 135"); + 4'h2 : $fwrite (fd, " 136"); + 4'h3 : $fwrite (fd, " 137"); + 4'h4 : $fwrite (fd, " 138"); + 4'h5 : $fwrite (fd, " 139"); + 4'h6 : $fwrite (fd, " 140"); + 4'h7 : $fwrite (fd, " 141"); + 4'h8 : $fwrite (fd, " 142"); + 4'h9 : $fwrite (fd, " 143"); + 4'ha : $fwrite (fd, " 144"); + 4'hb : $fwrite (fd, " 145"); + 4'hc : $fwrite (fd, " 146"); + 4'hd : $fwrite (fd, " 147"); + 4'he : $fwrite (fd, " 148"); + 4'hf : $fwrite (fd, " 149"); + endcase end endtask @@ -246,16 +246,16 @@ module t_case_write2_tasks (); input [`FD_BITS] fd; // verilator no_inline_task begin - case (foo[11: 9]) - 3'h0 : $fwrite (fd, " 158"); - 3'h1 : $fwrite (fd, " 159"); - 3'h2 : $fwrite (fd, " 160"); - 3'h3 : $fwrite (fd, " 161"); - 3'h4 : $fwrite (fd, " 162"); - 3'h5 : $fwrite (fd, " 163"); - 3'h6 : $fwrite (fd, " 164"); - 3'h7 : $fwrite (fd, " 165"); - endcase + case (foo[11: 9]) + 3'h0 : $fwrite (fd, " 158"); + 3'h1 : $fwrite (fd, " 159"); + 3'h2 : $fwrite (fd, " 160"); + 3'h3 : $fwrite (fd, " 161"); + 3'h4 : $fwrite (fd, " 162"); + 3'h5 : $fwrite (fd, " 163"); + 3'h6 : $fwrite (fd, " 164"); + 3'h7 : $fwrite (fd, " 165"); + endcase end endtask @@ -264,10 +264,10 @@ module t_case_write2_tasks (); input [`FD_BITS] fd; // verilator no_inline_task begin - if (k) - $fwrite (fd, " 166"); - else - $fwrite (fd, " 167"); + if (k) + $fwrite (fd, " 166"); + else + $fwrite (fd, " 167"); end endtask @@ -276,52 +276,52 @@ module t_case_write2_tasks (); input [`FD_BITS] fd; // verilator no_inline_task begin - case (ae) - 3'b000 : $fwrite (fd, " 168"); - 3'b001 : $fwrite (fd, " 169"); - 3'b010 : $fwrite (fd, " 170"); - 3'b011 : $fwrite (fd, " 171"); - 3'b100 : $fwrite (fd, " 172"); - 3'b101 : $fwrite (fd, " 173"); - 3'b110 : $fwrite (fd, " 174"); - 3'b111 : $fwrite (fd, " 175"); - endcase + case (ae) + 3'b000 : $fwrite (fd, " 168"); + 3'b001 : $fwrite (fd, " 169"); + 3'b010 : $fwrite (fd, " 170"); + 3'b011 : $fwrite (fd, " 171"); + 3'b100 : $fwrite (fd, " 172"); + 3'b101 : $fwrite (fd, " 173"); + 3'b110 : $fwrite (fd, " 174"); + 3'b111 : $fwrite (fd, " 175"); + endcase end endtask task ozoneaee; input [ 2:0] aee; - input [`FD_BITS] fd; + input [`FD_BITS] fd; // verilator no_inline_task begin - case (aee) - 3'b001, - 3'b011, - 3'b101, - 3'b111 : $fwrite (fd, " 176"); - 3'b000 : $fwrite (fd, " 177"); - 3'b010 : $fwrite (fd, " 178"); - 3'b100 : $fwrite (fd, " 179"); - 3'b110 : $fwrite (fd, " 180"); - endcase + case (aee) + 3'b001, + 3'b011, + 3'b101, + 3'b111 : $fwrite (fd, " 176"); + 3'b000 : $fwrite (fd, " 177"); + 3'b010 : $fwrite (fd, " 178"); + 3'b100 : $fwrite (fd, " 179"); + 3'b110 : $fwrite (fd, " 180"); + endcase end endtask task ozoneape; input [ 2:0] ape; - input [`FD_BITS] fd; + input [`FD_BITS] fd; // verilator no_inline_task begin - case (ape) - 3'b001, - 3'b011, - 3'b101, - 3'b111 : $fwrite (fd, " 181"); - 3'b000 : $fwrite (fd, " 182"); - 3'b010 : $fwrite (fd, " 183"); - 3'b100 : $fwrite (fd, " 184"); - 3'b110 : $fwrite (fd, " 185"); - endcase + case (ape) + 3'b001, + 3'b011, + 3'b101, + 3'b111 : $fwrite (fd, " 181"); + 3'b000 : $fwrite (fd, " 182"); + 3'b010 : $fwrite (fd, " 183"); + 3'b100 : $fwrite (fd, " 184"); + 3'b110 : $fwrite (fd, " 185"); + endcase end endtask @@ -330,98 +330,98 @@ module t_case_write2_tasks (); input [`FD_BITS] fd; // verilator no_inline_task begin - case (foo[24:21]) - 4'h0 : + case (foo[24:21]) + 4'h0 : if (foo[26]) $fwrite (fd, " 186"); else $fwrite (fd, " 187"); - 4'h1 : + 4'h1 : case (foo[26:25]) 2'b00 : $fwrite (fd, " 188"); 2'b01 : $fwrite (fd, " 189"); 2'b10 : $fwrite (fd, " 190"); 2'b11 : $fwrite (fd, " 191"); endcase - 4'h2 : $fwrite (fd, " 192"); - 4'h3 : + 4'h2 : $fwrite (fd, " 192"); + 4'h3 : case (foo[26:25]) 2'b00 : $fwrite (fd, " 193"); 2'b01 : $fwrite (fd, " 194"); 2'b10 : $fwrite (fd, " 195"); 2'b11 : $fwrite (fd, " 196"); endcase - 4'h4 : + 4'h4 : if (foo[26]) $fwrite (fd, " 197"); else $fwrite (fd, " 198"); - 4'h5 : + 4'h5 : case (foo[26:25]) 2'b00 : $fwrite (fd, " 199"); 2'b01 : $fwrite (fd, " 200"); 2'b10 : $fwrite (fd, " 201"); 2'b11 : $fwrite (fd, " 202"); endcase - 4'h6 : $fwrite (fd, " 203"); - 4'h7 : + 4'h6 : $fwrite (fd, " 203"); + 4'h7 : case (foo[26:25]) 2'b00 : $fwrite (fd, " 204"); 2'b01 : $fwrite (fd, " 205"); 2'b10 : $fwrite (fd, " 206"); 2'b11 : $fwrite (fd, " 207"); endcase - 4'h8 : + 4'h8 : case (foo[26:25]) 2'b00 : $fwrite (fd, " 208"); 2'b01 : $fwrite (fd, " 209"); 2'b10 : $fwrite (fd, " 210"); 2'b11 : $fwrite (fd, " 211"); endcase - 4'h9 : + 4'h9 : case (foo[26:25]) 2'b00 : $fwrite (fd, " 212"); 2'b01 : $fwrite (fd, " 213"); 2'b10 : $fwrite (fd, " 214"); 2'b11 : $fwrite (fd, " 215"); endcase - 4'ha : + 4'ha : if (foo[25]) $fwrite (fd, " 216"); else $fwrite (fd, " 217"); - 4'hb : + 4'hb : if (foo[25]) $fwrite (fd, " 218"); else $fwrite (fd, " 219"); - 4'hc : + 4'hc : if (foo[26]) $fwrite (fd, " 220"); else $fwrite (fd, " 221"); - 4'hd : + 4'hd : case (foo[26:25]) 2'b00 : $fwrite (fd, " 222"); 2'b01 : $fwrite (fd, " 223"); 2'b10 : $fwrite (fd, " 224"); 2'b11 : $fwrite (fd, " 225"); endcase - 4'he : + 4'he : case (foo[26:25]) 2'b00 : $fwrite (fd, " 226"); 2'b01 : $fwrite (fd, " 227"); 2'b10 : $fwrite (fd, " 228"); 2'b11 : $fwrite (fd, " 229"); endcase - 4'hf : + 4'hf : case (foo[26:25]) 2'b00 : $fwrite (fd, " 230"); 2'b01 : $fwrite (fd, " 231"); 2'b10 : $fwrite (fd, " 232"); 2'b11 : $fwrite (fd, " 233"); endcase - endcase + endcase end endtask @@ -430,1131 +430,1131 @@ module t_case_write2_tasks (); input [`FD_BITS] fd; // verilator no_inline_task begin - case (foo[27:21]) - 7'h00: - begin - ozoneae(foo[20:18], fd); - $fwrite (fd," 234"); - $fwrite (fd, " 235"); - end - 7'h01: - begin - ozoneae(foo[20:18], fd); - $fwrite (fd," 236"); - ozoneae(foo[17:15], fd); - $fwrite (fd," 237"); - $fwrite (fd, " 238"); - end - 7'h02: - $fwrite (fd, " 239"); - 7'h03: - begin - ozoneae(foo[20:18], fd); - $fwrite (fd," 240"); - ozoneae(foo[17:15], fd); - $fwrite (fd," 241"); - $fwrite (fd, " 242"); - end - 7'h04: - begin - ozoneae(foo[20:18], fd); - $fwrite (fd," 243"); - $fwrite (fd," 244"); - end - 7'h05: - begin - ozoneae(foo[20:18], fd); - $fwrite (fd," 245"); - ozoneae(foo[17:15], fd); - $fwrite (fd," 246"); - end - 7'h06: - $fwrite (fd, " 247"); - 7'h07: - begin - ozoneae(foo[20:18], fd); - $fwrite (fd," 248"); - ozoneae(foo[17:15], fd); - $fwrite (fd," 249"); - end - 7'h08: - begin - ozoneae(foo[20:18], fd); - $fwrite (fd," 250"); - ozoneae(foo[17:15], fd); - $fwrite (fd," 251"); - end - 7'h09: - begin - ozoneae(foo[20:18], fd); - $fwrite (fd," 252"); - ozoneae(foo[17:15], fd); - $fwrite (fd," 253"); - end - 7'h0a: - begin - ozoneae(foo[17:15], fd); - $fwrite (fd," 254"); - end - 7'h0b: - begin - ozoneae(foo[17:15], fd); - $fwrite (fd," 255"); - end - 7'h0c: - begin - ozoneae(foo[20:18], fd); - $fwrite (fd," 256"); - end - 7'h0d: - begin - ozoneae(foo[20:18], fd); - $fwrite (fd," 257"); - ozoneae(foo[17:15], fd); - $fwrite (fd," 258"); - end - 7'h0e: - begin - ozoneae(foo[20:18], fd); - $fwrite (fd," 259"); - ozoneae(foo[17:15], fd); - $fwrite (fd," 260"); - end - 7'h0f: - begin - ozoneae(foo[20:18], fd); - $fwrite (fd," 261"); - ozoneae(foo[17:15], fd); - $fwrite (fd," 262"); - end - 7'h10: - begin - ozoneae(foo[20:18], fd); - $fwrite (fd," 263"); - ozoneae(foo[17:15], fd); - $fwrite (fd," 264"); - $fwrite (fd, " 265"); - $fwrite (fd, " 266"); - end - 7'h11: - begin - ozoneae(foo[20:18], fd); - $fwrite (fd," 267"); - ozoneae(foo[17:15], fd); - $fwrite (fd," 268"); - $fwrite (fd, " 269"); - $fwrite (fd, " 270"); - end - 7'h12: - begin - ozoneae(foo[20:18], fd); - $fwrite (fd," 271"); - ozoneae(foo[17:15], fd); - $fwrite (fd," 272"); - $fwrite (fd, " 273"); - $fwrite (fd, " 274"); - end - 7'h13: - begin - ozoneae(foo[20:18], fd); - $fwrite (fd," 275"); - ozoneae(foo[17:15], fd); - $fwrite (fd," 276"); - $fwrite (fd, " 277"); - $fwrite (fd, " 278"); - end - 7'h14: - begin - ozoneaee(foo[20:18], fd); - $fwrite (fd," 279"); - ozoneaee(foo[17:15], fd); - $fwrite (fd," 280"); - ozoneape(foo[20:18], fd); - $fwrite (fd," 281"); - ozoneape(foo[17:15], fd); - $fwrite (fd," 282"); - $fwrite (fd, " 283"); - $fwrite (fd, " 284"); - end - 7'h15: - begin - ozoneaee(foo[20:18], fd); - $fwrite (fd," 285"); - ozoneaee(foo[17:15], fd); - $fwrite (fd," 286"); - ozoneape(foo[20:18], fd); - $fwrite (fd," 287"); - ozoneape(foo[17:15], fd); - $fwrite (fd," 288"); - $fwrite (fd, " 289"); - $fwrite (fd, " 290"); - end - 7'h16: - begin - ozoneaee(foo[20:18], fd); - $fwrite (fd," 291"); - ozoneaee(foo[17:15], fd); - $fwrite (fd," 292"); - ozoneape(foo[20:18], fd); - $fwrite (fd," 293"); - ozoneape(foo[17:15], fd); - $fwrite (fd," 294"); - $fwrite (fd, " 295"); - $fwrite (fd, " 296"); - end - 7'h17: - begin - ozoneaee(foo[20:18], fd); - $fwrite (fd," 297"); - ozoneaee(foo[17:15], fd); - $fwrite (fd," 298"); - ozoneape(foo[20:18], fd); - $fwrite (fd," 299"); - ozoneape(foo[17:15], fd); - $fwrite (fd," 300"); - $fwrite (fd, " 301"); - $fwrite (fd, " 302"); - end - 7'h18: - begin - ozoneae(foo[20:18], fd); - $fwrite (fd," 303"); - ozoneae(foo[17:15], fd); - $fwrite (fd," 304"); - $fwrite (fd, " 305"); - $fwrite (fd, " 306"); - end - 7'h19: - begin - ozoneae(foo[20:18], fd); - $fwrite (fd," 307"); - ozoneae(foo[17:15], fd); - $fwrite (fd," 308"); - $fwrite (fd, " 309"); - $fwrite (fd, " 310"); - end - 7'h1a: - begin - ozoneae(foo[20:18], fd); - $fwrite (fd," 311"); - ozoneae(foo[17:15], fd); - $fwrite (fd," 312"); - $fwrite (fd, " 313"); - $fwrite (fd, " 314"); - end - 7'h1b: - begin - ozoneae(foo[20:18], fd); - $fwrite (fd," 315"); - ozoneae(foo[17:15], fd); - $fwrite (fd," 316"); - $fwrite (fd, " 317"); - $fwrite (fd, " 318"); - end - 7'h1c: - begin - ozoneae(foo[20:18], fd); - $fwrite (fd," 319"); - ozoneae(foo[17:15], fd); - $fwrite (fd," 320"); - $fwrite (fd, " 321"); - $fwrite (fd, " 322"); - end - 7'h1d: - begin - ozoneae(foo[20:18], fd); - $fwrite (fd," 323"); - ozoneae(foo[17:15], fd); - $fwrite (fd," 324"); - $fwrite (fd, " 325"); - $fwrite (fd, " 326"); - end - 7'h1e: - begin - ozoneaee(foo[20:18], fd); - $fwrite (fd," 327"); - ozoneaee(foo[17:15], fd); - $fwrite (fd," 328"); - ozoneape(foo[20:18], fd); - $fwrite (fd," 329"); - ozoneape(foo[17:15], fd); - $fwrite (fd," 330"); - $fwrite (fd, " 331"); - $fwrite (fd, " 332"); - end - 7'h1f: - begin - ozoneaee(foo[20:18], fd); - $fwrite (fd," 333"); - ozoneaee(foo[17:15], fd); - $fwrite (fd," 334"); - ozoneape(foo[20:18], fd); - $fwrite (fd," 335"); - ozoneape(foo[17:15], fd); - $fwrite (fd," 336"); - $fwrite (fd, " 337"); - $fwrite (fd, " 338"); - end - 7'h20: - begin - ozoneaee(foo[20:18], fd); - $fwrite (fd," 339"); - ozoneaee(foo[17:15], fd); - $fwrite (fd," 340"); - ozoneape(foo[20:18], fd); - $fwrite (fd," 341"); - ozoneape(foo[17:15], fd); - $fwrite (fd," 342"); - $fwrite (fd, " 343"); - $fwrite (fd, " 344"); - end - 7'h21: - begin - ozoneaee(foo[20:18], fd); - $fwrite (fd," 345"); - ozoneaee(foo[17:15], fd); - $fwrite (fd," 346"); - ozoneape(foo[20:18], fd); - $fwrite (fd," 347"); - ozoneape(foo[17:15], fd); - $fwrite (fd," 348"); - $fwrite (fd, " 349"); - $fwrite (fd, " 350"); - end - 7'h22: - begin - ozoneae(foo[20:18], fd); - $fwrite (fd," 351"); - ozoneae(foo[17:15], fd); - $fwrite (fd," 352"); - $fwrite (fd, " 353"); - $fwrite (fd, " 354"); - end - 7'h23: - begin - ozoneae(foo[20:18], fd); - $fwrite (fd," 355"); - ozoneae(foo[17:15], fd); - $fwrite (fd," 356"); - $fwrite (fd, " 357"); - $fwrite (fd, " 358"); - end - 7'h24: - begin - ozoneae(foo[20:18], fd); - $fwrite (fd," 359"); - ozoneae(foo[17:15], fd); - $fwrite (fd," 360"); - $fwrite (fd, " 361"); - $fwrite (fd, " 362"); - end - 7'h25: - begin - ozoneae(foo[20:18], fd); - $fwrite (fd," 363"); - ozoneae(foo[17:15], fd); - $fwrite (fd," 364"); - $fwrite (fd, " 365"); - $fwrite (fd, " 366"); - end - 7'h26: - begin - ozoneae(foo[20:18], fd); - $fwrite (fd," 367"); - ozoneae(foo[17:15], fd); - $fwrite (fd," 368"); - $fwrite (fd, " 369"); - $fwrite (fd, " 370"); - end - 7'h27: - begin - ozoneae(foo[20:18], fd); - $fwrite (fd," 371"); - ozoneae(foo[17:15], fd); - $fwrite (fd," 372"); - $fwrite (fd, " 373"); - $fwrite (fd, " 374"); - end - 7'h28: - begin - ozoneaee(foo[20:18], fd); - $fwrite (fd," 375"); - ozoneaee(foo[17:15], fd); - $fwrite (fd," 376"); - ozoneape(foo[20:18], fd); - $fwrite (fd," 377"); - ozoneape(foo[17:15], fd); - $fwrite (fd," 378"); - $fwrite (fd, " 379"); - $fwrite (fd, " 380"); - end - 7'h29: - begin - ozoneaee(foo[20:18], fd); - $fwrite (fd," 381"); - ozoneaee(foo[17:15], fd); - $fwrite (fd," 382"); - ozoneape(foo[20:18], fd); - $fwrite (fd," 383"); - ozoneape(foo[17:15], fd); - $fwrite (fd," 384"); - $fwrite (fd, " 385"); - $fwrite (fd, " 386"); - end - 7'h2a: - begin - ozoneaee(foo[20:18], fd); - $fwrite (fd," 387"); - ozoneaee(foo[17:15], fd); - $fwrite (fd," 388"); - ozoneape(foo[20:18], fd); - $fwrite (fd," 389"); - ozoneape(foo[17:15], fd); - $fwrite (fd," 390"); - $fwrite (fd, " 391"); - $fwrite (fd, " 392"); - end - 7'h2b: - begin - ozoneaee(foo[20:18], fd); - $fwrite (fd," 393"); - ozoneaee(foo[17:15], fd); - $fwrite (fd," 394"); - ozoneape(foo[20:18], fd); - $fwrite (fd," 395"); - ozoneape(foo[17:15], fd); - $fwrite (fd," 396"); - $fwrite (fd, " 397"); - $fwrite (fd, " 398"); - end - 7'h2c: - begin - ozoneae(foo[20:18], fd); - $fwrite (fd," 399"); - ozoneae(foo[17:15], fd); - $fwrite (fd," 400"); - $fwrite (fd, " 401"); - $fwrite (fd, " 402"); - end - 7'h2d: - begin - ozoneae(foo[20:18], fd); - $fwrite (fd," 403"); - ozoneae(foo[17:15], fd); - $fwrite (fd," 404"); - $fwrite (fd, " 405"); - $fwrite (fd, " 406"); - end - 7'h2e: - begin - ozoneae(foo[20:18], fd); - $fwrite (fd," 407"); - ozoneae(foo[17:15], fd); - $fwrite (fd," 408"); - $fwrite (fd, " 409"); - $fwrite (fd, " 410"); - end - 7'h2f: - begin - ozoneae(foo[20:18], fd); - $fwrite (fd," 411"); - ozoneae(foo[17:15], fd); - $fwrite (fd," 412"); - $fwrite (fd, " 413"); - $fwrite (fd, " 414"); - end - 7'h30: - begin - ozoneae(foo[20:18], fd); - $fwrite (fd," 415"); - ozoneae(foo[17:15], fd); - $fwrite (fd," 416"); - $fwrite (fd, " 417"); - $fwrite (fd, " 418"); - end - 7'h31: - begin - ozoneae(foo[20:18], fd); - $fwrite (fd," 419"); - ozoneae(foo[17:15], fd); - $fwrite (fd," 420"); - $fwrite (fd, " 421"); - $fwrite (fd, " 422"); - end - 7'h32: - begin - ozoneaee(foo[20:18], fd); - $fwrite (fd," 423"); - ozoneaee(foo[17:15], fd); - $fwrite (fd," 424"); - ozoneape(foo[20:18], fd); - $fwrite (fd," 425"); - ozoneape(foo[17:15], fd); - $fwrite (fd," 426"); - $fwrite (fd, " 427"); - $fwrite (fd, " 428"); - end - 7'h33: - begin - ozoneaee(foo[20:18], fd); - $fwrite (fd," 429"); - ozoneaee(foo[17:15], fd); - $fwrite (fd," 430"); - ozoneape(foo[20:18], fd); - $fwrite (fd," 431"); - ozoneape(foo[17:15], fd); - $fwrite (fd," 432"); - $fwrite (fd, " 433"); - $fwrite (fd, " 434"); - end - 7'h34: - begin - ozoneaee(foo[20:18], fd); - $fwrite (fd," 435"); - ozoneaee(foo[17:15], fd); - $fwrite (fd," 436"); - ozoneape(foo[20:18], fd); - $fwrite (fd," 437"); - ozoneape(foo[17:15], fd); - $fwrite (fd," 438"); - $fwrite (fd, " 439"); - $fwrite (fd, " 440"); - end - 7'h35: - begin - ozoneaee(foo[20:18], fd); - $fwrite (fd," 441"); - ozoneaee(foo[17:15], fd); - $fwrite (fd," 442"); - ozoneape(foo[20:18], fd); - $fwrite (fd," 443"); - ozoneape(foo[17:15], fd); - $fwrite (fd," 444"); - $fwrite (fd, " 445"); - $fwrite (fd, " 446"); - end - 7'h36: - begin - ozoneae(foo[20:18], fd); - $fwrite (fd," 447"); - ozoneae(foo[17:15], fd); - $fwrite (fd," 448"); - $fwrite (fd, " 449"); - $fwrite (fd, " 450"); - end - 7'h37: - begin - ozoneae(foo[20:18], fd); - $fwrite (fd," 451"); - ozoneae(foo[17:15], fd); - $fwrite (fd," 452"); - $fwrite (fd, " 453"); - $fwrite (fd, " 454"); - end - 7'h38: - begin - ozoneae(foo[20:18], fd); - $fwrite (fd," 455"); - ozoneae(foo[17:15], fd); - $fwrite (fd," 456"); - $fwrite (fd, " 457"); - end - 7'h39: - begin - ozoneae(foo[20:18], fd); - $fwrite (fd," 458"); - ozoneae(foo[17:15], fd); - $fwrite (fd," 459"); - $fwrite (fd, " 460"); - end - 7'h3a: - begin - ozoneae(foo[20:18], fd); - $fwrite (fd," 461"); - ozoneae(foo[17:15], fd); - $fwrite (fd," 462"); - $fwrite (fd, " 463"); - end - 7'h3b: - begin - ozoneae(foo[20:18], fd); - $fwrite (fd," 464"); - ozoneae(foo[17:15], fd); - $fwrite (fd," 465"); - $fwrite (fd, " 466"); - end - 7'h3c: - begin - ozoneaee(foo[20:18], fd); - $fwrite (fd," 467"); - ozoneaee(foo[17:15], fd); - $fwrite (fd," 468"); - ozoneape(foo[20:18], fd); - $fwrite (fd," 469"); - ozoneape(foo[17:15], fd); - $fwrite (fd," 470"); - $fwrite (fd, " 471"); - end - 7'h3d: - begin - ozoneaee(foo[20:18], fd); - $fwrite (fd," 472"); - ozoneaee(foo[17:15], fd); - $fwrite (fd," 473"); - ozoneape(foo[20:18], fd); - $fwrite (fd," 474"); - ozoneape(foo[17:15], fd); - $fwrite (fd," 475"); - $fwrite (fd, " 476"); - end - 7'h3e: - begin - ozoneaee(foo[20:18], fd); - $fwrite (fd," 477"); - ozoneaee(foo[17:15], fd); - $fwrite (fd," 478"); - ozoneape(foo[20:18], fd); - $fwrite (fd," 479"); - ozoneape(foo[17:15], fd); - $fwrite (fd," 480"); - $fwrite (fd, " 481"); - end - 7'h3f: - begin - ozoneaee(foo[20:18], fd); - $fwrite (fd," 482"); - ozoneaee(foo[17:15], fd); - $fwrite (fd," 483"); - ozoneape(foo[20:18], fd); - $fwrite (fd," 484"); - ozoneape(foo[17:15], fd); - $fwrite (fd," 485"); - $fwrite (fd, " 486"); - end - 7'h40: - begin - ozoneae(foo[20:18], fd); - $fwrite (fd," 487"); - ozoneae(foo[17:15], fd); - $fwrite (fd," 488"); - $fwrite (fd, " 489"); - $fwrite (fd, " 490"); - end - 7'h41: - begin - $fwrite (fd, " 491"); - $fwrite (fd, " 492"); - end - 7'h42: - begin - $fwrite (fd, " 493"); - $fwrite (fd, " 494"); - end - 7'h43: - begin - $fwrite (fd, " 495"); - $fwrite (fd, " 496"); - end - 7'h44: - begin - $fwrite (fd, " 497"); - $fwrite (fd, " 498"); - end - 7'h45: - $fwrite (fd, " 499"); - 7'h46: - begin - ozoneae(foo[20:18], fd); - $fwrite (fd," 500"); - $fwrite (fd, " 501"); - $fwrite (fd, " 502"); - end - 7'h47: - begin - ozoneaee(foo[20:18], fd); - $fwrite (fd," 503"); - ozoneae(foo[17:15], fd); - $fwrite (fd," 504"); - ozoneape(foo[20:18], fd); - $fwrite (fd," 505"); - ozoneape(foo[20:18], fd); - $fwrite (fd," 506"); - $fwrite (fd, " 507"); - $fwrite (fd, " 508"); - end - 7'h48: - begin - ozoneaee(foo[20:18], fd); - $fwrite (fd," 509"); - ozoneape(foo[20:18], fd); - $fwrite (fd," 510"); - ozoneape(foo[20:18], fd); - $fwrite (fd," 511"); - ozoneaee(foo[17:15], fd); - $fwrite (fd," 512"); - ozoneape(foo[17:15], fd); - $fwrite (fd," 513"); - end - 7'h49: - begin - ozoneae(foo[20:18], fd); - $fwrite (fd," 514"); - ozoneaee(foo[17:15], fd); - $fwrite (fd," 515"); - ozoneape(foo[17:15], fd); - $fwrite (fd," 516"); - end - 7'h4a: + case (foo[27:21]) + 7'h00: + begin + ozoneae(foo[20:18], fd); + $fwrite (fd," 234"); + $fwrite (fd, " 235"); + end + 7'h01: + begin + ozoneae(foo[20:18], fd); + $fwrite (fd," 236"); + ozoneae(foo[17:15], fd); + $fwrite (fd," 237"); + $fwrite (fd, " 238"); + end + 7'h02: + $fwrite (fd, " 239"); + 7'h03: + begin + ozoneae(foo[20:18], fd); + $fwrite (fd," 240"); + ozoneae(foo[17:15], fd); + $fwrite (fd," 241"); + $fwrite (fd, " 242"); + end + 7'h04: + begin + ozoneae(foo[20:18], fd); + $fwrite (fd," 243"); + $fwrite (fd," 244"); + end + 7'h05: + begin + ozoneae(foo[20:18], fd); + $fwrite (fd," 245"); + ozoneae(foo[17:15], fd); + $fwrite (fd," 246"); + end + 7'h06: + $fwrite (fd, " 247"); + 7'h07: + begin + ozoneae(foo[20:18], fd); + $fwrite (fd," 248"); + ozoneae(foo[17:15], fd); + $fwrite (fd," 249"); + end + 7'h08: + begin + ozoneae(foo[20:18], fd); + $fwrite (fd," 250"); + ozoneae(foo[17:15], fd); + $fwrite (fd," 251"); + end + 7'h09: + begin + ozoneae(foo[20:18], fd); + $fwrite (fd," 252"); + ozoneae(foo[17:15], fd); + $fwrite (fd," 253"); + end + 7'h0a: + begin + ozoneae(foo[17:15], fd); + $fwrite (fd," 254"); + end + 7'h0b: + begin + ozoneae(foo[17:15], fd); + $fwrite (fd," 255"); + end + 7'h0c: + begin + ozoneae(foo[20:18], fd); + $fwrite (fd," 256"); + end + 7'h0d: + begin + ozoneae(foo[20:18], fd); + $fwrite (fd," 257"); + ozoneae(foo[17:15], fd); + $fwrite (fd," 258"); + end + 7'h0e: + begin + ozoneae(foo[20:18], fd); + $fwrite (fd," 259"); + ozoneae(foo[17:15], fd); + $fwrite (fd," 260"); + end + 7'h0f: + begin + ozoneae(foo[20:18], fd); + $fwrite (fd," 261"); + ozoneae(foo[17:15], fd); + $fwrite (fd," 262"); + end + 7'h10: + begin + ozoneae(foo[20:18], fd); + $fwrite (fd," 263"); + ozoneae(foo[17:15], fd); + $fwrite (fd," 264"); + $fwrite (fd, " 265"); + $fwrite (fd, " 266"); + end + 7'h11: + begin + ozoneae(foo[20:18], fd); + $fwrite (fd," 267"); + ozoneae(foo[17:15], fd); + $fwrite (fd," 268"); + $fwrite (fd, " 269"); + $fwrite (fd, " 270"); + end + 7'h12: + begin + ozoneae(foo[20:18], fd); + $fwrite (fd," 271"); + ozoneae(foo[17:15], fd); + $fwrite (fd," 272"); + $fwrite (fd, " 273"); + $fwrite (fd, " 274"); + end + 7'h13: + begin + ozoneae(foo[20:18], fd); + $fwrite (fd," 275"); + ozoneae(foo[17:15], fd); + $fwrite (fd," 276"); + $fwrite (fd, " 277"); + $fwrite (fd, " 278"); + end + 7'h14: + begin + ozoneaee(foo[20:18], fd); + $fwrite (fd," 279"); + ozoneaee(foo[17:15], fd); + $fwrite (fd," 280"); + ozoneape(foo[20:18], fd); + $fwrite (fd," 281"); + ozoneape(foo[17:15], fd); + $fwrite (fd," 282"); + $fwrite (fd, " 283"); + $fwrite (fd, " 284"); + end + 7'h15: + begin + ozoneaee(foo[20:18], fd); + $fwrite (fd," 285"); + ozoneaee(foo[17:15], fd); + $fwrite (fd," 286"); + ozoneape(foo[20:18], fd); + $fwrite (fd," 287"); + ozoneape(foo[17:15], fd); + $fwrite (fd," 288"); + $fwrite (fd, " 289"); + $fwrite (fd, " 290"); + end + 7'h16: + begin + ozoneaee(foo[20:18], fd); + $fwrite (fd," 291"); + ozoneaee(foo[17:15], fd); + $fwrite (fd," 292"); + ozoneape(foo[20:18], fd); + $fwrite (fd," 293"); + ozoneape(foo[17:15], fd); + $fwrite (fd," 294"); + $fwrite (fd, " 295"); + $fwrite (fd, " 296"); + end + 7'h17: + begin + ozoneaee(foo[20:18], fd); + $fwrite (fd," 297"); + ozoneaee(foo[17:15], fd); + $fwrite (fd," 298"); + ozoneape(foo[20:18], fd); + $fwrite (fd," 299"); + ozoneape(foo[17:15], fd); + $fwrite (fd," 300"); + $fwrite (fd, " 301"); + $fwrite (fd, " 302"); + end + 7'h18: + begin + ozoneae(foo[20:18], fd); + $fwrite (fd," 303"); + ozoneae(foo[17:15], fd); + $fwrite (fd," 304"); + $fwrite (fd, " 305"); + $fwrite (fd, " 306"); + end + 7'h19: + begin + ozoneae(foo[20:18], fd); + $fwrite (fd," 307"); + ozoneae(foo[17:15], fd); + $fwrite (fd," 308"); + $fwrite (fd, " 309"); + $fwrite (fd, " 310"); + end + 7'h1a: + begin + ozoneae(foo[20:18], fd); + $fwrite (fd," 311"); + ozoneae(foo[17:15], fd); + $fwrite (fd," 312"); + $fwrite (fd, " 313"); + $fwrite (fd, " 314"); + end + 7'h1b: + begin + ozoneae(foo[20:18], fd); + $fwrite (fd," 315"); + ozoneae(foo[17:15], fd); + $fwrite (fd," 316"); + $fwrite (fd, " 317"); + $fwrite (fd, " 318"); + end + 7'h1c: + begin + ozoneae(foo[20:18], fd); + $fwrite (fd," 319"); + ozoneae(foo[17:15], fd); + $fwrite (fd," 320"); + $fwrite (fd, " 321"); + $fwrite (fd, " 322"); + end + 7'h1d: + begin + ozoneae(foo[20:18], fd); + $fwrite (fd," 323"); + ozoneae(foo[17:15], fd); + $fwrite (fd," 324"); + $fwrite (fd, " 325"); + $fwrite (fd, " 326"); + end + 7'h1e: + begin + ozoneaee(foo[20:18], fd); + $fwrite (fd," 327"); + ozoneaee(foo[17:15], fd); + $fwrite (fd," 328"); + ozoneape(foo[20:18], fd); + $fwrite (fd," 329"); + ozoneape(foo[17:15], fd); + $fwrite (fd," 330"); + $fwrite (fd, " 331"); + $fwrite (fd, " 332"); + end + 7'h1f: + begin + ozoneaee(foo[20:18], fd); + $fwrite (fd," 333"); + ozoneaee(foo[17:15], fd); + $fwrite (fd," 334"); + ozoneape(foo[20:18], fd); + $fwrite (fd," 335"); + ozoneape(foo[17:15], fd); + $fwrite (fd," 336"); + $fwrite (fd, " 337"); + $fwrite (fd, " 338"); + end + 7'h20: + begin + ozoneaee(foo[20:18], fd); + $fwrite (fd," 339"); + ozoneaee(foo[17:15], fd); + $fwrite (fd," 340"); + ozoneape(foo[20:18], fd); + $fwrite (fd," 341"); + ozoneape(foo[17:15], fd); + $fwrite (fd," 342"); + $fwrite (fd, " 343"); + $fwrite (fd, " 344"); + end + 7'h21: + begin + ozoneaee(foo[20:18], fd); + $fwrite (fd," 345"); + ozoneaee(foo[17:15], fd); + $fwrite (fd," 346"); + ozoneape(foo[20:18], fd); + $fwrite (fd," 347"); + ozoneape(foo[17:15], fd); + $fwrite (fd," 348"); + $fwrite (fd, " 349"); + $fwrite (fd, " 350"); + end + 7'h22: + begin + ozoneae(foo[20:18], fd); + $fwrite (fd," 351"); + ozoneae(foo[17:15], fd); + $fwrite (fd," 352"); + $fwrite (fd, " 353"); + $fwrite (fd, " 354"); + end + 7'h23: + begin + ozoneae(foo[20:18], fd); + $fwrite (fd," 355"); + ozoneae(foo[17:15], fd); + $fwrite (fd," 356"); + $fwrite (fd, " 357"); + $fwrite (fd, " 358"); + end + 7'h24: + begin + ozoneae(foo[20:18], fd); + $fwrite (fd," 359"); + ozoneae(foo[17:15], fd); + $fwrite (fd," 360"); + $fwrite (fd, " 361"); + $fwrite (fd, " 362"); + end + 7'h25: + begin + ozoneae(foo[20:18], fd); + $fwrite (fd," 363"); + ozoneae(foo[17:15], fd); + $fwrite (fd," 364"); + $fwrite (fd, " 365"); + $fwrite (fd, " 366"); + end + 7'h26: + begin + ozoneae(foo[20:18], fd); + $fwrite (fd," 367"); + ozoneae(foo[17:15], fd); + $fwrite (fd," 368"); + $fwrite (fd, " 369"); + $fwrite (fd, " 370"); + end + 7'h27: + begin + ozoneae(foo[20:18], fd); + $fwrite (fd," 371"); + ozoneae(foo[17:15], fd); + $fwrite (fd," 372"); + $fwrite (fd, " 373"); + $fwrite (fd, " 374"); + end + 7'h28: + begin + ozoneaee(foo[20:18], fd); + $fwrite (fd," 375"); + ozoneaee(foo[17:15], fd); + $fwrite (fd," 376"); + ozoneape(foo[20:18], fd); + $fwrite (fd," 377"); + ozoneape(foo[17:15], fd); + $fwrite (fd," 378"); + $fwrite (fd, " 379"); + $fwrite (fd, " 380"); + end + 7'h29: + begin + ozoneaee(foo[20:18], fd); + $fwrite (fd," 381"); + ozoneaee(foo[17:15], fd); + $fwrite (fd," 382"); + ozoneape(foo[20:18], fd); + $fwrite (fd," 383"); + ozoneape(foo[17:15], fd); + $fwrite (fd," 384"); + $fwrite (fd, " 385"); + $fwrite (fd, " 386"); + end + 7'h2a: + begin + ozoneaee(foo[20:18], fd); + $fwrite (fd," 387"); + ozoneaee(foo[17:15], fd); + $fwrite (fd," 388"); + ozoneape(foo[20:18], fd); + $fwrite (fd," 389"); + ozoneape(foo[17:15], fd); + $fwrite (fd," 390"); + $fwrite (fd, " 391"); + $fwrite (fd, " 392"); + end + 7'h2b: + begin + ozoneaee(foo[20:18], fd); + $fwrite (fd," 393"); + ozoneaee(foo[17:15], fd); + $fwrite (fd," 394"); + ozoneape(foo[20:18], fd); + $fwrite (fd," 395"); + ozoneape(foo[17:15], fd); + $fwrite (fd," 396"); + $fwrite (fd, " 397"); + $fwrite (fd, " 398"); + end + 7'h2c: + begin + ozoneae(foo[20:18], fd); + $fwrite (fd," 399"); + ozoneae(foo[17:15], fd); + $fwrite (fd," 400"); + $fwrite (fd, " 401"); + $fwrite (fd, " 402"); + end + 7'h2d: + begin + ozoneae(foo[20:18], fd); + $fwrite (fd," 403"); + ozoneae(foo[17:15], fd); + $fwrite (fd," 404"); + $fwrite (fd, " 405"); + $fwrite (fd, " 406"); + end + 7'h2e: + begin + ozoneae(foo[20:18], fd); + $fwrite (fd," 407"); + ozoneae(foo[17:15], fd); + $fwrite (fd," 408"); + $fwrite (fd, " 409"); + $fwrite (fd, " 410"); + end + 7'h2f: + begin + ozoneae(foo[20:18], fd); + $fwrite (fd," 411"); + ozoneae(foo[17:15], fd); + $fwrite (fd," 412"); + $fwrite (fd, " 413"); + $fwrite (fd, " 414"); + end + 7'h30: + begin + ozoneae(foo[20:18], fd); + $fwrite (fd," 415"); + ozoneae(foo[17:15], fd); + $fwrite (fd," 416"); + $fwrite (fd, " 417"); + $fwrite (fd, " 418"); + end + 7'h31: + begin + ozoneae(foo[20:18], fd); + $fwrite (fd," 419"); + ozoneae(foo[17:15], fd); + $fwrite (fd," 420"); + $fwrite (fd, " 421"); + $fwrite (fd, " 422"); + end + 7'h32: + begin + ozoneaee(foo[20:18], fd); + $fwrite (fd," 423"); + ozoneaee(foo[17:15], fd); + $fwrite (fd," 424"); + ozoneape(foo[20:18], fd); + $fwrite (fd," 425"); + ozoneape(foo[17:15], fd); + $fwrite (fd," 426"); + $fwrite (fd, " 427"); + $fwrite (fd, " 428"); + end + 7'h33: + begin + ozoneaee(foo[20:18], fd); + $fwrite (fd," 429"); + ozoneaee(foo[17:15], fd); + $fwrite (fd," 430"); + ozoneape(foo[20:18], fd); + $fwrite (fd," 431"); + ozoneape(foo[17:15], fd); + $fwrite (fd," 432"); + $fwrite (fd, " 433"); + $fwrite (fd, " 434"); + end + 7'h34: + begin + ozoneaee(foo[20:18], fd); + $fwrite (fd," 435"); + ozoneaee(foo[17:15], fd); + $fwrite (fd," 436"); + ozoneape(foo[20:18], fd); + $fwrite (fd," 437"); + ozoneape(foo[17:15], fd); + $fwrite (fd," 438"); + $fwrite (fd, " 439"); + $fwrite (fd, " 440"); + end + 7'h35: + begin + ozoneaee(foo[20:18], fd); + $fwrite (fd," 441"); + ozoneaee(foo[17:15], fd); + $fwrite (fd," 442"); + ozoneape(foo[20:18], fd); + $fwrite (fd," 443"); + ozoneape(foo[17:15], fd); + $fwrite (fd," 444"); + $fwrite (fd, " 445"); + $fwrite (fd, " 446"); + end + 7'h36: + begin + ozoneae(foo[20:18], fd); + $fwrite (fd," 447"); + ozoneae(foo[17:15], fd); + $fwrite (fd," 448"); + $fwrite (fd, " 449"); + $fwrite (fd, " 450"); + end + 7'h37: + begin + ozoneae(foo[20:18], fd); + $fwrite (fd," 451"); + ozoneae(foo[17:15], fd); + $fwrite (fd," 452"); + $fwrite (fd, " 453"); + $fwrite (fd, " 454"); + end + 7'h38: + begin + ozoneae(foo[20:18], fd); + $fwrite (fd," 455"); + ozoneae(foo[17:15], fd); + $fwrite (fd," 456"); + $fwrite (fd, " 457"); + end + 7'h39: + begin + ozoneae(foo[20:18], fd); + $fwrite (fd," 458"); + ozoneae(foo[17:15], fd); + $fwrite (fd," 459"); + $fwrite (fd, " 460"); + end + 7'h3a: + begin + ozoneae(foo[20:18], fd); + $fwrite (fd," 461"); + ozoneae(foo[17:15], fd); + $fwrite (fd," 462"); + $fwrite (fd, " 463"); + end + 7'h3b: + begin + ozoneae(foo[20:18], fd); + $fwrite (fd," 464"); + ozoneae(foo[17:15], fd); + $fwrite (fd," 465"); + $fwrite (fd, " 466"); + end + 7'h3c: + begin + ozoneaee(foo[20:18], fd); + $fwrite (fd," 467"); + ozoneaee(foo[17:15], fd); + $fwrite (fd," 468"); + ozoneape(foo[20:18], fd); + $fwrite (fd," 469"); + ozoneape(foo[17:15], fd); + $fwrite (fd," 470"); + $fwrite (fd, " 471"); + end + 7'h3d: + begin + ozoneaee(foo[20:18], fd); + $fwrite (fd," 472"); + ozoneaee(foo[17:15], fd); + $fwrite (fd," 473"); + ozoneape(foo[20:18], fd); + $fwrite (fd," 474"); + ozoneape(foo[17:15], fd); + $fwrite (fd," 475"); + $fwrite (fd, " 476"); + end + 7'h3e: + begin + ozoneaee(foo[20:18], fd); + $fwrite (fd," 477"); + ozoneaee(foo[17:15], fd); + $fwrite (fd," 478"); + ozoneape(foo[20:18], fd); + $fwrite (fd," 479"); + ozoneape(foo[17:15], fd); + $fwrite (fd," 480"); + $fwrite (fd, " 481"); + end + 7'h3f: + begin + ozoneaee(foo[20:18], fd); + $fwrite (fd," 482"); + ozoneaee(foo[17:15], fd); + $fwrite (fd," 483"); + ozoneape(foo[20:18], fd); + $fwrite (fd," 484"); + ozoneape(foo[17:15], fd); + $fwrite (fd," 485"); + $fwrite (fd, " 486"); + end + 7'h40: + begin + ozoneae(foo[20:18], fd); + $fwrite (fd," 487"); + ozoneae(foo[17:15], fd); + $fwrite (fd," 488"); + $fwrite (fd, " 489"); + $fwrite (fd, " 490"); + end + 7'h41: + begin + $fwrite (fd, " 491"); + $fwrite (fd, " 492"); + end + 7'h42: + begin + $fwrite (fd, " 493"); + $fwrite (fd, " 494"); + end + 7'h43: + begin + $fwrite (fd, " 495"); + $fwrite (fd, " 496"); + end + 7'h44: + begin + $fwrite (fd, " 497"); + $fwrite (fd, " 498"); + end + 7'h45: + $fwrite (fd, " 499"); + 7'h46: + begin + ozoneae(foo[20:18], fd); + $fwrite (fd," 500"); + $fwrite (fd, " 501"); + $fwrite (fd, " 502"); + end + 7'h47: + begin + ozoneaee(foo[20:18], fd); + $fwrite (fd," 503"); + ozoneae(foo[17:15], fd); + $fwrite (fd," 504"); + ozoneape(foo[20:18], fd); + $fwrite (fd," 505"); + ozoneape(foo[20:18], fd); + $fwrite (fd," 506"); + $fwrite (fd, " 507"); + $fwrite (fd, " 508"); + end + 7'h48: + begin + ozoneaee(foo[20:18], fd); + $fwrite (fd," 509"); + ozoneape(foo[20:18], fd); + $fwrite (fd," 510"); + ozoneape(foo[20:18], fd); + $fwrite (fd," 511"); + ozoneaee(foo[17:15], fd); + $fwrite (fd," 512"); + ozoneape(foo[17:15], fd); + $fwrite (fd," 513"); + end + 7'h49: + begin + ozoneae(foo[20:18], fd); + $fwrite (fd," 514"); + ozoneaee(foo[17:15], fd); + $fwrite (fd," 515"); + ozoneape(foo[17:15], fd); + $fwrite (fd," 516"); + end + 7'h4a: $fwrite (fd," 517"); - 7'h4b: + 7'h4b: $fwrite (fd, " 518"); - 7'h4c: - begin - ozoneae(foo[20:18], fd); - $fwrite (fd," 519"); - $fwrite (fd, " 520"); - $fwrite (fd, " 521"); - end - 7'h4d: - begin - ozoneaee(foo[20:18], fd); - $fwrite (fd," 522"); - ozoneae(foo[17:15], fd); - $fwrite (fd," 523"); - ozoneape(foo[20:18], fd); - $fwrite (fd," 524"); - ozoneape(foo[20:18], fd); - $fwrite (fd," 525"); - $fwrite (fd, " 526"); - $fwrite (fd, " 527"); - end - 7'h4e: - begin - ozoneaee(foo[20:18], fd); - $fwrite (fd," 528"); - ozoneae(foo[17:15], fd); - $fwrite (fd," 529"); - ozoneape(foo[20:18], fd); - $fwrite (fd," 530"); - ozoneape(foo[20:18], fd); - $fwrite (fd," 531"); - end - 7'h4f: - begin - ozoneae(foo[20:18], fd); - $fwrite (fd," 532"); - end - 7'h50: - begin - ozoneaee(foo[20:18], fd); - $fwrite (fd," 533"); - ozoneae(foo[17:15], fd); - $fwrite (fd," 534"); - ozoneaee(foo[20:18], fd); - $fwrite (fd," 535"); - ozoneae(foo[17:15], fd); - $fwrite (fd," 536"); - ozoneape(foo[20:18], fd); - $fwrite (fd," 537"); - ozoneae(foo[17:15], fd); - $fwrite (fd," 538"); - ozoneape(foo[20:18], fd); - $fwrite (fd," 539"); - ozoneae(foo[17:15], fd); - $fwrite (fd," 540"); - end - 7'h51: - begin - ozoneaee(foo[20:18], fd); - $fwrite (fd," 541"); - ozoneape(foo[20:18], fd); - $fwrite (fd," 542"); - ozoneaee(foo[20:18], fd); - $fwrite (fd," 543"); - ozoneape(foo[20:18], fd); - $fwrite (fd," 544"); - ozoneae(foo[17:15], fd); - $fwrite (fd," 545"); - end - 7'h52: - $fwrite (fd, " 546"); - 7'h53: - begin - ozoneae(foo[20:18], fd); - $fwrite (fd, " 547"); - end - 7'h54: - begin - ozoneae(foo[20:18], fd); - $fwrite (fd," 548"); - ozoneae(foo[17:15], fd); - $fwrite (fd," 549"); - end - 7'h55: - begin - ozoneae(foo[20:18], fd); - $fwrite (fd," 550"); - ozoneae(foo[17:15], fd); - $fwrite (fd," 551"); - end - 7'h56: - begin - ozoneae(foo[20:18], fd); - $fwrite (fd," 552"); - ozoneae(foo[17:15], fd); - $fwrite (fd," 553"); - $fwrite (fd, " 554"); - end - 7'h57: - begin - ozoneaee(foo[20:18], fd); - $fwrite (fd," 555"); - ozoneae(foo[17:15], fd); - $fwrite (fd," 556"); - ozoneape(foo[20:18], fd); - $fwrite (fd," 557"); - ozoneape(foo[20:18], fd); - $fwrite (fd," 558"); - end - 7'h58: - begin - ozoneae(foo[20:18], fd); - $fwrite (fd, " 559"); - end - 7'h59: - begin - ozoneaee(foo[20:18], fd); - $fwrite (fd," 560"); - ozoneae(foo[17:15], fd); - $fwrite (fd," 561"); - ozoneape(foo[20:18], fd); - $fwrite (fd," 562"); - ozoneape(foo[20:18], fd); - $fwrite (fd," 563"); - end - 7'h5a: - begin - ozoneae(foo[20:18], fd); - $fwrite (fd," 564"); - ozoneae(foo[17:15], fd); - $fwrite (fd, " 565"); - end - 7'h5b: - begin - ozoneae(foo[20:18], fd); - $fwrite (fd," 566"); - ozoneae(foo[17:15], fd); - $fwrite (fd, " 567"); - end - 7'h5c: - begin - $fwrite (fd," 568"); - ozoneape(foo[17:15], fd); - $fwrite (fd," 569"); - $fwrite (fd," 570"); - ozoneape(foo[17:15], fd); - $fwrite (fd," 571"); - ozoneae(foo[20:18], fd); - $fwrite (fd," 572"); - ozoneaee(foo[17:15], fd); - $fwrite (fd, " 573"); - end - 7'h5d: - begin - $fwrite (fd," 574"); - ozoneape(foo[17:15], fd); - $fwrite (fd," 575"); - $fwrite (fd," 576"); - ozoneape(foo[17:15], fd); - $fwrite (fd," 577"); - ozoneae(foo[20:18], fd); - $fwrite (fd," 578"); - ozoneaee(foo[17:15], fd); - $fwrite (fd, " 579"); - end - 7'h5e: - begin - ozoneae(foo[20:18], fd); - $fwrite (fd," 580"); - ozoneae(foo[17:15], fd); - $fwrite (fd, " 581"); - end - 7'h5f: - begin - ozoneaee(foo[20:18], fd); - $fwrite (fd," 582"); - ozoneae(foo[17:15], fd); - $fwrite (fd," 583"); - ozoneaee(foo[20:18], fd); - $fwrite (fd," 584"); - ozoneae(foo[17:15], fd); - $fwrite (fd," 585"); - ozoneape(foo[20:18], fd); - $fwrite (fd," 586"); - ozoneae(foo[17:15], fd); - $fwrite (fd," 587"); - ozoneape(foo[20:18], fd); - $fwrite (fd," 588"); - ozoneae(foo[17:15], fd); - $fwrite (fd," 589"); - end - 7'h60: - begin - ozoneae(foo[20:18], fd); - $fwrite (fd," 590"); - ozoneae(foo[17:15], fd); - $fwrite (fd," 591"); - end - 7'h61: - begin - ozoneae(foo[20:18], fd); - $fwrite (fd," 592"); - ozoneae(foo[17:15], fd); - $fwrite (fd," 593"); - end - 7'h62: - begin - ozoneae(foo[20:18], fd); - $fwrite (fd," 594"); - ozoneae(foo[17:15], fd); - $fwrite (fd," 595"); - end - 7'h63: - begin - ozoneae(foo[20:18], fd); - $fwrite (fd," 596"); - ozoneae(foo[17:15], fd); - $fwrite (fd," 597"); - end - 7'h64: - begin - ozoneaee(foo[20:18], fd); - $fwrite (fd," 598"); - ozoneaee(foo[17:15], fd); - $fwrite (fd," 599"); - ozoneape(foo[20:18], fd); - $fwrite (fd," 600"); - ozoneape(foo[17:15], fd); - $fwrite (fd," 601"); - end - 7'h65: - begin - ozoneaee(foo[20:18], fd); - $fwrite (fd," 602"); - ozoneaee(foo[17:15], fd); - $fwrite (fd," 603"); - ozoneape(foo[20:18], fd); - $fwrite (fd," 604"); - ozoneape(foo[17:15], fd); - $fwrite (fd," 605"); - end - 7'h66: - begin - ozoneaee(foo[20:18], fd); - $fwrite (fd," 606"); - ozoneaee(foo[17:15], fd); - $fwrite (fd," 607"); - ozoneape(foo[20:18], fd); - $fwrite (fd," 608"); - ozoneape(foo[17:15], fd); - $fwrite (fd," 609"); - end - 7'h67: - begin - ozoneaee(foo[20:18], fd); - $fwrite (fd," 610"); - ozoneaee(foo[17:15], fd); - $fwrite (fd," 611"); - ozoneape(foo[20:18], fd); - $fwrite (fd," 612"); - ozoneape(foo[17:15], fd); - $fwrite (fd," 613"); - end - 7'h68: - begin - ozoneaee(foo[20:18], fd); - $fwrite (fd," 614"); - ozoneaee(foo[17:15], fd); - $fwrite (fd," 615"); - ozoneaee(foo[20:18], fd); - $fwrite (fd," 616"); - ozoneape(foo[20:18], fd); - $fwrite (fd," 617"); - ozoneape(foo[20:18], fd); - $fwrite (fd," 618"); - ozoneape(foo[17:15], fd); - end - 7'h69: - begin - ozoneae(foo[20:18], fd); - $fwrite (fd," 619"); - ozoneae(foo[17:15], fd); - $fwrite (fd," 620"); - ozoneae(foo[20:18], fd); - $fwrite (fd," 621"); - end - 7'h6a: - begin - ozoneaee(foo[20:18], fd); - $fwrite (fd," 622"); - ozoneae(foo[17:15], fd); - $fwrite (fd," 623"); - ozoneaee(foo[20:18], fd); - $fwrite (fd," 624"); - ozoneape(foo[20:18], fd); - $fwrite (fd," 625"); - ozoneaee(foo[20:18], fd); - $fwrite (fd," 626"); - ozoneae(foo[17:15], fd); - end - 7'h6b: - begin - ozoneae(foo[20:18], fd); - $fwrite (fd," 627"); - ozoneae(foo[17:15], fd); - $fwrite (fd," 628"); - ozoneae(foo[20:18], fd); - $fwrite (fd," 629"); - end - 7'h6c: - begin - ozoneaee(foo[20:18], fd); - $fwrite (fd," 630"); - ozoneae(foo[17:15], fd); - $fwrite (fd," 631"); - ozoneaee(foo[20:18], fd); - $fwrite (fd," 632"); - ozoneape(foo[20:18], fd); - $fwrite (fd," 633"); - ozoneaee(foo[20:18], fd); - $fwrite (fd," 634"); - ozoneae(foo[17:15], fd); - end - 7'h6d: - begin - ozoneae(foo[20:18], fd); - $fwrite (fd," 635"); - ozoneae(foo[17:15], fd); - $fwrite (fd," 636"); - ozoneae(foo[20:18], fd); - $fwrite (fd," 637"); - end - 7'h6e: - begin - ozoneaee(foo[20:18], fd); - $fwrite (fd," 638"); - ozoneaee(foo[17:15], fd); - $fwrite (fd," 639"); - ozoneape(foo[20:18], fd); - $fwrite (fd," 640"); - ozoneape(foo[17:15], fd); - $fwrite (fd," 641"); - end - 7'h6f: - begin - ozoneaee(foo[20:18], fd); - $fwrite (fd," 642"); - ozoneaee(foo[17:15], fd); - $fwrite (fd," 643"); - ozoneape(foo[20:18], fd); - $fwrite (fd," 644"); - ozoneape(foo[17:15], fd); - $fwrite (fd," 645"); - end - 7'h70: - begin - ozoneae(foo[20:18], fd); - $fwrite (fd," 646"); - ozoneae(foo[20:18], fd); - $fwrite (fd," 647"); - ozoneae(foo[17:15], fd); - $fwrite (fd," 648"); - ozoneae(foo[17:15], fd); - $fwrite (fd, " 649"); - end - 7'h71: - begin - ozoneae(foo[20:18], fd); - $fwrite (fd," 650"); - ozoneae(foo[17:15], fd); - $fwrite (fd, " 651"); - end - 7'h72: - begin - ozoneae(foo[20:18], fd); - $fwrite (fd," 652"); - ozoneae(foo[17:15], fd); - $fwrite (fd, " 653"); - end - 7'h73: - begin - ozoneae(foo[20:18], fd); - $fwrite (fd," 654"); - ozoneae(foo[20:18], fd); - $fwrite (fd," 655"); - ozoneae(foo[17:15], fd); - end - 7'h74: - begin - ozoneae(foo[20:18], fd); - $fwrite (fd," 656"); - ozoneae(foo[20:18], fd); - $fwrite (fd," 657"); - ozoneae(foo[17:15], fd); - end - 7'h75: - begin - ozoneaee(foo[20:18], fd); - $fwrite (fd," 658"); - ozoneaee(foo[17:15], fd); - $fwrite (fd," 659"); - ozoneape(foo[20:18], fd); - $fwrite (fd," 660"); - ozoneape(foo[17:15], fd); - $fwrite (fd," 661"); - $fwrite (fd, " 662"); - $fwrite (fd, " 663"); - end - 7'h76: - begin - ozoneaee(foo[20:18], fd); - $fwrite (fd," 664"); - ozoneaee(foo[17:15], fd); - $fwrite (fd," 665"); - ozoneaee(foo[20:18], fd); - $fwrite (fd," 666"); - ozoneape(foo[20:18], fd); - $fwrite (fd," 667"); - ozoneape(foo[17:15], fd); - $fwrite (fd," 668"); - ozoneape(foo[20:18], fd); - $fwrite (fd," 669"); - end - 7'h77: - begin - ozoneaee(foo[20:18], fd); - $fwrite (fd," 670"); - ozoneaee(foo[17:15], fd); - $fwrite (fd," 671"); - ozoneaee(foo[17:15], fd); - $fwrite (fd," 672"); - ozoneape(foo[20:18], fd); - $fwrite (fd," 673"); - ozoneape(foo[17:15], fd); - $fwrite (fd," 674"); - ozoneape(foo[17:15], fd); - $fwrite (fd," 675"); - end - 7'h78, - 7'h79, - 7'h7a, - 7'h7b, - 7'h7c, - 7'h7d, - 7'h7e, - 7'h7f: + 7'h4c: + begin + ozoneae(foo[20:18], fd); + $fwrite (fd," 519"); + $fwrite (fd, " 520"); + $fwrite (fd, " 521"); + end + 7'h4d: + begin + ozoneaee(foo[20:18], fd); + $fwrite (fd," 522"); + ozoneae(foo[17:15], fd); + $fwrite (fd," 523"); + ozoneape(foo[20:18], fd); + $fwrite (fd," 524"); + ozoneape(foo[20:18], fd); + $fwrite (fd," 525"); + $fwrite (fd, " 526"); + $fwrite (fd, " 527"); + end + 7'h4e: + begin + ozoneaee(foo[20:18], fd); + $fwrite (fd," 528"); + ozoneae(foo[17:15], fd); + $fwrite (fd," 529"); + ozoneape(foo[20:18], fd); + $fwrite (fd," 530"); + ozoneape(foo[20:18], fd); + $fwrite (fd," 531"); + end + 7'h4f: + begin + ozoneae(foo[20:18], fd); + $fwrite (fd," 532"); + end + 7'h50: + begin + ozoneaee(foo[20:18], fd); + $fwrite (fd," 533"); + ozoneae(foo[17:15], fd); + $fwrite (fd," 534"); + ozoneaee(foo[20:18], fd); + $fwrite (fd," 535"); + ozoneae(foo[17:15], fd); + $fwrite (fd," 536"); + ozoneape(foo[20:18], fd); + $fwrite (fd," 537"); + ozoneae(foo[17:15], fd); + $fwrite (fd," 538"); + ozoneape(foo[20:18], fd); + $fwrite (fd," 539"); + ozoneae(foo[17:15], fd); + $fwrite (fd," 540"); + end + 7'h51: + begin + ozoneaee(foo[20:18], fd); + $fwrite (fd," 541"); + ozoneape(foo[20:18], fd); + $fwrite (fd," 542"); + ozoneaee(foo[20:18], fd); + $fwrite (fd," 543"); + ozoneape(foo[20:18], fd); + $fwrite (fd," 544"); + ozoneae(foo[17:15], fd); + $fwrite (fd," 545"); + end + 7'h52: + $fwrite (fd, " 546"); + 7'h53: + begin + ozoneae(foo[20:18], fd); + $fwrite (fd, " 547"); + end + 7'h54: + begin + ozoneae(foo[20:18], fd); + $fwrite (fd," 548"); + ozoneae(foo[17:15], fd); + $fwrite (fd," 549"); + end + 7'h55: + begin + ozoneae(foo[20:18], fd); + $fwrite (fd," 550"); + ozoneae(foo[17:15], fd); + $fwrite (fd," 551"); + end + 7'h56: + begin + ozoneae(foo[20:18], fd); + $fwrite (fd," 552"); + ozoneae(foo[17:15], fd); + $fwrite (fd," 553"); + $fwrite (fd, " 554"); + end + 7'h57: + begin + ozoneaee(foo[20:18], fd); + $fwrite (fd," 555"); + ozoneae(foo[17:15], fd); + $fwrite (fd," 556"); + ozoneape(foo[20:18], fd); + $fwrite (fd," 557"); + ozoneape(foo[20:18], fd); + $fwrite (fd," 558"); + end + 7'h58: + begin + ozoneae(foo[20:18], fd); + $fwrite (fd, " 559"); + end + 7'h59: + begin + ozoneaee(foo[20:18], fd); + $fwrite (fd," 560"); + ozoneae(foo[17:15], fd); + $fwrite (fd," 561"); + ozoneape(foo[20:18], fd); + $fwrite (fd," 562"); + ozoneape(foo[20:18], fd); + $fwrite (fd," 563"); + end + 7'h5a: + begin + ozoneae(foo[20:18], fd); + $fwrite (fd," 564"); + ozoneae(foo[17:15], fd); + $fwrite (fd, " 565"); + end + 7'h5b: + begin + ozoneae(foo[20:18], fd); + $fwrite (fd," 566"); + ozoneae(foo[17:15], fd); + $fwrite (fd, " 567"); + end + 7'h5c: + begin + $fwrite (fd," 568"); + ozoneape(foo[17:15], fd); + $fwrite (fd," 569"); + $fwrite (fd," 570"); + ozoneape(foo[17:15], fd); + $fwrite (fd," 571"); + ozoneae(foo[20:18], fd); + $fwrite (fd," 572"); + ozoneaee(foo[17:15], fd); + $fwrite (fd, " 573"); + end + 7'h5d: + begin + $fwrite (fd," 574"); + ozoneape(foo[17:15], fd); + $fwrite (fd," 575"); + $fwrite (fd," 576"); + ozoneape(foo[17:15], fd); + $fwrite (fd," 577"); + ozoneae(foo[20:18], fd); + $fwrite (fd," 578"); + ozoneaee(foo[17:15], fd); + $fwrite (fd, " 579"); + end + 7'h5e: + begin + ozoneae(foo[20:18], fd); + $fwrite (fd," 580"); + ozoneae(foo[17:15], fd); + $fwrite (fd, " 581"); + end + 7'h5f: + begin + ozoneaee(foo[20:18], fd); + $fwrite (fd," 582"); + ozoneae(foo[17:15], fd); + $fwrite (fd," 583"); + ozoneaee(foo[20:18], fd); + $fwrite (fd," 584"); + ozoneae(foo[17:15], fd); + $fwrite (fd," 585"); + ozoneape(foo[20:18], fd); + $fwrite (fd," 586"); + ozoneae(foo[17:15], fd); + $fwrite (fd," 587"); + ozoneape(foo[20:18], fd); + $fwrite (fd," 588"); + ozoneae(foo[17:15], fd); + $fwrite (fd," 589"); + end + 7'h60: + begin + ozoneae(foo[20:18], fd); + $fwrite (fd," 590"); + ozoneae(foo[17:15], fd); + $fwrite (fd," 591"); + end + 7'h61: + begin + ozoneae(foo[20:18], fd); + $fwrite (fd," 592"); + ozoneae(foo[17:15], fd); + $fwrite (fd," 593"); + end + 7'h62: + begin + ozoneae(foo[20:18], fd); + $fwrite (fd," 594"); + ozoneae(foo[17:15], fd); + $fwrite (fd," 595"); + end + 7'h63: + begin + ozoneae(foo[20:18], fd); + $fwrite (fd," 596"); + ozoneae(foo[17:15], fd); + $fwrite (fd," 597"); + end + 7'h64: + begin + ozoneaee(foo[20:18], fd); + $fwrite (fd," 598"); + ozoneaee(foo[17:15], fd); + $fwrite (fd," 599"); + ozoneape(foo[20:18], fd); + $fwrite (fd," 600"); + ozoneape(foo[17:15], fd); + $fwrite (fd," 601"); + end + 7'h65: + begin + ozoneaee(foo[20:18], fd); + $fwrite (fd," 602"); + ozoneaee(foo[17:15], fd); + $fwrite (fd," 603"); + ozoneape(foo[20:18], fd); + $fwrite (fd," 604"); + ozoneape(foo[17:15], fd); + $fwrite (fd," 605"); + end + 7'h66: + begin + ozoneaee(foo[20:18], fd); + $fwrite (fd," 606"); + ozoneaee(foo[17:15], fd); + $fwrite (fd," 607"); + ozoneape(foo[20:18], fd); + $fwrite (fd," 608"); + ozoneape(foo[17:15], fd); + $fwrite (fd," 609"); + end + 7'h67: + begin + ozoneaee(foo[20:18], fd); + $fwrite (fd," 610"); + ozoneaee(foo[17:15], fd); + $fwrite (fd," 611"); + ozoneape(foo[20:18], fd); + $fwrite (fd," 612"); + ozoneape(foo[17:15], fd); + $fwrite (fd," 613"); + end + 7'h68: + begin + ozoneaee(foo[20:18], fd); + $fwrite (fd," 614"); + ozoneaee(foo[17:15], fd); + $fwrite (fd," 615"); + ozoneaee(foo[20:18], fd); + $fwrite (fd," 616"); + ozoneape(foo[20:18], fd); + $fwrite (fd," 617"); + ozoneape(foo[20:18], fd); + $fwrite (fd," 618"); + ozoneape(foo[17:15], fd); + end + 7'h69: + begin + ozoneae(foo[20:18], fd); + $fwrite (fd," 619"); + ozoneae(foo[17:15], fd); + $fwrite (fd," 620"); + ozoneae(foo[20:18], fd); + $fwrite (fd," 621"); + end + 7'h6a: + begin + ozoneaee(foo[20:18], fd); + $fwrite (fd," 622"); + ozoneae(foo[17:15], fd); + $fwrite (fd," 623"); + ozoneaee(foo[20:18], fd); + $fwrite (fd," 624"); + ozoneape(foo[20:18], fd); + $fwrite (fd," 625"); + ozoneaee(foo[20:18], fd); + $fwrite (fd," 626"); + ozoneae(foo[17:15], fd); + end + 7'h6b: + begin + ozoneae(foo[20:18], fd); + $fwrite (fd," 627"); + ozoneae(foo[17:15], fd); + $fwrite (fd," 628"); + ozoneae(foo[20:18], fd); + $fwrite (fd," 629"); + end + 7'h6c: + begin + ozoneaee(foo[20:18], fd); + $fwrite (fd," 630"); + ozoneae(foo[17:15], fd); + $fwrite (fd," 631"); + ozoneaee(foo[20:18], fd); + $fwrite (fd," 632"); + ozoneape(foo[20:18], fd); + $fwrite (fd," 633"); + ozoneaee(foo[20:18], fd); + $fwrite (fd," 634"); + ozoneae(foo[17:15], fd); + end + 7'h6d: + begin + ozoneae(foo[20:18], fd); + $fwrite (fd," 635"); + ozoneae(foo[17:15], fd); + $fwrite (fd," 636"); + ozoneae(foo[20:18], fd); + $fwrite (fd," 637"); + end + 7'h6e: + begin + ozoneaee(foo[20:18], fd); + $fwrite (fd," 638"); + ozoneaee(foo[17:15], fd); + $fwrite (fd," 639"); + ozoneape(foo[20:18], fd); + $fwrite (fd," 640"); + ozoneape(foo[17:15], fd); + $fwrite (fd," 641"); + end + 7'h6f: + begin + ozoneaee(foo[20:18], fd); + $fwrite (fd," 642"); + ozoneaee(foo[17:15], fd); + $fwrite (fd," 643"); + ozoneape(foo[20:18], fd); + $fwrite (fd," 644"); + ozoneape(foo[17:15], fd); + $fwrite (fd," 645"); + end + 7'h70: + begin + ozoneae(foo[20:18], fd); + $fwrite (fd," 646"); + ozoneae(foo[20:18], fd); + $fwrite (fd," 647"); + ozoneae(foo[17:15], fd); + $fwrite (fd," 648"); + ozoneae(foo[17:15], fd); + $fwrite (fd, " 649"); + end + 7'h71: + begin + ozoneae(foo[20:18], fd); + $fwrite (fd," 650"); + ozoneae(foo[17:15], fd); + $fwrite (fd, " 651"); + end + 7'h72: + begin + ozoneae(foo[20:18], fd); + $fwrite (fd," 652"); + ozoneae(foo[17:15], fd); + $fwrite (fd, " 653"); + end + 7'h73: + begin + ozoneae(foo[20:18], fd); + $fwrite (fd," 654"); + ozoneae(foo[20:18], fd); + $fwrite (fd," 655"); + ozoneae(foo[17:15], fd); + end + 7'h74: + begin + ozoneae(foo[20:18], fd); + $fwrite (fd," 656"); + ozoneae(foo[20:18], fd); + $fwrite (fd," 657"); + ozoneae(foo[17:15], fd); + end + 7'h75: + begin + ozoneaee(foo[20:18], fd); + $fwrite (fd," 658"); + ozoneaee(foo[17:15], fd); + $fwrite (fd," 659"); + ozoneape(foo[20:18], fd); + $fwrite (fd," 660"); + ozoneape(foo[17:15], fd); + $fwrite (fd," 661"); + $fwrite (fd, " 662"); + $fwrite (fd, " 663"); + end + 7'h76: + begin + ozoneaee(foo[20:18], fd); + $fwrite (fd," 664"); + ozoneaee(foo[17:15], fd); + $fwrite (fd," 665"); + ozoneaee(foo[20:18], fd); + $fwrite (fd," 666"); + ozoneape(foo[20:18], fd); + $fwrite (fd," 667"); + ozoneape(foo[17:15], fd); + $fwrite (fd," 668"); + ozoneape(foo[20:18], fd); + $fwrite (fd," 669"); + end + 7'h77: + begin + ozoneaee(foo[20:18], fd); + $fwrite (fd," 670"); + ozoneaee(foo[17:15], fd); + $fwrite (fd," 671"); + ozoneaee(foo[17:15], fd); + $fwrite (fd," 672"); + ozoneape(foo[20:18], fd); + $fwrite (fd," 673"); + ozoneape(foo[17:15], fd); + $fwrite (fd," 674"); + ozoneape(foo[17:15], fd); + $fwrite (fd," 675"); + end + 7'h78, + 7'h79, + 7'h7a, + 7'h7b, + 7'h7c, + 7'h7d, + 7'h7e, + 7'h7f: $fwrite (fd," 676"); - endcase + endcase end endtask @@ -1563,116 +1563,116 @@ module t_case_write2_tasks (); input [`FD_BITS] fd; // verilator no_inline_task begin - case (foo[24:21]) - 4'h0 : + case (foo[24:21]) + 4'h0 : case (foo[26:25]) 2'b00 : $fwrite (fd," 677"); 2'b01 : $fwrite (fd," 678"); 2'b10 : $fwrite (fd," 679"); 2'b11 : $fwrite (fd," 680"); endcase - 4'h1 : + 4'h1 : case (foo[26:25]) 2'b00 : $fwrite (fd," 681"); 2'b01 : $fwrite (fd," 682"); 2'b10 : $fwrite (fd," 683"); 2'b11 : $fwrite (fd," 684"); endcase - 4'h2 : + 4'h2 : case (foo[26:25]) 2'b00 : $fwrite (fd," 685"); 2'b01 : $fwrite (fd," 686"); 2'b10 : $fwrite (fd," 687"); 2'b11 : $fwrite (fd," 688"); endcase - 4'h3 : + 4'h3 : case (foo[26:25]) 2'b00 : $fwrite (fd," 689"); 2'b01 : $fwrite (fd," 690"); 2'b10 : $fwrite (fd," 691"); 2'b11 : $fwrite (fd," 692"); endcase - 4'h4 : + 4'h4 : case (foo[26:25]) 2'b00 : $fwrite (fd," 693"); 2'b01 : $fwrite (fd," 694"); 2'b10 : $fwrite (fd," 695"); 2'b11 : $fwrite (fd," 696"); endcase - 4'h5 : + 4'h5 : case (foo[26:25]) 2'b00 : $fwrite (fd," 697"); 2'b01 : $fwrite (fd," 698"); 2'b10 : $fwrite (fd," 699"); 2'b11 : $fwrite (fd," 700"); endcase - 4'h6 : + 4'h6 : case (foo[26:25]) 2'b00 : $fwrite (fd," 701"); 2'b01 : $fwrite (fd," 702"); 2'b10 : $fwrite (fd," 703"); 2'b11 : $fwrite (fd," 704"); endcase - 4'h7 : + 4'h7 : case (foo[26:25]) 2'b00 : $fwrite (fd," 705"); 2'b01 : $fwrite (fd," 706"); 2'b10 : $fwrite (fd," 707"); 2'b11 : $fwrite (fd," 708"); endcase - 4'h8 : + 4'h8 : if (foo[26]) $fwrite (fd," 709"); else $fwrite (fd," 710"); - 4'h9 : + 4'h9 : case (foo[26:25]) 2'b00 : $fwrite (fd," 711"); 2'b01 : $fwrite (fd," 712"); 2'b10 : $fwrite (fd," 713"); 2'b11 : $fwrite (fd," 714"); endcase - 4'ha : + 4'ha : case (foo[26:25]) 2'b00 : $fwrite (fd," 715"); 2'b01 : $fwrite (fd," 716"); 2'b10 : $fwrite (fd," 717"); 2'b11 : $fwrite (fd," 718"); endcase - 4'hb : + 4'hb : case (foo[26:25]) 2'b00 : $fwrite (fd," 719"); 2'b01 : $fwrite (fd," 720"); 2'b10 : $fwrite (fd," 721"); 2'b11 : $fwrite (fd," 722"); endcase - 4'hc : + 4'hc : if (foo[26]) $fwrite (fd," 723"); else $fwrite (fd," 724"); - 4'hd : + 4'hd : case (foo[26:25]) 2'b00 : $fwrite (fd," 725"); 2'b01 : $fwrite (fd," 726"); 2'b10 : $fwrite (fd," 727"); 2'b11 : $fwrite (fd," 728"); endcase - 4'he : + 4'he : case (foo[26:25]) 2'b00 : $fwrite (fd," 729"); 2'b01 : $fwrite (fd," 730"); 2'b10 : $fwrite (fd," 731"); 2'b11 : $fwrite (fd," 732"); endcase - 4'hf : + 4'hf : case (foo[26:25]) 2'b00 : $fwrite (fd," 733"); 2'b01 : $fwrite (fd," 734"); 2'b10 : $fwrite (fd," 735"); 2'b11 : $fwrite (fd," 736"); endcase - endcase + endcase end endtask @@ -1681,198 +1681,198 @@ module t_case_write2_tasks (); input [`FD_BITS] fd; // verilator no_inline_task begin - casez (foo[25:21]) - 5'h00 : - begin - ozoneae(foo[20:18], fd); - $fwrite (fd," 737"); - ozoneae(foo[17:15], fd); - $fwrite (fd," 738"); - end - 5'h01 : - begin - ozoneae(foo[20:18], fd); - $fwrite (fd," 739"); - ozoneae(foo[17:15], fd); - $fwrite (fd," 740"); - end - 5'h02 : - begin - ozoneae(foo[20:18], fd); - $fwrite (fd," 741"); - ozoneae(foo[17:15], fd); - $fwrite (fd," 742"); - end - 5'h03 : - begin - ozoneae(foo[20:18], fd); - $fwrite (fd," 743"); - ozoneae(foo[17:15], fd); - $fwrite (fd," 744"); - end - 5'h04 : - begin - ozoneae(foo[20:18], fd); - $fwrite (fd," 745"); - ozoneae(foo[17:15], fd); - $fwrite (fd," 746"); - end - 5'h05 : - begin - ozoneae(foo[20:18], fd); - $fwrite (fd," 747"); - ozoneae(foo[17:15], fd); - $fwrite (fd," 748"); - end - 5'h06 : - begin - ozoneae(foo[20:18], fd); - $fwrite (fd," 749"); - ozoneae(foo[17:15], fd); - $fwrite (fd," 750"); - end - 5'h07 : - begin - ozoneae(foo[20:18], fd); - $fwrite (fd," 751"); - ozoneae(foo[17:15], fd); - $fwrite (fd," 752"); - end - 5'h08 : - begin - ozoneae(foo[20:18], fd); - $fwrite (fd," 753"); - if (foo[ 6]) - $fwrite (fd," 754"); - else - $fwrite (fd," 755"); - end - 5'h09 : - begin - ozoneae(foo[20:18], fd); - $fwrite (fd," 756"); - ozoneae(foo[17:15], fd); - $fwrite (fd," 757"); - end - 5'h0a : - begin - ozoneae(foo[20:18], fd); - $fwrite (fd," 758"); - ozoneae(foo[17:15], fd); - end - 5'h0b : - begin - ozoneae(foo[20:18], fd); - $fwrite (fd," 759"); - ozoneae(foo[17:15], fd); - $fwrite (fd," 760"); - end - 5'h0c : - begin - ozoneae(foo[20:18], fd); - $fwrite (fd," 761"); - end - 5'h0d : - begin - ozoneae(foo[20:18], fd); - $fwrite (fd," 762"); - ozoneae(foo[17:15], fd); - $fwrite (fd," 763"); - end - 5'h0e : - begin - ozoneae(foo[20:18], fd); - $fwrite (fd," 764"); - ozoneae(foo[17:15], fd); - end - 5'h0f : - begin - ozoneae(foo[20:18], fd); - $fwrite (fd," 765"); - ozoneae(foo[17:15], fd); - end - 5'h10 : - begin - ozoneae(foo[20:18], fd); - $fwrite (fd," 766"); - ozoneae(foo[17:15], fd); - $fwrite (fd," 767"); - end - 5'h11 : - begin - ozoneae(foo[20:18], fd); - $fwrite (fd," 768"); - ozoneae(foo[17:15], fd); - $fwrite (fd," 769"); - end - 5'h18 : - begin - ozoneae(foo[20:18], fd); - $fwrite (fd," 770"); - if (foo[ 6]) - $fwrite (fd," 771"); - else - $fwrite (fd," 772"); - end - 5'h1a : - begin - ozoneae(foo[20:18], fd); - $fwrite (fd," 773"); - ozoneae(foo[17:15], fd); - $fwrite (fd," 774"); - end - 5'h1b : - begin - ozoneae(foo[20:18], fd); - $fwrite (fd," 775"); - ozoneae(foo[17:15], fd); - $fwrite (fd," 776"); - if (foo[ 6]) - $fwrite (fd," 777"); - else - $fwrite (fd," 778"); - $fwrite (fd," 779"); - end - 5'h1c : - begin - ozoneae(foo[20:18], fd); - $fwrite (fd," 780"); - end - 5'h1d : - begin - ozoneae(foo[20:18], fd); - $fwrite (fd," 781"); - if (foo[ 6]) - $fwrite (fd," 782"); - else - $fwrite (fd," 783"); - $fwrite (fd," 784"); - end - 5'h1e : - begin - ozoneae(foo[20:18], fd); - $fwrite (fd," 785"); - if (foo[ 6]) - $fwrite (fd," 786"); - else - $fwrite (fd," 787"); - $fwrite (fd," 788"); - end - 5'h1f : - begin - ozoneae(foo[20:18], fd); - $fwrite (fd," 789"); - ozoneae(foo[17:15], fd); - $fwrite (fd," 790"); - if (foo[ 6]) - $fwrite (fd," 791"); - else - $fwrite (fd," 792"); - $fwrite (fd," 793"); - end - default : + casez (foo[25:21]) + 5'h00 : + begin + ozoneae(foo[20:18], fd); + $fwrite (fd," 737"); + ozoneae(foo[17:15], fd); + $fwrite (fd," 738"); + end + 5'h01 : + begin + ozoneae(foo[20:18], fd); + $fwrite (fd," 739"); + ozoneae(foo[17:15], fd); + $fwrite (fd," 740"); + end + 5'h02 : + begin + ozoneae(foo[20:18], fd); + $fwrite (fd," 741"); + ozoneae(foo[17:15], fd); + $fwrite (fd," 742"); + end + 5'h03 : + begin + ozoneae(foo[20:18], fd); + $fwrite (fd," 743"); + ozoneae(foo[17:15], fd); + $fwrite (fd," 744"); + end + 5'h04 : + begin + ozoneae(foo[20:18], fd); + $fwrite (fd," 745"); + ozoneae(foo[17:15], fd); + $fwrite (fd," 746"); + end + 5'h05 : + begin + ozoneae(foo[20:18], fd); + $fwrite (fd," 747"); + ozoneae(foo[17:15], fd); + $fwrite (fd," 748"); + end + 5'h06 : + begin + ozoneae(foo[20:18], fd); + $fwrite (fd," 749"); + ozoneae(foo[17:15], fd); + $fwrite (fd," 750"); + end + 5'h07 : + begin + ozoneae(foo[20:18], fd); + $fwrite (fd," 751"); + ozoneae(foo[17:15], fd); + $fwrite (fd," 752"); + end + 5'h08 : + begin + ozoneae(foo[20:18], fd); + $fwrite (fd," 753"); + if (foo[ 6]) + $fwrite (fd," 754"); + else + $fwrite (fd," 755"); + end + 5'h09 : + begin + ozoneae(foo[20:18], fd); + $fwrite (fd," 756"); + ozoneae(foo[17:15], fd); + $fwrite (fd," 757"); + end + 5'h0a : + begin + ozoneae(foo[20:18], fd); + $fwrite (fd," 758"); + ozoneae(foo[17:15], fd); + end + 5'h0b : + begin + ozoneae(foo[20:18], fd); + $fwrite (fd," 759"); + ozoneae(foo[17:15], fd); + $fwrite (fd," 760"); + end + 5'h0c : + begin + ozoneae(foo[20:18], fd); + $fwrite (fd," 761"); + end + 5'h0d : + begin + ozoneae(foo[20:18], fd); + $fwrite (fd," 762"); + ozoneae(foo[17:15], fd); + $fwrite (fd," 763"); + end + 5'h0e : + begin + ozoneae(foo[20:18], fd); + $fwrite (fd," 764"); + ozoneae(foo[17:15], fd); + end + 5'h0f : + begin + ozoneae(foo[20:18], fd); + $fwrite (fd," 765"); + ozoneae(foo[17:15], fd); + end + 5'h10 : + begin + ozoneae(foo[20:18], fd); + $fwrite (fd," 766"); + ozoneae(foo[17:15], fd); + $fwrite (fd," 767"); + end + 5'h11 : + begin + ozoneae(foo[20:18], fd); + $fwrite (fd," 768"); + ozoneae(foo[17:15], fd); + $fwrite (fd," 769"); + end + 5'h18 : + begin + ozoneae(foo[20:18], fd); + $fwrite (fd," 770"); + if (foo[ 6]) + $fwrite (fd," 771"); + else + $fwrite (fd," 772"); + end + 5'h1a : + begin + ozoneae(foo[20:18], fd); + $fwrite (fd," 773"); + ozoneae(foo[17:15], fd); + $fwrite (fd," 774"); + end + 5'h1b : + begin + ozoneae(foo[20:18], fd); + $fwrite (fd," 775"); + ozoneae(foo[17:15], fd); + $fwrite (fd," 776"); + if (foo[ 6]) + $fwrite (fd," 777"); + else + $fwrite (fd," 778"); + $fwrite (fd," 779"); + end + 5'h1c : + begin + ozoneae(foo[20:18], fd); + $fwrite (fd," 780"); + end + 5'h1d : + begin + ozoneae(foo[20:18], fd); + $fwrite (fd," 781"); + if (foo[ 6]) + $fwrite (fd," 782"); + else + $fwrite (fd," 783"); + $fwrite (fd," 784"); + end + 5'h1e : + begin + ozoneae(foo[20:18], fd); + $fwrite (fd," 785"); + if (foo[ 6]) + $fwrite (fd," 786"); + else + $fwrite (fd," 787"); + $fwrite (fd," 788"); + end + 5'h1f : + begin + ozoneae(foo[20:18], fd); + $fwrite (fd," 789"); + ozoneae(foo[17:15], fd); + $fwrite (fd," 790"); + if (foo[ 6]) + $fwrite (fd," 791"); + else + $fwrite (fd," 792"); + $fwrite (fd," 793"); + end + default : $fwrite (fd," 794"); - endcase + endcase end endtask @@ -1881,148 +1881,148 @@ module t_case_write2_tasks (); input [`FD_BITS] fd; // verilator no_inline_task begin - case (foo[25:21]) - 5'h00, - 5'h01, - 5'h02: - begin - ozoneae(foo[20:18], fd); - case (foo[22:21]) - 2'h0: $fwrite (fd," 795"); - 2'h1: $fwrite (fd," 796"); - 2'h2: $fwrite (fd," 797"); - endcase - ozoneae(foo[17:15], fd); - $fwrite (fd," 798"); - if (foo[ 9]) - ozoneae(foo[ 8: 6], fd); - else - ozonef3e_te(foo[ 8: 6], fd); - $fwrite (fd," 799"); - end - 5'h08, - 5'h09, - 5'h0d, - 5'h0e, - 5'h0f: - begin - ozoneae(foo[20:18], fd); - $fwrite (fd," 800"); - ozoneae(foo[17:15], fd); - case (foo[23:21]) - 3'h0: $fwrite (fd," 801"); - 3'h1: $fwrite (fd," 802"); - 3'h5: $fwrite (fd," 803"); - 3'h6: $fwrite (fd," 804"); - 3'h7: $fwrite (fd," 805"); - endcase - if (foo[ 9]) - ozoneae(foo[ 8: 6], fd); - else - ozonef3e_te(foo[ 8: 6], fd); - end - 5'h0a, - 5'h0b: - begin - ozoneae(foo[17:15], fd); - if (foo[21]) - $fwrite (fd," 806"); - else - $fwrite (fd," 807"); - if (foo[ 9]) - ozoneae(foo[ 8: 6], fd); - else - ozonef3e_te(foo[ 8: 6], fd); - end - 5'h0c: - begin - ozoneae(foo[20:18], fd); - $fwrite (fd," 808"); - if (foo[ 9]) - ozoneae(foo[ 8: 6], fd); - else - ozonef3e_te(foo[ 8: 6], fd); - $fwrite (fd," 809"); - ozoneae(foo[17:15], fd); - end - 5'h10, - 5'h11, - 5'h12, - 5'h13: - begin - ozoneae(foo[20:18], fd); - $fwrite (fd," 810"); - ozoneae(foo[17:15], fd); - case (foo[22:21]) - 2'h0, - 2'h2: - $fwrite (fd," 811"); - 2'h1, - 2'h3: - $fwrite (fd," 812"); - endcase - ozoneae(foo[ 8: 6], fd); - $fwrite (fd," 813"); - ozoneae((foo[20:18]+1), fd); - $fwrite (fd," 814"); - ozoneae((foo[17:15]+1), fd); - case (foo[22:21]) - 2'h0, - 2'h3: - $fwrite (fd," 815"); - 2'h1, - 2'h2: - $fwrite (fd," 816"); - endcase - ozoneae((foo[ 8: 6]+1), fd); - end - 5'h18: - begin - ozoneae(foo[20:18], fd); - $fwrite (fd," 817"); - ozoneae(foo[17:15], fd); - $fwrite (fd," 818"); - ozoneae(foo[ 8: 6], fd); - $fwrite (fd," 819"); - ozoneae(foo[20:18], fd); - $fwrite (fd," 820"); - ozoneae(foo[17:15], fd); - $fwrite (fd," 821"); - ozoneae(foo[ 8: 6], fd); - end - default : + case (foo[25:21]) + 5'h00, + 5'h01, + 5'h02: + begin + ozoneae(foo[20:18], fd); + case (foo[22:21]) + 2'h0: $fwrite (fd," 795"); + 2'h1: $fwrite (fd," 796"); + 2'h2: $fwrite (fd," 797"); + endcase + ozoneae(foo[17:15], fd); + $fwrite (fd," 798"); + if (foo[ 9]) + ozoneae(foo[ 8: 6], fd); + else + ozonef3e_te(foo[ 8: 6], fd); + $fwrite (fd," 799"); + end + 5'h08, + 5'h09, + 5'h0d, + 5'h0e, + 5'h0f: + begin + ozoneae(foo[20:18], fd); + $fwrite (fd," 800"); + ozoneae(foo[17:15], fd); + case (foo[23:21]) + 3'h0: $fwrite (fd," 801"); + 3'h1: $fwrite (fd," 802"); + 3'h5: $fwrite (fd," 803"); + 3'h6: $fwrite (fd," 804"); + 3'h7: $fwrite (fd," 805"); + endcase + if (foo[ 9]) + ozoneae(foo[ 8: 6], fd); + else + ozonef3e_te(foo[ 8: 6], fd); + end + 5'h0a, + 5'h0b: + begin + ozoneae(foo[17:15], fd); + if (foo[21]) + $fwrite (fd," 806"); + else + $fwrite (fd," 807"); + if (foo[ 9]) + ozoneae(foo[ 8: 6], fd); + else + ozonef3e_te(foo[ 8: 6], fd); + end + 5'h0c: + begin + ozoneae(foo[20:18], fd); + $fwrite (fd," 808"); + if (foo[ 9]) + ozoneae(foo[ 8: 6], fd); + else + ozonef3e_te(foo[ 8: 6], fd); + $fwrite (fd," 809"); + ozoneae(foo[17:15], fd); + end + 5'h10, + 5'h11, + 5'h12, + 5'h13: + begin + ozoneae(foo[20:18], fd); + $fwrite (fd," 810"); + ozoneae(foo[17:15], fd); + case (foo[22:21]) + 2'h0, + 2'h2: + $fwrite (fd," 811"); + 2'h1, + 2'h3: + $fwrite (fd," 812"); + endcase + ozoneae(foo[ 8: 6], fd); + $fwrite (fd," 813"); + ozoneae((foo[20:18]+1), fd); + $fwrite (fd," 814"); + ozoneae((foo[17:15]+1), fd); + case (foo[22:21]) + 2'h0, + 2'h3: + $fwrite (fd," 815"); + 2'h1, + 2'h2: + $fwrite (fd," 816"); + endcase + ozoneae((foo[ 8: 6]+1), fd); + end + 5'h18: + begin + ozoneae(foo[20:18], fd); + $fwrite (fd," 817"); + ozoneae(foo[17:15], fd); + $fwrite (fd," 818"); + ozoneae(foo[ 8: 6], fd); + $fwrite (fd," 819"); + ozoneae(foo[20:18], fd); + $fwrite (fd," 820"); + ozoneae(foo[17:15], fd); + $fwrite (fd," 821"); + ozoneae(foo[ 8: 6], fd); + end + default : $fwrite (fd," 822"); - endcase + endcase end endtask task ozonef3e_te; input [ 2:0] te; - input [`FD_BITS] fd; + input [`FD_BITS] fd; // verilator no_inline_task begin - case (te) - 3'b100 : $fwrite (fd, " 823"); - 3'b101 : $fwrite (fd, " 824"); - 3'b110 : $fwrite (fd, " 825"); - default: $fwrite (fd, " 826"); - endcase + case (te) + 3'b100 : $fwrite (fd, " 823"); + 3'b101 : $fwrite (fd, " 824"); + 3'b110 : $fwrite (fd, " 825"); + default: $fwrite (fd, " 826"); + endcase end endtask task ozonearm; input [ 2:0] ate; - input [`FD_BITS] fd; + input [`FD_BITS] fd; // verilator no_inline_task begin - case (ate) - 3'b000 : $fwrite (fd, " 827"); - 3'b001 : $fwrite (fd, " 828"); - 3'b010 : $fwrite (fd, " 829"); - 3'b011 : $fwrite (fd, " 830"); - 3'b100 : $fwrite (fd, " 831"); - 3'b101 : $fwrite (fd, " 832"); - 3'b110 : $fwrite (fd, " 833"); - 3'b111 : $fwrite (fd, " 834"); - endcase + case (ate) + 3'b000 : $fwrite (fd, " 827"); + 3'b001 : $fwrite (fd, " 828"); + 3'b010 : $fwrite (fd, " 829"); + 3'b011 : $fwrite (fd, " 830"); + 3'b100 : $fwrite (fd, " 831"); + 3'b101 : $fwrite (fd, " 832"); + 3'b110 : $fwrite (fd, " 833"); + 3'b111 : $fwrite (fd, " 834"); + endcase end endtask task ozonebmuop; @@ -2030,136 +2030,136 @@ module t_case_write2_tasks (); input [`FD_BITS] fd; // verilator no_inline_task begin - case (f4[ 4:0]) - 5'h00, - 5'h04 : + case (f4[ 4:0]) + 5'h00, + 5'h04 : $fwrite (fd, " 835"); - 5'h01, - 5'h05 : + 5'h01, + 5'h05 : $fwrite (fd, " 836"); - 5'h02, - 5'h06 : + 5'h02, + 5'h06 : $fwrite (fd, " 837"); - 5'h03, - 5'h07 : + 5'h03, + 5'h07 : $fwrite (fd, " 838"); - 5'h08, - 5'h18 : + 5'h08, + 5'h18 : $fwrite (fd, " 839"); - 5'h09, - 5'h19 : + 5'h09, + 5'h19 : $fwrite (fd, " 840"); - 5'h0a, - 5'h1a : + 5'h0a, + 5'h1a : $fwrite (fd, " 841"); - 5'h0b : + 5'h0b : $fwrite (fd, " 842"); - 5'h1b : + 5'h1b : $fwrite (fd, " 843"); - 5'h0c, - 5'h1c : + 5'h0c, + 5'h1c : $fwrite (fd, " 844"); - 5'h0d, - 5'h1d : + 5'h0d, + 5'h1d : $fwrite (fd, " 845"); - 5'h1e : + 5'h1e : $fwrite (fd, " 846"); - endcase + endcase end endtask task ozonef3; input [ 31:0] foo; input [`FD_BITS] fd; - reg nacho; + reg nacho; // verilator no_inline_task begin : f3_body - nacho = 1'b0; - case (foo[24:21]) - 4'h0: + nacho = 1'b0; + case (foo[24:21]) + 4'h0: case (foo[26:25]) 2'b00 : $fwrite (fd, " 847"); 2'b01 : $fwrite (fd, " 848"); 2'b10 : $fwrite (fd, " 849"); 2'b11 : $fwrite (fd, " 850"); endcase - 4'h1: + 4'h1: case (foo[26:25]) 2'b00 : $fwrite (fd, " 851"); 2'b01 : $fwrite (fd, " 852"); 2'b10 : $fwrite (fd, " 853"); 2'b11 : $fwrite (fd, " 854"); endcase - 4'h2: + 4'h2: case (foo[26:25]) 2'b00 : $fwrite (fd, " 855"); 2'b01 : $fwrite (fd, " 856"); 2'b10 : $fwrite (fd, " 857"); 2'b11 : $fwrite (fd, " 858"); endcase - 4'h8, - 4'h9, - 4'hd, - 4'he, - 4'hf : + 4'h8, + 4'h9, + 4'hd, + 4'he, + 4'hf : case (foo[26:25]) - 2'b00 : $fwrite (fd, " 859"); - 2'b01 : $fwrite (fd, " 860"); - 2'b10 : $fwrite (fd, " 861"); - 2'b11 : $fwrite (fd, " 862"); + 2'b00 : $fwrite (fd, " 859"); + 2'b01 : $fwrite (fd, " 860"); + 2'b10 : $fwrite (fd, " 861"); + 2'b11 : $fwrite (fd, " 862"); endcase - 4'ha, - 4'hb : + 4'ha, + 4'hb : if (foo[25]) - $fwrite (fd, " 863"); + $fwrite (fd, " 863"); else - $fwrite (fd, " 864"); - 4'hc : + $fwrite (fd, " 864"); + 4'hc : if (foo[26]) $fwrite (fd, " 865"); else $fwrite (fd, " 866"); - default : - begin - $fwrite (fd, " 867"); - nacho = 1'b1; - end - endcase - if (~nacho) - begin - case (foo[24:21]) - 4'h8 : - $fwrite (fd, " 868"); - 4'h9 : - $fwrite (fd, " 869"); - 4'ha, - 4'he : - $fwrite (fd, " 870"); - 4'hb, - 4'hf : - $fwrite (fd, " 871"); - 4'hd : - $fwrite (fd, " 872"); - endcase - if (foo[20]) - case (foo[18:16]) - 3'b000 : $fwrite (fd, " 873"); - 3'b100 : $fwrite (fd, " 874"); - default: $fwrite (fd, " 875"); - endcase - else - ozoneae(foo[18:16], fd); - if (foo[24:21] === 4'hc) - if (foo[25]) - $fwrite (fd, " 876"); - else - $fwrite (fd, " 877"); - case (foo[24:21]) - 4'h0, - 4'h1, - 4'h2: - $fwrite (fd, " 878"); - endcase - end + default : + begin + $fwrite (fd, " 867"); + nacho = 1'b1; + end + endcase + if (~nacho) + begin + case (foo[24:21]) + 4'h8 : + $fwrite (fd, " 868"); + 4'h9 : + $fwrite (fd, " 869"); + 4'ha, + 4'he : + $fwrite (fd, " 870"); + 4'hb, + 4'hf : + $fwrite (fd, " 871"); + 4'hd : + $fwrite (fd, " 872"); + endcase + if (foo[20]) + case (foo[18:16]) + 3'b000 : $fwrite (fd, " 873"); + 3'b100 : $fwrite (fd, " 874"); + default: $fwrite (fd, " 875"); + endcase + else + ozoneae(foo[18:16], fd); + if (foo[24:21] === 4'hc) + if (foo[25]) + $fwrite (fd, " 876"); + else + $fwrite (fd, " 877"); + case (foo[24:21]) + 4'h0, + 4'h1, + 4'h2: + $fwrite (fd, " 878"); + endcase + end end endtask task ozonerx; @@ -2167,17 +2167,17 @@ module t_case_write2_tasks (); input [`FD_BITS] fd; // verilator no_inline_task begin - case (foo[19:18]) - 2'h0 : $fwrite (fd, " 879"); - 2'h1 : $fwrite (fd, " 880"); - 2'h2 : $fwrite (fd, " 881"); - 2'h3 : $fwrite (fd, " 882"); - endcase - case (foo[17:16]) - 2'h1 : $fwrite (fd, " 883"); - 2'h2 : $fwrite (fd, " 884"); - 2'h3 : $fwrite (fd, " 885"); - endcase + case (foo[19:18]) + 2'h0 : $fwrite (fd, " 879"); + 2'h1 : $fwrite (fd, " 880"); + 2'h2 : $fwrite (fd, " 881"); + 2'h3 : $fwrite (fd, " 882"); + endcase + case (foo[17:16]) + 2'h1 : $fwrite (fd, " 883"); + 2'h2 : $fwrite (fd, " 884"); + 2'h3 : $fwrite (fd, " 885"); + endcase end endtask task ozonerme; @@ -2185,47 +2185,47 @@ module t_case_write2_tasks (); input [`FD_BITS] fd; // verilator no_inline_task begin - case (rme) - 3'h0 : $fwrite (fd, " 886"); - 3'h1 : $fwrite (fd, " 887"); - 3'h2 : $fwrite (fd, " 888"); - 3'h3 : $fwrite (fd, " 889"); - 3'h4 : $fwrite (fd, " 890"); - 3'h5 : $fwrite (fd, " 891"); - 3'h6 : $fwrite (fd, " 892"); - 3'h7 : $fwrite (fd, " 893"); - endcase + case (rme) + 3'h0 : $fwrite (fd, " 886"); + 3'h1 : $fwrite (fd, " 887"); + 3'h2 : $fwrite (fd, " 888"); + 3'h3 : $fwrite (fd, " 889"); + 3'h4 : $fwrite (fd, " 890"); + 3'h5 : $fwrite (fd, " 891"); + 3'h6 : $fwrite (fd, " 892"); + 3'h7 : $fwrite (fd, " 893"); + endcase end endtask task ozoneye; input [5:0] ye; - input l; + input l; input [`FD_BITS] fd; // verilator no_inline_task begin - $fwrite (fd, " 894"); - ozonerme(ye[5:3], fd); - case ({ye[ 2:0], l}) - 4'h2, - 4'ha: $fwrite (fd, " 895"); - 4'h4, - 4'hb: $fwrite (fd, " 896"); - 4'h6, - 4'he: $fwrite (fd, " 897"); - 4'h8, - 4'hc: $fwrite (fd, " 898"); - endcase + $fwrite (fd, " 894"); + ozonerme(ye[5:3], fd); + case ({ye[ 2:0], l}) + 4'h2, + 4'ha: $fwrite (fd, " 895"); + 4'h4, + 4'hb: $fwrite (fd, " 896"); + 4'h6, + 4'he: $fwrite (fd, " 897"); + 4'h8, + 4'hc: $fwrite (fd, " 898"); + endcase end endtask task ozonef1e_ye; input [5:0] ye; - input l; + input l; input [`FD_BITS] fd; // verilator no_inline_task begin - $fwrite (fd, " 899"); - ozonerme(ye[5:3], fd); - ozonef1e_inc_dec(ye[5:0], l , fd); + $fwrite (fd, " 899"); + ozonerme(ye[5:3], fd); + ozonef1e_inc_dec(ye[5:0], l , fd); end endtask task ozonef1e_h; @@ -2233,31 +2233,31 @@ module t_case_write2_tasks (); input [`FD_BITS] fd; // verilator no_inline_task begin - if (e[ 2:0] <= 3'h4) - $fwrite (fd, " 900"); + if (e[ 2:0] <= 3'h4) + $fwrite (fd, " 900"); end endtask task ozonef1e_inc_dec; input [5:0] ye; - input l; + input l; input [`FD_BITS] fd; // verilator no_inline_task begin - case ({ye[ 2:0], l}) - 4'h2, - 4'h3, - 4'ha: $fwrite (fd, " 901"); - 4'h4, - 4'h5, - 4'hb: $fwrite (fd, " 902"); - 4'h6, - 4'h7, - 4'he: $fwrite (fd, " 903"); - 4'h8, - 4'h9, - 4'hc: $fwrite (fd, " 904"); - 4'hf: $fwrite (fd, " 905"); - endcase + case ({ye[ 2:0], l}) + 4'h2, + 4'h3, + 4'ha: $fwrite (fd, " 901"); + 4'h4, + 4'h5, + 4'hb: $fwrite (fd, " 902"); + 4'h6, + 4'h7, + 4'he: $fwrite (fd, " 903"); + 4'h8, + 4'h9, + 4'hc: $fwrite (fd, " 904"); + 4'hf: $fwrite (fd, " 905"); + endcase end endtask task ozonef1e_hl; @@ -2266,18 +2266,18 @@ module t_case_write2_tasks (); input [`FD_BITS] fd; // verilator no_inline_task begin - case ({e[ 2:0], l}) - 4'h0, - 4'h2, - 4'h4, - 4'h6, - 4'h8: $fwrite (fd, " 906"); - 4'h1, - 4'h3, - 4'h5, - 4'h7, - 4'h9: $fwrite (fd, " 907"); - endcase + case ({e[ 2:0], l}) + 4'h0, + 4'h2, + 4'h4, + 4'h6, + 4'h8: $fwrite (fd, " 906"); + 4'h1, + 4'h3, + 4'h5, + 4'h7, + 4'h9: $fwrite (fd, " 907"); + endcase end endtask task ozonexe; @@ -2285,19 +2285,19 @@ module t_case_write2_tasks (); input [`FD_BITS] fd; // verilator no_inline_task begin - case (xe[3]) - 1'b0 : $fwrite (fd, " 908"); - 1'b1 : $fwrite (fd, " 909"); - endcase - case (xe[ 2:0]) - 3'h1, - 3'h5: $fwrite (fd, " 910"); - 3'h2, - 3'h6: $fwrite (fd, " 911"); - 3'h3, - 3'h7: $fwrite (fd, " 912"); - 3'h4: $fwrite (fd, " 913"); - endcase + case (xe[3]) + 1'b0 : $fwrite (fd, " 908"); + 1'b1 : $fwrite (fd, " 909"); + endcase + case (xe[ 2:0]) + 3'h1, + 3'h5: $fwrite (fd, " 910"); + 3'h2, + 3'h6: $fwrite (fd, " 911"); + 3'h3, + 3'h7: $fwrite (fd, " 912"); + 3'h4: $fwrite (fd, " 913"); + endcase end endtask task ozonerp; @@ -2305,16 +2305,16 @@ module t_case_write2_tasks (); input [`FD_BITS] fd; // verilator no_inline_task begin - case (rp) - 3'h0 : $fwrite (fd, " 914"); - 3'h1 : $fwrite (fd, " 915"); - 3'h2 : $fwrite (fd, " 916"); - 3'h3 : $fwrite (fd, " 917"); - 3'h4 : $fwrite (fd, " 918"); - 3'h5 : $fwrite (fd, " 919"); - 3'h6 : $fwrite (fd, " 920"); - 3'h7 : $fwrite (fd, " 921"); - endcase + case (rp) + 3'h0 : $fwrite (fd, " 914"); + 3'h1 : $fwrite (fd, " 915"); + 3'h2 : $fwrite (fd, " 916"); + 3'h3 : $fwrite (fd, " 917"); + 3'h4 : $fwrite (fd, " 918"); + 3'h5 : $fwrite (fd, " 919"); + 3'h6 : $fwrite (fd, " 920"); + 3'h7 : $fwrite (fd, " 921"); + endcase end endtask task ozonery; @@ -2322,24 +2322,24 @@ module t_case_write2_tasks (); input [`FD_BITS] fd; // verilator no_inline_task begin - case (ry) - 4'h0 : $fwrite (fd, " 922"); - 4'h1 : $fwrite (fd, " 923"); - 4'h2 : $fwrite (fd, " 924"); - 4'h3 : $fwrite (fd, " 925"); - 4'h4 : $fwrite (fd, " 926"); - 4'h5 : $fwrite (fd, " 927"); - 4'h6 : $fwrite (fd, " 928"); - 4'h7 : $fwrite (fd, " 929"); - 4'h8 : $fwrite (fd, " 930"); - 4'h9 : $fwrite (fd, " 931"); - 4'ha : $fwrite (fd, " 932"); - 4'hb : $fwrite (fd, " 933"); - 4'hc : $fwrite (fd, " 934"); - 4'hd : $fwrite (fd, " 935"); - 4'he : $fwrite (fd, " 936"); - 4'hf : $fwrite (fd, " 937"); - endcase + case (ry) + 4'h0 : $fwrite (fd, " 922"); + 4'h1 : $fwrite (fd, " 923"); + 4'h2 : $fwrite (fd, " 924"); + 4'h3 : $fwrite (fd, " 925"); + 4'h4 : $fwrite (fd, " 926"); + 4'h5 : $fwrite (fd, " 927"); + 4'h6 : $fwrite (fd, " 928"); + 4'h7 : $fwrite (fd, " 929"); + 4'h8 : $fwrite (fd, " 930"); + 4'h9 : $fwrite (fd, " 931"); + 4'ha : $fwrite (fd, " 932"); + 4'hb : $fwrite (fd, " 933"); + 4'hc : $fwrite (fd, " 934"); + 4'hd : $fwrite (fd, " 935"); + 4'he : $fwrite (fd, " 936"); + 4'hf : $fwrite (fd, " 937"); + endcase end endtask task ozonearx; @@ -2347,12 +2347,12 @@ module t_case_write2_tasks (); input [`FD_BITS] fd; // verilator no_inline_task begin - case (foo[1:0]) - 2'h0 : $fwrite (fd, " 938"); - 2'h1 : $fwrite (fd, " 939"); - 2'h2 : $fwrite (fd, " 940"); - 2'h3 : $fwrite (fd, " 941"); - endcase + case (foo[1:0]) + 2'h0 : $fwrite (fd, " 938"); + 2'h1 : $fwrite (fd, " 939"); + 2'h2 : $fwrite (fd, " 940"); + 2'h3 : $fwrite (fd, " 941"); + endcase end endtask task ozonef3f4imop; @@ -2360,19 +2360,19 @@ module t_case_write2_tasks (); input [`FD_BITS] fd; // verilator no_inline_task begin - casez (f3f4iml) - 5'b000??: $fwrite (fd, " 942"); - 5'b001??: $fwrite (fd, " 943"); - 5'b?10??: $fwrite (fd, " 944"); - 5'b0110?: $fwrite (fd, " 945"); - 5'b01110: $fwrite (fd, " 946"); - 5'b01111: $fwrite (fd, " 947"); - 5'b10???: $fwrite (fd, " 948"); - 5'b11100: $fwrite (fd, " 949"); - 5'b11101: $fwrite (fd, " 950"); - 5'b11110: $fwrite (fd, " 951"); - 5'b11111: $fwrite (fd, " 952"); - endcase + casez (f3f4iml) + 5'b000??: $fwrite (fd, " 942"); + 5'b001??: $fwrite (fd, " 943"); + 5'b?10??: $fwrite (fd, " 944"); + 5'b0110?: $fwrite (fd, " 945"); + 5'b01110: $fwrite (fd, " 946"); + 5'b01111: $fwrite (fd, " 947"); + 5'b10???: $fwrite (fd, " 948"); + 5'b11100: $fwrite (fd, " 949"); + 5'b11101: $fwrite (fd, " 950"); + 5'b11110: $fwrite (fd, " 951"); + 5'b11111: $fwrite (fd, " 952"); + endcase end endtask task ozonecon; @@ -2380,40 +2380,40 @@ module t_case_write2_tasks (); input [`FD_BITS] fd; // verilator no_inline_task begin - case (con) - 5'h00 : $fwrite (fd, " 953"); - 5'h01 : $fwrite (fd, " 954"); - 5'h02 : $fwrite (fd, " 955"); - 5'h03 : $fwrite (fd, " 956"); - 5'h04 : $fwrite (fd, " 957"); - 5'h05 : $fwrite (fd, " 958"); - 5'h06 : $fwrite (fd, " 959"); - 5'h07 : $fwrite (fd, " 960"); - 5'h08 : $fwrite (fd, " 961"); - 5'h09 : $fwrite (fd, " 962"); - 5'h0a : $fwrite (fd, " 963"); - 5'h0b : $fwrite (fd, " 964"); - 5'h0c : $fwrite (fd, " 965"); - 5'h0d : $fwrite (fd, " 966"); - 5'h0e : $fwrite (fd, " 967"); - 5'h0f : $fwrite (fd, " 968"); - 5'h10 : $fwrite (fd, " 969"); - 5'h11 : $fwrite (fd, " 970"); - 5'h12 : $fwrite (fd, " 971"); - 5'h13 : $fwrite (fd, " 972"); - 5'h14 : $fwrite (fd, " 973"); - 5'h15 : $fwrite (fd, " 974"); - 5'h16 : $fwrite (fd, " 975"); - 5'h17 : $fwrite (fd, " 976"); - 5'h18 : $fwrite (fd, " 977"); - 5'h19 : $fwrite (fd, " 978"); - 5'h1a : $fwrite (fd, " 979"); - 5'h1b : $fwrite (fd, " 980"); - 5'h1c : $fwrite (fd, " 981"); - 5'h1d : $fwrite (fd, " 982"); - 5'h1e : $fwrite (fd, " 983"); - 5'h1f : $fwrite (fd, " 984"); - endcase + case (con) + 5'h00 : $fwrite (fd, " 953"); + 5'h01 : $fwrite (fd, " 954"); + 5'h02 : $fwrite (fd, " 955"); + 5'h03 : $fwrite (fd, " 956"); + 5'h04 : $fwrite (fd, " 957"); + 5'h05 : $fwrite (fd, " 958"); + 5'h06 : $fwrite (fd, " 959"); + 5'h07 : $fwrite (fd, " 960"); + 5'h08 : $fwrite (fd, " 961"); + 5'h09 : $fwrite (fd, " 962"); + 5'h0a : $fwrite (fd, " 963"); + 5'h0b : $fwrite (fd, " 964"); + 5'h0c : $fwrite (fd, " 965"); + 5'h0d : $fwrite (fd, " 966"); + 5'h0e : $fwrite (fd, " 967"); + 5'h0f : $fwrite (fd, " 968"); + 5'h10 : $fwrite (fd, " 969"); + 5'h11 : $fwrite (fd, " 970"); + 5'h12 : $fwrite (fd, " 971"); + 5'h13 : $fwrite (fd, " 972"); + 5'h14 : $fwrite (fd, " 973"); + 5'h15 : $fwrite (fd, " 974"); + 5'h16 : $fwrite (fd, " 975"); + 5'h17 : $fwrite (fd, " 976"); + 5'h18 : $fwrite (fd, " 977"); + 5'h19 : $fwrite (fd, " 978"); + 5'h1a : $fwrite (fd, " 979"); + 5'h1b : $fwrite (fd, " 980"); + 5'h1c : $fwrite (fd, " 981"); + 5'h1d : $fwrite (fd, " 982"); + 5'h1e : $fwrite (fd, " 983"); + 5'h1f : $fwrite (fd, " 984"); + endcase end endtask task ozonedr; @@ -2421,24 +2421,24 @@ module t_case_write2_tasks (); input [`FD_BITS] fd; // verilator no_inline_task begin - case (foo[ 9: 6]) - 4'h0 : $fwrite (fd, " 985"); - 4'h1 : $fwrite (fd, " 986"); - 4'h2 : $fwrite (fd, " 987"); - 4'h3 : $fwrite (fd, " 988"); - 4'h4 : $fwrite (fd, " 989"); - 4'h5 : $fwrite (fd, " 990"); - 4'h6 : $fwrite (fd, " 991"); - 4'h7 : $fwrite (fd, " 992"); - 4'h8 : $fwrite (fd, " 993"); - 4'h9 : $fwrite (fd, " 994"); - 4'ha : $fwrite (fd, " 995"); - 4'hb : $fwrite (fd, " 996"); - 4'hc : $fwrite (fd, " 997"); - 4'hd : $fwrite (fd, " 998"); - 4'he : $fwrite (fd, " 999"); - 4'hf : $fwrite (fd, " 1000"); - endcase + case (foo[ 9: 6]) + 4'h0 : $fwrite (fd, " 985"); + 4'h1 : $fwrite (fd, " 986"); + 4'h2 : $fwrite (fd, " 987"); + 4'h3 : $fwrite (fd, " 988"); + 4'h4 : $fwrite (fd, " 989"); + 4'h5 : $fwrite (fd, " 990"); + 4'h6 : $fwrite (fd, " 991"); + 4'h7 : $fwrite (fd, " 992"); + 4'h8 : $fwrite (fd, " 993"); + 4'h9 : $fwrite (fd, " 994"); + 4'ha : $fwrite (fd, " 995"); + 4'hb : $fwrite (fd, " 996"); + 4'hc : $fwrite (fd, " 997"); + 4'hd : $fwrite (fd, " 998"); + 4'he : $fwrite (fd, " 999"); + 4'hf : $fwrite (fd, " 1000"); + endcase end endtask task ozoneshift; @@ -2446,12 +2446,12 @@ module t_case_write2_tasks (); input [`FD_BITS] fd; // verilator no_inline_task begin - case (foo[ 4: 3]) - 2'h0 : $fwrite (fd, " 1001"); - 2'h1 : $fwrite (fd, " 1002"); - 2'h2 : $fwrite (fd, " 1003"); - 2'h3 : $fwrite (fd, " 1004"); - endcase + case (foo[ 4: 3]) + 2'h0 : $fwrite (fd, " 1001"); + 2'h1 : $fwrite (fd, " 1002"); + 2'h2 : $fwrite (fd, " 1003"); + 2'h3 : $fwrite (fd, " 1004"); + endcase end endtask task ozoneacc; @@ -2459,10 +2459,10 @@ module t_case_write2_tasks (); input [`FD_BITS] fd; // verilator no_inline_task begin - case (foo) - 2'h0 : $fwrite (fd, " 1005"); - 2'h1 : $fwrite (fd, " 1006"); - endcase + case (foo) + 2'h0 : $fwrite (fd, " 1005"); + 2'h1 : $fwrite (fd, " 1006"); + endcase end endtask task ozonehl; @@ -2470,10 +2470,10 @@ module t_case_write2_tasks (); input [`FD_BITS] fd; // verilator no_inline_task begin - case (foo) - 2'h0 : $fwrite (fd, " 1007"); - 2'h1 : $fwrite (fd, " 1008"); - endcase + case (foo) + 2'h0 : $fwrite (fd, " 1007"); + 2'h1 : $fwrite (fd, " 1008"); + endcase end endtask task dude; @@ -2487,1284 +2487,1284 @@ module t_case_write2_tasks (); input [ 31:0] foo; // verilator no_inline_task begin - $fwrite(fd," 1009"); - if (&foo === 1'bx) - $fwrite(fd, " 1010"); - else - casez ( {foo[31:26], foo[19:15], foo[5:0]} ) + $fwrite(fd," 1009"); + if (&foo === 1'bx) + $fwrite(fd, " 1010"); + else + casez ( {foo[31:26], foo[19:15], foo[5:0]} ) 17'b00_111?_?_????_??_???? : begin - ozonef1(foo, fd); - $fwrite (fd, " 1011"); - ozoneacc(~foo[26], fd); - ozonehl(foo[20], fd); - $fwrite (fd, " 1012"); - ozonerx(foo, fd); - dude(fd); - $fwrite (fd, " 1013"); + ozonef1(foo, fd); + $fwrite (fd, " 1011"); + ozoneacc(~foo[26], fd); + ozonehl(foo[20], fd); + $fwrite (fd, " 1012"); + ozonerx(foo, fd); + dude(fd); + $fwrite (fd, " 1013"); end 17'b01_001?_?_????_??_???? : begin - ozonef1(foo, fd); - $fwrite (fd, " 1014"); - ozonerx(foo, fd); - $fwrite (fd, " 1015"); - $fwrite (fd, " 1016:%x", foo[20]); - ozonehl(foo[20], fd); - dude(fd); - $fwrite (fd, " 1017"); + ozonef1(foo, fd); + $fwrite (fd, " 1014"); + ozonerx(foo, fd); + $fwrite (fd, " 1015"); + $fwrite (fd, " 1016:%x", foo[20]); + ozonehl(foo[20], fd); + dude(fd); + $fwrite (fd, " 1017"); end 17'b10_100?_?_????_??_???? : begin - ozonef1(foo, fd); - $fwrite (fd, " 1018"); - ozonerx(foo, fd); - $fwrite (fd, " 1019"); - $fwrite (fd, " 1020"); - ozonehl(foo[20], fd); - dude(fd); - $fwrite (fd, " 1021"); + ozonef1(foo, fd); + $fwrite (fd, " 1018"); + ozonerx(foo, fd); + $fwrite (fd, " 1019"); + $fwrite (fd, " 1020"); + ozonehl(foo[20], fd); + dude(fd); + $fwrite (fd, " 1021"); end 17'b10_101?_?_????_??_???? : begin - ozonef1(foo, fd); - $fwrite (fd, " 1022"); - if (foo[20]) - begin - $fwrite (fd, " 1023"); - ozoneacc(foo[18], fd); - $fwrite (fd, " 1024"); - $fwrite (fd, " 1025"); - if (foo[19]) - $fwrite (fd, " 1026"); - else - $fwrite (fd, " 1027"); - end - else - ozonerx(foo, fd); - dude(fd); - $fwrite (fd, " 1028"); + ozonef1(foo, fd); + $fwrite (fd, " 1022"); + if (foo[20]) + begin + $fwrite (fd, " 1023"); + ozoneacc(foo[18], fd); + $fwrite (fd, " 1024"); + $fwrite (fd, " 1025"); + if (foo[19]) + $fwrite (fd, " 1026"); + else + $fwrite (fd, " 1027"); + end + else + ozonerx(foo, fd); + dude(fd); + $fwrite (fd, " 1028"); end 17'b10_110?_?_????_??_???? : begin - ozonef1(foo, fd); - $fwrite (fd, " 1029"); - $fwrite (fd, " 1030"); - ozonehl(foo[20], fd); - $fwrite (fd, " 1031"); - ozonerx(foo, fd); - dude(fd); - $fwrite (fd, " 1032"); + ozonef1(foo, fd); + $fwrite (fd, " 1029"); + $fwrite (fd, " 1030"); + ozonehl(foo[20], fd); + $fwrite (fd, " 1031"); + ozonerx(foo, fd); + dude(fd); + $fwrite (fd, " 1032"); end 17'b10_111?_?_????_??_???? : begin - ozonef1(foo, fd); - $fwrite (fd, " 1033"); - $fwrite (fd, " 1034"); - ozonehl(foo[20], fd); - $fwrite (fd, " 1035"); - ozonerx(foo, fd); - dude(fd); - $fwrite (fd, " 1036"); + ozonef1(foo, fd); + $fwrite (fd, " 1033"); + $fwrite (fd, " 1034"); + ozonehl(foo[20], fd); + $fwrite (fd, " 1035"); + ozonerx(foo, fd); + dude(fd); + $fwrite (fd, " 1036"); end 17'b11_001?_?_????_??_???? : begin - ozonef1(foo, fd); - $fwrite (fd, " 1037"); - ozonerx(foo, fd); - $fwrite (fd, " 1038"); - $fwrite (fd, " 1039"); - ozonehl(foo[20], fd); - dude(fd); - $fwrite (fd, " 1040"); + ozonef1(foo, fd); + $fwrite (fd, " 1037"); + ozonerx(foo, fd); + $fwrite (fd, " 1038"); + $fwrite (fd, " 1039"); + ozonehl(foo[20], fd); + dude(fd); + $fwrite (fd, " 1040"); end 17'b11_111?_?_????_??_???? : begin - ozonef1(foo, fd); - $fwrite (fd, " 1041"); - $fwrite (fd, " 1042"); - ozonerx(foo, fd); - $fwrite (fd, " 1043"); - if (foo[20]) - $fwrite (fd, " 1044"); - else - $fwrite (fd, " 1045"); - dude(fd); - $fwrite (fd, " 1046"); + ozonef1(foo, fd); + $fwrite (fd, " 1041"); + $fwrite (fd, " 1042"); + ozonerx(foo, fd); + $fwrite (fd, " 1043"); + if (foo[20]) + $fwrite (fd, " 1044"); + else + $fwrite (fd, " 1045"); + dude(fd); + $fwrite (fd, " 1046"); end 17'b00_10??_?_????_?1_1111 : casez (foo[11: 5]) - 7'b??_0_010_0: - begin - $fwrite (fd, " 1047"); - ozonecon(foo[14:10], fd); - $fwrite (fd, " 1048"); - ozonef1e(foo, fd); - dude(fd); - $fwrite (fd, " 1049"); - end - 7'b00_?_110_?: - begin - ozonef1e(foo, fd); - $fwrite (fd, " 1050"); - case ({foo[ 9],foo[ 5]}) - 2'b00: - begin - $fwrite (fd, " 1051"); - ozoneae(foo[14:12], fd); - ozonehl(foo[ 5], fd); - end - 2'b01: - begin - $fwrite (fd, " 1052"); - ozoneae(foo[14:12], fd); - ozonehl(foo[ 5], fd); - end - 2'b10: - begin - $fwrite (fd, " 1053"); - ozoneae(foo[14:12], fd); - end - 2'b11: $fwrite (fd, " 1054"); - endcase - dude(fd); - $fwrite (fd, " 1055"); - end - 7'b01_?_110_?: - begin - ozonef1e(foo, fd); - $fwrite (fd, " 1056"); - case ({foo[ 9],foo[ 5]}) - 2'b00: - begin - ozoneae(foo[14:12], fd); - ozonehl(foo[ 5], fd); - $fwrite (fd, " 1057"); - end - 2'b01: - begin - ozoneae(foo[14:12], fd); - ozonehl(foo[ 5], fd); - $fwrite (fd, " 1058"); - end - 2'b10: - begin - ozoneae(foo[14:12], fd); - $fwrite (fd, " 1059"); - end - 2'b11: $fwrite (fd, " 1060"); - endcase - dude(fd); - $fwrite (fd, " 1061"); - end - 7'b10_0_110_0: - begin - ozonef1e(foo, fd); - $fwrite (fd, " 1062"); - $fwrite (fd, " 1063"); - if (foo[12]) - $fwrite (fd, " 1064"); - else - ozonerab({4'b1001, foo[14:12]}, fd); - dude(fd); - $fwrite (fd, " 1065"); - end - 7'b10_0_110_1: - begin - ozonef1e(foo, fd); - $fwrite (fd, " 1066"); - if (foo[12]) - $fwrite (fd, " 1067"); - else - ozonerab({4'b1001, foo[14:12]}, fd); - $fwrite (fd, " 1068"); - dude(fd); - $fwrite (fd, " 1069"); - end - 7'b??_?_000_?: - begin - ozonef1e(foo, fd); - $fwrite (fd, " 1070"); - $fwrite (fd, " 1071"); - ozonef1e_hl(foo[11:9],foo[ 5], fd); - $fwrite (fd, " 1072"); - ozonef1e_ye(foo[14:9],foo[ 5], fd); - dude(fd); - $fwrite (fd, " 1073"); - end - 7'b??_?_100_?: - begin - ozonef1e(foo, fd); - $fwrite (fd, " 1074"); - $fwrite (fd, " 1075"); - ozonef1e_hl(foo[11:9],foo[ 5], fd); - $fwrite (fd, " 1076"); - ozonef1e_ye(foo[14:9],foo[ 5], fd); - dude(fd); - $fwrite (fd, " 1077"); - end - 7'b??_?_001_?: - begin - ozonef1e(foo, fd); - $fwrite (fd, " 1078"); - ozonef1e_ye(foo[14:9],foo[ 5], fd); - $fwrite (fd, " 1079"); - $fwrite (fd, " 1080"); - ozonef1e_hl(foo[11:9],foo[ 5], fd); - dude(fd); - $fwrite (fd, " 1081"); - end - 7'b??_?_011_?: - begin - ozonef1e(foo, fd); - $fwrite (fd, " 1082"); - ozonef1e_ye(foo[14:9],foo[ 5], fd); - $fwrite (fd, " 1083"); - $fwrite (fd, " 1084"); - ozonef1e_hl(foo[11:9],foo[ 5], fd); - dude(fd); - $fwrite (fd, " 1085"); - end - 7'b??_?_101_?: - begin - ozonef1e(foo, fd); - $fwrite (fd, " 1086"); - ozonef1e_ye(foo[14:9],foo[ 5], fd); - dude(fd); - $fwrite (fd, " 1087"); - end + 7'b??_0_010_0: + begin + $fwrite (fd, " 1047"); + ozonecon(foo[14:10], fd); + $fwrite (fd, " 1048"); + ozonef1e(foo, fd); + dude(fd); + $fwrite (fd, " 1049"); + end + 7'b00_?_110_?: + begin + ozonef1e(foo, fd); + $fwrite (fd, " 1050"); + case ({foo[ 9],foo[ 5]}) + 2'b00: + begin + $fwrite (fd, " 1051"); + ozoneae(foo[14:12], fd); + ozonehl(foo[ 5], fd); + end + 2'b01: + begin + $fwrite (fd, " 1052"); + ozoneae(foo[14:12], fd); + ozonehl(foo[ 5], fd); + end + 2'b10: + begin + $fwrite (fd, " 1053"); + ozoneae(foo[14:12], fd); + end + 2'b11: $fwrite (fd, " 1054"); + endcase + dude(fd); + $fwrite (fd, " 1055"); + end + 7'b01_?_110_?: + begin + ozonef1e(foo, fd); + $fwrite (fd, " 1056"); + case ({foo[ 9],foo[ 5]}) + 2'b00: + begin + ozoneae(foo[14:12], fd); + ozonehl(foo[ 5], fd); + $fwrite (fd, " 1057"); + end + 2'b01: + begin + ozoneae(foo[14:12], fd); + ozonehl(foo[ 5], fd); + $fwrite (fd, " 1058"); + end + 2'b10: + begin + ozoneae(foo[14:12], fd); + $fwrite (fd, " 1059"); + end + 2'b11: $fwrite (fd, " 1060"); + endcase + dude(fd); + $fwrite (fd, " 1061"); + end + 7'b10_0_110_0: + begin + ozonef1e(foo, fd); + $fwrite (fd, " 1062"); + $fwrite (fd, " 1063"); + if (foo[12]) + $fwrite (fd, " 1064"); + else + ozonerab({4'b1001, foo[14:12]}, fd); + dude(fd); + $fwrite (fd, " 1065"); + end + 7'b10_0_110_1: + begin + ozonef1e(foo, fd); + $fwrite (fd, " 1066"); + if (foo[12]) + $fwrite (fd, " 1067"); + else + ozonerab({4'b1001, foo[14:12]}, fd); + $fwrite (fd, " 1068"); + dude(fd); + $fwrite (fd, " 1069"); + end + 7'b??_?_000_?: + begin + ozonef1e(foo, fd); + $fwrite (fd, " 1070"); + $fwrite (fd, " 1071"); + ozonef1e_hl(foo[11:9],foo[ 5], fd); + $fwrite (fd, " 1072"); + ozonef1e_ye(foo[14:9],foo[ 5], fd); + dude(fd); + $fwrite (fd, " 1073"); + end + 7'b??_?_100_?: + begin + ozonef1e(foo, fd); + $fwrite (fd, " 1074"); + $fwrite (fd, " 1075"); + ozonef1e_hl(foo[11:9],foo[ 5], fd); + $fwrite (fd, " 1076"); + ozonef1e_ye(foo[14:9],foo[ 5], fd); + dude(fd); + $fwrite (fd, " 1077"); + end + 7'b??_?_001_?: + begin + ozonef1e(foo, fd); + $fwrite (fd, " 1078"); + ozonef1e_ye(foo[14:9],foo[ 5], fd); + $fwrite (fd, " 1079"); + $fwrite (fd, " 1080"); + ozonef1e_hl(foo[11:9],foo[ 5], fd); + dude(fd); + $fwrite (fd, " 1081"); + end + 7'b??_?_011_?: + begin + ozonef1e(foo, fd); + $fwrite (fd, " 1082"); + ozonef1e_ye(foo[14:9],foo[ 5], fd); + $fwrite (fd, " 1083"); + $fwrite (fd, " 1084"); + ozonef1e_hl(foo[11:9],foo[ 5], fd); + dude(fd); + $fwrite (fd, " 1085"); + end + 7'b??_?_101_?: + begin + ozonef1e(foo, fd); + $fwrite (fd, " 1086"); + ozonef1e_ye(foo[14:9],foo[ 5], fd); + dude(fd); + $fwrite (fd, " 1087"); + end endcase 17'b00_10??_?_????_?0_0110 : begin - ozonef1e(foo, fd); - $fwrite (fd, " 1088"); - ozoneae(foo[ 8: 6], fd); - ozonef1e_hl(foo[11:9],foo[ 5], fd); - $fwrite (fd, " 1089"); - ozonef1e_ye(foo[14:9],foo[ 5], fd); - dude(fd); - $fwrite (fd, " 1090"); + ozonef1e(foo, fd); + $fwrite (fd, " 1088"); + ozoneae(foo[ 8: 6], fd); + ozonef1e_hl(foo[11:9],foo[ 5], fd); + $fwrite (fd, " 1089"); + ozonef1e_ye(foo[14:9],foo[ 5], fd); + dude(fd); + $fwrite (fd, " 1090"); end 17'b00_10??_?_????_00_0111 : begin - ozonef1e(foo, fd); - $fwrite (fd, " 1091"); - if (foo[ 6]) - $fwrite (fd, " 1092"); - else - ozonerab({4'b1001, foo[ 8: 6]}, fd); - $fwrite (fd, " 1093"); - $fwrite (fd, " 1094"); - ozonerme(foo[14:12], fd); - case (foo[11: 9]) - 3'h2, - 3'h5, - 3'h6, - 3'h7: - ozonef1e_inc_dec(foo[14:9],1'b0, fd); - 3'h1, - 3'h3, - 3'h4: - $fwrite (fd, " 1095"); - endcase - dude(fd); - $fwrite (fd, " 1096"); + ozonef1e(foo, fd); + $fwrite (fd, " 1091"); + if (foo[ 6]) + $fwrite (fd, " 1092"); + else + ozonerab({4'b1001, foo[ 8: 6]}, fd); + $fwrite (fd, " 1093"); + $fwrite (fd, " 1094"); + ozonerme(foo[14:12], fd); + case (foo[11: 9]) + 3'h2, + 3'h5, + 3'h6, + 3'h7: + ozonef1e_inc_dec(foo[14:9],1'b0, fd); + 3'h1, + 3'h3, + 3'h4: + $fwrite (fd, " 1095"); + endcase + dude(fd); + $fwrite (fd, " 1096"); end 17'b00_10??_?_????_?0_0100 : begin - ozonef1e(foo, fd); - $fwrite (fd, " 1097"); - ozonef1e_ye(foo[14:9],foo[ 5], fd); - $fwrite (fd, " 1098"); - ozoneae(foo[ 8: 6], fd); - ozonef1e_hl(foo[11:9],foo[ 5], fd); - dude(fd); - $fwrite (fd, " 1099"); + ozonef1e(foo, fd); + $fwrite (fd, " 1097"); + ozonef1e_ye(foo[14:9],foo[ 5], fd); + $fwrite (fd, " 1098"); + ozoneae(foo[ 8: 6], fd); + ozonef1e_hl(foo[11:9],foo[ 5], fd); + dude(fd); + $fwrite (fd, " 1099"); end 17'b00_10??_?_????_10_0111 : begin - ozonef1e(foo, fd); - $fwrite (fd, " 1100"); - $fwrite (fd, " 1101"); - ozonerme(foo[14:12], fd); - case (foo[11: 9]) - 3'h2, - 3'h5, - 3'h6, - 3'h7: - ozonef1e_inc_dec(foo[14:9],1'b0, fd); - 3'h1, - 3'h3, - 3'h4: - $fwrite (fd, " 1102"); - endcase - $fwrite (fd, " 1103"); - if (foo[ 6]) - $fwrite (fd, " 1104"); - else - ozonerab({4'b1001, foo[ 8: 6]}, fd); - dude(fd); - $fwrite (fd, " 1105"); + ozonef1e(foo, fd); + $fwrite (fd, " 1100"); + $fwrite (fd, " 1101"); + ozonerme(foo[14:12], fd); + case (foo[11: 9]) + 3'h2, + 3'h5, + 3'h6, + 3'h7: + ozonef1e_inc_dec(foo[14:9],1'b0, fd); + 3'h1, + 3'h3, + 3'h4: + $fwrite (fd, " 1102"); + endcase + $fwrite (fd, " 1103"); + if (foo[ 6]) + $fwrite (fd, " 1104"); + else + ozonerab({4'b1001, foo[ 8: 6]}, fd); + dude(fd); + $fwrite (fd, " 1105"); end 17'b00_10??_?_????_?0_1110 : begin - ozonef1e(foo, fd); - $fwrite (fd, " 1106"); - case (foo[11:9]) - 3'h2: - begin - $fwrite (fd, " 1107"); - if (foo[14:12] == 3'h0) - $fwrite (fd, " 1108"); - else - ozonerme(foo[14:12], fd); - $fwrite (fd, " 1109"); - end - 3'h6: - begin - $fwrite (fd, " 1110"); - if (foo[14:12] == 3'h0) - $fwrite (fd, " 1111"); - else - ozonerme(foo[14:12], fd); - $fwrite (fd, " 1112"); - end - 3'h0: - begin - $fwrite (fd, " 1113"); - if (foo[14:12] == 3'h0) - $fwrite (fd, " 1114"); - else - ozonerme(foo[14:12], fd); - $fwrite (fd, " 1115"); - if (foo[ 7: 5] >= 3'h5) - $fwrite (fd, " 1116"); - else - ozonexe(foo[ 8: 5], fd); - end - 3'h1: - begin - $fwrite (fd, " 1117"); - if (foo[14:12] == 3'h0) - $fwrite (fd, " 1118"); - else - ozonerme(foo[14:12], fd); - $fwrite (fd, " 1119"); - if (foo[ 7: 5] >= 3'h5) - $fwrite (fd, " 1120"); - else - ozonexe(foo[ 8: 5], fd); - end - 3'h4: - begin - $fwrite (fd, " 1121"); - if (foo[14:12] == 3'h0) - $fwrite (fd, " 1122"); - else - ozonerme(foo[14:12], fd); - $fwrite (fd, " 1123"); - if (foo[ 7: 5] >= 3'h5) - $fwrite (fd, " 1124"); - else - ozonexe(foo[ 8: 5], fd); - end - 3'h5: - begin - $fwrite (fd, " 1125"); - if (foo[14:12] == 3'h0) - $fwrite (fd, " 1126"); - else - ozonerme(foo[14:12], fd); - $fwrite (fd, " 1127"); - if (foo[ 7: 5] >= 3'h5) - $fwrite (fd, " 1128"); - else - ozonexe(foo[ 8: 5], fd); - end - endcase - dude(fd); - $fwrite (fd, " 1129"); + ozonef1e(foo, fd); + $fwrite (fd, " 1106"); + case (foo[11:9]) + 3'h2: + begin + $fwrite (fd, " 1107"); + if (foo[14:12] == 3'h0) + $fwrite (fd, " 1108"); + else + ozonerme(foo[14:12], fd); + $fwrite (fd, " 1109"); + end + 3'h6: + begin + $fwrite (fd, " 1110"); + if (foo[14:12] == 3'h0) + $fwrite (fd, " 1111"); + else + ozonerme(foo[14:12], fd); + $fwrite (fd, " 1112"); + end + 3'h0: + begin + $fwrite (fd, " 1113"); + if (foo[14:12] == 3'h0) + $fwrite (fd, " 1114"); + else + ozonerme(foo[14:12], fd); + $fwrite (fd, " 1115"); + if (foo[ 7: 5] >= 3'h5) + $fwrite (fd, " 1116"); + else + ozonexe(foo[ 8: 5], fd); + end + 3'h1: + begin + $fwrite (fd, " 1117"); + if (foo[14:12] == 3'h0) + $fwrite (fd, " 1118"); + else + ozonerme(foo[14:12], fd); + $fwrite (fd, " 1119"); + if (foo[ 7: 5] >= 3'h5) + $fwrite (fd, " 1120"); + else + ozonexe(foo[ 8: 5], fd); + end + 3'h4: + begin + $fwrite (fd, " 1121"); + if (foo[14:12] == 3'h0) + $fwrite (fd, " 1122"); + else + ozonerme(foo[14:12], fd); + $fwrite (fd, " 1123"); + if (foo[ 7: 5] >= 3'h5) + $fwrite (fd, " 1124"); + else + ozonexe(foo[ 8: 5], fd); + end + 3'h5: + begin + $fwrite (fd, " 1125"); + if (foo[14:12] == 3'h0) + $fwrite (fd, " 1126"); + else + ozonerme(foo[14:12], fd); + $fwrite (fd, " 1127"); + if (foo[ 7: 5] >= 3'h5) + $fwrite (fd, " 1128"); + else + ozonexe(foo[ 8: 5], fd); + end + endcase + dude(fd); + $fwrite (fd, " 1129"); end 17'b00_10??_?_????_?0_1111 : casez (foo[14: 9]) - 6'b001_10_?: - begin - ozonef1e(foo, fd); - $fwrite (fd, " 1130"); - $fwrite (fd, " 1131"); - ozonef1e_hl(foo[ 7: 5],foo[ 9], fd); - $fwrite (fd, " 1132"); - ozonexe(foo[ 8: 5], fd); - dude(fd); - $fwrite (fd, " 1133"); - end - 6'b???_11_?: - begin - ozonef1e(foo, fd); - $fwrite (fd, " 1134"); - ozoneae(foo[14:12], fd); - ozonef1e_hl(foo[ 7: 5],foo[ 9], fd); - $fwrite (fd, " 1135"); - ozonexe(foo[ 8: 5], fd); - dude(fd); - $fwrite (fd, " 1136"); - end - 6'b000_10_1, - 6'b010_10_1, - 6'b100_10_1, - 6'b110_10_1: - begin - ozonef1e(foo, fd); - $fwrite (fd, " 1137"); - ozonerab({4'b1001, foo[14:12]}, fd); - $fwrite (fd, " 1138"); - if ((foo[ 7: 5] >= 3'h1) & (foo[ 7: 5] <= 3'h3)) - $fwrite (fd, " 1139"); - else - ozonexe(foo[ 8: 5], fd); - dude(fd); - $fwrite (fd, " 1140"); - end - 6'b000_10_0, - 6'b010_10_0, - 6'b100_10_0, - 6'b110_10_0: - begin - ozonef1e(foo, fd); - $fwrite (fd, " 1141"); - $fwrite (fd, " 1142"); - ozonerab({4'b1001, foo[14:12]}, fd); - $fwrite (fd, " 1143"); - $fwrite (fd, " 1144"); - ozonef1e_h(foo[ 7: 5], fd); - $fwrite (fd, " 1145"); - ozonexe(foo[ 8: 5], fd); - dude(fd); - $fwrite (fd, " 1146"); - end - 6'b???_00_?: - begin - ozonef1e(foo, fd); - $fwrite (fd, " 1147"); - if (foo[ 9]) - begin - $fwrite (fd, " 1148"); - ozoneae(foo[14:12], fd); - end - else - begin - $fwrite (fd, " 1149"); - ozoneae(foo[14:12], fd); - $fwrite (fd, " 1150"); - end - $fwrite (fd, " 1151"); - $fwrite (fd, " 1152"); - ozonef1e_h(foo[ 7: 5], fd); - $fwrite (fd, " 1153"); - ozonexe(foo[ 8: 5], fd); - dude(fd); - $fwrite (fd, " 1154"); - end - 6'b???_01_?: - begin - ozonef1e(foo, fd); - $fwrite (fd, " 1155"); - ozoneae(foo[14:12], fd); - if (foo[ 9]) - $fwrite (fd, " 1156"); - else - $fwrite (fd, " 1157"); - $fwrite (fd, " 1158"); - $fwrite (fd, " 1159"); - ozonef1e_h(foo[ 7: 5], fd); - $fwrite (fd, " 1160"); - ozonexe(foo[ 8: 5], fd); - dude(fd); - $fwrite (fd, " 1161"); - end - 6'b011_10_0: - begin - ozonef1e(foo, fd); - $fwrite (fd, " 1162"); - case (foo[ 8: 5]) - 4'h0: $fwrite (fd, " 1163"); - 4'h1: $fwrite (fd, " 1164"); - 4'h2: $fwrite (fd, " 1165"); - 4'h3: $fwrite (fd, " 1166"); - 4'h4: $fwrite (fd, " 1167"); - 4'h5: $fwrite (fd, " 1168"); - 4'h8: $fwrite (fd, " 1169"); - 4'h9: $fwrite (fd, " 1170"); - 4'ha: $fwrite (fd, " 1171"); - 4'hb: $fwrite (fd, " 1172"); - 4'hc: $fwrite (fd, " 1173"); - 4'hd: $fwrite (fd, " 1174"); - default: $fwrite (fd, " 1175"); - endcase - dude(fd); - $fwrite (fd, " 1176"); - end - default: $fwrite (fd, " 1177"); + 6'b001_10_?: + begin + ozonef1e(foo, fd); + $fwrite (fd, " 1130"); + $fwrite (fd, " 1131"); + ozonef1e_hl(foo[ 7: 5],foo[ 9], fd); + $fwrite (fd, " 1132"); + ozonexe(foo[ 8: 5], fd); + dude(fd); + $fwrite (fd, " 1133"); + end + 6'b???_11_?: + begin + ozonef1e(foo, fd); + $fwrite (fd, " 1134"); + ozoneae(foo[14:12], fd); + ozonef1e_hl(foo[ 7: 5],foo[ 9], fd); + $fwrite (fd, " 1135"); + ozonexe(foo[ 8: 5], fd); + dude(fd); + $fwrite (fd, " 1136"); + end + 6'b000_10_1, + 6'b010_10_1, + 6'b100_10_1, + 6'b110_10_1: + begin + ozonef1e(foo, fd); + $fwrite (fd, " 1137"); + ozonerab({4'b1001, foo[14:12]}, fd); + $fwrite (fd, " 1138"); + if ((foo[ 7: 5] >= 3'h1) & (foo[ 7: 5] <= 3'h3)) + $fwrite (fd, " 1139"); + else + ozonexe(foo[ 8: 5], fd); + dude(fd); + $fwrite (fd, " 1140"); + end + 6'b000_10_0, + 6'b010_10_0, + 6'b100_10_0, + 6'b110_10_0: + begin + ozonef1e(foo, fd); + $fwrite (fd, " 1141"); + $fwrite (fd, " 1142"); + ozonerab({4'b1001, foo[14:12]}, fd); + $fwrite (fd, " 1143"); + $fwrite (fd, " 1144"); + ozonef1e_h(foo[ 7: 5], fd); + $fwrite (fd, " 1145"); + ozonexe(foo[ 8: 5], fd); + dude(fd); + $fwrite (fd, " 1146"); + end + 6'b???_00_?: + begin + ozonef1e(foo, fd); + $fwrite (fd, " 1147"); + if (foo[ 9]) + begin + $fwrite (fd, " 1148"); + ozoneae(foo[14:12], fd); + end + else + begin + $fwrite (fd, " 1149"); + ozoneae(foo[14:12], fd); + $fwrite (fd, " 1150"); + end + $fwrite (fd, " 1151"); + $fwrite (fd, " 1152"); + ozonef1e_h(foo[ 7: 5], fd); + $fwrite (fd, " 1153"); + ozonexe(foo[ 8: 5], fd); + dude(fd); + $fwrite (fd, " 1154"); + end + 6'b???_01_?: + begin + ozonef1e(foo, fd); + $fwrite (fd, " 1155"); + ozoneae(foo[14:12], fd); + if (foo[ 9]) + $fwrite (fd, " 1156"); + else + $fwrite (fd, " 1157"); + $fwrite (fd, " 1158"); + $fwrite (fd, " 1159"); + ozonef1e_h(foo[ 7: 5], fd); + $fwrite (fd, " 1160"); + ozonexe(foo[ 8: 5], fd); + dude(fd); + $fwrite (fd, " 1161"); + end + 6'b011_10_0: + begin + ozonef1e(foo, fd); + $fwrite (fd, " 1162"); + case (foo[ 8: 5]) + 4'h0: $fwrite (fd, " 1163"); + 4'h1: $fwrite (fd, " 1164"); + 4'h2: $fwrite (fd, " 1165"); + 4'h3: $fwrite (fd, " 1166"); + 4'h4: $fwrite (fd, " 1167"); + 4'h5: $fwrite (fd, " 1168"); + 4'h8: $fwrite (fd, " 1169"); + 4'h9: $fwrite (fd, " 1170"); + 4'ha: $fwrite (fd, " 1171"); + 4'hb: $fwrite (fd, " 1172"); + 4'hc: $fwrite (fd, " 1173"); + 4'hd: $fwrite (fd, " 1174"); + default: $fwrite (fd, " 1175"); + endcase + dude(fd); + $fwrite (fd, " 1176"); + end + default: $fwrite (fd, " 1177"); endcase 17'b00_10??_?_????_?0_110? : begin - ozonef1e(foo, fd); - $fwrite (fd, " 1178"); - $fwrite (fd, " 1179"); - ozonef1e_hl(foo[11:9], foo[0], fd); - $fwrite (fd, " 1180"); - ozonef1e_ye(foo[14:9],1'b0, fd); - $fwrite (fd, " 1181"); - ozonef1e_h(foo[ 7: 5], fd); - $fwrite (fd, " 1182"); - ozonexe(foo[ 8: 5], fd); - dude(fd); - $fwrite (fd, " 1183"); + ozonef1e(foo, fd); + $fwrite (fd, " 1178"); + $fwrite (fd, " 1179"); + ozonef1e_hl(foo[11:9], foo[0], fd); + $fwrite (fd, " 1180"); + ozonef1e_ye(foo[14:9],1'b0, fd); + $fwrite (fd, " 1181"); + ozonef1e_h(foo[ 7: 5], fd); + $fwrite (fd, " 1182"); + ozonexe(foo[ 8: 5], fd); + dude(fd); + $fwrite (fd, " 1183"); end 17'b00_10??_?_????_?1_110? : begin - ozonef1e(foo, fd); - $fwrite (fd, " 1184"); - $fwrite (fd, " 1185"); - ozonef1e_hl(foo[11:9],foo[0], fd); - $fwrite (fd, " 1186"); - ozonef1e_ye(foo[14:9],foo[ 0], fd); - $fwrite (fd, " 1187"); - $fwrite (fd, " 1188"); - ozonef1e_h(foo[ 7: 5], fd); - $fwrite (fd, " 1189"); - ozonexe(foo[ 8: 5], fd); - dude(fd); - $fwrite (fd, " 1190"); + ozonef1e(foo, fd); + $fwrite (fd, " 1184"); + $fwrite (fd, " 1185"); + ozonef1e_hl(foo[11:9],foo[0], fd); + $fwrite (fd, " 1186"); + ozonef1e_ye(foo[14:9],foo[ 0], fd); + $fwrite (fd, " 1187"); + $fwrite (fd, " 1188"); + ozonef1e_h(foo[ 7: 5], fd); + $fwrite (fd, " 1189"); + ozonexe(foo[ 8: 5], fd); + dude(fd); + $fwrite (fd, " 1190"); end 17'b00_10??_?_????_?0_101? : begin - ozonef1e(foo, fd); - $fwrite (fd, " 1191"); - ozonef1e_ye(foo[14:9],foo[ 0], fd); - $fwrite (fd, " 1192"); - $fwrite (fd, " 1193"); - ozonef1e_hl(foo[11:9],foo[0], fd); - $fwrite (fd, " 1194"); - $fwrite (fd, " 1195"); - ozonef1e_h(foo[ 7: 5], fd); - $fwrite (fd, " 1196"); - ozonexe(foo[ 8: 5], fd); - dude(fd); - $fwrite (fd, " 1197"); + ozonef1e(foo, fd); + $fwrite (fd, " 1191"); + ozonef1e_ye(foo[14:9],foo[ 0], fd); + $fwrite (fd, " 1192"); + $fwrite (fd, " 1193"); + ozonef1e_hl(foo[11:9],foo[0], fd); + $fwrite (fd, " 1194"); + $fwrite (fd, " 1195"); + ozonef1e_h(foo[ 7: 5], fd); + $fwrite (fd, " 1196"); + ozonexe(foo[ 8: 5], fd); + dude(fd); + $fwrite (fd, " 1197"); end 17'b00_10??_?_????_?0_1001 : begin - ozonef1e(foo, fd); - $fwrite (fd, " 1198"); - $fwrite (fd, " 1199"); - ozonef1e_h(foo[11:9], fd); - $fwrite (fd, " 1200"); - ozonef1e_ye(foo[14:9],1'b0, fd); - $fwrite (fd, " 1201"); - case (foo[ 7: 5]) - 3'h1, - 3'h2, - 3'h3: - $fwrite (fd, " 1202"); - default: - begin - $fwrite (fd, " 1203"); - $fwrite (fd, " 1204"); - ozonexe(foo[ 8: 5], fd); - end - endcase - dude(fd); - $fwrite (fd, " 1205"); + ozonef1e(foo, fd); + $fwrite (fd, " 1198"); + $fwrite (fd, " 1199"); + ozonef1e_h(foo[11:9], fd); + $fwrite (fd, " 1200"); + ozonef1e_ye(foo[14:9],1'b0, fd); + $fwrite (fd, " 1201"); + case (foo[ 7: 5]) + 3'h1, + 3'h2, + 3'h3: + $fwrite (fd, " 1202"); + default: + begin + $fwrite (fd, " 1203"); + $fwrite (fd, " 1204"); + ozonexe(foo[ 8: 5], fd); + end + endcase + dude(fd); + $fwrite (fd, " 1205"); end 17'b00_10??_?_????_?0_0101 : begin - ozonef1e(foo, fd); - $fwrite (fd, " 1206"); - case (foo[11: 9]) - 3'h1, - 3'h3, - 3'h4: - $fwrite (fd, " 1207"); - default: - begin - ozonef1e_ye(foo[14:9],1'b0, fd); - $fwrite (fd, " 1208"); - $fwrite (fd, " 1209"); - end - endcase - $fwrite (fd, " 1210"); - $fwrite (fd, " 1211"); - ozonef1e_h(foo[ 7: 5], fd); - $fwrite (fd, " 1212"); - ozonexe(foo[ 8: 5], fd); - dude(fd); - $fwrite (fd, " 1213"); + ozonef1e(foo, fd); + $fwrite (fd, " 1206"); + case (foo[11: 9]) + 3'h1, + 3'h3, + 3'h4: + $fwrite (fd, " 1207"); + default: + begin + ozonef1e_ye(foo[14:9],1'b0, fd); + $fwrite (fd, " 1208"); + $fwrite (fd, " 1209"); + end + endcase + $fwrite (fd, " 1210"); + $fwrite (fd, " 1211"); + ozonef1e_h(foo[ 7: 5], fd); + $fwrite (fd, " 1212"); + ozonexe(foo[ 8: 5], fd); + dude(fd); + $fwrite (fd, " 1213"); end 17'b00_10??_?_????_?1_1110 : begin - ozonef1e(foo, fd); - $fwrite (fd, " 1214"); - ozonef1e_ye(foo[14:9],1'b0, fd); - $fwrite (fd, " 1215"); - $fwrite (fd, " 1216"); - ozonef1e_h(foo[11: 9], fd); - $fwrite (fd, " 1217"); - $fwrite (fd, " 1218"); - ozonef1e_h(foo[ 7: 5], fd); - $fwrite (fd, " 1219"); - ozonexe(foo[ 8: 5], fd); - dude(fd); - $fwrite (fd, " 1220"); + ozonef1e(foo, fd); + $fwrite (fd, " 1214"); + ozonef1e_ye(foo[14:9],1'b0, fd); + $fwrite (fd, " 1215"); + $fwrite (fd, " 1216"); + ozonef1e_h(foo[11: 9], fd); + $fwrite (fd, " 1217"); + $fwrite (fd, " 1218"); + ozonef1e_h(foo[ 7: 5], fd); + $fwrite (fd, " 1219"); + ozonexe(foo[ 8: 5], fd); + dude(fd); + $fwrite (fd, " 1220"); end 17'b00_10??_?_????_?0_1000 : begin - ozonef1e(foo, fd); - $fwrite (fd, " 1221"); - ozonef1e_ye(foo[14:9],1'b0, fd); - $fwrite (fd, " 1222"); - $fwrite (fd, " 1223"); - ozonef1e_h(foo[11: 9], fd); - $fwrite (fd, " 1224"); - $fwrite (fd, " 1225"); - ozonef1e_h(foo[ 7: 5], fd); - $fwrite (fd, " 1226"); - ozonexe(foo[ 8: 5], fd); - dude(fd); - $fwrite (fd, " 1227"); + ozonef1e(foo, fd); + $fwrite (fd, " 1221"); + ozonef1e_ye(foo[14:9],1'b0, fd); + $fwrite (fd, " 1222"); + $fwrite (fd, " 1223"); + ozonef1e_h(foo[11: 9], fd); + $fwrite (fd, " 1224"); + $fwrite (fd, " 1225"); + ozonef1e_h(foo[ 7: 5], fd); + $fwrite (fd, " 1226"); + ozonexe(foo[ 8: 5], fd); + dude(fd); + $fwrite (fd, " 1227"); end 17'b10_01??_?_????_??_???? : begin - if (foo[27]) - $fwrite (fd," 1228"); - else - $fwrite (fd," 1229"); - ozonecon(foo[20:16], fd); - $fwrite (fd, " 1230"); - ozonef2(foo[31:0], fd); - dude(fd); - $fwrite (fd, " 1231"); + if (foo[27]) + $fwrite (fd," 1228"); + else + $fwrite (fd," 1229"); + ozonecon(foo[20:16], fd); + $fwrite (fd, " 1230"); + ozonef2(foo[31:0], fd); + dude(fd); + $fwrite (fd, " 1231"); end 17'b00_1000_?_????_01_0011 : if (~|foo[ 9: 8]) - begin - if (foo[ 7]) - $fwrite (fd," 1232"); - else - $fwrite (fd," 1233"); - ozonecon(foo[14:10], fd); - $fwrite (fd, " 1234"); - ozonef2e(foo[31:0], fd); - dude(fd); - $fwrite (fd, " 1235"); - end + begin + if (foo[ 7]) + $fwrite (fd," 1232"); + else + $fwrite (fd," 1233"); + ozonecon(foo[14:10], fd); + $fwrite (fd, " 1234"); + ozonef2e(foo[31:0], fd); + dude(fd); + $fwrite (fd, " 1235"); + end else - begin - $fwrite (fd, " 1236"); - ozonecon(foo[14:10], fd); - $fwrite (fd, " 1237"); - ozonef3e(foo[31:0], fd); - dude(fd); - $fwrite (fd, " 1238"); - end + begin + $fwrite (fd, " 1236"); + ozonecon(foo[14:10], fd); + $fwrite (fd, " 1237"); + ozonef3e(foo[31:0], fd); + dude(fd); + $fwrite (fd, " 1238"); + end 17'b11_110?_1_????_??_???? : begin - ozonef3(foo[31:0], fd); - dude(fd); - $fwrite(fd, " 1239"); + ozonef3(foo[31:0], fd); + dude(fd); + $fwrite(fd, " 1239"); end 17'b11_110?_0_????_??_???? : begin : f4_body - casez (foo[24:20]) - 5'b0_1110, - 5'b1_0???, - 5'b1_1111: - begin - $fwrite (fd, " 1240"); - end - 5'b0_00??: - begin - ozoneacc(foo[26], fd); - $fwrite (fd, " 1241"); - ozoneacc(foo[25], fd); - ozonebmuop(foo[24:20], fd); - ozoneae(foo[18:16], fd); - $fwrite (fd, " 1242"); - dude(fd); - $fwrite(fd, " 1243"); - end - 5'b0_01??: - begin - ozoneacc(foo[26], fd); - $fwrite (fd, " 1244"); - ozoneacc(foo[25], fd); - ozonebmuop(foo[24:20], fd); - ozonearm(foo[18:16], fd); - dude(fd); - $fwrite(fd, " 1245"); - end - 5'b0_1011: - begin - ozoneacc(foo[26], fd); - $fwrite (fd, " 1246"); - ozonebmuop(foo[24:20], fd); - $fwrite (fd, " 1247"); - ozoneae(foo[18:16], fd); - $fwrite (fd, " 1248"); - dude(fd); - $fwrite(fd, " 1249"); - end - 5'b0_100?, - 5'b0_1010, - 5'b0_110? : - begin - ozoneacc(foo[26], fd); - $fwrite (fd, " 1250"); - ozonebmuop(foo[24:20], fd); - $fwrite (fd, " 1251"); - ozoneacc(foo[25], fd); - $fwrite (fd, " 1252"); - ozoneae(foo[18:16], fd); - $fwrite (fd, " 1253"); - dude(fd); - $fwrite(fd, " 1254"); - end - 5'b0_1111 : - begin - ozoneacc(foo[26], fd); - $fwrite (fd, " 1255"); - ozoneacc(foo[25], fd); - $fwrite (fd, " 1256"); - ozoneae(foo[18:16], fd); - dude(fd); - $fwrite(fd, " 1257"); - end - 5'b1_10??, - 5'b1_110?, - 5'b1_1110 : - begin - ozoneacc(foo[26], fd); - $fwrite (fd, " 1258"); - ozonebmuop(foo[24:20], fd); - $fwrite (fd, " 1259"); - ozoneacc(foo[25], fd); - $fwrite (fd, " 1260"); - ozonearm(foo[18:16], fd); - $fwrite (fd, " 1261"); - dude(fd); - $fwrite(fd, " 1262"); - end - endcase + casez (foo[24:20]) + 5'b0_1110, + 5'b1_0???, + 5'b1_1111: + begin + $fwrite (fd, " 1240"); + end + 5'b0_00??: + begin + ozoneacc(foo[26], fd); + $fwrite (fd, " 1241"); + ozoneacc(foo[25], fd); + ozonebmuop(foo[24:20], fd); + ozoneae(foo[18:16], fd); + $fwrite (fd, " 1242"); + dude(fd); + $fwrite(fd, " 1243"); + end + 5'b0_01??: + begin + ozoneacc(foo[26], fd); + $fwrite (fd, " 1244"); + ozoneacc(foo[25], fd); + ozonebmuop(foo[24:20], fd); + ozonearm(foo[18:16], fd); + dude(fd); + $fwrite(fd, " 1245"); + end + 5'b0_1011: + begin + ozoneacc(foo[26], fd); + $fwrite (fd, " 1246"); + ozonebmuop(foo[24:20], fd); + $fwrite (fd, " 1247"); + ozoneae(foo[18:16], fd); + $fwrite (fd, " 1248"); + dude(fd); + $fwrite(fd, " 1249"); + end + 5'b0_100?, + 5'b0_1010, + 5'b0_110? : + begin + ozoneacc(foo[26], fd); + $fwrite (fd, " 1250"); + ozonebmuop(foo[24:20], fd); + $fwrite (fd, " 1251"); + ozoneacc(foo[25], fd); + $fwrite (fd, " 1252"); + ozoneae(foo[18:16], fd); + $fwrite (fd, " 1253"); + dude(fd); + $fwrite(fd, " 1254"); + end + 5'b0_1111 : + begin + ozoneacc(foo[26], fd); + $fwrite (fd, " 1255"); + ozoneacc(foo[25], fd); + $fwrite (fd, " 1256"); + ozoneae(foo[18:16], fd); + dude(fd); + $fwrite(fd, " 1257"); + end + 5'b1_10??, + 5'b1_110?, + 5'b1_1110 : + begin + ozoneacc(foo[26], fd); + $fwrite (fd, " 1258"); + ozonebmuop(foo[24:20], fd); + $fwrite (fd, " 1259"); + ozoneacc(foo[25], fd); + $fwrite (fd, " 1260"); + ozonearm(foo[18:16], fd); + $fwrite (fd, " 1261"); + dude(fd); + $fwrite(fd, " 1262"); + end + endcase end 17'b11_100?_?_????_??_???? : casez (foo[23:19]) - 5'b111??, - 5'b0111?: - begin - ozoneae(foo[26:24], fd); - $fwrite (fd, " 1263"); - ozonef3f4imop(foo[23:19], fd); - $fwrite (fd, " 1264"); - ozoneae(foo[18:16], fd); - $fwrite (fd, " 1265"); - skyway(foo[15:12], fd); - skyway(foo[11: 8], fd); - skyway(foo[ 7: 4], fd); - skyway(foo[ 3:0], fd); - $fwrite (fd, " 1266"); - dude(fd); - $fwrite(fd, " 1267"); - end - 5'b?0???, - 5'b110??: - begin - ozoneae(foo[26:24], fd); - $fwrite (fd, " 1268"); - if (foo[23:21] == 3'b100) - $fwrite (fd, " 1269"); - ozoneae(foo[18:16], fd); - if (foo[19]) - $fwrite (fd, " 1270"); - else - $fwrite (fd, " 1271"); - ozonef3f4imop(foo[23:19], fd); - $fwrite (fd, " 1272"); - ozonef3f4_iext(foo[20:19], foo[15:0], fd); - dude(fd); - $fwrite(fd, " 1273"); - end - 5'b010??, - 5'b0110?: - begin - ozoneae(foo[18:16], fd); - if (foo[19]) - $fwrite (fd, " 1274"); - else - $fwrite (fd, " 1275"); - ozonef3f4imop(foo[23:19], fd); - $fwrite (fd, " 1276"); - ozonef3f4_iext(foo[20:19], foo[15:0], fd); - dude(fd); - $fwrite(fd, " 1277"); - end + 5'b111??, + 5'b0111?: + begin + ozoneae(foo[26:24], fd); + $fwrite (fd, " 1263"); + ozonef3f4imop(foo[23:19], fd); + $fwrite (fd, " 1264"); + ozoneae(foo[18:16], fd); + $fwrite (fd, " 1265"); + skyway(foo[15:12], fd); + skyway(foo[11: 8], fd); + skyway(foo[ 7: 4], fd); + skyway(foo[ 3:0], fd); + $fwrite (fd, " 1266"); + dude(fd); + $fwrite(fd, " 1267"); + end + 5'b?0???, + 5'b110??: + begin + ozoneae(foo[26:24], fd); + $fwrite (fd, " 1268"); + if (foo[23:21] == 3'b100) + $fwrite (fd, " 1269"); + ozoneae(foo[18:16], fd); + if (foo[19]) + $fwrite (fd, " 1270"); + else + $fwrite (fd, " 1271"); + ozonef3f4imop(foo[23:19], fd); + $fwrite (fd, " 1272"); + ozonef3f4_iext(foo[20:19], foo[15:0], fd); + dude(fd); + $fwrite(fd, " 1273"); + end + 5'b010??, + 5'b0110?: + begin + ozoneae(foo[18:16], fd); + if (foo[19]) + $fwrite (fd, " 1274"); + else + $fwrite (fd, " 1275"); + ozonef3f4imop(foo[23:19], fd); + $fwrite (fd, " 1276"); + ozonef3f4_iext(foo[20:19], foo[15:0], fd); + dude(fd); + $fwrite(fd, " 1277"); + end endcase 17'b00_1000_?_????_11_0011 : begin - $fwrite (fd," 1278"); - ozonecon(foo[14:10], fd); - $fwrite (fd, " 1279"); - casez (foo[25:21]) - 5'b0_1110, - 5'b1_0???, - 5'b1_1111: - begin - $fwrite(fd, " 1280"); - end - 5'b0_00??: - begin - ozoneae(foo[20:18], fd); - $fwrite (fd, " 1281"); - ozoneae(foo[17:15], fd); - ozonebmuop(foo[25:21], fd); - ozoneae(foo[ 8: 6], fd); - $fwrite (fd, " 1282"); - dude(fd); - $fwrite(fd, " 1283"); - end - 5'b0_01??: - begin - ozoneae(foo[20:18], fd); - $fwrite (fd, " 1284"); - ozoneae(foo[17:15], fd); - ozonebmuop(foo[25:21], fd); - ozonearm(foo[ 8: 6], fd); - dude(fd); - $fwrite(fd, " 1285"); - end - 5'b0_1011: - begin - ozoneae(foo[20:18], fd); - $fwrite (fd, " 1286"); - ozonebmuop(foo[25:21], fd); - $fwrite (fd, " 1287"); - ozoneae(foo[ 8: 6], fd); - $fwrite (fd, " 1288"); - dude(fd); - $fwrite(fd, " 1289"); - end - 5'b0_100?, - 5'b0_1010, - 5'b0_110? : - begin - ozoneae(foo[20:18], fd); - $fwrite (fd, " 1290"); - ozonebmuop(foo[25:21], fd); - $fwrite (fd, " 1291"); - ozoneae(foo[17:15], fd); - $fwrite (fd, " 1292"); - ozoneae(foo[ 8: 6], fd); - $fwrite (fd, " 1293"); - dude(fd); - $fwrite(fd, " 1294"); - end - 5'b0_1111 : - begin - ozoneae(foo[20:18], fd); - $fwrite (fd, " 1295"); - ozoneae(foo[17:15], fd); - $fwrite (fd, " 1296"); - ozoneae(foo[ 8: 6], fd); - dude(fd); - $fwrite(fd, " 1297"); - end - 5'b1_10??, - 5'b1_110?, - 5'b1_1110 : - begin - ozoneae(foo[20:18], fd); - $fwrite (fd, " 1298"); - ozonebmuop(foo[25:21], fd); - $fwrite (fd, " 1299"); - ozoneae(foo[17:15], fd); - $fwrite (fd, " 1300"); - ozonearm(foo[ 8: 6], fd); - $fwrite (fd, " 1301"); - dude(fd); - $fwrite(fd, " 1302"); - end - endcase + $fwrite (fd," 1278"); + ozonecon(foo[14:10], fd); + $fwrite (fd, " 1279"); + casez (foo[25:21]) + 5'b0_1110, + 5'b1_0???, + 5'b1_1111: + begin + $fwrite(fd, " 1280"); + end + 5'b0_00??: + begin + ozoneae(foo[20:18], fd); + $fwrite (fd, " 1281"); + ozoneae(foo[17:15], fd); + ozonebmuop(foo[25:21], fd); + ozoneae(foo[ 8: 6], fd); + $fwrite (fd, " 1282"); + dude(fd); + $fwrite(fd, " 1283"); + end + 5'b0_01??: + begin + ozoneae(foo[20:18], fd); + $fwrite (fd, " 1284"); + ozoneae(foo[17:15], fd); + ozonebmuop(foo[25:21], fd); + ozonearm(foo[ 8: 6], fd); + dude(fd); + $fwrite(fd, " 1285"); + end + 5'b0_1011: + begin + ozoneae(foo[20:18], fd); + $fwrite (fd, " 1286"); + ozonebmuop(foo[25:21], fd); + $fwrite (fd, " 1287"); + ozoneae(foo[ 8: 6], fd); + $fwrite (fd, " 1288"); + dude(fd); + $fwrite(fd, " 1289"); + end + 5'b0_100?, + 5'b0_1010, + 5'b0_110? : + begin + ozoneae(foo[20:18], fd); + $fwrite (fd, " 1290"); + ozonebmuop(foo[25:21], fd); + $fwrite (fd, " 1291"); + ozoneae(foo[17:15], fd); + $fwrite (fd, " 1292"); + ozoneae(foo[ 8: 6], fd); + $fwrite (fd, " 1293"); + dude(fd); + $fwrite(fd, " 1294"); + end + 5'b0_1111 : + begin + ozoneae(foo[20:18], fd); + $fwrite (fd, " 1295"); + ozoneae(foo[17:15], fd); + $fwrite (fd, " 1296"); + ozoneae(foo[ 8: 6], fd); + dude(fd); + $fwrite(fd, " 1297"); + end + 5'b1_10??, + 5'b1_110?, + 5'b1_1110 : + begin + ozoneae(foo[20:18], fd); + $fwrite (fd, " 1298"); + ozonebmuop(foo[25:21], fd); + $fwrite (fd, " 1299"); + ozoneae(foo[17:15], fd); + $fwrite (fd, " 1300"); + ozonearm(foo[ 8: 6], fd); + $fwrite (fd, " 1301"); + dude(fd); + $fwrite(fd, " 1302"); + end + endcase end 17'b00_0010_?_????_??_???? : begin - ozonerab({1'b0, foo[25:20]}, fd); - $fwrite (fd, " 1303"); - skyway(foo[19:16], fd); - dude(fd); - $fwrite(fd, " 1304"); + ozonerab({1'b0, foo[25:20]}, fd); + $fwrite (fd, " 1303"); + skyway(foo[19:16], fd); + dude(fd); + $fwrite(fd, " 1304"); end 17'b00_01??_?_????_??_???? : begin - if (foo[27]) - begin - $fwrite (fd, " 1305"); - if (foo[26]) - $fwrite (fd, " 1306"); - else - $fwrite (fd, " 1307"); - skyway(foo[19:16], fd); - $fwrite (fd, " 1308"); - ozonerab({1'b0, foo[25:20]}, fd); - end - else - begin - ozonerab({1'b0, foo[25:20]}, fd); - $fwrite (fd, " 1309"); - if (foo[26]) - $fwrite (fd, " 1310"); - else - $fwrite (fd, " 1311"); - skyway(foo[19:16], fd); - $fwrite (fd, " 1312"); - end - dude(fd); - $fwrite(fd, " 1313"); + if (foo[27]) + begin + $fwrite (fd, " 1305"); + if (foo[26]) + $fwrite (fd, " 1306"); + else + $fwrite (fd, " 1307"); + skyway(foo[19:16], fd); + $fwrite (fd, " 1308"); + ozonerab({1'b0, foo[25:20]}, fd); + end + else + begin + ozonerab({1'b0, foo[25:20]}, fd); + $fwrite (fd, " 1309"); + if (foo[26]) + $fwrite (fd, " 1310"); + else + $fwrite (fd, " 1311"); + skyway(foo[19:16], fd); + $fwrite (fd, " 1312"); + end + dude(fd); + $fwrite(fd, " 1313"); end 17'b01_000?_?_????_??_???? : begin - if (foo[26]) - begin - ozonerb(foo[25:20], fd); - $fwrite (fd, " 1314"); - ozoneae(foo[18:16], fd); - ozonehl(foo[19], fd); - end - else - begin - ozoneae(foo[18:16], fd); - ozonehl(foo[19], fd); - $fwrite (fd, " 1315"); - ozonerb(foo[25:20], fd); - end - dude(fd); - $fwrite(fd, " 1316"); + if (foo[26]) + begin + ozonerb(foo[25:20], fd); + $fwrite (fd, " 1314"); + ozoneae(foo[18:16], fd); + ozonehl(foo[19], fd); + end + else + begin + ozoneae(foo[18:16], fd); + ozonehl(foo[19], fd); + $fwrite (fd, " 1315"); + ozonerb(foo[25:20], fd); + end + dude(fd); + $fwrite(fd, " 1316"); end 17'b01_10??_?_????_??_???? : begin - if (foo[27]) - begin - ozonerab({1'b0, foo[25:20]}, fd); - $fwrite (fd, " 1317"); - ozonerx(foo, fd); - end - else - begin - ozonerx(foo, fd); - $fwrite (fd, " 1318"); - ozonerab({1'b0, foo[25:20]}, fd); - end - dude(fd); - $fwrite(fd, " 1319"); + if (foo[27]) + begin + ozonerab({1'b0, foo[25:20]}, fd); + $fwrite (fd, " 1317"); + ozonerx(foo, fd); + end + else + begin + ozonerx(foo, fd); + $fwrite (fd, " 1318"); + ozonerab({1'b0, foo[25:20]}, fd); + end + dude(fd); + $fwrite(fd, " 1319"); end 17'b11_101?_?_????_??_???? : begin - ozonerab (foo[26:20], fd); - $fwrite (fd, " 1320"); - skyway(foo[19:16], fd); - skyway(foo[15:12], fd); - skyway(foo[11: 8], fd); - skyway(foo[ 7: 4], fd); - skyway(foo[ 3: 0], fd); - dude(fd); - $fwrite(fd, " 1321"); + ozonerab (foo[26:20], fd); + $fwrite (fd, " 1320"); + skyway(foo[19:16], fd); + skyway(foo[15:12], fd); + skyway(foo[11: 8], fd); + skyway(foo[ 7: 4], fd); + skyway(foo[ 3: 0], fd); + dude(fd); + $fwrite(fd, " 1321"); end 17'b11_0000_?_????_??_???? : begin - casez (foo[25:23]) - 3'b00?: - begin - ozonerab(foo[22:16], fd); - $fwrite (fd, " 1322"); - end - 3'b01?: - begin - $fwrite (fd, " 1323"); - if (foo[22:16]>=7'h60) - $fwrite (fd, " 1324"); - else - ozonerab(foo[22:16], fd); - end - 3'b110: - $fwrite (fd, " 1325"); - 3'b10?: - begin - $fwrite (fd, " 1326"); - if (foo[22:16]>=7'h60) - $fwrite (fd, " 1327"); - else - ozonerab(foo[22:16], fd); - end - 3'b111: - begin - $fwrite (fd, " 1328"); - ozonerab(foo[22:16], fd); - $fwrite (fd, " 1329"); - end - endcase - dude(fd); - $fwrite(fd, " 1330"); + casez (foo[25:23]) + 3'b00?: + begin + ozonerab(foo[22:16], fd); + $fwrite (fd, " 1322"); + end + 3'b01?: + begin + $fwrite (fd, " 1323"); + if (foo[22:16]>=7'h60) + $fwrite (fd, " 1324"); + else + ozonerab(foo[22:16], fd); + end + 3'b110: + $fwrite (fd, " 1325"); + 3'b10?: + begin + $fwrite (fd, " 1326"); + if (foo[22:16]>=7'h60) + $fwrite (fd, " 1327"); + else + ozonerab(foo[22:16], fd); + end + 3'b111: + begin + $fwrite (fd, " 1328"); + ozonerab(foo[22:16], fd); + $fwrite (fd, " 1329"); + end + endcase + dude(fd); + $fwrite(fd, " 1330"); end 17'b00_10??_?_????_?1_0000 : begin - if (foo[27]) - begin - $fwrite (fd, " 1331"); - ozonerp(foo[14:12], fd); - $fwrite (fd, " 1332"); - skyway(foo[19:16], fd); - skyway({foo[15],foo[11: 9]}, fd); - skyway(foo[ 8: 5], fd); - $fwrite (fd, " 1333"); - if (foo[26:20]>=7'h60) - $fwrite (fd, " 1334"); - else - ozonerab(foo[26:20], fd); - end - else - begin - ozonerab(foo[26:20], fd); - $fwrite (fd, " 1335"); - $fwrite (fd, " 1336"); - ozonerp(foo[14:12], fd); - $fwrite (fd, " 1337"); - skyway(foo[19:16], fd); - skyway({foo[15],foo[11: 9]}, fd); - skyway(foo[ 8: 5], fd); - $fwrite (fd, " 1338"); - end - dude(fd); - $fwrite(fd, " 1339"); + if (foo[27]) + begin + $fwrite (fd, " 1331"); + ozonerp(foo[14:12], fd); + $fwrite (fd, " 1332"); + skyway(foo[19:16], fd); + skyway({foo[15],foo[11: 9]}, fd); + skyway(foo[ 8: 5], fd); + $fwrite (fd, " 1333"); + if (foo[26:20]>=7'h60) + $fwrite (fd, " 1334"); + else + ozonerab(foo[26:20], fd); + end + else + begin + ozonerab(foo[26:20], fd); + $fwrite (fd, " 1335"); + $fwrite (fd, " 1336"); + ozonerp(foo[14:12], fd); + $fwrite (fd, " 1337"); + skyway(foo[19:16], fd); + skyway({foo[15],foo[11: 9]}, fd); + skyway(foo[ 8: 5], fd); + $fwrite (fd, " 1338"); + end + dude(fd); + $fwrite(fd, " 1339"); end 17'b00_101?_1_0000_?1_0010 : if (~|foo[11: 7]) - begin - if (foo[ 6]) - begin - $fwrite (fd, " 1340"); - ozonerp(foo[14:12], fd); - $fwrite (fd, " 1341"); - ozonejk(foo[ 5], fd); - $fwrite (fd, " 1342"); - if (foo[26:20]>=7'h60) - $fwrite (fd, " 1343"); - else - ozonerab(foo[26:20], fd); - end - else - begin - ozonerab(foo[26:20], fd); - $fwrite (fd, " 1344"); - $fwrite (fd, " 1345"); - ozonerp(foo[14:12], fd); - $fwrite (fd, " 1346"); - ozonejk(foo[ 5], fd); - $fwrite (fd, " 1347"); - end - dude(fd); - $fwrite(fd, " 1348"); - end + begin + if (foo[ 6]) + begin + $fwrite (fd, " 1340"); + ozonerp(foo[14:12], fd); + $fwrite (fd, " 1341"); + ozonejk(foo[ 5], fd); + $fwrite (fd, " 1342"); + if (foo[26:20]>=7'h60) + $fwrite (fd, " 1343"); + else + ozonerab(foo[26:20], fd); + end + else + begin + ozonerab(foo[26:20], fd); + $fwrite (fd, " 1344"); + $fwrite (fd, " 1345"); + ozonerp(foo[14:12], fd); + $fwrite (fd, " 1346"); + ozonejk(foo[ 5], fd); + $fwrite (fd, " 1347"); + end + dude(fd); + $fwrite(fd, " 1348"); + end else - $fwrite(fd, " 1349"); + $fwrite(fd, " 1349"); 17'b00_100?_0_0011_?1_0101 : if (~|foo[ 8: 7]) - begin - if (foo[6]) - begin - ozonerab(foo[26:20], fd); - $fwrite (fd, " 1350"); - ozoneye(foo[14: 9],foo[ 5], fd); - end - else - begin - ozoneye(foo[14: 9],foo[ 5], fd); - $fwrite (fd, " 1351"); - if (foo[26:20]>=7'h60) - $fwrite (fd, " 1352"); - else - ozonerab(foo[26:20], fd); - end - dude(fd); - $fwrite(fd, " 1353"); - end + begin + if (foo[6]) + begin + ozonerab(foo[26:20], fd); + $fwrite (fd, " 1350"); + ozoneye(foo[14: 9],foo[ 5], fd); + end + else + begin + ozoneye(foo[14: 9],foo[ 5], fd); + $fwrite (fd, " 1351"); + if (foo[26:20]>=7'h60) + $fwrite (fd, " 1352"); + else + ozonerab(foo[26:20], fd); + end + dude(fd); + $fwrite(fd, " 1353"); + end else - $fwrite(fd, " 1354"); + $fwrite(fd, " 1354"); 17'b00_1001_0_0000_?1_0010 : if (~|foo[25:20]) - begin - ozoneye(foo[14: 9],1'b0, fd); - $fwrite (fd, " 1355"); - ozonef1e_h(foo[11: 9], fd); - $fwrite (fd, " 1356"); - ozonef1e_h(foo[ 7: 5], fd); - $fwrite (fd, " 1357"); - ozonexe(foo[ 8: 5], fd); - dude(fd); - $fwrite(fd, " 1358"); - end + begin + ozoneye(foo[14: 9],1'b0, fd); + $fwrite (fd, " 1355"); + ozonef1e_h(foo[11: 9], fd); + $fwrite (fd, " 1356"); + ozonef1e_h(foo[ 7: 5], fd); + $fwrite (fd, " 1357"); + ozonexe(foo[ 8: 5], fd); + dude(fd); + $fwrite(fd, " 1358"); + end else - $fwrite(fd, " 1359"); + $fwrite(fd, " 1359"); 17'b00_101?_0_????_?1_0010 : if (~foo[13]) - begin - if (foo[12]) - begin - $fwrite (fd, " 1360"); - if (foo[26:20]>=7'h60) - $fwrite (fd, " 1361"); - else - ozonerab(foo[26:20], fd); - $fwrite (fd, " 1362"); - $fwrite (fd, " 1363"); - skyway({1'b0,foo[18:16]}, fd); - skyway({foo[15],foo[11: 9]}, fd); - skyway(foo[ 8: 5], fd); - dude(fd); - $fwrite(fd, " 1364"); - end - else - begin - ozonerab(foo[26:20], fd); - $fwrite (fd, " 1365"); - $fwrite (fd, " 1366"); - skyway({1'b0,foo[18:16]}, fd); - skyway({foo[15],foo[11: 9]}, fd); - skyway(foo[ 8: 5], fd); - dude(fd); - $fwrite(fd, " 1367"); - end - end + begin + if (foo[12]) + begin + $fwrite (fd, " 1360"); + if (foo[26:20]>=7'h60) + $fwrite (fd, " 1361"); + else + ozonerab(foo[26:20], fd); + $fwrite (fd, " 1362"); + $fwrite (fd, " 1363"); + skyway({1'b0,foo[18:16]}, fd); + skyway({foo[15],foo[11: 9]}, fd); + skyway(foo[ 8: 5], fd); + dude(fd); + $fwrite(fd, " 1364"); + end + else + begin + ozonerab(foo[26:20], fd); + $fwrite (fd, " 1365"); + $fwrite (fd, " 1366"); + skyway({1'b0,foo[18:16]}, fd); + skyway({foo[15],foo[11: 9]}, fd); + skyway(foo[ 8: 5], fd); + dude(fd); + $fwrite(fd, " 1367"); + end + end else - $fwrite(fd, " 1368"); + $fwrite(fd, " 1368"); 17'b01_01??_?_????_??_???? : begin - ozonerab({1'b0,foo[27:26],foo[19:16]}, fd); - $fwrite (fd, " 1369"); - ozonerab({1'b0,foo[25:20]}, fd); - dude(fd); - $fwrite(fd, " 1370"); + ozonerab({1'b0,foo[27:26],foo[19:16]}, fd); + $fwrite (fd, " 1369"); + ozonerab({1'b0,foo[25:20]}, fd); + dude(fd); + $fwrite(fd, " 1370"); end 17'b00_100?_?_???0_11_0101 : if (~foo[6]) - begin - $fwrite (fd," 1371"); - ozonecon(foo[14:10], fd); - $fwrite (fd, " 1372"); - ozonerab({foo[ 9: 7],foo[19:16]}, fd); - $fwrite (fd, " 1373"); - ozonerab({foo[26:20]}, fd); - dude(fd); - $fwrite(fd, " 1374"); - end + begin + $fwrite (fd," 1371"); + ozonecon(foo[14:10], fd); + $fwrite (fd, " 1372"); + ozonerab({foo[ 9: 7],foo[19:16]}, fd); + $fwrite (fd, " 1373"); + ozonerab({foo[26:20]}, fd); + dude(fd); + $fwrite(fd, " 1374"); + end else - $fwrite(fd, " 1375"); + $fwrite(fd, " 1375"); 17'b00_1000_?_????_?1_0010 : if (~|foo[25:24]) - begin - ozonery(foo[23:20], fd); - $fwrite (fd, " 1376"); - ozonerp(foo[14:12], fd); - $fwrite (fd, " 1377"); - skyway(foo[19:16], fd); - skyway({foo[15],foo[11: 9]}, fd); - skyway(foo[ 8: 5], fd); - dude(fd); - $fwrite(fd, " 1378"); - end + begin + ozonery(foo[23:20], fd); + $fwrite (fd, " 1376"); + ozonerp(foo[14:12], fd); + $fwrite (fd, " 1377"); + skyway(foo[19:16], fd); + skyway({foo[15],foo[11: 9]}, fd); + skyway(foo[ 8: 5], fd); + dude(fd); + $fwrite(fd, " 1378"); + end else if ((foo[25:24] == 2'b10) & ~|foo[19:15] & ~|foo[11: 6]) - begin - ozonery(foo[23:20], fd); - $fwrite (fd, " 1379"); - ozonerp(foo[14:12], fd); - $fwrite (fd, " 1380"); - ozonejk(foo[ 5], fd); - dude(fd); - $fwrite(fd, " 1381"); - end + begin + ozonery(foo[23:20], fd); + $fwrite (fd, " 1379"); + ozonerp(foo[14:12], fd); + $fwrite (fd, " 1380"); + ozonejk(foo[ 5], fd); + dude(fd); + $fwrite(fd, " 1381"); + end else - $fwrite(fd, " 1382"); + $fwrite(fd, " 1382"); 17'b11_01??_?_????_??_????, 17'b10_00??_?_????_??_???? : - if (foo[30]) - $fwrite(fd, " 1383:%x", foo[27:16]); - else - $fwrite(fd, " 1384:%x", foo[27:16]); + if (foo[30]) + $fwrite(fd, " 1383:%x", foo[27:16]); + else + $fwrite(fd, " 1384:%x", foo[27:16]); 17'b00_10??_?_????_01_1000 : if (~foo[6]) - begin - if (foo[7]) - $fwrite(fd, " 1385:%x", foo[27: 8]); - else - $fwrite(fd, " 1386:%x", foo[27: 8]); - end + begin + if (foo[7]) + $fwrite(fd, " 1385:%x", foo[27: 8]); + else + $fwrite(fd, " 1386:%x", foo[27: 8]); + end else - $fwrite(fd, " 1387"); + $fwrite(fd, " 1387"); 17'b00_10??_?_????_11_1000 : begin - $fwrite (fd," 1388"); - ozonecon(foo[14:10], fd); - $fwrite (fd, " 1389"); - if (foo[15]) - $fwrite (fd, " 1390"); - else - $fwrite (fd, " 1391"); - skyway(foo[27:24], fd); - skyway(foo[23:20], fd); - skyway(foo[19:16], fd); - skyway(foo[ 9: 6], fd); - dude(fd); - $fwrite(fd, " 1392"); + $fwrite (fd," 1388"); + ozonecon(foo[14:10], fd); + $fwrite (fd, " 1389"); + if (foo[15]) + $fwrite (fd, " 1390"); + else + $fwrite (fd, " 1391"); + skyway(foo[27:24], fd); + skyway(foo[23:20], fd); + skyway(foo[19:16], fd); + skyway(foo[ 9: 6], fd); + dude(fd); + $fwrite(fd, " 1392"); end 17'b11_0001_?_????_??_???? : casez (foo[25:22]) - 4'b01?? : - begin - $fwrite (fd," 1393"); - ozonecon(foo[20:16], fd); - case (foo[23:21]) - 3'h0 : $fwrite (fd, " 1394"); - 3'h1 : $fwrite (fd, " 1395"); - 3'h2 : $fwrite (fd, " 1396"); - 3'h3 : $fwrite (fd, " 1397"); - 3'h4 : $fwrite (fd, " 1398"); - 3'h5 : $fwrite (fd, " 1399"); - 3'h6 : $fwrite (fd, " 1400"); - 3'h7 : $fwrite (fd, " 1401"); - endcase - dude(fd); - $fwrite(fd, " 1402"); - end - 4'b0000 : - $fwrite(fd, " 1403:%x", foo[21:16]); - 4'b0010 : - if (~|foo[21:16]) + 4'b01?? : + begin + $fwrite (fd," 1393"); + ozonecon(foo[20:16], fd); + case (foo[23:21]) + 3'h0 : $fwrite (fd, " 1394"); + 3'h1 : $fwrite (fd, " 1395"); + 3'h2 : $fwrite (fd, " 1396"); + 3'h3 : $fwrite (fd, " 1397"); + 3'h4 : $fwrite (fd, " 1398"); + 3'h5 : $fwrite (fd, " 1399"); + 3'h6 : $fwrite (fd, " 1400"); + 3'h7 : $fwrite (fd, " 1401"); + endcase + dude(fd); + $fwrite(fd, " 1402"); + end + 4'b0000 : + $fwrite(fd, " 1403:%x", foo[21:16]); + 4'b0010 : + if (~|foo[21:16]) $fwrite(fd, " 1404"); - 4'b1010 : - if (~|foo[21:17]) - begin - if (foo[16]) - $fwrite(fd, " 1405"); - else - $fwrite(fd, " 1406"); - end - default : - $fwrite(fd, " 1407"); + 4'b1010 : + if (~|foo[21:17]) + begin + if (foo[16]) + $fwrite(fd, " 1405"); + else + $fwrite(fd, " 1406"); + end + default : + $fwrite(fd, " 1407"); endcase 17'b01_11??_?_????_??_???? : if (foo[27:23] === 5'h00) - $fwrite(fd, " 1408:%x", foo[22:16]); + $fwrite(fd, " 1408:%x", foo[22:16]); else - $fwrite(fd, " 1409:%x", foo[22:16]); + $fwrite(fd, " 1409:%x", foo[22:16]); default: $fwrite(fd, " 1410"); - endcase + endcase end endtask diff --git a/test_regress/t/t_case_x.v b/test_regress/t/t_case_x.v index ac2ef544c..3f06f3e17 100644 --- a/test_regress/t/t_case_x.v +++ b/test_regress/t/t_case_x.v @@ -19,45 +19,45 @@ module t (/*AUTOARG*/); value = 4'b1001; valuex = 4'b1xxx; case (value) - 4'b1xxx: $stop; - 4'b1???: $stop; - 4'b1001: ; - default: $stop; + 4'b1xxx: $stop; + 4'b1???: $stop; + 4'b1001: ; + default: $stop; endcase case (valuex) - 4'b1???: $stop; - 4'b1xxx: ; - 4'b1001: ; - 4'b1000: ; // 1xxx is mapped to this by Verilator -x-assign 0 - default: $stop; + 4'b1???: $stop; + 4'b1xxx: ; + 4'b1001: ; + 4'b1000: ; // 1xxx is mapped to this by Verilator -x-assign 0 + default: $stop; endcase // casex (value) - 4'b100x: ; - default: $stop; + 4'b100x: ; + default: $stop; endcase casex (value) - 4'b100?: ; - default: $stop; + 4'b100?: ; + default: $stop; endcase casex (valuex) - 4'b100x: ; - default: $stop; + 4'b100x: ; + default: $stop; endcase casex (valuex) - 4'b100?: ; - default: $stop; + 4'b100?: ; + default: $stop; endcase // casez (value) - 4'bxxxx: $stop; - 4'b100?: ; - default: $stop; + 4'bxxxx: $stop; + 4'b100?: ; + default: $stop; endcase casez (valuex) - 4'b1xx?: ; - 4'b100?: ; // 1xxx is mapped to this by Verilator -x-assign 0 - default: $stop; + 4'b1xx?: ; + 4'b100?: ; // 1xxx is mapped to this by Verilator -x-assign 0 + default: $stop; endcase $write("*-* All Finished *-*\n"); $finish; diff --git a/test_regress/t/t_cast.v b/test_regress/t/t_cast.v index 6a3990561..7d19dc870 100644 --- a/test_regress/t/t_cast.v +++ b/test_regress/t/t_cast.v @@ -59,8 +59,8 @@ module t; logic signed [26:0] midb = 15'((27'(coeff2 * samp2) >>> 11)); // verilator lint_on WIDTH logic signed [14:0] outa = 15'((27'(coeff0 * samp0) >>> 11) + // 27' size casting in order for intermediate result to not be truncated to the width of LHS vector - (27'(coeff1 * samp1) >>> 11) + - (27'(coeff2 * samp2) >>> 11)); // 15' size casting to avoid synthesis/simulator warnings + (27'(coeff1 * samp1) >>> 11) + + (27'(coeff2 * samp2) >>> 11)); // 15' size casting to avoid synthesis/simulator warnings logic one = 1'b1; logic [32:0] b33 = {32'(0), one}; diff --git a/test_regress/t/t_chg_first.v b/test_regress/t/t_chg_first.v index 41cde7a1a..4b43f5761 100644 --- a/test_regress/t/t_chg_first.v +++ b/test_regress/t/t_chg_first.v @@ -10,7 +10,7 @@ module t (/*AUTOARG*/ ); input clk; - input fastclk; // surefire lint_off_line UDDIXN + input fastclk; // surefire lint_off_line UDDIXN integer _mode; initial _mode=0; @@ -24,11 +24,11 @@ module t (/*AUTOARG*/ // verilator lint_off UNOPT t_chg_a a ( - .a(ord1), .a_p1(ord2), - .b(ord4), .b_p1(ord5), - .c(ord3), .c_p1(ord4), - .d(ord6), .d_p1(ord7) - ); + .a(ord1), .a_p1(ord2), + .b(ord4), .b_p1(ord5), + .c(ord3), .c_p1(ord4), + .d(ord6), .d_p1(ord7) + ); // surefire lint_off ASWEMB assign ord6 = ord5 + 1; @@ -38,22 +38,22 @@ module t (/*AUTOARG*/ always @ (fastclk) begin // surefire lint_off_line ALWLTR ALWMTR if (_mode==1) begin - //$write("[%0t] t_chg: %d: Values: %x %x %x %x %x %x %x\n", $time,fastclk,ord1,ord2,ord3,ord4,ord5,ord6,ord7); - //if (ord2 == 2 && ord7 != 7) $stop; + //$write("[%0t] t_chg: %d: Values: %x %x %x %x %x %x %x\n", $time,fastclk,ord1,ord2,ord3,ord4,ord5,ord6,ord7); + //if (ord2 == 2 && ord7 != 7) $stop; end end always @ (posedge clk) begin if (_mode==0) begin - $write("[%0t] t_chg: Running\n", $time); - _mode<=1; - ord1 <= 1; + $write("[%0t] t_chg: Running\n", $time); + _mode<=1; + ord1 <= 1; end else if (_mode==1) begin - _mode<=2; - if (ord7 !== 7) $stop; - $write("*-* All Finished *-*\n"); - $finish; + _mode<=2; + if (ord7 !== 7) $stop; + $write("*-* All Finished *-*\n"); + $finish; end end diff --git a/test_regress/t/t_clk_2in.v b/test_regress/t/t_clk_2in.v index 21bc8b253..9248dfb75 100644 --- a/test_regress/t/t_clk_2in.v +++ b/test_regress/t/t_clk_2in.v @@ -8,17 +8,17 @@ module t; /*AUTOREGINPUT*/ // Beginning of automatic reg inputs (for undeclared instantiated-module inputs) - reg c0; // To t2 of t2.v - reg c1; // To t2 of t2.v - reg check; // To t2 of t2.v - reg [1:0] clks; // To t2 of t2.v + reg c0; // To t2 of t2.v + reg c1; // To t2 of t2.v + reg check; // To t2 of t2.v + reg [1:0] clks; // To t2 of t2.v // End of automatics t2 t2 (/*AUTOINST*/ - // Inputs - .clks (clks[1:0]), - .c0 (c0), - .c1 (c1), - .check (check)); + // Inputs + .clks (clks[1:0]), + .c0 (c0), + .c1 (c1), + .check (check)); task clockit (input v1, v0); c1 = v1; c0 = v0; @@ -36,17 +36,17 @@ module t; t2.clear(); #10; for (int i=0; i<2; i++) begin - clockit(0, 0); - clockit(0, 0); - clockit(0, 1); - clockit(1, 1); - clockit(0, 0); - clockit(1, 1); - clockit(1, 0); - clockit(0, 0); - clockit(1, 0); - clockit(0, 1); - clockit(0, 0); + clockit(0, 0); + clockit(0, 0); + clockit(0, 1); + clockit(1, 1); + clockit(0, 0); + clockit(1, 1); + clockit(1, 0); + clockit(0, 0); + clockit(1, 0); + clockit(0, 1); + clockit(0, 0); end check = 1; clockit(0, 0); @@ -61,10 +61,10 @@ endmodule `endif module `t2 ( - input [1:0] clks, - input c0, - input c1, - input check + input [1:0] clks, + input c0, + input c1, + input check ); `ifdef T_CLK_2IN_VEC diff --git a/test_regress/t/t_clk_concat.v b/test_regress/t/t_clk_concat.v index 6ece8b5a3..b66a9282d 100644 --- a/test_regress/t/t_clk_concat.v +++ b/test_regress/t/t_clk_concat.v @@ -5,11 +5,11 @@ // SPDX-License-Identifier: CC0-1.0 module some_module ( - input wrclk - ); + input wrclk + ); - logic [ 1 : 0 ] some_state; - logic [1:0] some_other_state; + logic [ 1 : 0 ] some_state; + logic [1:0] some_other_state; always @(posedge wrclk) begin case (some_state) @@ -29,31 +29,31 @@ endmodule `define BROKEN module t1( - input [3:0] i_clks, - input i_clk0, - input i_clk1 - ); + input [3:0] i_clks, + input i_clk0, + input i_clk1 + ); some_module some_module ( `ifdef BROKEN - .wrclk (i_clks[3]) + .wrclk (i_clks[3]) `else - .wrclk (i_clk1) + .wrclk (i_clk1) `endif - ); + ); endmodule module t2( - input [2:0] i_clks, - input i_clk0, - input i_clk1, - input i_clk2, - input i_data - ); - logic [3:0] the_clks; - logic data_q; + input [2:0] i_clks, + input i_clk0, + input i_clk1, + input i_clk2, + input i_data + ); + logic [3:0] the_clks; + logic data_q; assign the_clks = {i_clk1, i_clk2, i_clk1, i_clk0}; @@ -71,16 +71,16 @@ endmodule module t( `ifdef ATTRIBUTES - input clk0 /*verilator clocker*/, - input clk1 /*verilator clocker*/, - input clk2 /*verilator clocker*/, + input clk0 /*verilator clocker*/, + input clk1 /*verilator clocker*/, + input clk2 /*verilator clocker*/, `else - input clk0, - input clk1, - input clk2, + input clk0, + input clk1, + input clk2, `endif - input data_in - ); + input data_in + ); logic [2:0] clks; @@ -89,12 +89,12 @@ module t( t2 t2 ( - .i_clks (clks), - .i_clk0 (clk0), - .i_clk1 (clk1), - .i_clk2 (clk2), - .i_data (data_in) - ); + .i_clks (clks), + .i_clk0 (clk0), + .i_clk1 (clk1), + .i_clk2 (clk2), + .i_data (data_in) + ); initial begin $write("*-* All Finished *-*\n"); diff --git a/test_regress/t/t_clk_concat2.v b/test_regress/t/t_clk_concat2.v index 5c0654268..d1d641457 100644 --- a/test_regress/t/t_clk_concat2.v +++ b/test_regress/t/t_clk_concat2.v @@ -5,11 +5,11 @@ // SPDX-License-Identifier: CC0-1.0 module some_module ( - input wrclk - ); + input wrclk + ); - logic [ 1 : 0 ] some_state; - logic [1:0] some_other_state; + logic [ 1 : 0 ] some_state; + logic [1:0] some_other_state; always @(posedge wrclk) begin case (some_state) @@ -29,31 +29,31 @@ endmodule `define BROKEN module t1( - input [3:0] i_clks, - input i_clk0, - input i_clk1 - ); + input [3:0] i_clks, + input i_clk0, + input i_clk1 + ); some_module some_module ( `ifdef BROKEN - .wrclk (i_clks[3]) + .wrclk (i_clks[3]) `else - .wrclk (i_clk1) + .wrclk (i_clk1) `endif - ); + ); endmodule module t2( - input [2:0] i_clks, - input i_clk0, - input i_clk1, - input i_clk2, - input i_data - ); - logic [3:0] the_clks; - logic data_q; + input [2:0] i_clks, + input i_clk0, + input i_clk1, + input i_clk2, + input i_data + ); + logic [3:0] the_clks; + logic data_q; assign the_clks[3] = i_clk1; assign the_clks[2] = i_clk2; @@ -73,14 +73,14 @@ module t2( endmodule module t( - /*AUTOARG*/ - // Inputs - clk /*verilator clocker*/, - input clk0 /*verilator clocker*/, - input clk1 /*verilator clocker*/, - input clk2 /*verilator clocker*/, - input data_in - ); + /*AUTOARG*/ + // Inputs + clk /*verilator clocker*/, + input clk0 /*verilator clocker*/, + input clk1 /*verilator clocker*/, + input clk2 /*verilator clocker*/, + input data_in + ); input clk; @@ -91,12 +91,12 @@ module t( t2 t2 ( - .i_clks (clks), - .i_clk0 (clk0), - .i_clk1 (clk), - .i_clk2 (clk2), - .i_data (data_in) - ); + .i_clks (clks), + .i_clk0 (clk0), + .i_clk1 (clk), + .i_clk2 (clk2), + .i_data (data_in) + ); always @(posedge clk) begin $write("*-* All Finished *-*\n"); diff --git a/test_regress/t/t_clk_concat3.v b/test_regress/t/t_clk_concat3.v index 16d07f895..87fb40db8 100644 --- a/test_regress/t/t_clk_concat3.v +++ b/test_regress/t/t_clk_concat3.v @@ -6,11 +6,11 @@ /* verilator lint_off LITENDIAN */ module some_module ( - input wrclk - ); + input wrclk + ); - logic [ 1 : 0 ] some_state; - logic [1:0] some_other_state; + logic [ 1 : 0 ] some_state; + logic [1:0] some_other_state; always @(posedge wrclk) begin case (some_state) @@ -30,31 +30,31 @@ endmodule `define BROKEN module t1( - input [-12:-9] i_clks, - input i_clk0, - input i_clk1 - ); + input [-12:-9] i_clks, + input i_clk0, + input i_clk1 + ); some_module some_module ( `ifdef BROKEN - .wrclk (i_clks[-12]) + .wrclk (i_clks[-12]) `else - .wrclk (i_clk1) + .wrclk (i_clk1) `endif - ); + ); endmodule module t2( - input [2:0] i_clks, - input i_clk0, - input i_clk1, - input i_clk2, - input i_data - ); + input [2:0] i_clks, + input i_clk0, + input i_clk1, + input i_clk2, + input i_data + ); logic [-12:-9] the_clks; - logic data_q; + logic data_q; assign the_clks[-12] = i_clk1; assign the_clks[-11] = i_clk2; @@ -74,11 +74,11 @@ module t2( endmodule module t( - input clk0 /*verilator clocker*/, - input clk1 /*verilator clocker*/, - input clk2 /*verilator clocker*/, - input data_in - ); + input clk0 /*verilator clocker*/, + input clk1 /*verilator clocker*/, + input clk2 /*verilator clocker*/, + input data_in + ); logic [2:0] clks; @@ -87,12 +87,12 @@ module t( t2 t2 ( - .i_clks (clks), - .i_clk0 (clk0), - .i_clk1 (clk1), - .i_clk2 (clk2), - .i_data (data_in) - ); + .i_clks (clks), + .i_clk0 (clk0), + .i_clk1 (clk1), + .i_clk2 (clk2), + .i_data (data_in) + ); initial begin $write("*-* All Finished *-*\n"); diff --git a/test_regress/t/t_clk_concat4.v b/test_regress/t/t_clk_concat4.v index 9d811a406..58539dd4b 100644 --- a/test_regress/t/t_clk_concat4.v +++ b/test_regress/t/t_clk_concat4.v @@ -5,11 +5,11 @@ // SPDX-License-Identifier: CC0-1.0 module some_module ( - input wrclk - ); + input wrclk + ); - logic [ 1 : 0 ] some_state; - logic [1:0] some_other_state; + logic [ 1 : 0 ] some_state; + logic [1:0] some_other_state; always @(posedge wrclk) begin case (some_state) @@ -29,36 +29,36 @@ endmodule `define BROKEN module t1( - input [3:0] i_clks, - input i_clk0, - input i_clk1 - ); + input [3:0] i_clks, + input i_clk0, + input i_clk1 + ); generate - genvar i; + genvar i; for (i = 0; i < 2; i = i + 1) begin: a_generate_block some_module some_module ( `ifdef BROKEN - .wrclk (i_clks[3]) + .wrclk (i_clks[3]) `else - .wrclk (i_clk1) + .wrclk (i_clk1) `endif - ); + ); end endgenerate endmodule module t2( - input [2:0] i_clks, - input i_clk0, - input i_clk1, - input i_clk2, - input i_data - ); - logic [3:0] the_clks; - logic data_q; + input [2:0] i_clks, + input i_clk0, + input i_clk1, + input i_clk2, + input i_data + ); + logic [3:0] the_clks; + logic data_q; assign the_clks[3] = i_clk1; assign the_clks[2] = i_clk2; @@ -78,11 +78,11 @@ module t2( endmodule module t( - input clk0 /*verilator clocker*/, - input clk1 /*verilator clocker*/, - input clk2 /*verilator clocker*/, - input data_in - ); + input clk0 /*verilator clocker*/, + input clk1 /*verilator clocker*/, + input clk2 /*verilator clocker*/, + input data_in + ); logic [2:0] clks; @@ -91,12 +91,12 @@ module t( t2 t2 ( - .i_clks (clks), - .i_clk0 (clk0), - .i_clk1 (clk1), - .i_clk2 (clk2), - .i_data (data_in) - ); + .i_clks (clks), + .i_clk0 (clk0), + .i_clk1 (clk1), + .i_clk2 (clk2), + .i_data (data_in) + ); initial begin $write("*-* All Finished *-*\n"); diff --git a/test_regress/t/t_clk_concat5.v b/test_regress/t/t_clk_concat5.v index c6d4af8ae..359ea01a2 100644 --- a/test_regress/t/t_clk_concat5.v +++ b/test_regress/t/t_clk_concat5.v @@ -5,11 +5,11 @@ // SPDX-License-Identifier: CC0-1.0 module some_module ( - input [3:0] i_clks - ); + input [3:0] i_clks + ); - logic [ 1 : 0 ] some_state; - logic [1:0] some_other_state; + logic [ 1 : 0 ] some_state; + logic [1:0] some_other_state; always @(posedge i_clks[3]) begin case (some_state) @@ -32,27 +32,27 @@ endmodule `define BROKEN module t1( - input [3:0] i_clks, - input i_clk0, - input i_clk1 - ); + input [3:0] i_clks, + input i_clk0, + input i_clk1 + ); some_module some_module ( - .i_clks (i_clks) - ); + .i_clks (i_clks) + ); endmodule module t2( - input [2:0] i_clks, - input i_clk0, - input i_clk1, - input i_clk2, - input i_data - ); - logic [3:0] the_clks; - logic data_q; + input [2:0] i_clks, + input i_clk0, + input i_clk1, + input i_clk2, + input i_data + ); + logic [3:0] the_clks; + logic data_q; assign the_clks[3] = i_clk1; assign the_clks[2] = i_clk2; @@ -72,14 +72,14 @@ module t2( endmodule module t( - /*AUTOARG*/ - // Inputs - clk /*verilator clocker*/, - input clk0 /*verilator clocker*/, - input clk1 /*verilator clocker*/, - input clk2 /*verilator clocker*/, - input data_in - ); + /*AUTOARG*/ + // Inputs + clk /*verilator clocker*/, + input clk0 /*verilator clocker*/, + input clk1 /*verilator clocker*/, + input clk2 /*verilator clocker*/, + input data_in + ); input clk; @@ -90,12 +90,12 @@ module t( t2 t2 ( - .i_clks (clks), - .i_clk0 (clk0), - .i_clk1 (clk), - .i_clk2 (clk2), - .i_data (data_in) - ); + .i_clks (clks), + .i_clk0 (clk0), + .i_clk1 (clk), + .i_clk2 (clk2), + .i_data (data_in) + ); // initial begin // $write("*-* All Finished *-*\n"); diff --git a/test_regress/t/t_clk_concat6.v b/test_regress/t/t_clk_concat6.v index 61e1a07a8..87fad0d11 100644 --- a/test_regress/t/t_clk_concat6.v +++ b/test_regress/t/t_clk_concat6.v @@ -5,12 +5,12 @@ // SPDX-License-Identifier: CC0-1.0 module some_module ( - input [3:0] i_clks - ); + input [3:0] i_clks + ); - logic [ 1 : 0 ] some_state; - logic [1:0] some_other_state; - logic the_clk; + logic [ 1 : 0 ] some_state; + logic [1:0] some_other_state; + logic the_clk; assign the_clk = i_clks[3]; @@ -35,35 +35,35 @@ endmodule `define BROKEN module t1( - input [3:0] i_clks, - input i_clk0, - input i_clk1 - ); + input [3:0] i_clks, + input i_clk0, + input i_clk1 + ); some_module some_module ( - .i_clks (i_clks) - ); + .i_clks (i_clks) + ); endmodule module ident( - input i_ident, - output o_ident - ); + input i_ident, + output o_ident + ); assign o_ident = i_ident; endmodule module t2( - input [2:0] i_clks, - input i_clk0, - input i_clk1, - input i_clk2, - input i_data - ); - logic [3:0] the_clks; - logic data_q; - logic ident_clk1; + input [2:0] i_clks, + input i_clk0, + input i_clk1, + input i_clk2, + input i_data + ); + logic [3:0] the_clks; + logic data_q; + logic ident_clk1; always @(posedge i_clk0) begin data_q <= i_data; @@ -72,9 +72,9 @@ module t2( ident ident ( - .i_ident (i_clk1), - .o_ident (ident_clk1) - ); + .i_ident (i_clk1), + .o_ident (ident_clk1) + ); t1 t1 ( @@ -85,14 +85,14 @@ module t2( endmodule module t( - /*AUTOARG*/ - // Inputs - clk /*verilator clocker*/ /*verilator public_flat*/, - input clk0 /*verilator clocker*/, - input clk1 /*verilator clocker*/, - input clk2 /*verilator clocker*/, - input data_in - ); + /*AUTOARG*/ + // Inputs + clk /*verilator clocker*/ /*verilator public_flat*/, + input clk0 /*verilator clocker*/, + input clk1 /*verilator clocker*/, + input clk2 /*verilator clocker*/, + input data_in + ); input clk; @@ -103,11 +103,11 @@ module t( t2 t2 ( - .i_clks (clks), - .i_clk0 (clk0), - .i_clk1 (clk), - .i_clk2 (clk2), - .i_data (data_in) - ); + .i_clks (clks), + .i_clk0 (clk0), + .i_clk1 (clk), + .i_clk2 (clk2), + .i_data (data_in) + ); endmodule diff --git a/test_regress/t/t_clk_condflop.v b/test_regress/t/t_clk_condflop.v index 98852229a..a28335121 100644 --- a/test_regress/t/t_clk_condflop.v +++ b/test_regress/t/t_clk_condflop.v @@ -16,7 +16,7 @@ module t (clk); wire [7:0] q8; // verilator lint_off UNOPTFLAT - reg ena; + reg ena; // verilator lint_on UNOPTFLAT condff #(12) condff @@ -27,42 +27,42 @@ module t (clk); integer cyc; initial cyc=1; always @ (posedge clk) begin if (cyc!=0) begin - //$write("%x %x %x %x\n", cyc, q8, q3, q1); - cyc <= cyc + 1; - if (cyc==1) begin - d1 <= 1'b1; d3<=3'h1; d8<=8'h11; - ena <= 1'b1; - end - if (cyc==2) begin - d1 <= 1'b0; d3<=3'h2; d8<=8'h33; - ena <= 1'b0; - end - if (cyc==3) begin - d1 <= 1'b1; d3<=3'h3; d8<=8'h44; - ena <= 1'b1; - if (q8 != 8'h11) $stop; - end - if (cyc==4) begin - d1 <= 1'b1; d3<=3'h4; d8<=8'h77; - ena <= 1'b1; - if (q8 != 8'h11) $stop; - end - if (cyc==5) begin - d1 <= 1'b1; d3<=3'h0; d8<=8'h88; - ena <= 1'b1; - if (q8 != 8'h44) $stop; - end - if (cyc==6) begin - if (q8 != 8'h77) $stop; - end - if (cyc==7) begin - if (q8 != 8'h88) $stop; - end - // - if (cyc==20) begin - $write("*-* All Finished *-*\n"); - $finish; - end + //$write("%x %x %x %x\n", cyc, q8, q3, q1); + cyc <= cyc + 1; + if (cyc==1) begin + d1 <= 1'b1; d3<=3'h1; d8<=8'h11; + ena <= 1'b1; + end + if (cyc==2) begin + d1 <= 1'b0; d3<=3'h2; d8<=8'h33; + ena <= 1'b0; + end + if (cyc==3) begin + d1 <= 1'b1; d3<=3'h3; d8<=8'h44; + ena <= 1'b1; + if (q8 != 8'h11) $stop; + end + if (cyc==4) begin + d1 <= 1'b1; d3<=3'h4; d8<=8'h77; + ena <= 1'b1; + if (q8 != 8'h11) $stop; + end + if (cyc==5) begin + d1 <= 1'b1; d3<=3'h0; d8<=8'h88; + ena <= 1'b1; + if (q8 != 8'h44) $stop; + end + if (cyc==6) begin + if (q8 != 8'h77) $stop; + end + if (cyc==7) begin + if (q8 != 8'h88) $stop; + end + // + if (cyc==20) begin + $write("*-* All Finished *-*\n"); + $finish; + end end end endmodule @@ -93,22 +93,22 @@ module condffimp (clk, sen, ena, d, q); always @(posedge gatedclk) begin if (gatedclk === 1'bX) begin - q <= {WIDTH{1'bX}}; + q <= {WIDTH{1'bX}}; end else begin - q <= d; + q <= d; end end endmodule module clockgate (clk, sen, ena, gatedclk); - input clk; - input sen; - input ena; - output gatedclk; + input clk; + input sen; + input ena; + output gatedclk; - reg ena_b; + reg ena_b; wire gatedclk = clk & ena_b; // verilator lint_off COMBDLY @@ -118,7 +118,7 @@ module clockgate (clk, sen, ena, gatedclk); ena_b <= ena | sen; end else begin - if ((clk^sen)===1'bX) ena_b <= 1'bX; + if ((clk^sen)===1'bX) ena_b <= 1'bX; end end // verilator lint_on LATCH diff --git a/test_regress/t/t_clk_condflop_nord.v b/test_regress/t/t_clk_condflop_nord.v index 98852229a..a28335121 100644 --- a/test_regress/t/t_clk_condflop_nord.v +++ b/test_regress/t/t_clk_condflop_nord.v @@ -16,7 +16,7 @@ module t (clk); wire [7:0] q8; // verilator lint_off UNOPTFLAT - reg ena; + reg ena; // verilator lint_on UNOPTFLAT condff #(12) condff @@ -27,42 +27,42 @@ module t (clk); integer cyc; initial cyc=1; always @ (posedge clk) begin if (cyc!=0) begin - //$write("%x %x %x %x\n", cyc, q8, q3, q1); - cyc <= cyc + 1; - if (cyc==1) begin - d1 <= 1'b1; d3<=3'h1; d8<=8'h11; - ena <= 1'b1; - end - if (cyc==2) begin - d1 <= 1'b0; d3<=3'h2; d8<=8'h33; - ena <= 1'b0; - end - if (cyc==3) begin - d1 <= 1'b1; d3<=3'h3; d8<=8'h44; - ena <= 1'b1; - if (q8 != 8'h11) $stop; - end - if (cyc==4) begin - d1 <= 1'b1; d3<=3'h4; d8<=8'h77; - ena <= 1'b1; - if (q8 != 8'h11) $stop; - end - if (cyc==5) begin - d1 <= 1'b1; d3<=3'h0; d8<=8'h88; - ena <= 1'b1; - if (q8 != 8'h44) $stop; - end - if (cyc==6) begin - if (q8 != 8'h77) $stop; - end - if (cyc==7) begin - if (q8 != 8'h88) $stop; - end - // - if (cyc==20) begin - $write("*-* All Finished *-*\n"); - $finish; - end + //$write("%x %x %x %x\n", cyc, q8, q3, q1); + cyc <= cyc + 1; + if (cyc==1) begin + d1 <= 1'b1; d3<=3'h1; d8<=8'h11; + ena <= 1'b1; + end + if (cyc==2) begin + d1 <= 1'b0; d3<=3'h2; d8<=8'h33; + ena <= 1'b0; + end + if (cyc==3) begin + d1 <= 1'b1; d3<=3'h3; d8<=8'h44; + ena <= 1'b1; + if (q8 != 8'h11) $stop; + end + if (cyc==4) begin + d1 <= 1'b1; d3<=3'h4; d8<=8'h77; + ena <= 1'b1; + if (q8 != 8'h11) $stop; + end + if (cyc==5) begin + d1 <= 1'b1; d3<=3'h0; d8<=8'h88; + ena <= 1'b1; + if (q8 != 8'h44) $stop; + end + if (cyc==6) begin + if (q8 != 8'h77) $stop; + end + if (cyc==7) begin + if (q8 != 8'h88) $stop; + end + // + if (cyc==20) begin + $write("*-* All Finished *-*\n"); + $finish; + end end end endmodule @@ -93,22 +93,22 @@ module condffimp (clk, sen, ena, d, q); always @(posedge gatedclk) begin if (gatedclk === 1'bX) begin - q <= {WIDTH{1'bX}}; + q <= {WIDTH{1'bX}}; end else begin - q <= d; + q <= d; end end endmodule module clockgate (clk, sen, ena, gatedclk); - input clk; - input sen; - input ena; - output gatedclk; + input clk; + input sen; + input ena; + output gatedclk; - reg ena_b; + reg ena_b; wire gatedclk = clk & ena_b; // verilator lint_off COMBDLY @@ -118,7 +118,7 @@ module clockgate (clk, sen, ena, gatedclk); ena_b <= ena | sen; end else begin - if ((clk^sen)===1'bX) ena_b <= 1'bX; + if ((clk^sen)===1'bX) ena_b <= 1'bX; end end // verilator lint_on LATCH diff --git a/test_regress/t/t_clk_dpulse.v b/test_regress/t/t_clk_dpulse.v index 9cedf8e33..fdb1b2499 100644 --- a/test_regress/t/t_clk_dpulse.v +++ b/test_regress/t/t_clk_dpulse.v @@ -14,7 +14,7 @@ module t (/*AUTOARG*/ // verilator lint_off GENCLK reg [7:0] cyc; initial cyc = 0; - reg genclk; + reg genclk; // verilator lint_off MULTIDRIVEN reg [7:0] set_both; // verilator lint_on MULTIDRIVEN @@ -27,14 +27,14 @@ module t (/*AUTOARG*/ set_both <= cyc; $write ("SB set_both %x <= cyc %x\n", set_both, cyc); if (genthiscyc) begin - if (cyc>1 && set_both != (cyc - 8'h1)) $stop; + if (cyc>1 && set_both != (cyc - 8'h1)) $stop; end else begin - if (cyc>1 && set_both != ~(cyc - 8'h1)) $stop; + if (cyc>1 && set_both != ~(cyc - 8'h1)) $stop; end if (cyc==10) begin - $write("*-* All Finished *-*\n"); - $finish; + $write("*-* All Finished *-*\n"); + $finish; end end diff --git a/test_regress/t/t_clk_dsp.v b/test_regress/t/t_clk_dsp.v index f991e87eb..0f656e3df 100644 --- a/test_regress/t/t_clk_dsp.v +++ b/test_regress/t/t_clk_dsp.v @@ -15,62 +15,62 @@ module t (/*AUTOARG*/ reg [7:0] cyc; initial cyc = 0; reg [7:0] padd; - reg dsp_ph1, dsp_ph2, dsp_reset; + reg dsp_ph1, dsp_ph2, dsp_reset; /*AUTOWIRE*/ // Beginning of automatic wires (for undeclared instantiated-module outputs) - wire [7:0] out; // From dspchip of t_dspchip.v + wire [7:0] out; // From dspchip of t_dspchip.v // End of automatics t_dspchip dspchip (/*AUTOINST*/ - // Outputs - .out (out[7:0]), - // Inputs - .dsp_ph1 (dsp_ph1), - .dsp_ph2 (dsp_ph2), - .dsp_reset (dsp_reset), - .padd (padd[7:0])); + // Outputs + .out (out[7:0]), + // Inputs + .dsp_ph1 (dsp_ph1), + .dsp_ph2 (dsp_ph2), + .dsp_reset (dsp_reset), + .padd (padd[7:0])); always @ (posedge clk) begin $write("cyc %d\n",cyc); if (cyc == 8'd0) begin - cyc <= 8'd1; - dsp_reset <= 0; // Need a posedge - padd <= 0; + cyc <= 8'd1; + dsp_reset <= 0; // Need a posedge + padd <= 0; end else if (cyc == 8'd20) begin - $write("*-* All Finished *-*\n"); - $finish; + $write("*-* All Finished *-*\n"); + $finish; end else begin - cyc <= cyc + 8'd1; - dsp_ph1 <= ((cyc&8'd3) == 8'd0); - dsp_ph2 <= ((cyc&8'd3) == 8'd2); - dsp_reset <= (cyc == 8'd1); - padd <= cyc; - //$write("[%0t] cyc %d %x->%x\n", $time, cyc, padd, out); - case (cyc) - default: $stop; - 8'd01: ; - 8'd02: ; - 8'd03: ; - 8'd04: ; - 8'd05: ; - 8'd06: ; - 8'd07: ; - 8'd08: ; - 8'd09: if (out!==8'h04) $stop; - 8'd10: if (out!==8'h04) $stop; - 8'd11: if (out!==8'h08) $stop; - 8'd12: if (out!==8'h08) $stop; - 8'd13: if (out!==8'h00) $stop; - 8'd14: if (out!==8'h00) $stop; - 8'd15: if (out!==8'h00) $stop; - 8'd16: if (out!==8'h00) $stop; - 8'd17: if (out!==8'h0c) $stop; - 8'd18: if (out!==8'h0c) $stop; - 8'd19: if (out!==8'h10) $stop; - endcase + cyc <= cyc + 8'd1; + dsp_ph1 <= ((cyc&8'd3) == 8'd0); + dsp_ph2 <= ((cyc&8'd3) == 8'd2); + dsp_reset <= (cyc == 8'd1); + padd <= cyc; + //$write("[%0t] cyc %d %x->%x\n", $time, cyc, padd, out); + case (cyc) + default: $stop; + 8'd01: ; + 8'd02: ; + 8'd03: ; + 8'd04: ; + 8'd05: ; + 8'd06: ; + 8'd07: ; + 8'd08: ; + 8'd09: if (out!==8'h04) $stop; + 8'd10: if (out!==8'h04) $stop; + 8'd11: if (out!==8'h08) $stop; + 8'd12: if (out!==8'h08) $stop; + 8'd13: if (out!==8'h00) $stop; + 8'd14: if (out!==8'h00) $stop; + 8'd15: if (out!==8'h00) $stop; + 8'd16: if (out!==8'h00) $stop; + 8'd17: if (out!==8'h0c) $stop; + 8'd18: if (out!==8'h0c) $stop; + 8'd19: if (out!==8'h10) $stop; + endcase end end @@ -86,34 +86,34 @@ module t_dspchip (/*AUTOARG*/ input [7:0] padd; output [7:0] out; - wire dsp_ph1, dsp_ph2; - wire [7:0] out; - wire pla_ph1, pla_ph2; - wire out1_r; - wire [7:0] out2_r, padd; - wire clk_en; + wire dsp_ph1, dsp_ph2; + wire [7:0] out; + wire pla_ph1, pla_ph2; + wire out1_r; + wire [7:0] out2_r, padd; + wire clk_en; t_dspcore t_dspcore (/*AUTOINST*/ - // Outputs - .out1_r (out1_r), - .pla_ph1 (pla_ph1), - .pla_ph2 (pla_ph2), - // Inputs - .dsp_ph1 (dsp_ph1), - .dsp_ph2 (dsp_ph2), - .dsp_reset (dsp_reset), - .clk_en (clk_en)); + // Outputs + .out1_r (out1_r), + .pla_ph1 (pla_ph1), + .pla_ph2 (pla_ph2), + // Inputs + .dsp_ph1 (dsp_ph1), + .dsp_ph2 (dsp_ph2), + .dsp_reset (dsp_reset), + .clk_en (clk_en)); t_dsppla t_dsppla (/*AUTOINST*/ - // Outputs - .out2_r (out2_r[7:0]), - // Inputs - .pla_ph1 (pla_ph1), - .pla_ph2 (pla_ph2), - .dsp_reset (dsp_reset), - .padd (padd[7:0])); + // Outputs + .out2_r (out2_r[7:0]), + // Inputs + .pla_ph1 (pla_ph1), + .pla_ph2 (pla_ph2), + .dsp_reset (dsp_reset), + .padd (padd[7:0])); - assign out = out1_r ? 8'h00 : out2_r; - assign clk_en = 1'b1; + assign out = out1_r ? 8'h00 : out2_r; + assign clk_en = 1'b1; endmodule @@ -129,13 +129,13 @@ module t_dspcore (/*AUTOARG*/ wire dsp_ph1, dsp_ph2, dsp_reset; wire pla_ph1, pla_ph2; - reg out1_r; + reg out1_r; always @(posedge dsp_ph1 or posedge dsp_reset) begin if (dsp_reset) - out1_r <= 1'h0; + out1_r <= 1'h0; else - out1_r <= ~out1_r; + out1_r <= ~out1_r; end assign pla_ph1 = dsp_ph1; @@ -153,24 +153,24 @@ module t_dsppla (/*AUTOARG*/ input [7:0] padd; output [7:0] out2_r; - wire pla_ph1, pla_ph2, dsp_reset; - wire [7:0] padd; - reg [7:0] out2_r; + wire pla_ph1, pla_ph2, dsp_reset; + wire [7:0] padd; + reg [7:0] out2_r; - reg [7:0] latched_r; + reg [7:0] latched_r; always @(posedge pla_ph1 or posedge dsp_reset) begin if (dsp_reset) - latched_r <= 8'h00; + latched_r <= 8'h00; else - latched_r <= padd; + latched_r <= padd; end always @(posedge pla_ph2 or posedge dsp_reset) begin if (dsp_reset) - out2_r <= 8'h00; + out2_r <= 8'h00; else - out2_r <= latched_r; + out2_r <= latched_r; end endmodule diff --git a/test_regress/t/t_clk_first.v b/test_regress/t/t_clk_first.v index 92285011c..03ae64841 100644 --- a/test_regress/t/t_clk_first.v +++ b/test_regress/t/t_clk_first.v @@ -11,7 +11,7 @@ module t (/*AUTOARG*/ input clk; input fastclk; - reg reset_l; + reg reset_l; int cyc; initial reset_l = 0; @@ -22,10 +22,10 @@ module t (/*AUTOARG*/ end t_clk t (/*AUTOINST*/ - // Inputs - .clk (clk), - .fastclk (fastclk), - .reset_l (reset_l)); + // Inputs + .clk (clk), + .fastclk (fastclk), + .reset_l (reset_l)); endmodule module t_clk (/*AUTOARG*/ @@ -40,7 +40,7 @@ module t_clk (/*AUTOARG*/ // surefire lint_off STMINI // surefire lint_off CWECSB // surefire lint_off NBAJAM - reg _ranit; initial _ranit=0; + reg _ranit; initial _ranit=0; // surefire lint_off UDDSMX reg [7:0] clk_clocks; initial clk_clocks = 0; // surefire lint_off_line WRTWRT wire [7:0] clk_clocks_d1r; @@ -53,8 +53,8 @@ module t_clk (/*AUTOARG*/ reg [7:0] int_clocks_copy; // verilator lint_off GENCLK - reg internal_clk; initial internal_clk = 0; - reg reset_int_; + reg internal_clk; initial internal_clk = 0; + reg reset_int_; // verilator lint_on GENCLK always @ (posedge clk) begin @@ -62,20 +62,20 @@ module t_clk (/*AUTOARG*/ $write("[%0t] CLK1 %x\n", $time, reset_l); `endif if (!reset_l) begin - clk_clocks <= 0; - int_clocks <= 0; - internal_clk <= 1'b1; - reset_int_ <= 0; + clk_clocks <= 0; + int_clocks <= 0; + internal_clk <= 1'b1; + reset_int_ <= 0; end else begin - internal_clk <= ~internal_clk; - if (!_ranit) begin - _ranit <= 1; + internal_clk <= ~internal_clk; + if (!_ranit) begin + _ranit <= 1; `ifdef TEST_VERBOSE - $write("[%0t] t_clk: Running\n", $time); + $write("[%0t] t_clk: Running\n", $time); `endif - reset_int_ <= 1; - end + reset_int_ <= 1; + end end end @@ -85,10 +85,10 @@ module t_clk (/*AUTOARG*/ $write("[%0t] CLK2 %x sr=%x\n", $time, reset_l, sig_rst); `endif if (!reset_l) begin - sig_rst <= 0; + sig_rst <= 0; end else begin - sig_rst <= sig_rst + 1; // surefire lint_off_line ASWIBB + sig_rst <= sig_rst + 1; // surefire lint_off_line ASWIBB end end @@ -97,20 +97,20 @@ module t_clk (/*AUTOARG*/ $write("[%0t] CLK3 %x cc=%x sr=%x\n", $time, reset_l, clk_clocks, sig_rst); `endif if (!reset_l) begin - clk_clocks <= 0; + clk_clocks <= 0; end else begin - clk_clocks <= clk_clocks + 8'd1; - if (clk_clocks == 4) begin - if (sig_rst !== 4) $stop; - if (clk_clocks_d1r !== 3) $stop; - if (int_clocks !== 2) $stop; - if (int_clocks_copy !== 2) $stop; - if (clk_clocks_d1r !== clk_clocks_cp2_d1r) $stop; - if (clk_clocks_d1sr !== clk_clocks_cp2_d1sr) $stop; - $write("*-* All Finished *-*\n"); - $finish; - end + clk_clocks <= clk_clocks + 8'd1; + if (clk_clocks == 4) begin + if (sig_rst !== 4) $stop; + if (clk_clocks_d1r !== 3) $stop; + if (int_clocks !== 2) $stop; + if (int_clocks_copy !== 2) $stop; + if (clk_clocks_d1r !== clk_clocks_cp2_d1r) $stop; + if (clk_clocks_d1sr !== clk_clocks_cp2_d1sr) $stop; + $write("*-* All Finished *-*\n"); + $finish; + end end end @@ -120,10 +120,10 @@ module t_clk (/*AUTOARG*/ $write("[%0t] CLK4 %x\n", $time, reset_l); `endif if (!reset_int_) begin - resetted <= 0; + resetted <= 0; end else begin - resetted <= resetted + 8'd1; + resetted <= resetted + 8'd1; end end @@ -136,13 +136,13 @@ module t_clk (/*AUTOARG*/ end t_clk_flop flopa (.clk(clk), .clk2(fastclk), .a(clk_clocks), - .q(clk_clocks_d1r), .q2(clk_clocks_d1sr)); + .q(clk_clocks_d1r), .q2(clk_clocks_d1sr)); t_clk_flop flopb (.clk(clk), .clk2(fastclk), .a(clk_clocks), - .q(clk_clocks_cp2_d1r), .q2(clk_clocks_cp2_d1sr)); + .q(clk_clocks_cp2_d1r), .q2(clk_clocks_cp2_d1sr)); t_clk_two two (/*AUTOINST*/ - // Inputs - .fastclk (fastclk), - .reset_l (reset_l)); + // Inputs + .fastclk (fastclk), + .reset_l (reset_l)); endmodule diff --git a/test_regress/t/t_clk_gate_ext.v b/test_regress/t/t_clk_gate_ext.v index 02f595828..170ce63e6 100644 --- a/test_regress/t/t_clk_gate_ext.v +++ b/test_regress/t/t_clk_gate_ext.v @@ -17,8 +17,8 @@ module t(/*AUTOARG*/ always @(posedge clk) begin cyc <= cyc + 1; if (cyc == 99) begin - $write("*-* All Finished *-*\n"); - $finish; + $write("*-* All Finished *-*\n"); + $finish; end end diff --git a/test_regress/t/t_clk_gater.v b/test_regress/t/t_clk_gater.v index 4c2d253de..fb5f43c60 100644 --- a/test_regress/t/t_clk_gater.v +++ b/test_regress/t/t_clk_gater.v @@ -10,28 +10,28 @@ module t (/*AUTOARG*/ ); input clk; - integer cyc = 0; - reg [63:0] crc; - reg [63:0] sum; - reg reset; - reg enable; + integer cyc = 0; + reg [63:0] crc; + reg [63:0] sum; + reg reset; + reg enable; /*AUTOWIRE*/ // Beginning of automatic wires (for undeclared instantiated-module outputs) - wire [31:0] out; // From test of Test.v + wire [31:0] out; // From test of Test.v // End of automatics // Take CRC data and apply to testblock inputs wire [31:0] in = crc[31:0]; Test test (/*AUTOINST*/ - // Outputs - .out (out[31:0]), - // Inputs - .clk (clk), - .reset (reset), - .enable (enable), - .in (in[31:0])); + // Outputs + .out (out[31:0]), + // Inputs + .clk (clk), + .reset (reset), + .enable (enable), + .in (in[31:0])); wire [63:0] result = {32'h0, out}; @@ -46,21 +46,21 @@ module t (/*AUTOARG*/ reset <= (cyc < 5); enable <= cyc[4] || (cyc < 2); if (cyc==0) begin - // Setup - crc <= 64'h5aef0c8d_d70a4497; + // Setup + crc <= 64'h5aef0c8d_d70a4497; end else if (cyc<10) begin - sum <= 64'h0; + sum <= 64'h0; end else if (cyc<90) begin end else if (cyc==99) begin - $write("[%0t] cyc==%0d crc=%x sum=%x\n", $time, cyc, crc, sum); - if (crc !== 64'hc77bb9b3784ea091) $stop; + $write("[%0t] cyc==%0d crc=%x sum=%x\n", $time, cyc, crc, sum); + if (crc !== 64'hc77bb9b3784ea091) $stop; `define EXPECTED_SUM 64'h01e1553da1dcf3af - if (sum !== `EXPECTED_SUM) $stop; - $write("*-* All Finished *-*\n"); - $finish; + if (sum !== `EXPECTED_SUM) $stop; + $write("*-* All Finished *-*\n"); + $finish; end end @@ -81,7 +81,7 @@ module Test (/*AUTOARG*/ // No gating - reg [31:0] d10; + reg [31:0] d10; always @(posedge clk) begin d10 <= in; end @@ -94,46 +94,46 @@ module Test (/*AUTOARG*/ `endif // Obvious gating + PLI - reg [31:0] d20; + reg [31:0] d20; always @(posedge clk) begin if (enable) begin - d20 <= d10; // Obvious gating - if (displayit) begin - $display("hello!"); // Must glob with other PLI statements - end + d20 <= d10; // Obvious gating + if (displayit) begin + $display("hello!"); // Must glob with other PLI statements + end end end // Reset means second-level gating - reg [31:0] d30, d31a, d31b, d32; + reg [31:0] d30, d31a, d31b, d32; always @(posedge clk) begin d32 <= d31b; if (reset) begin - d30 <= 32'h0; - d31a <= 32'h0; - d31b <= 32'h0; - d32 <= 32'h0; // Overlaps above, just to make things interesting + d30 <= 32'h0; + d31a <= 32'h0; + d31b <= 32'h0; + d32 <= 32'h0; // Overlaps above, just to make things interesting end else begin - // Mix two outputs - d30 <= d20; - if (enable) begin - d31a <= d30; - d31b <= d31a; - end + // Mix two outputs + d30 <= d20; + if (enable) begin + d31a <= d30; + d31b <= d31a; + end end end // Multiple ORs for gater - reg [31:0] d40a,d40b; + reg [31:0] d40a,d40b; always @(posedge clk) begin if (reset) begin - d40a <= 32'h0; - d40b <= 32'h0; + d40a <= 32'h0; + d40b <= 32'h0; end if (enable) begin - d40a <= d32; - d40b <= d40a; + d40a <= d32; + d40b <= d40a; end end @@ -143,15 +143,15 @@ module Test (/*AUTOARG*/ always @(posedge clk) begin inverted = ~d40b; if (reset) begin - d91 <= 32'h0; + d91 <= 32'h0; end else begin - if (enable) begin - d91 <= inverted; - end - else begin - d92 <= inverted ^ 32'h12341234; // Inverted gating condition - end + if (enable) begin + d91 <= inverted; + end + else begin + d92 <= inverted ^ 32'h12341234; // Inverted gating condition + end end end diff --git a/test_regress/t/t_clk_gen.v b/test_regress/t/t_clk_gen.v index 9a07b7150..fcc149f68 100644 --- a/test_regress/t/t_clk_gen.v +++ b/test_regress/t/t_clk_gen.v @@ -13,11 +13,11 @@ module t (/*AUTOARG*/ integer cyc; initial cyc=1; // verilator lint_off GENCLK - reg gendlyclk_r; + reg gendlyclk_r; reg [31:0] gendlydata_r; reg [31:0] dlydata_gr; - reg genblkclk; + reg genblkclk; reg [31:0] genblkdata; reg [31:0] blkdata_gr; @@ -27,7 +27,7 @@ module t (/*AUTOARG*/ integer i; initial begin for (i=0; i<10000; i=i+1) begin - initwire = 32'h2200; + initwire = 32'h2200; end end @@ -41,46 +41,46 @@ module t (/*AUTOARG*/ genblkclk = 0; genblkdata = 0; if (cyc!=0) begin - cyc <= cyc + 1; - if (cyc==2) begin - gendlyclk_r <= 1; - gendlydata_r <= 32'h00540000; - genblkclk = 1; - genblkdata = 32'hace; - $write("[%0t] Send pulse\n", $time); - end - if (cyc==3) begin - genblkdata = 32'hdce; - gendlydata_r <= 32'h00ff0000; - if (either != 32'h87542211) $stop; - $write("*-* All Finished *-*\n"); - $finish; - end + cyc <= cyc + 1; + if (cyc==2) begin + gendlyclk_r <= 1; + gendlydata_r <= 32'h00540000; + genblkclk = 1; + genblkdata = 32'hace; + $write("[%0t] Send pulse\n", $time); + end + if (cyc==3) begin + genblkdata = 32'hdce; + gendlydata_r <= 32'h00ff0000; + if (either != 32'h87542211) $stop; + $write("*-* All Finished *-*\n"); + $finish; + end end // surefire lint_on SEQASS end always @ (posedge gendlyclk_r) begin - if ($time>0) begin // Hack, don't split the block - $write("[%0t] Got gendlyclk_r, d=%x b=%x\n", $time, gendlydata_r, genblkdata); - dlydata_gr <= 32'h80000000; - // Delayed activity list will already be completed for gendlydata - // because genclk is from a delayed assignment. - // Thus we get the NEW not old value of gendlydata_r - if (gendlydata_r != 32'h00540000) $stop; - if (genblkdata != 32'hace) $stop; + if ($time>0) begin // Hack, don't split the block + $write("[%0t] Got gendlyclk_r, d=%x b=%x\n", $time, gendlydata_r, genblkdata); + dlydata_gr <= 32'h80000000; + // Delayed activity list will already be completed for gendlydata + // because genclk is from a delayed assignment. + // Thus we get the NEW not old value of gendlydata_r + if (gendlydata_r != 32'h00540000) $stop; + if (genblkdata != 32'hace) $stop; end end always @ (posedge genblkclk) begin - if ($time>0) begin // Hack, don't split the block - $write("[%0t] Got genblkclk, d=%x b=%x\n", $time, gendlydata_r, genblkdata); - blkdata_gr <= 32'h07000000; - // Clock from non-delayed assignment, we get old value of gendlydata_r -`ifdef verilator `else // V3.2 races... technically legal - if (gendlydata_r != 32'h00110000) $stop; + if ($time>0) begin // Hack, don't split the block + $write("[%0t] Got genblkclk, d=%x b=%x\n", $time, gendlydata_r, genblkdata); + blkdata_gr <= 32'h07000000; + // Clock from non-delayed assignment, we get old value of gendlydata_r +`ifdef verilator `else // V3.2 races... technically legal + if (gendlydata_r != 32'h00110000) $stop; `endif - if (genblkdata != 32'hace) $stop; + if (genblkdata != 32'hace) $stop; end end diff --git a/test_regress/t/t_clk_latch.v b/test_regress/t/t_clk_latch.v index 487920783..4f1bf498f 100644 --- a/test_regress/t/t_clk_latch.v +++ b/test_regress/t/t_clk_latch.v @@ -9,7 +9,7 @@ module t (/*AUTOARG*/ fastclk, clk ); -`ifdef EDGE_DETECT_STYLE // Two 'common' forms of latching, with full combo, and with pos/negedge +`ifdef EDGE_DETECT_STYLE // Two 'common' forms of latching, with full combo, and with pos/negedge `define posstyle posedge `define negstyle negedge `else @@ -56,27 +56,27 @@ module t (/*AUTOARG*/ // verilator lint_off LATCH always @ (`posstyle clk /*AS*/ or data) begin if (clk) begin - data_a <= data + 8'd1; + data_a <= data + 8'd1; end end always @ (`posstyle clk /*AS*/ or data_a) begin if (clk) begin - data_a_a <= data_a + 8'd1; + data_a_a <= data_a + 8'd1; end end always @ (`posstyle clk /*AS*/ or data_b) begin if (clk) begin - data_b_a <= data_b + 8'd1; + data_b_a <= data_b + 8'd1; end end always @ (`negstyle clk /*AS*/ or data or data_a) begin if (~clk) begin - data_b <= data + 8'd1; - data_a_b <= data_a + 8'd1; - data_b_b <= data_b + 8'd1; + data_b <= data + 8'd1; + data_a_b <= data_a + 8'd1; + data_b_b <= data_b + 8'd1; end end @@ -88,23 +88,23 @@ module t (/*AUTOARG*/ $write("%d %x %x %x %x %x %x\n",cyc,data_a,data_a_a,data_b_a,data_b,data_a_b,data_b_b); `endif if (cyc>=19 && cyc<36) begin - if (compare !== check[cyc]) begin - $write("[%0t] Mismatch, got=%x, exp=%x\n", $time, compare, check[cyc]); - $stop; - end + if (compare !== check[cyc]) begin + $write("[%0t] Mismatch, got=%x, exp=%x\n", $time, compare, check[cyc]); + $stop; + end end if (cyc == 10) begin - data <= 8'd12; + data <= 8'd12; end if (cyc == 20) begin - data <= 8'd20; + data <= 8'd20; end if (cyc == 30) begin - data <= 8'd30; + data <= 8'd30; end if (cyc == 40) begin - $write("*-* All Finished *-*\n"); - $finish; + $write("*-* All Finished *-*\n"); + $finish; end end diff --git a/test_regress/t/t_clk_latchgate.v b/test_regress/t/t_clk_latchgate.v index b18af26c5..c6ad11ca8 100644 --- a/test_regress/t/t_clk_latchgate.v +++ b/test_regress/t/t_clk_latchgate.v @@ -28,8 +28,8 @@ module t (/*AUTOARG*/ ); input clk; - integer cyc = 0; - reg [63:0] crc; + integer cyc = 0; + reg [63:0] crc; // Take CRC data and apply to testblock inputs wire [7:0] dvld = crc[7:0]; @@ -37,18 +37,18 @@ module t (/*AUTOARG*/ /*AUTOWIRE*/ // Beginning of automatic wires (for undeclared instantiated-module outputs) - wire [7:0] entry_vld; // From test of Test.v - wire [7:0] ff_en_vld; // From test of Test.v + wire [7:0] entry_vld; // From test of Test.v + wire [7:0] ff_en_vld; // From test of Test.v // End of automatics Test test (/*AUTOINST*/ - // Outputs - .ff_en_vld (ff_en_vld[7:0]), - .entry_vld (entry_vld[7:0]), - // Inputs - .clk (clk), - .dvld (dvld[7:0]), - .ff_en_e1 (ff_en_e1[7:0])); + // Outputs + .ff_en_vld (ff_en_vld[7:0]), + .entry_vld (entry_vld[7:0]), + // Inputs + .clk (clk), + .dvld (dvld[7:0]), + .ff_en_e1 (ff_en_e1[7:0])); reg err_code; reg ffq_clk_active; @@ -71,16 +71,16 @@ module t (/*AUTOARG*/ `ifdef TEST_VERBOSE $write("[%0t] cyc==%0d crc=%x ", $time, cyc, crc); $display(" en=%b fen=%b d=%b ev=%b", - test.flop_en_vld[0], test.ff_en_vld[0], - test.dvld[0], test.entry_vld[0]); + test.flop_en_vld[0], test.ff_en_vld[0], + test.dvld[0], test.entry_vld[0]); `endif cyc <= cyc + 1; crc <= {crc[62:0], crc[63] ^ crc[2] ^ crc[0]}; if (cyc<3) begin - crc <= 64'h5aef0c8d_d70a4497; + crc <= 64'h5aef0c8d_d70a4497; end else if (cyc==99) begin - $write("[%0t] cyc==%0d crc=%x\n", $time, cyc, crc); + $write("[%0t] cyc==%0d crc=%x\n", $time, cyc, crc); if (ffq_clk_active == 0) begin $display ("----"); $display ("%%Error: TESTCASE FAILED with no Clock arriving at FFQs"); @@ -94,8 +94,8 @@ module t (/*AUTOARG*/ $stop; end else begin - $write("*-* All Finished *-*\n"); - $finish; + $write("*-* All Finished *-*\n"); + $finish; end end end diff --git a/test_regress/t/t_clk_powerdn.v b/test_regress/t/t_clk_powerdn.v index bb496db57..067ead2a4 100644 --- a/test_regress/t/t_clk_powerdn.v +++ b/test_regress/t/t_clk_powerdn.v @@ -11,7 +11,7 @@ module t (/*AUTOARG*/ input clk; - reg reset_l; + reg reset_l; // verilator lint_off GENCLK @@ -20,13 +20,13 @@ module t (/*AUTOARG*/ // End of automatics reg clkgate_e2r; - reg clkgate_e1r_l; + reg clkgate_e1r_l; always @(posedge clk or negedge reset_l) begin if (!reset_l) begin - clkgate_e1r_l <= ~1'b1; + clkgate_e1r_l <= ~1'b1; end else begin - clkgate_e1r_l <= ~clkgate_e2r; + clkgate_e1r_l <= ~clkgate_e2r; end end @@ -41,20 +41,20 @@ module t (/*AUTOARG*/ reg [31:0] countgated; always @(posedge clkgated or negedge reset_l) begin if (!reset_l) begin - countgated <= 32'h1000; + countgated <= 32'h1000; end else begin - countgated <= countgated + 32'd1; + countgated <= countgated + 32'd1; end end reg [31:0] count; always @(posedge clk or negedge reset_l) begin if (!reset_l) begin - count <= 32'h1000; + count <= 32'h1000; end else begin - count <= count + 32'd1; + count <= count + 32'd1; end end @@ -65,58 +65,58 @@ module t (/*AUTOARG*/ `endif cyc <= cyc + 8'd1; case (cyc) - 8'd00: begin - reset_l <= ~1'b0; - clkgate_e2r <= 1'b1; - end - 8'd01: begin - reset_l <= ~1'b0; - end - 8'd02: begin - end - 8'd03: begin - reset_l <= ~1'b1; // Need a posedge - end - 8'd04: begin - end - 8'd05: begin - reset_l <= ~1'b0; - end - 8'd09: begin - clkgate_e2r <= 1'b0; - end - 8'd11: begin - clkgate_e2r <= 1'b1; - end - 8'd20: begin - $write("*-* All Finished *-*\n"); - $finish; - end - default: ; + 8'd00: begin + reset_l <= ~1'b0; + clkgate_e2r <= 1'b1; + end + 8'd01: begin + reset_l <= ~1'b0; + end + 8'd02: begin + end + 8'd03: begin + reset_l <= ~1'b1; // Need a posedge + end + 8'd04: begin + end + 8'd05: begin + reset_l <= ~1'b0; + end + 8'd09: begin + clkgate_e2r <= 1'b0; + end + 8'd11: begin + clkgate_e2r <= 1'b1; + end + 8'd20: begin + $write("*-* All Finished *-*\n"); + $finish; + end + default: ; endcase case (cyc) - 8'd00: ; - 8'd01: ; - 8'd02: ; - 8'd03: ; - 8'd04: if (count!=32'h00001000 || countgated!=32'h 00001000) $stop; - 8'd05: if (count!=32'h00001000 || countgated!=32'h 00001000) $stop; - 8'd06: if (count!=32'h00001000 || countgated!=32'h 00001000) $stop; - 8'd07: if (count!=32'h00001001 || countgated!=32'h 00001001) $stop; - 8'd08: if (count!=32'h00001002 || countgated!=32'h 00001002) $stop; - 8'd09: if (count!=32'h00001003 || countgated!=32'h 00001003) $stop; - 8'd10: if (count!=32'h00001004 || countgated!=32'h 00001004) $stop; - 8'd11: if (count!=32'h00001005 || countgated!=32'h 00001005) $stop; - 8'd12: if (count!=32'h00001006 || countgated!=32'h 00001005) $stop; - 8'd13: if (count!=32'h00001007 || countgated!=32'h 00001005) $stop; - 8'd14: if (count!=32'h00001008 || countgated!=32'h 00001006) $stop; - 8'd15: if (count!=32'h00001009 || countgated!=32'h 00001007) $stop; - 8'd16: if (count!=32'h0000100a || countgated!=32'h 00001008) $stop; - 8'd17: if (count!=32'h0000100b || countgated!=32'h 00001009) $stop; - 8'd18: if (count!=32'h0000100c || countgated!=32'h 0000100a) $stop; - 8'd19: if (count!=32'h0000100d || countgated!=32'h 0000100b) $stop; - 8'd20: if (count!=32'h0000100e || countgated!=32'h 0000100c) $stop; - default: $stop; + 8'd00: ; + 8'd01: ; + 8'd02: ; + 8'd03: ; + 8'd04: if (count!=32'h00001000 || countgated!=32'h 00001000) $stop; + 8'd05: if (count!=32'h00001000 || countgated!=32'h 00001000) $stop; + 8'd06: if (count!=32'h00001000 || countgated!=32'h 00001000) $stop; + 8'd07: if (count!=32'h00001001 || countgated!=32'h 00001001) $stop; + 8'd08: if (count!=32'h00001002 || countgated!=32'h 00001002) $stop; + 8'd09: if (count!=32'h00001003 || countgated!=32'h 00001003) $stop; + 8'd10: if (count!=32'h00001004 || countgated!=32'h 00001004) $stop; + 8'd11: if (count!=32'h00001005 || countgated!=32'h 00001005) $stop; + 8'd12: if (count!=32'h00001006 || countgated!=32'h 00001005) $stop; + 8'd13: if (count!=32'h00001007 || countgated!=32'h 00001005) $stop; + 8'd14: if (count!=32'h00001008 || countgated!=32'h 00001006) $stop; + 8'd15: if (count!=32'h00001009 || countgated!=32'h 00001007) $stop; + 8'd16: if (count!=32'h0000100a || countgated!=32'h 00001008) $stop; + 8'd17: if (count!=32'h0000100b || countgated!=32'h 00001009) $stop; + 8'd18: if (count!=32'h0000100c || countgated!=32'h 0000100a) $stop; + 8'd19: if (count!=32'h0000100d || countgated!=32'h 0000100b) $stop; + 8'd20: if (count!=32'h0000100e || countgated!=32'h 0000100c) $stop; + default: $stop; endcase end diff --git a/test_regress/t/t_clk_vecgen1.v b/test_regress/t/t_clk_vecgen1.v index 8c7535c07..c4eb66356 100644 --- a/test_regress/t/t_clk_vecgen1.v +++ b/test_regress/t/t_clk_vecgen1.v @@ -10,22 +10,22 @@ module t (/*AUTOARG*/ ); input clk; - integer cyc = 0; - reg [63:0] crc; - reg [63:0] sum; + integer cyc = 0; + reg [63:0] crc; + reg [63:0] sum; wire [1:0] clkvec = crc[1:0]; /*AUTOWIRE*/ // Beginning of automatic wires (for undeclared instantiated-module outputs) - wire [1:0] count; // From test of Test.v + wire [1:0] count; // From test of Test.v // End of automatics Test test (/*AUTOINST*/ - // Outputs - .count (count[1:0]), - // Inputs - .clkvec (clkvec[1:0])); + // Outputs + .count (count[1:0]), + // Inputs + .clkvec (clkvec[1:0])); // Aggregate outputs into a single result vector wire [63:0] result = {62'h0, count}; @@ -39,21 +39,21 @@ module t (/*AUTOARG*/ crc <= {crc[62:0], crc[63] ^ crc[2] ^ crc[0]}; sum <= result ^ {sum[62:0], sum[63] ^ sum[2] ^ sum[0]}; if (cyc==0) begin - // Setup - crc <= 64'h5aef0c8d_d70a4497; + // Setup + crc <= 64'h5aef0c8d_d70a4497; end else if (cyc<10) begin - sum <= 64'h0; + sum <= 64'h0; end else if (cyc<90) begin end else if (cyc==99) begin - $write("[%0t] cyc==%0d crc=%x sum=%x\n", $time, cyc, crc, sum); - if (crc !== 64'hc77bb9b3784ea091) $stop; + $write("[%0t] cyc==%0d crc=%x sum=%x\n", $time, cyc, crc, sum); + if (crc !== 64'hc77bb9b3784ea091) $stop; `define EXPECTED_SUM 64'hfe8bac0bb1a0e53b - if (sum !== `EXPECTED_SUM) $stop; - $write("*-* All Finished *-*\n"); - $finish; + if (sum !== `EXPECTED_SUM) $stop; + $write("*-* All Finished *-*\n"); + $finish; end end @@ -67,12 +67,12 @@ module Test output reg [1:0] count // verilator lint_on MULTIDRIVEN ); - genvar igen; + genvar igen; generate for (igen=0; igen<2; igen=igen+1) begin : code_gen - initial count[igen] = 1'b0; - always @ (posedge clkvec[igen]) - count[igen] <= count[igen] + 1; + initial count[igen] = 1'b0; + always @ (posedge clkvec[igen]) + count[igen] <= count[igen] + 1; end endgenerate always @ (count) begin @@ -89,15 +89,15 @@ module Test output reg [1:0] count // verilator lint_on MULTIDRIVEN ); - genvar igen; + genvar igen; generate for (igen=0; igen<2; igen=igen+1) begin : code_gen - wire clk_tmp = clkvec[igen]; - // Unsupported: Count is multidriven, though if we did better analysis it wouldn't - // need to be. - initial count[igen] = 1'b0; - always @ (posedge clk_tmp) - count[igen] <= count[igen] + 1; + wire clk_tmp = clkvec[igen]; + // Unsupported: Count is multidriven, though if we did better analysis it wouldn't + // need to be. + initial count[igen] = 1'b0; + always @ (posedge clk_tmp) + count[igen] <= count[igen] + 1; end endgenerate endmodule @@ -112,12 +112,12 @@ module Test genvar igen; generate for (igen=0; igen<2; igen=igen+1) begin : code_gen - wire clk_tmp = clkvec[igen]; - reg tmp_count = 1'b0; - always @ (posedge clk_tmp) begin - tmp_count <= tmp_count + 1; - end - assign count[igen] = tmp_count; + wire clk_tmp = clkvec[igen]; + reg tmp_count = 1'b0; + always @ (posedge clk_tmp) begin + tmp_count <= tmp_count + 1; + end + assign count[igen] = tmp_count; end endgenerate endmodule diff --git a/test_regress/t/t_clocker.v b/test_regress/t/t_clocker.v index 1694ae894..c71e22c68 100644 --- a/test_regress/t/t_clocker.v +++ b/test_regress/t/t_clocker.v @@ -56,8 +56,8 @@ module t (/*AUTOARG*/ // because CLOCK signal is used as DATA in sequential block res <= clk_final; if ( count == 8'hf) begin - $write("*-* All Finished *-*\n"); - $finish; + $write("*-* All Finished *-*\n"); + $finish; end end diff --git a/test_regress/t/t_concat_opt.v b/test_regress/t/t_concat_opt.v index ae3014280..5a09562af 100644 --- a/test_regress/t/t_concat_opt.v +++ b/test_regress/t/t_concat_opt.v @@ -40,7 +40,7 @@ module t (/*AUTOARG*/ always @ (posedge clk) begin if (cyc!=0) begin - cyc <= cyc + 1; + cyc <= cyc + 1; in_a <= cyc; in_b <= cyc + 1; in_c <= cyc + 3; @@ -61,10 +61,10 @@ module t (/*AUTOARG*/ if (out_q != (in_a ^ in_g)) $stop; - if (cyc==100) begin - $write("*-* All Finished *-*\n"); - $finish; - end + if (cyc==100) begin + $write("*-* All Finished *-*\n"); + $finish; + end end end diff --git a/test_regress/t/t_cover_sva_notflat.v b/test_regress/t/t_cover_sva_notflat.v index cc55c400e..ab3db9c7f 100644 --- a/test_regress/t/t_cover_sva_notflat.v +++ b/test_regress/t/t_cover_sva_notflat.v @@ -10,35 +10,35 @@ module t (/*AUTOARG*/ ); input clk; - reg toggle; + reg toggle; integer cyc; initial cyc=1; Test suba (/*AUTOINST*/ - // Inputs - .clk (clk), - .toggle (toggle), - .cyc (cyc[31:0])); + // Inputs + .clk (clk), + .toggle (toggle), + .cyc (cyc[31:0])); Test subb (/*AUTOINST*/ - // Inputs - .clk (clk), - .toggle (toggle), - .cyc (cyc[31:0])); + // Inputs + .clk (clk), + .toggle (toggle), + .cyc (cyc[31:0])); Test subc (/*AUTOINST*/ - // Inputs - .clk (clk), - .toggle (toggle), - .cyc (cyc[31:0])); + // Inputs + .clk (clk), + .toggle (toggle), + .cyc (cyc[31:0])); always @ (posedge clk) begin if (cyc!=0) begin - cyc <= cyc + 1; - toggle <= !cyc[0]; - if (cyc==9) begin - end - if (cyc==10) begin - $write("*-* All Finished *-*\n"); - $finish; - end + cyc <= cyc + 1; + toggle <= !cyc[0]; + if (cyc==9) begin + end + if (cyc==10) begin + $write("*-* All Finished *-*\n"); + $finish; + end end end diff --git a/test_regress/t/t_cover_toggle.v b/test_regress/t/t_cover_toggle.v index a2920779f..a6ed04bd4 100644 --- a/test_regress/t/t_cover_toggle.v +++ b/test_regress/t/t_cover_toggle.v @@ -17,13 +17,13 @@ module t (/*AUTOARG*/ typedef struct packed { union packed { - logic ua; - logic ub; + logic ua; + logic ub; } u; logic b; } str_t; - reg toggle; initial toggle='0; + reg toggle; initial toggle='0; str_t stoggle; initial stoggle='0; @@ -36,29 +36,29 @@ module t (/*AUTOARG*/ wire toggle_up; alpha a1 (/*AUTOINST*/ - // Outputs - .toggle_up (toggle_up), - // Inputs - .clk (clk), - .toggle (toggle), - .cyc_copy (cyc_copy[7:0])); + // Outputs + .toggle_up (toggle_up), + // Inputs + .clk (clk), + .toggle (toggle), + .cyc_copy (cyc_copy[7:0])); alpha a2 (/*AUTOINST*/ - // Outputs - .toggle_up (toggle_up), - // Inputs - .clk (clk), - .toggle (toggle), - .cyc_copy (cyc_copy[7:0])); + // Outputs + .toggle_up (toggle_up), + // Inputs + .clk (clk), + .toggle (toggle), + .cyc_copy (cyc_copy[7:0])); beta b1 (/*AUTOINST*/ - // Inputs - .clk (clk), - .toggle_up (toggle_up)); + // Inputs + .clk (clk), + .toggle_up (toggle_up)); off o1 (/*AUTOINST*/ - // Inputs - .clk (clk), - .toggle (toggle)); + // Inputs + .clk (clk), + .toggle (toggle)); reg [1:0] memory[121:110]; @@ -67,22 +67,22 @@ module t (/*AUTOARG*/ always @ (posedge clk) begin if (cyc!=0) begin - cyc <= cyc + 1; - memory[cyc + 'd100] <= memory[cyc + 'd100] + 2'b1; - toggle <= '0; - stoggle.u <= toggle; - stoggle.b <= toggle; - ptoggle[0][0] <= toggle; - if (cyc==3) begin - toggle <= '1; - end - if (cyc==4) begin - toggle <= '0; - end - else if (cyc==10) begin - $write("*-* All Finished *-*\n"); - $finish; - end + cyc <= cyc + 1; + memory[cyc + 'd100] <= memory[cyc + 'd100] + 2'b1; + toggle <= '0; + stoggle.u <= toggle; + stoggle.b <= toggle; + ptoggle[0][0] <= toggle; + if (cyc==3) begin + toggle <= '1; + end + if (cyc==4) begin + toggle <= '0; + end + else if (cyc==10) begin + $write("*-* All Finished *-*\n"); + $finish; + end end end @@ -113,7 +113,7 @@ module alpha (/*AUTOARG*/ // CHECK_COVER(-7,"top.t.a*","cyc_copy[6]",0) // CHECK_COVER(-8,"top.t.a*","cyc_copy[7]",0) - reg toggle_internal; + reg toggle_internal; // CHECK_COVER(-1,"top.t.a*",4) // 2 edges * (t.a1 and t.a2) diff --git a/test_regress/t/t_detectarray_1.v b/test_regress/t/t_detectarray_1.v index 15f72f77c..aa2f20e04 100644 --- a/test_regress/t/t_detectarray_1.v +++ b/test_regress/t/t_detectarray_1.v @@ -16,7 +16,7 @@ module t (/*AUTOARG*/ input clk; typedef struct packed { - logic [ID_MSB:0] id; + logic [ID_MSB:0] id; } context_t; context_t tsb; @@ -34,8 +34,8 @@ module t (/*AUTOARG*/ `endif if (tsb.id[1] != 0) begin - $write("*-* All Finished *-*\n"); - $finish; + $write("*-* All Finished *-*\n"); + $finish; end end diff --git a/test_regress/t/t_detectarray_2.v b/test_regress/t/t_detectarray_2.v index f6da72827..72df7ad80 100644 --- a/test_regress/t/t_detectarray_2.v +++ b/test_regress/t/t_detectarray_2.v @@ -18,7 +18,7 @@ module t (/*AUTOARG*/ input clk; typedef struct packed { - logic [1:0] id; + logic [1:0] id; } context_t; context_t tsb; @@ -36,8 +36,8 @@ module t (/*AUTOARG*/ `endif if (tsb.id[1] != 0) begin - $write("*-* All Finished *-*\n"); - $finish; + $write("*-* All Finished *-*\n"); + $finish; end end diff --git a/test_regress/t/t_detectarray_3.v b/test_regress/t/t_detectarray_3.v index f83bf384d..13b1e0592 100644 --- a/test_regress/t/t_detectarray_3.v +++ b/test_regress/t/t_detectarray_3.v @@ -32,8 +32,8 @@ module t (/*AUTOARG*/ always @(posedge clk or negedge clk) begin if (res != 0) begin - $write("*-* All Finished *-*\n"); - $finish; + $write("*-* All Finished *-*\n"); + $finish; end end diff --git a/test_regress/t/t_dpi_accessors.v b/test_regress/t/t_dpi_accessors.v index c41fea0bc..b4b367a8e 100644 --- a/test_regress/t/t_dpi_accessors.v +++ b/test_regress/t/t_dpi_accessors.v @@ -56,13 +56,13 @@ module test_sub (/*AUTOARG*/ input clk; - integer i; // General counter + integer i; // General counter // Elements we would like to access from outside - reg a; + reg a; reg [`REG_WIDTH - 1:0] b; reg [`REG_WIDTH - 1:0] mem [`MEM_SIZE - 1:0]; - wire c; + wire c; wire [`REG_WIDTH - 1:0] d; reg [`REG_WIDTH - 1:0] e; reg [`REG_WIDTH - 1:0] f; @@ -77,7 +77,7 @@ module test_sub (/*AUTOARG*/ b = `REG_WIDTH'h0; for (i = 0; i < `MEM_SIZE; i++) begin - mem[i] = i [`REG_WIDTH - 1:0]; + mem[i] = i [`REG_WIDTH - 1:0]; end e = 0; diff --git a/test_regress/t/t_dpi_imp_gen.v b/test_regress/t/t_dpi_imp_gen.v index e7678be43..dc9a49eb0 100644 --- a/test_regress/t/t_dpi_imp_gen.v +++ b/test_regress/t/t_dpi_imp_gen.v @@ -17,12 +17,12 @@ module t (/*AUTOARG*/ generate for (genvar blkIdx=0; blkIdx < BLKS; blkIdx=blkIdx+1 ) begin : slice - import "DPI-C" context function void dpi_genvarTest (); + import "DPI-C" context function void dpi_genvarTest (); initial begin - dpi_genvarTest(); - $display("slice = %0d : %m", blkIdx); - end + dpi_genvarTest(); + $display("slice = %0d : %m", blkIdx); + end end endgenerate diff --git a/test_regress/t/t_dpi_import.v b/test_regress/t/t_dpi_import.v index 1f45833ae..0274af337 100644 --- a/test_regress/t/t_dpi_import.v +++ b/test_regress/t/t_dpi_import.v @@ -32,7 +32,7 @@ module t (/*AUTOARG*/ // Scalar bit and logic // // Allowed argument types: - // Same as above plus packed arrays + // Same as above plus packed arrays import "DPI-C" pure function bit dpii_f_bit (input bit i); import "DPI-C" pure function bit [8-1:0] dpii_f_bit8 (input bit [8-1:0] i); @@ -42,7 +42,7 @@ module t (/*AUTOARG*/ import "DPI-C" pure function bit [32-1:0] dpii_f_bit32 (input bit [32-1:0] i); // Illegal to return > 32 bits, so we use longint import "DPI-C" pure function longint dpii_f_bit33 (input bit [33-1:0] i); - import "DPI-C" pure function longint dpii_f_bit64 (input bit [64-1:0] i); + import "DPI-C" pure function longint dpii_f_bit64 (input bit [64-1:0] i); import "DPI-C" pure function int dpii_f_int (input int i); import "DPI-C" pure function byte dpii_f_byte (input byte i); import "DPI-C" pure function shortint dpii_f_shortint (input shortint i); @@ -97,34 +97,34 @@ module t (/*AUTOARG*/ import "DPI-C" dpii_fa_bit = function int oth_f_int1(input int i); import "DPI-C" dpii_fa_bit = function int oth_f_int2(input int i); - bit i_b, o_b; + bit i_b, o_b; bit [7:0] i_b8; - bit [8:0] i_b9; - bit [15:0] i_b16; + bit [8:0] i_b9; + bit [15:0] i_b16; bit [16:0] i_b17; - bit [31:0] i_b32; - bit [32:0] i_b33, o_b33; - bit [63:0] i_b64, o_b64; - bit [94:0] i_b95, o_b95; - bit [95:0] i_b96, o_b96; + bit [31:0] i_b32; + bit [32:0] i_b33, o_b33; + bit [63:0] i_b64, o_b64; + bit [94:0] i_b95, o_b95; + bit [95:0] i_b96, o_b96; - int i_i, o_i; - byte i_y, o_y; - shortint i_s, o_s; - longint i_l, o_l; + int i_i, o_i; + byte i_y, o_y; + shortint i_s, o_s; + longint i_l, o_l; str_t i_t, o_t; substr_t i_ss; - int o_ss; - int unsigned i_iu, o_iu; - shortint unsigned i_su, o_su; - longint unsigned i_lu, o_lu; + int o_ss; + int unsigned i_iu, o_iu; + shortint unsigned i_su, o_su; + longint unsigned i_lu, o_lu; // verilator lint_off UNDRIVEN - chandle i_c, o_c; - string i_n, o_n; + chandle i_c, o_c; + string i_n, o_n; // verilator lint_on UNDRIVEN - real i_d, o_d; + real i_d, o_d; `ifndef NO_SHORTREAL - shortreal i_f, o_f; + shortreal i_f, o_f; `endif reg i_r, o_r; diff --git a/test_regress/t/t_dpi_qw.v b/test_regress/t/t_dpi_qw.v index a23e50304..42e580f3b 100644 --- a/test_regress/t/t_dpi_qw.v +++ b/test_regress/t/t_dpi_qw.v @@ -17,8 +17,8 @@ module t; initial begin poke_value(32'hdeadbeef); if (out !== 40'hdeadbeef) begin - $display("[%0t] %%Error: t_dpi_qw: failed", $time); - $stop; + $display("[%0t] %%Error: t_dpi_qw: failed", $time); + $stop; end $write("*-* All Finished *-*\n"); diff --git a/test_regress/t/t_dpi_shortcircuit.v b/test_regress/t/t_dpi_shortcircuit.v index 1b2c7b463..6aeb3a5e7 100644 --- a/test_regress/t/t_dpi_shortcircuit.v +++ b/test_regress/t/t_dpi_shortcircuit.v @@ -27,19 +27,19 @@ module t (/*AUTOARG*/); integer i; integer j; - bit b; + bit b; integer errors; task check1(integer line, bit got, bit ex); if (got != ex) begin - $display("%%Error: Line %0d: Bad result, got=%0d expect=%0d",line,got,ex); - errors++; + $display("%%Error: Line %0d: Bad result, got=%0d expect=%0d",line,got,ex); + errors++; end endtask task check(integer line, int got, int ex); if (got != ex) begin - $display("%%Error: Line %0d: Bad result, got=%0d expect=%0d",line,got,ex); - errors++; + $display("%%Error: Line %0d: Bad result, got=%0d expect=%0d",line,got,ex); + errors++; end endtask @@ -192,12 +192,12 @@ module t (/*AUTOARG*/); // Something a lot more complicated dpii_clear(); for (i=0; i<64; i++) begin - b = ( ((dpii_incx(0,i[0]) - && (dpii_incx(1,i[1]) - || dpii_incx(2,i[2]) - | dpii_incx(3,i[3]))) // | not || - || dpii_incx(4,i[4])) - -> dpii_incx(5,i[5])); + b = ( ((dpii_incx(0,i[0]) + && (dpii_incx(1,i[1]) + || dpii_incx(2,i[2]) + | dpii_incx(3,i[3]))) // | not || + || dpii_incx(4,i[4])) + -> dpii_incx(5,i[5])); end check (`__LINE__, dpii_count(0), 64); check (`__LINE__, dpii_count(1), 32); diff --git a/test_regress/t/t_dpi_shortcircuit2.v b/test_regress/t/t_dpi_shortcircuit2.v index ae2ec9476..07b90a38e 100644 --- a/test_regress/t/t_dpi_shortcircuit2.v +++ b/test_regress/t/t_dpi_shortcircuit2.v @@ -28,19 +28,19 @@ module t (/*AUTOARG*/); integer i; integer j; integer k; - bit b; + bit b; integer errors; task check1(integer line, bit got, bit ex); if (got != ex) begin - $display("%%Error: Line %0d: Bad result, got=%0d expect=%0d",line,got,ex); - errors++; + $display("%%Error: Line %0d: Bad result, got=%0d expect=%0d",line,got,ex); + errors++; end endtask task check(integer line, int got, int ex); if (got != ex) begin - $display("%%Error: Line %0d: Bad result, got=%0d expect=%0d",line,got,ex); - errors++; + $display("%%Error: Line %0d: Bad result, got=%0d expect=%0d",line,got,ex); + errors++; end endtask @@ -52,11 +52,11 @@ module t (/*AUTOARG*/); // verilator lint_on IGNOREDRETURN j = 0; for (i=0; i<64; i++) begin - if (i[0]) - j = 0; - else - j = {31'b0, dpii_inc1(0)}; - k = k + j; + if (i[0]) + j = 0; + else + j = {31'b0, dpii_inc1(0)}; + k = k + j; end $write("%x\n",k); check (`__LINE__, dpii_count(0), 32); diff --git a/test_regress/t/t_dpi_var.v b/test_regress/t/t_dpi_var.v index 7909867bc..e5829cb89 100644 --- a/test_regress/t/t_dpi_var.v +++ b/test_regress/t/t_dpi_var.v @@ -16,10 +16,10 @@ module t (/*AUTOARG*/ wire monclk = ~clk; - int in; - int fr_a; - int fr_b; - int fr_chk; + int in; + int fr_a; + int fr_b; + int fr_chk; sub sub (.*); // Test loop @@ -30,18 +30,18 @@ module t (/*AUTOARG*/ cyc <= cyc + 1; in <= {in[30:0], in[31]^in[2]^in[0]}; if (cyc==0) begin - // Setup - in <= 32'hd70a4497; + // Setup + in <= 32'hd70a4497; end else if (cyc<3) begin end else if (cyc<10) begin - if (fr_chk != fr_a) $stop; - if (fr_chk != fr_b) $stop; + if (fr_chk != fr_a) $stop; + if (fr_chk != fr_b) $stop; end else if (cyc==10) begin - $write("*-* All Finished *-*\n"); - $finish; + $write("*-* All Finished *-*\n"); + $finish; end end diff --git a/test_regress/t/t_embed1.v b/test_regress/t/t_embed1.v index 0ba86f13c..94039be73 100644 --- a/test_regress/t/t_embed1.v +++ b/test_regress/t/t_embed1.v @@ -10,9 +10,9 @@ module t (/*AUTOARG*/ ); input clk; - integer cyc = 0; - reg [63:0] crc; - reg [63:0] sum; + integer cyc = 0; + reg [63:0] crc; + reg [63:0] sum; // Take CRC data and apply to testblock inputs wire bit_in = crc[0]; @@ -21,14 +21,14 @@ module t (/*AUTOARG*/ /*AUTOWIRE*/ // Beginning of automatic wires (for undeclared instantiated-module outputs) - wire exp_bit_out; // From reference of t_embed1_child.v - wire exp_did_init_out; // From reference of t_embed1_child.v - wire [30:0] exp_vec_out; // From reference of t_embed1_child.v - wire [123:0] exp_wide_out; // From reference of t_embed1_child.v - wire got_bit_out; // From test of t_embed1_wrap.v - wire got_did_init_out; // From test of t_embed1_wrap.v - wire [30:0] got_vec_out; // From test of t_embed1_wrap.v - wire [123:0] got_wide_out; // From test of t_embed1_wrap.v + wire exp_bit_out; // From reference of t_embed1_child.v + wire exp_did_init_out; // From reference of t_embed1_child.v + wire [30:0] exp_vec_out; // From reference of t_embed1_child.v + wire [123:0] exp_wide_out; // From reference of t_embed1_child.v + wire got_bit_out; // From test of t_embed1_wrap.v + wire got_did_init_out; // From test of t_embed1_wrap.v + wire [30:0] got_vec_out; // From test of t_embed1_wrap.v + wire [123:0] got_wide_out; // From test of t_embed1_wrap.v // End of automatics // A non-embedded master @@ -40,16 +40,16 @@ module t (/*AUTOARG*/ t_embed1_child reference (/*AUTOINST*/ // Outputs - .bit_out (exp_bit_out), // Templated - .vec_out (exp_vec_out[30:0]), // Templated - .wide_out (exp_wide_out[123:0]), // Templated - .did_init_out (exp_did_init_out), // Templated + .bit_out (exp_bit_out), // Templated + .vec_out (exp_vec_out[30:0]), // Templated + .wide_out (exp_wide_out[123:0]), // Templated + .did_init_out (exp_did_init_out), // Templated // Inputs - .clk (clk), - .bit_in (bit_in), - .vec_in (vec_in[30:0]), - .wide_in (wide_in[123:0]), - .is_ref (1'b1)); // Templated + .clk (clk), + .bit_in (bit_in), + .vec_in (vec_in[30:0]), + .wide_in (wide_in[123:0]), + .is_ref (1'b1)); // Templated // The embeded comparison @@ -61,49 +61,49 @@ module t (/*AUTOARG*/ t_embed1_wrap test (/*AUTOINST*/ // Outputs - .bit_out (got_bit_out), // Templated - .vec_out (got_vec_out[30:0]), // Templated - .wide_out (got_wide_out[123:0]), // Templated - .did_init_out (got_did_init_out), // Templated + .bit_out (got_bit_out), // Templated + .vec_out (got_vec_out[30:0]), // Templated + .wide_out (got_wide_out[123:0]), // Templated + .did_init_out (got_did_init_out), // Templated // Inputs - .clk (clk), - .bit_in (bit_in), - .vec_in (vec_in[30:0]), - .wide_in (wide_in[123:0]), - .is_ref (1'b0)); // Templated + .clk (clk), + .bit_in (bit_in), + .vec_in (vec_in[30:0]), + .wide_in (wide_in[123:0]), + .is_ref (1'b0)); // Templated // Aggregate outputs into a single result vector wire [63:0] result = {60'h0, - got_wide_out !== exp_wide_out, - got_vec_out !== exp_vec_out, - got_bit_out !== exp_bit_out, - got_did_init_out !== exp_did_init_out}; + got_wide_out !== exp_wide_out, + got_vec_out !== exp_vec_out, + got_bit_out !== exp_bit_out, + got_did_init_out !== exp_did_init_out}; // Test loop always @ (posedge clk) begin `ifdef TEST_VERBOSE $write("[%0t] cyc==%0d crc=%x result=%x gv=%x ev=%x\n", $time, cyc, crc, result, - got_vec_out, exp_vec_out); + got_vec_out, exp_vec_out); `endif cyc <= cyc + 1; crc <= {crc[62:0], crc[63] ^ crc[2] ^ crc[0]}; if (cyc==0) begin - // Setup - crc <= 64'h5aef0c8d_d70a4497; + // Setup + crc <= 64'h5aef0c8d_d70a4497; end else if (cyc<10) begin end else if (cyc<90) begin - if (result != 64'h0) begin - $display("Bit mismatch, result=%x\n", result); - $stop; - end + if (result != 64'h0) begin + $display("Bit mismatch, result=%x\n", result); + $stop; + end end else if (cyc==99) begin - $write("[%0t] cyc==%0d crc=%x sum=%x\n", $time, cyc, crc, sum); - if (crc !== 64'hc77bb9b3784ea091) $stop; - //Child prints this: $write("*-* All Finished *-*\n"); - $finish; + $write("[%0t] cyc==%0d crc=%x sum=%x\n", $time, cyc, crc, sum); + if (crc !== 64'hc77bb9b3784ea091) $stop; + //Child prints this: $write("*-* All Finished *-*\n"); + $finish; end end diff --git a/test_regress/t/t_embed1_child.v b/test_regress/t/t_embed1_child.v index 3a78275b3..1af251ffd 100644 --- a/test_regress/t/t_embed1_child.v +++ b/test_regress/t/t_embed1_child.v @@ -18,9 +18,9 @@ module t_embed1_child (/*AUTOARG*/ output logic [30:0] vec_out; input [123:0] wide_in; output logic [123:0] wide_out; - output did_init_out; + output did_init_out; - input is_ref; + input is_ref; reg did_init; initial did_init = 0; initial begin diff --git a/test_regress/t/t_embed1_wrap.v b/test_regress/t/t_embed1_wrap.v index 5aac6e631..27432fb5b 100644 --- a/test_regress/t/t_embed1_wrap.v +++ b/test_regress/t/t_embed1_wrap.v @@ -17,11 +17,11 @@ module t_embed1_wrap (/*AUTOARG*/ output bit [30:0] vec_out; output bit [123:0] wide_out; output bit did_init_out; - input clk; - input bit_in; - input [30:0] vec_in; - input [123:0] wide_in; - input is_ref; + input clk; + input bit_in; + input [30:0] vec_in; + input [123:0] wide_in; + input is_ref; // End of automatics `ifdef verilator @@ -61,16 +61,16 @@ module t_embed1_wrap (/*AUTOARG*/ bit [123:0] _temp_wide_out; always @* begin t_embed_child_io_eval( - clk, - bit_in, - vec_in, - wide_in, - is_ref, - _temp_bit_out, - _temp_vec_out, - _temp_wide_out, - _temp_did_init_out - ); + clk, + bit_in, + vec_in, + wide_in, + is_ref, + _temp_bit_out, + _temp_vec_out, + _temp_wide_out, + _temp_did_init_out + ); // TODO might eliminate these temporaries bit_out = _temp_bit_out; did_init_out = _temp_did_init_out; diff --git a/test_regress/t/t_emit_constw.v b/test_regress/t/t_emit_constw.v index 20fa8a9ed..a265089db 100644 --- a/test_regress/t/t_emit_constw.v +++ b/test_regress/t/t_emit_constw.v @@ -12,9 +12,9 @@ module t (/*AUTOARG*/ ); input clk; - integer cyc = 0; - reg [63:0] crc; - reg [63:0] sum; + integer cyc = 0; + reg [63:0] crc; + reg [63:0] sum; bit [4*32-1:0] w4 = {32'h7c709753, 32'hbc8f6059, 32'h3b0db464, 32'h721a8fad}; @@ -25,26 +25,26 @@ module t (/*AUTOARG*/ bit [8*32-0:0] w8p = {1'b1, 32'h096aa54b, 32'h48aae18e, 32'hf9502cea, 32'h518c8b61, 32'h9e8641a2, 32'h0dc0249c, 32'hd421a87a, 32'hb8ee9199}; bit [9*32-1:0] w9 = {32'hca800ac1, - 32'h0de4823a, 32'ha51663ac, 32'h96351446, 32'h6b0bbcd5, 32'h4a64b530, 32'h4967d59a, 32'hfcc17292, 32'h57926621}; + 32'h0de4823a, 32'ha51663ac, 32'h96351446, 32'h6b0bbcd5, 32'h4a64b530, 32'h4967d59a, 32'hfcc17292, 32'h57926621}; bit [16*32-2:0] w16m = {31'h77ad72c7, 32'h73aa9cbb, 32'h7ecf026d, 32'h985a3ed2, 32'hfe961c1d, 32'h7a01df72, 32'h79e13d71, 32'hb69e2e32, - 32'h09fcbc45, 32'hcfd738c1, 32'hc197ac7c, 32'hc316d727, 32'h903034e4, 32'h92a047d1, 32'h6a5357af, 32'ha82ce9c8}; + 32'h09fcbc45, 32'hcfd738c1, 32'hc197ac7c, 32'hc316d727, 32'h903034e4, 32'h92a047d1, 32'h6a5357af, 32'ha82ce9c8}; bit [16*32-1:0] w16 = {32'he49548a7, 32'ha02336a2, 32'h2bb48f0d, 32'h9974e098, 32'h34ae644f, 32'hca46dc2c, 32'h9f71a468, 32'h64ae043e, - 32'h7bc94d66, 32'h57aba588, 32'h5b9bb4fe, 32'hb87ed644, 32'hd34b5b20, 32'h712928de, 32'h4bdbd28e, 32'ha0576784}; + 32'h7bc94d66, 32'h57aba588, 32'h5b9bb4fe, 32'hb87ed644, 32'hd34b5b20, 32'h712928de, 32'h4bdbd28e, 32'ha0576784}; bit [16*32-0:0] w16p = {1'b1, 32'hd278a306, 32'h374ce262, 32'hb608c88e, 32'h43d3e446, 32'h42e26866, 32'h44c31148, 32'hd3db659f, 32'hb3b84b2e, - 32'h1aa7a184, 32'h73b28538, 32'h6384e801, 32'h98d58e00, 32'h9c1d1429, 32'hb407730e, 32'he974c1fd, 32'he787c302}; + 32'h1aa7a184, 32'h73b28538, 32'h6384e801, 32'h98d58e00, 32'h9c1d1429, 32'hb407730e, 32'he974c1fd, 32'he787c302}; bit [17*32-1:0] w17 = {32'hf1e322ac, - 32'hbbdbd761, 32'h760fe07d, 32'h3808cb28, 32'haf313051, 32'h37dc63b9, 32'hdddb418b, 32'he65a9d64, 32'hc1b6ab23, - 32'h11131ac1, 32'h0050e0bc, 32'h442e3754, 32'h0eb4556e, 32'hd153064b, 32'h41349f97, 32'hb6f4149f, 32'h34bb1fb1}; + 32'hbbdbd761, 32'h760fe07d, 32'h3808cb28, 32'haf313051, 32'h37dc63b9, 32'hdddb418b, 32'he65a9d64, 32'hc1b6ab23, + 32'h11131ac1, 32'h0050e0bc, 32'h442e3754, 32'h0eb4556e, 32'hd153064b, 32'h41349f97, 32'hb6f4149f, 32'h34bb1fb1}; function [7:0] bytehash (input [32*32-1:0] data); integer i; bytehash = 0; for (i=0; i<32*32; ++i) begin - bytehash = {bytehash[0], bytehash[7:1]} ^ data[i +: 8]; + bytehash = {bytehash[0], bytehash[7:1]} ^ data[i +: 8]; end return bytehash; endfunction @@ -52,14 +52,14 @@ module t (/*AUTOARG*/ // Aggregate outputs into a single result vector // verilator lint_off WIDTH wire [63:0] result = (bytehash(w4) - ^ bytehash(w8m) - ^ bytehash(w8) - ^ bytehash(w8p) - ^ bytehash(w9) - ^ bytehash(w16m) - ^ bytehash(w16) - ^ bytehash(w16p) - ^ bytehash(w17)); + ^ bytehash(w8m) + ^ bytehash(w8) + ^ bytehash(w8p) + ^ bytehash(w9) + ^ bytehash(w16m) + ^ bytehash(w16) + ^ bytehash(w16p) + ^ bytehash(w17)); // verilator lint_on WIDTH `define EXPECTED_SUM 64'h2bc7c2a98a302891 @@ -73,8 +73,8 @@ module t (/*AUTOARG*/ crc <= {crc[62:0], crc[63] ^ crc[2] ^ crc[0]}; sum <= result ^ {sum[62:0], sum[63] ^ sum[2] ^ sum[0]}; if (cyc==0) begin - // Setup - crc <= 64'h5aef0c8d_d70a4497; + // Setup + crc <= 64'h5aef0c8d_d70a4497; // verilator lint_off SELRANGE `checkhw(w4,3,32'h7c709753); `checkhw(w4,2,32'hbc8f6059); @@ -133,25 +133,25 @@ module t (/*AUTOARG*/ // verilator lint_on SELRANGE end else if (cyc<10) begin - sum <= 64'h0; + sum <= 64'h0; end else if (cyc<90) begin - w4 = w4 >>> 1; - w8m = w8m >>> 1; - w8 = w8 >>> 1; - w8p = w8p >>> 1; - w9 = w9 >>> 1; - w16m = w16m >>> 1; - w16 = w16 >>> 1; - w16p = w16p >>> 1; - w17 = w17 >>> 1; + w4 = w4 >>> 1; + w8m = w8m >>> 1; + w8 = w8 >>> 1; + w8p = w8p >>> 1; + w9 = w9 >>> 1; + w16m = w16m >>> 1; + w16 = w16 >>> 1; + w16p = w16p >>> 1; + w17 = w17 >>> 1; end else if (cyc==99) begin - $write("[%0t] cyc==%0d crc=%x sum=%x\n", $time, cyc, crc, sum); - if (crc !== 64'hc77bb9b3784ea091) $stop; - if (sum !== `EXPECTED_SUM) $stop; - $write("*-* All Finished *-*\n"); - $finish; + $write("[%0t] cyc==%0d crc=%x sum=%x\n", $time, cyc, crc, sum); + if (crc !== 64'hc77bb9b3784ea091) $stop; + if (sum !== `EXPECTED_SUM) $stop; + $write("*-* All Finished *-*\n"); + $finish; end end diff --git a/test_regress/t/t_enum.v b/test_regress/t/t_enum.v index 569c2e4b3..2182ce9de 100644 --- a/test_regress/t/t_enum.v +++ b/test_regress/t/t_enum.v @@ -16,20 +16,20 @@ module t (/*AUTOARG*/); localparam FIVE = 5; enum { e0, - e1, - e3=3, - e5=FIVE, - e10_[2] = 10, - e12, - e20_[5:7] = 25, - e20_z, - e30_[7:5] = 30, - e30_z - } EN; + e1, + e3=3, + e5=FIVE, + e10_[2] = 10, + e12, + e20_[5:7] = 25, + e20_z, + e30_[7:5] = 30, + e30_z + } EN; enum { - z5 = e5 - } ZN; + z5 = e5 + } ZN; typedef enum three_t; // Forward typedef enum [2:0] { ONES=~0 } three_t; @@ -38,7 +38,7 @@ module t (/*AUTOARG*/); var logic [ONES:0] sized_based_on_enum; var enum logic [3:0] { QINVALID='1, QSEND={2'b0,2'h0}, QOP={2'b0,2'h1}, QCL={2'b0,2'h2}, - QPR={2'b0,2'h3 }, QACK, QRSP } inv; + QPR={2'b0,2'h3 }, QACK, QRSP } inv; initial begin if (e0 !== 0) $stop; diff --git a/test_regress/t/t_enum_func.v b/test_regress/t/t_enum_func.v index e9ae74c70..429c2a7bb 100644 --- a/test_regress/t/t_enum_func.v +++ b/test_regress/t/t_enum_func.v @@ -5,8 +5,8 @@ // SPDX-License-Identifier: CC0-1.0 typedef enum { EN_ZERO, - EN_ONE - } En_t; + EN_ONE + } En_t; module t (/*AUTOARG*/ // Inputs @@ -16,9 +16,9 @@ module t (/*AUTOARG*/ // Insure that we can declare a type with a function declaration function enum integer { - EF_TRUE = 1, - EF_FALSE = 0 } - f_enum_inv ( input a); + EF_TRUE = 1, + EF_FALSE = 0 } + f_enum_inv ( input a); f_enum_inv = a ? EF_FALSE : EF_TRUE; endfunction initial begin @@ -29,29 +29,29 @@ module t (/*AUTOARG*/ En_t a, z; sub sub (/*AUTOINST*/ - // Outputs - .z (z), - // Inputs - .a (a)); + // Outputs + .z (z), + // Inputs + .a (a)); integer cyc; initial cyc=1; always @ (posedge clk) begin if (cyc!=0) begin - cyc <= cyc + 1; - if (cyc==1) begin - a <= EN_ZERO; - end - if (cyc==2) begin - a <= EN_ONE; - if (z != EN_ONE) $stop; - end - if (cyc==3) begin - if (z != EN_ZERO) $stop; - end - if (cyc==9) begin - $write("*-* All Finished *-*\n"); - $finish; - end + cyc <= cyc + 1; + if (cyc==1) begin + a <= EN_ZERO; + end + if (cyc==2) begin + a <= EN_ONE; + if (z != EN_ONE) $stop; + end + if (cyc==3) begin + if (z != EN_ZERO) $stop; + end + if (cyc==9) begin + $write("*-* All Finished *-*\n"); + $finish; + end end end diff --git a/test_regress/t/t_enum_huge_methods_bad.out b/test_regress/t/t_enum_huge_methods_bad.out index 885a3cd7f..b5d5e6853 100644 --- a/test_regress/t/t_enum_huge_methods_bad.out +++ b/test_regress/t/t_enum_huge_methods_bad.out @@ -1,9 +1,9 @@ -%Error: t/t_enum_huge_methods_bad.v:15:11: Value too wide for 64-bits expected in this context 160'h12344567abcd12344567abcd - 15 | ELARGE = 160'h1234_4567_abcd_1234_4567_abcd - | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -%Error-UNSUPPORTED: t/t_enum_huge_methods_bad.v:30:14: Unsupported: enum next/prev/name method on enum with > 64 bits +%Error: t/t_enum_huge_methods_bad.v:15:18: Value too wide for 64-bits expected in this context 160'h12344567abcd12344567abcd + 15 | ELARGE = 160'h1234_4567_abcd_1234_4567_abcd + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +%Error-UNSUPPORTED: t/t_enum_huge_methods_bad.v:30:21: Unsupported: enum next/prev/name method on enum with > 64 bits : ... In instance t - 30 | $display(e.name); - | ^~~~ + 30 | $display(e.name); + | ^~~~ ... For error description see https://verilator.org/warn/UNSUPPORTED?v=latest %Error: Exiting due to diff --git a/test_regress/t/t_enum_huge_methods_bad.v b/test_regress/t/t_enum_huge_methods_bad.v index 8502a98c0..21bcc4fcc 100644 --- a/test_regress/t/t_enum_huge_methods_bad.v +++ b/test_regress/t/t_enum_huge_methods_bad.v @@ -12,27 +12,27 @@ module t (/*AUTOARG*/ typedef enum logic [159:0] { E01 = 160'h1, - ELARGE = 160'h1234_4567_abcd_1234_4567_abcd - } my_t; + ELARGE = 160'h1234_4567_abcd_1234_4567_abcd + } my_t; my_t e; - int cyc; + int cyc; // Check runtime always @ (posedge clk) begin cyc <= cyc + 1; if (cyc==0) begin - // Setup - e <= E01; + // Setup + e <= E01; end else if (cyc==1) begin - $display(e.name); - e <= ELARGE; + $display(e.name); + e <= ELARGE; end else if (cyc==99) begin - $write("*-* All Finished *-*\n"); - $finish; + $write("*-* All Finished *-*\n"); + $finish; end end diff --git a/test_regress/t/t_enum_int.v b/test_regress/t/t_enum_int.v index a23b8a91e..368c6b64b 100644 --- a/test_regress/t/t_enum_int.v +++ b/test_regress/t/t_enum_int.v @@ -13,32 +13,32 @@ module t (/*AUTOARG*/ enum integer { - EP_State_IDLE , - EP_State_CMDSHIFT0 , - EP_State_CMDSHIFT13 , - EP_State_CMDSHIFT14 , - EP_State_CMDSHIFT15 , - EP_State_CMDSHIFT16 , - EP_State_DWAIT , - EP_State_DSHIFT0 , - EP_State_DSHIFT1 , - EP_State_DSHIFT15 } m_state_xr, m_state2_xr; + EP_State_IDLE , + EP_State_CMDSHIFT0 , + EP_State_CMDSHIFT13 , + EP_State_CMDSHIFT14 , + EP_State_CMDSHIFT15 , + EP_State_CMDSHIFT16 , + EP_State_DWAIT , + EP_State_DSHIFT0 , + EP_State_DSHIFT1 , + EP_State_DSHIFT15 } m_state_xr, m_state2_xr; // Beginning of automatic ASCII enum decoding - reg [79:0] m_stateAscii_xr; // Decode of m_state_xr + reg [79:0] m_stateAscii_xr; // Decode of m_state_xr always @(m_state_xr) begin case ({m_state_xr}) - EP_State_IDLE: m_stateAscii_xr = "idle "; - EP_State_CMDSHIFT0: m_stateAscii_xr = "cmdshift0 "; - EP_State_CMDSHIFT13: m_stateAscii_xr = "cmdshift13"; - EP_State_CMDSHIFT14: m_stateAscii_xr = "cmdshift14"; - EP_State_CMDSHIFT15: m_stateAscii_xr = "cmdshift15"; - EP_State_CMDSHIFT16: m_stateAscii_xr = "cmdshift16"; - EP_State_DWAIT: m_stateAscii_xr = "dwait "; - EP_State_DSHIFT0: m_stateAscii_xr = "dshift0 "; - EP_State_DSHIFT1: m_stateAscii_xr = "dshift1 "; - EP_State_DSHIFT15: m_stateAscii_xr = "dshift15 "; - default: m_stateAscii_xr = "%Error "; + EP_State_IDLE: m_stateAscii_xr = "idle "; + EP_State_CMDSHIFT0: m_stateAscii_xr = "cmdshift0 "; + EP_State_CMDSHIFT13: m_stateAscii_xr = "cmdshift13"; + EP_State_CMDSHIFT14: m_stateAscii_xr = "cmdshift14"; + EP_State_CMDSHIFT15: m_stateAscii_xr = "cmdshift15"; + EP_State_CMDSHIFT16: m_stateAscii_xr = "cmdshift16"; + EP_State_DWAIT: m_stateAscii_xr = "dwait "; + EP_State_DSHIFT0: m_stateAscii_xr = "dshift0 "; + EP_State_DSHIFT1: m_stateAscii_xr = "dshift1 "; + EP_State_DSHIFT15: m_stateAscii_xr = "dshift15 "; + default: m_stateAscii_xr = "%Error "; endcase end // End of automatics @@ -46,36 +46,36 @@ module t (/*AUTOARG*/ integer cyc; initial cyc=1; always @ (posedge clk) begin if (cyc!=0) begin - cyc <= cyc + 1; - //$write("%d %x %x %x\n", cyc, data, wrapcheck_a, wrapcheck_b); - if (cyc==1) begin - m_state_xr <= EP_State_IDLE; - m_state2_xr <= EP_State_IDLE; - end - if (cyc==2) begin - if (m_stateAscii_xr != "idle ") $stop; - m_state_xr <= EP_State_CMDSHIFT13; - if (m_state2_xr != EP_State_IDLE) $stop; - m_state2_xr <= EP_State_CMDSHIFT13; - end - if (cyc==3) begin - if (m_stateAscii_xr != "cmdshift13") $stop; - m_state_xr <= EP_State_CMDSHIFT16; - if (m_state2_xr != EP_State_CMDSHIFT13) $stop; - m_state2_xr <= EP_State_CMDSHIFT16; - end - if (cyc==4) begin - if (m_stateAscii_xr != "cmdshift16") $stop; - m_state_xr <= EP_State_DWAIT; - if (m_state2_xr != EP_State_CMDSHIFT16) $stop; - m_state2_xr <= EP_State_DWAIT; - end - if (cyc==9) begin - if (m_stateAscii_xr != "dwait ") $stop; - if (m_state2_xr != EP_State_DWAIT) $stop; - $write("*-* All Finished *-*\n"); - $finish; - end + cyc <= cyc + 1; + //$write("%d %x %x %x\n", cyc, data, wrapcheck_a, wrapcheck_b); + if (cyc==1) begin + m_state_xr <= EP_State_IDLE; + m_state2_xr <= EP_State_IDLE; + end + if (cyc==2) begin + if (m_stateAscii_xr != "idle ") $stop; + m_state_xr <= EP_State_CMDSHIFT13; + if (m_state2_xr != EP_State_IDLE) $stop; + m_state2_xr <= EP_State_CMDSHIFT13; + end + if (cyc==3) begin + if (m_stateAscii_xr != "cmdshift13") $stop; + m_state_xr <= EP_State_CMDSHIFT16; + if (m_state2_xr != EP_State_CMDSHIFT13) $stop; + m_state2_xr <= EP_State_CMDSHIFT16; + end + if (cyc==4) begin + if (m_stateAscii_xr != "cmdshift16") $stop; + m_state_xr <= EP_State_DWAIT; + if (m_state2_xr != EP_State_CMDSHIFT16) $stop; + m_state2_xr <= EP_State_DWAIT; + end + if (cyc==9) begin + if (m_stateAscii_xr != "dwait ") $stop; + if (m_state2_xr != EP_State_DWAIT) $stop; + $write("*-* All Finished *-*\n"); + $finish; + end end end diff --git a/test_regress/t/t_enum_large_methods.v b/test_regress/t/t_enum_large_methods.v index 84255f66e..7e24b50a8 100644 --- a/test_regress/t/t_enum_large_methods.v +++ b/test_regress/t/t_enum_large_methods.v @@ -14,11 +14,11 @@ module t (/*AUTOARG*/ input clk; typedef enum { - E01 = 'h1, - ELARGE = 'hf00d - } my_t; + E01 = 'h1, + ELARGE = 'hf00d + } my_t; - integer cyc = 0; + integer cyc = 0; my_t e; string all; @@ -27,29 +27,29 @@ module t (/*AUTOARG*/ always @ (posedge clk) begin cyc <= cyc + 1; if (cyc==0) begin - // Setup - e <= E01; + // Setup + e <= E01; end else if (cyc==1) begin - `checks(e.name, "E01"); - `checkh(e.next, ELARGE); - e <= ELARGE; + `checks(e.name, "E01"); + `checkh(e.next, ELARGE); + e <= ELARGE; end else if (cyc==3) begin - `checks(e.name, "ELARGE"); - `checkh(e.next, E01); - `checkh(e.prev, E01); - e <= E01; + `checks(e.name, "ELARGE"); + `checkh(e.next, E01); + `checkh(e.prev, E01); + e <= E01; end else if (cyc==20) begin - e <= my_t'('h11); // Unknown + e <= my_t'('h11); // Unknown end else if (cyc==21) begin - `checks(e.name, ""); // Unknown + `checks(e.name, ""); // Unknown end else if (cyc==99) begin - $write("*-* All Finished *-*\n"); - $finish; + $write("*-* All Finished *-*\n"); + $finish; end end diff --git a/test_regress/t/t_enum_name2.v b/test_regress/t/t_enum_name2.v index 0048905aa..776692f30 100644 --- a/test_regress/t/t_enum_name2.v +++ b/test_regress/t/t_enum_name2.v @@ -6,11 +6,11 @@ package our_pkg; typedef enum logic [8-1:0] { - ADC_IN2IN = 8'h99, - ADC_IMMED = 8'h88, - ADC_INDIR = 8'h86, - ADC_INIDX = 8'h97 - } T_Opcode; + ADC_IN2IN = 8'h99, + ADC_IMMED = 8'h88, + ADC_INDIR = 8'h86, + ADC_INIDX = 8'h97 + } T_Opcode; endpackage : our_pkg module t (); diff --git a/test_regress/t/t_enum_public.v b/test_regress/t/t_enum_public.v index 60ed94800..4fcf012ff 100644 --- a/test_regress/t/t_enum_public.v +++ b/test_regress/t/t_enum_public.v @@ -22,10 +22,10 @@ endpackage module t (/*AUTOARG*/); enum integer { - EI_A, - EI_B, - EI_C - } m_state; + EI_A, + EI_B, + EI_C + } m_state; initial begin m_state = EI_A; diff --git a/test_regress/t/t_enum_type_methods.v b/test_regress/t/t_enum_type_methods.v index 5d30a0534..8328a729b 100644 --- a/test_regress/t/t_enum_type_methods.v +++ b/test_regress/t/t_enum_type_methods.v @@ -14,12 +14,12 @@ module t (/*AUTOARG*/ input clk; typedef enum [3:0] { - E01 = 1, - E03 = 3, - E04 = 4 - } my_t; + E01 = 1, + E03 = 3, + E04 = 4 + } my_t; - integer cyc = 0; + integer cyc = 0; my_t e; int arrayfits [e.num]; // Check can use as constant @@ -49,7 +49,7 @@ module t (/*AUTOARG*/ // all = ""; for (my_t e = e.first; e != e.last; e = e.next) begin - all = {all, e.name}; + all = {all, e.name}; end e = e.last; all = {all, e.name}; @@ -60,42 +60,42 @@ module t (/*AUTOARG*/ always @ (posedge clk) begin cyc <= cyc + 1; if (cyc==0) begin - // Setup - e <= E01; + // Setup + e <= E01; end else if (cyc==1) begin - `checks(e.name, "E01"); - `checkh(e.next, E03); - `checkh(e.next(1), E03); - `checkh(e.next(2), E04); - `checkh(e.prev, E04); - `checkh(e.prev(1), E04); - `checkh(e.prev(2), E03); - e <= E03; + `checks(e.name, "E01"); + `checkh(e.next, E03); + `checkh(e.next(1), E03); + `checkh(e.next(2), E04); + `checkh(e.prev, E04); + `checkh(e.prev(1), E04); + `checkh(e.prev(2), E03); + e <= E03; end else if (cyc==2) begin - `checks(e.name, "E03"); - `checkh(e.next, E04); - `checkh(e.next(1), E04); - `checkh(e.next(2), E01); - `checkh(e.prev, E01); - `checkh(e.prev(1), E01); - `checkh(e.prev(2), E04); - e <= E04; + `checks(e.name, "E03"); + `checkh(e.next, E04); + `checkh(e.next(1), E04); + `checkh(e.next(2), E01); + `checkh(e.prev, E01); + `checkh(e.prev(1), E01); + `checkh(e.prev(2), E04); + e <= E04; end else if (cyc==3) begin - `checks(e.name, "E04"); - `checkh(e.next, E01); - `checkh(e.next(1), E01); - `checkh(e.next(2), E03); - `checkh(e.prev, E03); - `checkh(e.prev(1), E03); - `checkh(e.prev(2), E01); - e <= E01; + `checks(e.name, "E04"); + `checkh(e.next, E01); + `checkh(e.next(1), E01); + `checkh(e.next(2), E03); + `checkh(e.prev, E03); + `checkh(e.prev(1), E03); + `checkh(e.prev(2), E01); + e <= E01; end else if (cyc==99) begin - $write("*-* All Finished *-*\n"); - $finish; + $write("*-* All Finished *-*\n"); + $finish; end end diff --git a/test_regress/t/t_enum_type_pins.v b/test_regress/t/t_enum_type_pins.v index de16dc9d5..eaeb9d3d5 100644 --- a/test_regress/t/t_enum_type_pins.v +++ b/test_regress/t/t_enum_type_pins.v @@ -56,8 +56,8 @@ module t (/*AUTOARG*/ reg c; test test_i (/*AUTOINST*/ - // Inputs - .clk (clk)); + // Inputs + .clk (clk)); // This is a compile time only test. Immediately finish always @(posedge clk) begin @@ -76,7 +76,7 @@ module test (/*AUTOARG*/ // Use the enumeration size to initialize a dynamic array t_pinid e; - int myarray1 [] = new [e.num]; + int myarray1 [] = new [e.num]; always @(posedge clk) begin @@ -87,18 +87,18 @@ module test (/*AUTOARG*/ e = e.first; forever begin - myarray1[e] <= e.prev; + myarray1[e] <= e.prev; `ifdef TEST_VERBOSE - $write ("myarray1[%d] (enum %s) = %d\n", e, e.name, myarray1[e]); + $write ("myarray1[%d] (enum %s) = %d\n", e, e.name, myarray1[e]); `endif - if (e == e.last) begin - break; - end - else begin - e = e.next; - end + if (e == e.last) begin + break; + end + else begin + e = e.next; + end end end diff --git a/test_regress/t/t_extend.v b/test_regress/t/t_extend.v index 7a0c372b3..78cd9ede5 100644 --- a/test_regress/t/t_extend.v +++ b/test_regress/t/t_extend.v @@ -14,7 +14,7 @@ module t (/*AUTOARG*/ input clk; // No verilator_public needed, because it's outside the "" in the $c statement reg [7:0] cyc; initial cyc = 0; - reg c_worked; + reg c_worked; reg [8:0] c_wider; wire one = 1'b1; @@ -28,23 +28,23 @@ module t (/*AUTOARG*/ if (cyc[0]) begin end if (!cyc[0]) begin end // multiple on a line if (cyc == 8'd1) begin - c_worked <= 0; + c_worked <= 0; end if (cyc == 8'd2) begin `ifdef VERILATOR - $c("VL_PRINTF(\"Calling $c, calling $c...\\n\");"); - $c("VL_PRINTF(\"Cyc=%d\\n\",", cyc, ");"); - c_worked <= $c("this->my_function()"); - c_wider <= $c9("0x10"); + $c("VL_PRINTF(\"Calling $c, calling $c...\\n\");"); + $c("VL_PRINTF(\"Cyc=%d\\n\",", cyc, ");"); + c_worked <= $c("this->my_function()"); + c_wider <= $c9("0x10"); `else - c_worked <= 1'b1; - c_wider <= 9'h10; + c_worked <= 1'b1; + c_wider <= 9'h10; `endif end if (cyc == 8'd3) begin - if (c_worked !== 1'b1) $stop; - if (c_wider !== 9'h10) $stop; - $finish; + if (c_worked !== 1'b1) $stop; + if (c_wider !== 9'h10) $stop; + $finish; end end diff --git a/test_regress/t/t_extend_class.v b/test_regress/t/t_extend_class.v index a12826fc6..5ecbf8c4a 100644 --- a/test_regress/t/t_extend_class.v +++ b/test_regress/t/t_extend_class.v @@ -19,14 +19,14 @@ module t (/*AUTOARG*/ always @ (posedge clk) begin cyc <= cyc + 8'd1; if (cyc == 8'd1) begin - in <= 32'h10; + in <= 32'h10; end if (cyc == 8'd2) begin - if (out != 32'h11) $stop; + if (out != 32'h11) $stop; end if (cyc == 8'd9) begin - $write("*-* All Finished *-*\n"); - $finish; + $write("*-* All Finished *-*\n"); + $finish; end end endmodule @@ -47,13 +47,13 @@ module t_extend_class_v (/*AUTOARG*/ end `systemc_header -#include "t_extend_class_c.h" // Header for contained object +#include "t_extend_class_c.h" // Header for contained object `systemc_interface - t_extend_class_c* m_myobjp; // Pointer to object we are embedding + t_extend_class_c* m_myobjp; // Pointer to object we are embedding `systemc_ctor - m_myobjp = new t_extend_class_c(); // Construct contained object + m_myobjp = new t_extend_class_c(); // Construct contained object `systemc_dtor - delete m_myobjp; // Destruct contained object + delete m_myobjp; // Destruct contained object `verilog endmodule diff --git a/test_regress/t/t_flag_compiler.v b/test_regress/t/t_flag_compiler.v index df8446ba5..826dc2ddd 100644 --- a/test_regress/t/t_flag_compiler.v +++ b/test_regress/t/t_flag_compiler.v @@ -10,25 +10,25 @@ module t (/*AUTOARG*/ ); input clk; - integer cyc = 0; + integer cyc = 0; - reg [89:0] in; + reg [89:0] in; /*AUTOWIRE*/ // Beginning of automatic wires (for undeclared instantiated-module outputs) - wire [89:0] out; // From test of Test.v - wire [44:0] line0; - wire [44:0] line1; + wire [89:0] out; // From test of Test.v + wire [44:0] line0; + wire [44:0] line1; // End of automatics Test test (/*AUTOINST*/ - // Outputs - .out (out[89:0]), - .line0 (line0[44:0]), - .line1 (line1[44:0]), - // Inputs - .clk (clk), - .in (in[89:0])); + // Outputs + .out (out[89:0]), + .line0 (line0[44:0]), + .line1 (line1[44:0]), + // Inputs + .clk (clk), + .in (in[89:0])); // Test loop always @ (posedge clk) begin @@ -37,18 +37,18 @@ module t (/*AUTOARG*/ `endif cyc <= cyc + 1; if (cyc==0) begin - // Setup - in <= 90'h3FFFFFFFFFFFFFFFFFFFFFF; + // Setup + in <= 90'h3FFFFFFFFFFFFFFFFFFFFFF; end else if (cyc==10) begin if (in==out) begin - $write("*-* All Finished *-*\n"); - $finish; - end - else begin - $write("*-* Failed!! *-*\n"); - $finish; - end + $write("*-* All Finished *-*\n"); + $finish; + end + else begin + $write("*-* Failed!! *-*\n"); + $finish; + end end end @@ -64,9 +64,9 @@ module Test (/*AUTOARG*/ input clk; input [89:0] in; - output reg [44:0] line0; - output reg [44:0] line1; - output reg [89:0] out; + output reg [44:0] line0; + output reg [44:0] line1; + output reg [89:0] out; assign {line0,line1} = in; always @(posedge clk) begin diff --git a/test_regress/t/t_flag_topmodule_inline.v b/test_regress/t/t_flag_topmodule_inline.v index 45904e3ae..4a75d8099 100644 --- a/test_regress/t/t_flag_topmodule_inline.v +++ b/test_regress/t/t_flag_topmodule_inline.v @@ -23,8 +23,8 @@ endmodule module l3 (input tmp); initial begin if (tmp) begin - $write("*-* All Finished *-*\n"); - $finish; + $write("*-* All Finished *-*\n"); + $finish; end end endmodule diff --git a/test_regress/t/t_for_break.v b/test_regress/t/t_for_break.v index fabb7b3b9..0b12b7d38 100644 --- a/test_regress/t/t_for_break.v +++ b/test_regress/t/t_for_break.v @@ -10,9 +10,9 @@ module t (/*AUTOARG*/ ); input clk; - integer cyc = 0; - reg [63:0] crc; - reg [63:0] sum; + integer cyc = 0; + reg [63:0] crc; + reg [63:0] sum; // Take CRC data and apply to testblock inputs wire [3:0] l_stop = crc[3:0]; @@ -38,26 +38,26 @@ module t (/*AUTOARG*/ crc <= {crc[62:0], crc[63] ^ crc[2] ^ crc[0]}; sum <= result ^ {sum[62:0], sum[63] ^ sum[2] ^ sum[0]}; if (cyc==0) begin - // Setup - crc <= 64'h5aef0c8d_d70a4497; - sum <= 64'h0; + // Setup + crc <= 64'h5aef0c8d_d70a4497; + sum <= 64'h0; end else if (cyc<10) begin - sum <= 64'h0; + sum <= 64'h0; end else if (cyc<90) begin - if (out0!==out1) $stop; - if (out0!==out2) $stop; - if (out0!==out3) $stop; + if (out0!==out1) $stop; + if (out0!==out2) $stop; + if (out0!==out3) $stop; end else if (cyc==99) begin - $write("[%0t] cyc==%0d crc=%x sum=%x\n", $time, cyc, crc, sum); - if (crc !== 64'hc77bb9b3784ea091) $stop; - // What checksum will we end up with (above print should match) + $write("[%0t] cyc==%0d crc=%x sum=%x\n", $time, cyc, crc, sum); + if (crc !== 64'hc77bb9b3784ea091) $stop; + // What checksum will we end up with (above print should match) `define EXPECTED_SUM 64'h293e9f9798e97da0 - if (sum !== `EXPECTED_SUM) $stop; - $write("*-* All Finished *-*\n"); - $finish; + if (sum !== `EXPECTED_SUM) $stop; + $write("*-* All Finished *-*\n"); + $finish; end end @@ -65,25 +65,25 @@ module t (/*AUTOARG*/ input [3:0] loop_stop; input [3:0] loop_break; input [3:0] loop_continue; - integer i; - reg broken; + integer i; + reg broken; Test0 = 0; broken = 0; begin - for (i=1; i<20; i=i+1) begin - if (!broken) begin - Test0 = Test0 + 1; - if (i[3:0] != loop_continue) begin // continue - if (i[3:0] == loop_break) begin - broken = 1'b1; - end - if (!broken) begin - Test0 = Test0 + i[15:0]; - end - end - end - end + for (i=1; i<20; i=i+1) begin + if (!broken) begin + Test0 = Test0 + 1; + if (i[3:0] != loop_continue) begin // continue + if (i[3:0] == loop_break) begin + broken = 1'b1; + end + if (!broken) begin + Test0 = Test0 + i[15:0]; + end + end + end + end end endfunction @@ -91,17 +91,17 @@ module t (/*AUTOARG*/ input [3:0] loop_stop; input [3:0] loop_break; input [3:0] loop_continue; - integer i; + integer i; Test1 = 0; begin : outer_block for (i=1; i<20; i=i+1) begin : inner_block - Test1 = Test1 + 1; - // continue, IE jump to end-of-inner_block. Must be inside inner_block. + Test1 = Test1 + 1; + // continue, IE jump to end-of-inner_block. Must be inside inner_block. if (i[3:0] == loop_continue) disable inner_block; - // break, IE jump to end-of-outer_block. Must be inside outer_block. - if (i[3:0] == loop_break) disable outer_block; - Test1 = Test1 + i[15:0]; + // break, IE jump to end-of-outer_block. Must be inside outer_block. + if (i[3:0] == loop_break) disable outer_block; + Test1 = Test1 + i[15:0]; end : inner_block end : outer_block endfunction @@ -110,15 +110,15 @@ module t (/*AUTOARG*/ input [3:0] loop_stop; input [3:0] loop_break; input [3:0] loop_continue; - integer i; + integer i; Test2 = 0; begin for (i=1; i<20; i=i+1) begin - Test2 = Test2 + 1; - if (i[3:0] == loop_continue) continue; - if (i[3:0] == loop_break) break; - Test2 = Test2 + i[15:0]; + Test2 = Test2 + 1; + if (i[3:0] == loop_continue) continue; + if (i[3:0] == loop_break) break; + Test2 = Test2 + i[15:0]; end end endfunction @@ -127,16 +127,16 @@ module t (/*AUTOARG*/ input [3:0] loop_stop; input [3:0] loop_break; input [3:0] loop_continue; - integer i; + integer i; Test3 = 0; begin for (i=1; i<20; i=i+1) begin - Test3 = Test3 + 1; - if (i[3:0] == loop_continue) continue; - // return, IE jump to end-of-function optionally setting return value - if (i[3:0] == loop_break) return Test3; - Test3 = Test3 + i[15:0]; + Test3 = Test3 + 1; + if (i[3:0] == loop_continue) continue; + // return, IE jump to end-of-function optionally setting return value + if (i[3:0] == loop_break) return Test3; + Test3 = Test3 + i[15:0]; end end endfunction diff --git a/test_regress/t/t_for_count.v b/test_regress/t/t_for_count.v index c294853dc..362902e79 100644 --- a/test_regress/t/t_for_count.v +++ b/test_regress/t/t_for_count.v @@ -19,7 +19,7 @@ module t (/*AUTOARG*/ always @(/*AUTOSENSE*/cam_lookup_hit_vector) begin hit_count = 0; for (j=0; j < 64; j=j+1) begin - hit_count = hit_count + {31'h0, cam_lookup_hit_vector[j]}; + hit_count = hit_count + {31'h0, cam_lookup_hit_vector[j]}; end end @@ -27,7 +27,7 @@ module t (/*AUTOARG*/ always @(/*AUTOSENSE*/cam_lookup_hit_vector) begin hit_count2 = 0; for (j=63; j >= 0; j=j-1) begin - hit_count2 = hit_count2 + {31'h0, cam_lookup_hit_vector[j]}; + hit_count2 = hit_count2 + {31'h0, cam_lookup_hit_vector[j]}; end end @@ -35,7 +35,7 @@ module t (/*AUTOARG*/ always @(/*AUTOSENSE*/cam_lookup_hit_vector) begin hit_count3 = 0; for (j=63; j > 0; j=j-1) begin - if (cam_lookup_hit_vector[j]) hit_count3 = hit_count3 + 32'd1; + if (cam_lookup_hit_vector[j]) hit_count3 = hit_count3 + 32'd1; end end @@ -44,9 +44,9 @@ module t (/*AUTOARG*/ always @(/*AUTOSENSE*/cam_lookup_hit_vector) begin wide_for_count = 0; for (wide_for_index = 128'hff_00000000_00000000; - wide_for_index < 128'hff_00000000_00000100; - wide_for_index = wide_for_index + 2) begin - wide_for_count = wide_for_count+32'h1; + wide_for_index < 128'hff_00000000_00000100; + wide_for_index = wide_for_index + 2) begin + wide_for_count = wide_for_count+32'h1; end end @@ -74,26 +74,26 @@ module t (/*AUTOARG*/ always @ (posedge clk) begin cam_lookup_hit_vector <= 0; if (cyc!=0) begin - cyc <= cyc + 1; - if (cyc==1) begin - cam_lookup_hit_vector <= 64'h00010000_00010000; - end - if (cyc==2) begin - if (hit_count != 32'd2) $stop; - if (hit_count2 != 32'd2) $stop; - if (hit_count3 != 32'd2) $stop; - cam_lookup_hit_vector <= 64'h01010010_00010001; - end - if (cyc==3) begin - if (hit_count != 32'd5) $stop; - if (hit_count2 != 32'd5) $stop; - if (hit_count3 != 32'd4) $stop; - if (wide_for_count != 32'h80) $stop; - end - if (cyc==9) begin - $write("*-* All Finished *-*\n"); - $finish; - end + cyc <= cyc + 1; + if (cyc==1) begin + cam_lookup_hit_vector <= 64'h00010000_00010000; + end + if (cyc==2) begin + if (hit_count != 32'd2) $stop; + if (hit_count2 != 32'd2) $stop; + if (hit_count3 != 32'd2) $stop; + cam_lookup_hit_vector <= 64'h01010010_00010001; + end + if (cyc==3) begin + if (hit_count != 32'd5) $stop; + if (hit_count2 != 32'd5) $stop; + if (hit_count3 != 32'd4) $stop; + if (wide_for_count != 32'h80) $stop; + end + if (cyc==9) begin + $write("*-* All Finished *-*\n"); + $finish; + end end end diff --git a/test_regress/t/t_for_funcbound.v b/test_regress/t/t_for_funcbound.v index b217dd246..91df6403b 100644 --- a/test_regress/t/t_for_funcbound.v +++ b/test_regress/t/t_for_funcbound.v @@ -20,14 +20,14 @@ module t (/*AUTOARG*/ task show; input [8*8-1:0] str; reg [7:0] char; - integer loc; + integer loc; begin - $write("[%0t] ", $time); - strings.stringStart(8*8-1); - for (char = strings.stringByte(str); !strings.isNull(char); char = strings.stringByte(str)) begin - $write("%c",char); - end - $write("\n"); + $write("[%0t] ", $time); + strings.stringStart(8*8-1); + for (char = strings.stringByte(str); !strings.isNull(char); char = strings.stringByte(str)) begin + $write("%c",char); + end + $write("\n"); end endtask @@ -35,17 +35,17 @@ module t (/*AUTOARG*/ integer cyc; initial cyc=1; always @ (posedge clk) begin if (cyc!=0) begin - cyc <= cyc + 1; - if (cyc==1) begin - show("hello\000xx"); - end - if (cyc==2) begin - show("world\000xx"); - end - if (cyc==4) begin - $write("*-* All Finished *-*\n"); - $finish; - end + cyc <= cyc + 1; + if (cyc==1) begin + show("hello\000xx"); + end + if (cyc==2) begin + show("world\000xx"); + end + if (cyc==4) begin + $write("*-* All Finished *-*\n"); + $finish; + end end end @@ -57,7 +57,7 @@ module strings; task stringStart; input [31:0] bits; begin - index = (bits-1)/8; + index = (bits-1)/8; end endtask @@ -69,9 +69,9 @@ module strings; function [7:0] stringByte; input [8*8-1:0] str; begin - if (index<=0) stringByte=8'h0; - else stringByte = str[index*8 +: 8]; - index = index - 1; + if (index<=0) stringByte=8'h0; + else stringByte = str[index*8 +: 8]; + index = index - 1; end endfunction endmodule diff --git a/test_regress/t/t_for_init_bug.v b/test_regress/t/t_for_init_bug.v index 9a3eab084..e638ffaac 100644 --- a/test_regress/t/t_for_init_bug.v +++ b/test_regress/t/t_for_init_bug.v @@ -22,10 +22,10 @@ module t (/*AUTOARG*/ always @* begin for (i=ARW-1;i>0;i=i-1) begin - priority_mask[i]=1'b0; - // vvvv=== note j=j not j=i; was bug - for( j=j;j>=0;j=j-1) - priority_mask[i]=priority_mask[j] | muxed_requests[j]; + priority_mask[i]=1'b0; + // vvvv=== note j=j not j=i; was bug + for( j=j;j>=0;j=j-1) + priority_mask[i]=priority_mask[j] | muxed_requests[j]; end //Bit zero is always enabled priority_mask[0]=1'b0; diff --git a/test_regress/t/t_for_local.v b/test_regress/t/t_for_local.v index f7deaa4eb..44d8b1359 100644 --- a/test_regress/t/t_for_local.v +++ b/test_regress/t/t_for_local.v @@ -18,36 +18,36 @@ module t (/*AUTOARG*/ always @ (posedge clk) begin cyc <= cyc+8'd1; if (cyc == 8'd1) begin - $write("[%0t] t_loop: Running\n", $time); - // Unwind < - loops = 0; - loops2 = 0; - for (int i=0; i<16; i=i+1) begin - loops = loops + i; // surefire lint_off_line ASWEMB - loops2 = loops2 + i; // surefire lint_off_line ASWEMB - end - if (loops !== 120) $stop; - if (loops2 !== 120) $stop; - // Check we can declare the same signal twice - loops = 0; - for (int i=0; i<=16; i=i+1) begin - loops = loops + 1; - end - if (loops !== 17) $stop; - // Check type is correct - loops = 0; - for (byte unsigned i=5; i>4; i=i+1) begin - loops = loops + 1; - end - if (loops !== 251) $stop; - // Check large loops - loops = 0; - for (int i=0; i<100000; i=i+1) begin - loops = loops + 1; - end - if (loops !== 100000) $stop; - $write("*-* All Finished *-*\n"); - $finish; + $write("[%0t] t_loop: Running\n", $time); + // Unwind < + loops = 0; + loops2 = 0; + for (int i=0; i<16; i=i+1) begin + loops = loops + i; // surefire lint_off_line ASWEMB + loops2 = loops2 + i; // surefire lint_off_line ASWEMB + end + if (loops !== 120) $stop; + if (loops2 !== 120) $stop; + // Check we can declare the same signal twice + loops = 0; + for (int i=0; i<=16; i=i+1) begin + loops = loops + 1; + end + if (loops !== 17) $stop; + // Check type is correct + loops = 0; + for (byte unsigned i=5; i>4; i=i+1) begin + loops = loops + 1; + end + if (loops !== 251) $stop; + // Check large loops + loops = 0; + for (int i=0; i<100000; i=i+1) begin + loops = loops + 1; + end + if (loops !== 100000) $stop; + $write("*-* All Finished *-*\n"); + $finish; end end diff --git a/test_regress/t/t_for_loop.v b/test_regress/t/t_for_loop.v index 23912a81f..8569e0b0f 100644 --- a/test_regress/t/t_for_loop.v +++ b/test_regress/t/t_for_loop.v @@ -19,98 +19,98 @@ module t (/*AUTOARG*/ always @ (posedge clk) begin cyc <= cyc+8'd1; if (cyc == 8'd1) begin - $write("[%0t] t_loop: Running\n", $time); - // Unwind < - loops = 0; - loops2 = 0; - for (i=0; i<16; i=i+1) begin - loops = loops + i; // surefire lint_off_line ASWEMB - loops2 = loops2 + i; // surefire lint_off_line ASWEMB - end - if (i !== 16) $stop; - if (loops !== 120) $stop; - if (loops2 !== 120) $stop; - // Unwind <= - loops = 0; - for (i=0; i<=16; i=i+1) begin - loops = loops + 1; - end - if (i !== 17) $stop; - if (loops !== 17) $stop; - // Don't unwind breaked loops - loops = 0; - for (i=0; i<16; i=i+1) begin - loops = loops + 1; - if (i==7) i=99; // break out of loop - end - if (loops !== 8) $stop; - // Don't unwind large loops! - loops = 0; - for (i=0; i<100000; i=i+1) begin - loops = loops + 1; - end - if (loops !== 100000) $stop; - // Test post-increment - loops = 0; - for (i=0; i<=16; i++) begin - loops = loops + 1; - end - if (i !== 17) $stop; - if (loops !== 17) $stop; - // Test pre-increment - loops = 0; - for (i=0; i<=16; ++i) begin - loops = loops + 1; - end - if (i !== 17) $stop; - if (loops !== 17) $stop; - // Test post-decrement - loops = 0; - for (i=16; i>=0; i--) begin - loops = loops + 1; - end - if (i !== -1) $stop; - if (loops !== 17) $stop; - // Test pre-decrement - loops = 0; - for (i=16; i>=0; --i) begin - loops = loops + 1; - end - if (i !== -1) $stop; - if (loops !== 17) $stop; - // - // 1800-2017 optionals init/expr/incr - loops = 0; - i = 0; - for (; i<10; ++i) ++loops; - if (loops !== 10) $stop; - // - loops = 0; - i = 0; - for (i=0; i<10; ) begin ++loops; ++i; end - if (loops !== 10) $stop; - // - loops = 0; - i = 0; - for (; ; ++i) begin ++loops; break; end - if (loops !== 1) $stop; - // - // bug1605 - i = 1; - for (i=20; 0; ) ; - if (i != 20) $stop; - for (i=30; i<10; i++) ; - if (i != 30) $stop; - // Comma - loops = 0; - for (i=0; i<20; ++i, ++loops); - if (loops !== 20) $stop; - loops = 0; - for (i=0; i<20; ++loops, ++i); - if (loops !== 20) $stop; - // - $write("*-* All Finished *-*\n"); - $finish; + $write("[%0t] t_loop: Running\n", $time); + // Unwind < + loops = 0; + loops2 = 0; + for (i=0; i<16; i=i+1) begin + loops = loops + i; // surefire lint_off_line ASWEMB + loops2 = loops2 + i; // surefire lint_off_line ASWEMB + end + if (i !== 16) $stop; + if (loops !== 120) $stop; + if (loops2 !== 120) $stop; + // Unwind <= + loops = 0; + for (i=0; i<=16; i=i+1) begin + loops = loops + 1; + end + if (i !== 17) $stop; + if (loops !== 17) $stop; + // Don't unwind breaked loops + loops = 0; + for (i=0; i<16; i=i+1) begin + loops = loops + 1; + if (i==7) i=99; // break out of loop + end + if (loops !== 8) $stop; + // Don't unwind large loops! + loops = 0; + for (i=0; i<100000; i=i+1) begin + loops = loops + 1; + end + if (loops !== 100000) $stop; + // Test post-increment + loops = 0; + for (i=0; i<=16; i++) begin + loops = loops + 1; + end + if (i !== 17) $stop; + if (loops !== 17) $stop; + // Test pre-increment + loops = 0; + for (i=0; i<=16; ++i) begin + loops = loops + 1; + end + if (i !== 17) $stop; + if (loops !== 17) $stop; + // Test post-decrement + loops = 0; + for (i=16; i>=0; i--) begin + loops = loops + 1; + end + if (i !== -1) $stop; + if (loops !== 17) $stop; + // Test pre-decrement + loops = 0; + for (i=16; i>=0; --i) begin + loops = loops + 1; + end + if (i !== -1) $stop; + if (loops !== 17) $stop; + // + // 1800-2017 optionals init/expr/incr + loops = 0; + i = 0; + for (; i<10; ++i) ++loops; + if (loops !== 10) $stop; + // + loops = 0; + i = 0; + for (i=0; i<10; ) begin ++loops; ++i; end + if (loops !== 10) $stop; + // + loops = 0; + i = 0; + for (; ; ++i) begin ++loops; break; end + if (loops !== 1) $stop; + // + // bug1605 + i = 1; + for (i=20; 0; ) ; + if (i != 20) $stop; + for (i=30; i<10; i++) ; + if (i != 30) $stop; + // Comma + loops = 0; + for (i=0; i<20; ++i, ++loops); + if (loops !== 20) $stop; + loops = 0; + for (i=0; i<20; ++loops, ++i); + if (loops !== 20) $stop; + // + $write("*-* All Finished *-*\n"); + $finish; end end diff --git a/test_regress/t/t_func.v b/test_regress/t/t_func.v index c13221fdf..eb59f633f 100644 --- a/test_regress/t/t_func.v +++ b/test_regress/t/t_func.v @@ -68,12 +68,12 @@ module t; function [2:0] add; input [2:0] fromv; begin - add = fromv + 3'd1; - begin : named - reg [31:0] flocal; - flocal = 1; - rglobal = rglobal + flocal; - end : named // SystemVerilog end labels + add = fromv + 3'd1; + begin : named + reg [31:0] flocal; + flocal = 1; + rglobal = rglobal + flocal; + end : named // SystemVerilog end labels end endfunction @@ -81,26 +81,26 @@ module t; input [3:0] fromv; // Different fromv than the 'fromv' signal above reg one; begin : named - reg [1:0] flocal; - // Function calling a function - one = 1'b1; - munge4 = {one, add(fromv[2:0])}; + reg [1:0] flocal; + // Function calling a function + one = 1'b1; + munge4 = {one, add(fromv[2:0])}; end endfunction task setit; reg [31:0] temp; begin - temp = rglobal + 32'h1; - rglobal = temp + 32'h1; + temp = rglobal + 32'h1; + rglobal = temp + 32'h1; end endtask task incr ( - // Check a V2K style input/output list + // Check a V2K style input/output list output [31:0] z, input [31:0] a, inc - ); + ); z = a + inc; endtask @@ -118,8 +118,8 @@ module t; input [3:0] bitnum; reg [4:0] bitnum2; begin - bitnum2 = {1'b1, bitnum}; // A little math to test constant propagation - vector[bitnum2] = vector[bitnum2] ^ 1'b1; + bitnum2 = {1'b1, bitnum}; // A little math to test constant propagation + vector[bitnum2] = vector[bitnum2] ^ 1'b1; end endtask diff --git a/test_regress/t/t_func_begin2.v b/test_regress/t/t_func_begin2.v index 605eade03..57f1dc4a0 100644 --- a/test_regress/t/t_func_begin2.v +++ b/test_regress/t/t_func_begin2.v @@ -7,16 +7,16 @@ module init; task t1; - reg ba,bb,bc,bd,be,bf,bg,bh,bi,bj,bk,bl,bm,bn,bo,bp,bq,br,bs,bt,bu,bv,bw,bx,by,bz; - reg ca,cb,cc,cd,ce,cf,cg,ch,ci,cj,ck,cl,cm,cn,co,cp,cq,cr,cs,ct,cu,cv,cw,cx,cy,cz; - reg da,db,dc,dd,de,df,dg,dh,di,dj,dk,dl,dm,dn, dp,dq,dr,ds,dt,du,dv,dw,dx,dy,dz; + reg ba,bb,bc,bd,be,bf,bg,bh,bi,bj,bk,bl,bm,bn,bo,bp,bq,br,bs,bt,bu,bv,bw,bx,by,bz; + reg ca,cb,cc,cd,ce,cf,cg,ch,ci,cj,ck,cl,cm,cn,co,cp,cq,cr,cs,ct,cu,cv,cw,cx,cy,cz; + reg da,db,dc,dd,de,df,dg,dh,di,dj,dk,dl,dm,dn, dp,dq,dr,ds,dt,du,dv,dw,dx,dy,dz; begin : READER $display ("Time: %0t Instance: %m", $time); end endtask task t2; - reg ba,bb,bc,bd,be,bf,bg,bh,bi,bj,bk,bl,bm,bn,bo,bp,bq,br,bs,bt,bu,bv,bw,bx,by,bz; + reg ba,bb,bc,bd,be,bf,bg,bh,bi,bj,bk,bl,bm,bn,bo,bp,bq,br,bs,bt,bu,bv,bw,bx,by,bz; begin : READER $display ("Time: %0t Instance: %m", $time); end diff --git a/test_regress/t/t_func_check.v b/test_regress/t/t_func_check.v index 4fb6c33c9..d0f2a06f2 100644 --- a/test_regress/t/t_func_check.v +++ b/test_regress/t/t_func_check.v @@ -10,25 +10,25 @@ module t ( clk ); input clk; - integer cyc = 0; - reg [63:0] crc; initial crc = 64'h1; + integer cyc = 0; + reg [63:0] crc; initial crc = 64'h1; - chk chk (.clk (clk), - .rst_l (1'b1), - .expr (|crc) - ); + chk chk (.clk (clk), + .rst_l (1'b1), + .expr (|crc) + ); always @ (posedge clk) begin cyc <= cyc + 1; crc <= {crc[62:0], crc[63] ^ crc[2] ^ crc[0]}; if (cyc==0) begin - crc <= 64'h5aef0c8d_d70a4497; + crc <= 64'h5aef0c8d_d70a4497; end else if (cyc<90) begin end else if (cyc==99) begin - $write("*-* All Finished *-*\n"); - $finish; + $write("*-* All Finished *-*\n"); + $finish; end end endmodule @@ -40,23 +40,23 @@ module chk (input clk, input rst_l, input expr); task printerr; input [8*64:1] msg; begin - errors = errors + 1; - $write("%%Error: %0s\n", msg); - $stop; + errors = errors + 1; + $write("%%Error: %0s\n", msg); + $stop; end endtask always @(posedge clk) begin if (rst_l) begin - if (expr == 1'b0) begin + if (expr == 1'b0) begin printerr("expr not asserted"); - end + end end end wire noxs = ((expr ^ expr) == 1'b0); - reg hasx; + reg hasx; always @ (noxs) begin if (noxs) begin hasx = 1'b0; diff --git a/test_regress/t/t_func_const.v b/test_regress/t/t_func_const.v index 8fc23468e..2955bf3d2 100644 --- a/test_regress/t/t_func_const.v +++ b/test_regress/t/t_func_const.v @@ -72,45 +72,45 @@ module t; integer i; integer times; begin - times = 1; - for (i=0; i1) break; + out = out+1; + if (a>1) break; end while (1) begin - out = out+1; - if (a>1) return 2+out; + out = out+1; + if (a>1) return 2+out; end f_return = 0; endfunction diff --git a/test_regress/t/t_func_crc.v b/test_regress/t/t_func_crc.v index 21bc8a036..34a510412 100644 --- a/test_regress/t/t_func_crc.v +++ b/test_regress/t/t_func_crc.v @@ -19,33 +19,33 @@ module t (/*AUTOARG*/ integer cyc; initial cyc=1; always @ (posedge clk) begin if (cyc!=0) begin - cyc <= cyc + 1; - q_r <= q; - c <= q; + cyc <= cyc + 1; + q_r <= q; + c <= q; d <= {d[62:0], ^d[63:48]}; - //$write("%d crc(%x,%x)=%x\n", cyc, d, c, q); - if (cyc==1) begin - // Assign inputs randomly - q_r <= 32'h12345678; - c <= 32'h12345678; - d <= 64'hffffffff_ffffffff; - end - if (cyc==2) begin - d <= 64'hffffffff_ffffffff; - end - if (cyc==3) begin - d <= 64'hffffffff_ffffffff; - end - if (cyc==4) begin - d <= 64'h50183721_81a04b1a; - end - if (cyc==5) begin - end - if (cyc==9) begin - if (q !== 32'h38295e96) $stop; - $write("*-* All Finished *-*\n"); - $finish; - end + //$write("%d crc(%x,%x)=%x\n", cyc, d, c, q); + if (cyc==1) begin + // Assign inputs randomly + q_r <= 32'h12345678; + c <= 32'h12345678; + d <= 64'hffffffff_ffffffff; + end + if (cyc==2) begin + d <= 64'hffffffff_ffffffff; + end + if (cyc==3) begin + d <= 64'hffffffff_ffffffff; + end + if (cyc==4) begin + d <= 64'h50183721_81a04b1a; + end + if (cyc==5) begin + end + if (cyc==9) begin + if (q !== 32'h38295e96) $stop; + $write("*-* All Finished *-*\n"); + $finish; + end end end @@ -54,14 +54,14 @@ module t (/*AUTOARG*/ input [31:0] ci; reg [63:0] drev; begin - drev = reverse(di); - crc = newcrc(drev, ci); + drev = reverse(di); + crc = newcrc(drev, ci); end endfunction function [63:0] reverse; input [63:0] di; - integer i; + integer i; begin reverse = 64'b0; for (i=0; i<64; i=i+1) reverse[i] = di[63-i]; @@ -74,8 +74,8 @@ module t (/*AUTOARG*/ reg [31:0] N; reg [31:0] DT; begin - N = 32'b0; - // Note this isn't a real CRC code; it's been munged for privacy + N = 32'b0; + // Note this isn't a real CRC code; it's been munged for privacy N[0] = D[59]^D[53]^D[52]^D[49]^D[44]^D[41]^D[40]^D[39]^D[37]^D[32]^D[29]^D[26]^D[22]^D[21]^D[20]^D[16]^D[15]^D[14]^D[9]^D[7]^D[0] ^C[29]^C[27]^C[24]^C[23]^C[22]^C[21]^C[19]^C[15]^C[13]^C[10]^C[8]^C[3]^C[1]; N[1] = D[61]^D[57]^D[51]^D[47]^D[43]^D[37]^D[35]^D[32]^D[28]^D[24]^D[22]^D[21]^D[20]^D[16]^D[12]^D[11]^D[10]^D[8]^D[7]^D[6]^D[1]^D[0] @@ -140,7 +140,7 @@ module t (/*AUTOARG*/ ^C[28]^C[25]^C[24]^C[22]^C[20]^C[15]^C[14]^C[12]^C[10]^C[9]^C[4]^C[0]; N[31] = D[61]^D[58]^D[56]^D[55]^D[54]^D[52]^D[51]^D[50]^D[49]^D[42]^D[38]^D[37]^D[36]^D[34]^D[31]^D[30]^D[27]^D[26]^D[23]^D[22]^D[21]^D[19]^D[18]^D[12]^D[0] ^C[28]^C[26]^C[24]^C[21]^C[17]^C[16]^C[14]^C[13]^C[10]^C[8]^C[2]; - newcrc = N; + newcrc = N; end endfunction endmodule diff --git a/test_regress/t/t_func_dotted.v b/test_regress/t/t_func_dotted.v index c7e6a42e4..e858b2ef8 100644 --- a/test_regress/t/t_func_dotted.v +++ b/test_regress/t/t_func_dotted.v @@ -27,27 +27,27 @@ module t (/*AUTOARG*/ always @ (posedge clk) begin cyc <= cyc + 1; if (cyc==2) begin - if (global_cell. getGlob(1'b0) !== 32'hf00d) $stop; - if (global_cell2.getGlob(1'b0) !== 32'hf22d) $stop; + if (global_cell. getGlob(1'b0) !== 32'hf00d) $stop; + if (global_cell2.getGlob(1'b0) !== 32'hf22d) $stop; end if (cyc==3) begin - if (ma0. getName(1'b0) !== "ma ") $stop; - if (ma0.mb0. getName(1'b0) !== "mb ") $stop; - if (ma0.mb0.mc0.getName(1'b0) !== "mc ") $stop; + if (ma0. getName(1'b0) !== "ma ") $stop; + if (ma0.mb0. getName(1'b0) !== "mb ") $stop; + if (ma0.mb0.mc0.getName(1'b0) !== "mc ") $stop; end if (cyc==4) begin - if (ma0.mb0. getP2(1'b0) !== 32'h0) $stop; - if (ma0.mb0.mc0.getP3(1'b0) !== 32'h0) $stop; - if (ma0.mb0.mc1.getP3(1'b0) !== 32'h1) $stop; + if (ma0.mb0. getP2(1'b0) !== 32'h0) $stop; + if (ma0.mb0.mc0.getP3(1'b0) !== 32'h0) $stop; + if (ma0.mb0.mc1.getP3(1'b0) !== 32'h1) $stop; end if (cyc==5) begin - ma0. checkName(ma0. getName(1'b0)); - ma0.mb0. checkName(ma0.mb0. getName(1'b0)); - ma0.mb0.mc0.checkName(ma0.mb0.mc0.getName(1'b0)); + ma0. checkName(ma0. getName(1'b0)); + ma0.mb0. checkName(ma0.mb0. getName(1'b0)); + ma0.mb0.mc0.checkName(ma0.mb0.mc0.getName(1'b0)); end if (cyc==9) begin - $write("*-* All Finished *-*\n"); - $finish; + $write("*-* All Finished *-*\n"); + $finish; end end diff --git a/test_regress/t/t_func_endian.v b/test_regress/t/t_func_endian.v index 85cccec96..260e3a987 100644 --- a/test_regress/t/t_func_endian.v +++ b/test_regress/t/t_func_endian.v @@ -10,28 +10,28 @@ module t (/*AUTOARG*/ ); input clk; - integer cyc = 0; - reg [63:0] crc; - reg [63:0] sum; + integer cyc = 0; + reg [63:0] crc; + reg [63:0] sum; // Take CRC data and apply to testblock inputs wire [31:0] in = crc[31:0]; - wire noswap = crc[32]; - wire nibble = crc[33]; + wire noswap = crc[32]; + wire nibble = crc[33]; /*AUTOWIRE*/ // Beginning of automatic wires (for undeclared instantiated-module outputs) - wire [31:0] out; // From test of Test.v + wire [31:0] out; // From test of Test.v // End of automatics Test test (/*AUTOINST*/ - // Outputs - .out (out[31:0]), - // Inputs - .clk (clk), - .noswap (noswap), - .nibble (nibble), - .in (in[31:0])); + // Outputs + .out (out[31:0]), + // Inputs + .clk (clk), + .noswap (noswap), + .nibble (nibble), + .in (in[31:0])); // Aggregate outputs into a single result vector wire [63:0] result = {32'h0, out}; @@ -45,20 +45,20 @@ module t (/*AUTOARG*/ crc <= {crc[62:0], crc[63] ^ crc[2] ^ crc[0]}; sum <= result ^ {sum[62:0], sum[63] ^ sum[2] ^ sum[0]}; if (cyc==0) begin - // Setup - crc <= 64'h5aef0c8d_d70a4497; + // Setup + crc <= 64'h5aef0c8d_d70a4497; end else if (cyc<10) begin - sum <= 64'h0; + sum <= 64'h0; end else if (cyc<90) begin end else if (cyc==99) begin - $write("*-* All Finished *-*\n"); - $write("[%0t] cyc==%0d crc=%x sum=%x\n", $time, cyc, crc, sum); - if (crc !== 64'hc77bb9b3784ea091) $stop; - if (sum !== 64'h89522c3f5e5ca324) $stop; - $finish; + $write("*-* All Finished *-*\n"); + $write("[%0t] cyc==%0d crc=%x sum=%x\n", $time, cyc, crc, sum); + if (crc !== 64'hc77bb9b3784ea091) $stop; + if (sum !== 64'h89522c3f5e5ca324) $stop; + $finish; end end @@ -83,17 +83,17 @@ module Test (/*AUTOARG*/ input [7:0] Data; begin EndianSwap = (Nibble ? { Data[0], Data[1], Data[2], Data[3], - Data[4], Data[5], Data[6], Data[7] } + Data[4], Data[5], Data[6], Data[7] } : { 4'h0, Data[0], Data[1], Data[2], Data[3] }); end endfunction assign out[31:24] = (noswap ? in[31:24] - : EndianSwap(nibble, in[31:24])); + : EndianSwap(nibble, in[31:24])); assign out[23:16] = (noswap ? in[23:16] - : EndianSwap(nibble, in[23:16])); + : EndianSwap(nibble, in[23:16])); assign out[15:8] = (noswap ? in[15:8] - : EndianSwap(nibble, in[15:8])); + : EndianSwap(nibble, in[15:8])); assign out[7:0] = (noswap ? in[7:0] - : EndianSwap(nibble, in[7:0])); + : EndianSwap(nibble, in[7:0])); endmodule diff --git a/test_regress/t/t_func_first.v b/test_regress/t/t_func_first.v index f882fac13..22c7c52dd 100644 --- a/test_regress/t/t_func_first.v +++ b/test_regress/t/t_func_first.v @@ -11,28 +11,28 @@ module t (/*AUTOARG*/ input clk; reg [7:0] cyc; initial cyc = 0; - reg set_in_task; + reg set_in_task; always @ (posedge clk) begin if (cyc == 8'd0) begin - cyc <= 8'd1; - set_in_task <= 0; + cyc <= 8'd1; + set_in_task <= 0; end if (cyc == 8'd1) begin - cyc <= 8'h2; - ttask; + cyc <= 8'h2; + ttask; end if (cyc == 8'd2) begin - if (!set_in_task) $stop; - cyc <= 8'hf; - $write("*-* All Finished *-*\n"); - $finish; + if (!set_in_task) $stop; + cyc <= 8'hf; + $write("*-* All Finished *-*\n"); + $finish; end end task ttask; begin - set_in_task <= 1'b1; + set_in_task <= 1'b1; end endtask diff --git a/test_regress/t/t_func_flip.v b/test_regress/t/t_func_flip.v index 302b6b0d5..ad1e197f0 100644 --- a/test_regress/t/t_func_flip.v +++ b/test_regress/t/t_func_flip.v @@ -5,7 +5,7 @@ // SPDX-License-Identifier: CC0-1.0 `define INT_RANGE 31:0 -`define INT_RANGE 31:0 // Duplicate identical defs are OK +`define INT_RANGE 31:0 // Duplicate identical defs are OK `define INT_RANGE_MAX 31 `define VECTOR_RANGE 511:0 @@ -23,13 +23,13 @@ module t (clk); input [`VECTOR_RANGE] x; // x[width-1:0] is the input vector reg [`VECTOR_RANGE] flip; begin - flip = 'd0; - func_tree_left = flip; + flip = 'd0; + func_tree_left = flip; end endfunction reg [WIDTH-1:0] a; // value to be shifted - reg [WIDTH-1:0] tree_left; + reg [WIDTH-1:0] tree_left; always @(a) begin : barrel_shift tree_left = func_tree_left (a); end // barrel_shift @@ -37,16 +37,16 @@ module t (clk); integer cyc; initial cyc=1; always @ (posedge clk) begin if (cyc!=0) begin - cyc <= cyc + 1; - if (cyc==1) begin - a = 5; - end - if (cyc==2) begin - $display ("%x\n",tree_left); - //if (tree_left != 'd15) $stop; - $write("*-* All Finished *-*\n"); - $finish; - end + cyc <= cyc + 1; + if (cyc==1) begin + a = 5; + end + if (cyc==2) begin + $display ("%x\n",tree_left); + //if (tree_left != 'd15) $stop; + $write("*-* All Finished *-*\n"); + $finish; + end end end diff --git a/test_regress/t/t_func_gen.v b/test_regress/t/t_func_gen.v index 410d7e0b9..1904643cf 100644 --- a/test_regress/t/t_func_gen.v +++ b/test_regress/t/t_func_gen.v @@ -15,20 +15,20 @@ module t (/*AUTOARG*/ logic [1:0] mask = 0; generate for (g=0; g<2; g++) - begin : picker - logic block_passed = 0; // Just for visualizing V3LinkDot debug - function [3:0] pick; - input [3:0] randnum; - pick = randnum+g[3:0]; - endfunction - always @(posedge clk) begin - if (pick(3)!=3+g[3:0]) $stop; - else mask[g] = 1'b1; - if (mask == 2'b11) begin // All iterations must be finished - $write("*-* All Finished *-*\n"); - $finish; - end - end - end + begin : picker + logic block_passed = 0; // Just for visualizing V3LinkDot debug + function [3:0] pick; + input [3:0] randnum; + pick = randnum+g[3:0]; + endfunction + always @(posedge clk) begin + if (pick(3)!=3+g[3:0]) $stop; + else mask[g] = 1'b1; + if (mask == 2'b11) begin // All iterations must be finished + $write("*-* All Finished *-*\n"); + $finish; + end + end + end endgenerate endmodule diff --git a/test_regress/t/t_func_graphcirc.v b/test_regress/t/t_func_graphcirc.v index 6a9a00dc9..8097ca345 100644 --- a/test_regress/t/t_func_graphcirc.v +++ b/test_regress/t/t_func_graphcirc.v @@ -12,11 +12,11 @@ module t (clk); always @(posedge clk) begin cyc <= cyc + 1; if (cyc == 1) begin - ReadContDisps; + ReadContDisps; end else if (cyc == 5) begin - $write("*-* All Finished *-*\n"); - $finish; + $write("*-* All Finished *-*\n"); + $finish; end `ifndef verilator DispContDisps; @@ -25,7 +25,7 @@ module t (clk); task ReadContDisps; begin - $display("%m: Here: %d", cyc); + $display("%m: Here: %d", cyc); end endtask @@ -34,19 +34,19 @@ module t (clk); task DispContDisps; /* verilator public */ begin - if (cyc >= 2) begin + if (cyc >= 2) begin if ( cyc >= 4 ) begin - dindex = dindex + 2; //*** Error line - $display("%m: DIndex increment %d", cyc); + dindex = dindex + 2; //*** Error line + $display("%m: DIndex increment %d", cyc); `ifdef VERILATOR - $c("VL_PRINTF(\"Hello1?\\n\");"); + $c("VL_PRINTF(\"Hello1?\\n\");"); `endif end `ifdef VERILATOR - $c("VL_PRINTF(\"Hello2?\\n\");"); - $c("VL_PRINTF(\"Hello3?\\n\");"); + $c("VL_PRINTF(\"Hello2?\\n\");"); + $c("VL_PRINTF(\"Hello3?\\n\");"); `endif - end + end end endtask diff --git a/test_regress/t/t_func_grey.v b/test_regress/t/t_func_grey.v index 2e77f477a..c93305c3f 100644 --- a/test_regress/t/t_func_grey.v +++ b/test_regress/t/t_func_grey.v @@ -23,16 +23,16 @@ module t (/*AUTOARG*/ always @ (posedge clk) begin if (_mode==0) begin - _mode <= 1; - g3 <= 3'b101; - g6 <= 6'b110101; + _mode <= 1; + g3 <= 3'b101; + g6 <= 6'b110101; end else if (_mode==1) begin - if (b3 !== 3'b110) $stop; - if (b6 !== 6'b100110) $stop; - _mode <= 2; - $write("*-* All Finished *-*\n"); - $finish; + if (b3 !== 3'b110) $stop; + if (b6 !== 6'b100110) $stop; + _mode <= 2; + $write("*-* All Finished *-*\n"); + $finish; end end @@ -44,7 +44,7 @@ endmodule // b[3] = ^g[3] = g[3] // b[2] = ^g[3:2] // b[1] = ^g[3:1] -// b[0] = ^g[3:[SZ-1:0] cur0] +// b[0] = ^g[3:[SZ-1:0] cur0] module t_func_grey2bin (/*AUTOARG*/ // Outputs @@ -61,10 +61,10 @@ module t_func_grey2bin (/*AUTOARG*/ /*AUTOREG*/ // Beginning of automatic regs (for this module's undeclared outputs) - reg [SZ-1:0] b; + reg [SZ-1:0] b; // End of automatics - integer i; + integer i; always @(/*AUTOSENSE*/g) for (i=0; i> i); // surefire lint_off_line LATASS diff --git a/test_regress/t/t_func_lib_sub.v b/test_regress/t/t_func_lib_sub.v index 18e9b477f..23eca8af5 100644 --- a/test_regress/t/t_func_lib_sub.v +++ b/test_regress/t/t_func_lib_sub.v @@ -45,11 +45,11 @@ generate for (i=0;i<8;i=i+1) begin : dnlpyw DecCountReg4 bzpytc (zfghtn, fgzsox, zlnzlj[i], - knquim[3:0], covfok, grvsrs[i]); + knquim[3:0], covfok, grvsrs[i]); DecCountReg4 oghukp (zfghtn, fgzsox, zlnzlj[i], - knquim[7:4], covfok, kyxrft[i]); + knquim[7:4], covfok, kyxrft[i]); DecCountReg4 ttvjoo (zfghtn, fgzsox, nahzat[i], - kqxkkr[3:0], covfok, uxhkka[i]); + kqxkkr[3:0], covfok, uxhkka[i]); end endgenerate @@ -93,7 +93,7 @@ always @(posedge clk) begin Xinit; if (X(qqibou)) - udbvtl <= #`zednkw mppedc; + udbvtl <= #`zednkw mppedc; Xcheck(fgzsox); end diff --git a/test_regress/t/t_func_mlog2.v b/test_regress/t/t_func_mlog2.v index 4dfe03bfa..1d85a39f6 100644 --- a/test_regress/t/t_func_mlog2.v +++ b/test_regress/t/t_func_mlog2.v @@ -12,35 +12,35 @@ module t (clk); integer cpre; always @ (posedge clk) begin if (cyc!=0) begin - cpre = cyc; - cyc <= cyc + 1; - if (cyc==1) begin - if (mlog2(32'd0) != 32'd0) $stop; - if (mlog2(32'd1) != 32'd0) $stop; - if (mlog2(32'd3) != 32'd2) $stop; - sum <= 32'd0; - end - else if (cyc<90) begin - // (cyc) so if we trash the variable things will get upset. - sum <= mlog2(cyc) + sum * 32'd42; - if (cpre != cyc) $stop; - end - else if (cyc==90) begin - if (sum !== 32'h0f12bb51) $stop; - $write("*-* All Finished *-*\n"); - $finish; - end + cpre = cyc; + cyc <= cyc + 1; + if (cyc==1) begin + if (mlog2(32'd0) != 32'd0) $stop; + if (mlog2(32'd1) != 32'd0) $stop; + if (mlog2(32'd3) != 32'd2) $stop; + sum <= 32'd0; + end + else if (cyc<90) begin + // (cyc) so if we trash the variable things will get upset. + sum <= mlog2(cyc) + sum * 32'd42; + if (cpre != cyc) $stop; + end + else if (cyc==90) begin + if (sum !== 32'h0f12bb51) $stop; + $write("*-* All Finished *-*\n"); + $finish; + end end end function integer mlog2; input [31:0] value; - integer i; + integer i; begin - if(value < 32'd1) begin + if(value < 32'd1) begin mlog2 = 0; - end - else begin + end + else begin value = value - 32'd1; mlog2 = 0; for(i=0;i<32;i=i+1) begin @@ -49,7 +49,7 @@ module t (clk); end value = value >> 1; end - end + end end endfunction diff --git a/test_regress/t/t_func_named.v b/test_regress/t/t_func_named.v index f3c016dd5..2ecd570d7 100644 --- a/test_regress/t/t_func_named.v +++ b/test_regress/t/t_func_named.v @@ -13,14 +13,14 @@ module t (/*AUTOARG*/); `define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); $stop; end while(0); initial begin - `checkh( f(.j(2), .s(1)) , 32'h2_0001 ); - `checkh( f(.s(1)) , 32'h1_0001 ); - `checkh( f(, 1) , 32'h1_0001 ); - `checkh( f(.j(2)) , 32'h2_0000 ); - `checkh( f(.s(1), .j(2)) , 32'h2_0001 ); - `checkh( f(.s(), .j()) , 32'h1_0000 ); - `checkh( f(2) , 32'h2_0000 ); - `checkh( f() , 32'h1_0000 ); + `checkh( f(.j(2), .s(1)) , 32'h2_0001 ); + `checkh( f(.s(1)) , 32'h1_0001 ); + `checkh( f(, 1) , 32'h1_0001 ); + `checkh( f(.j(2)) , 32'h2_0000 ); + `checkh( f(.s(1), .j(2)) , 32'h2_0001 ); + `checkh( f(.s(), .j()) , 32'h1_0000 ); + `checkh( f(2) , 32'h2_0000 ); + `checkh( f() , 32'h1_0000 ); $write("*-* All Finished *-*\n"); $finish; diff --git a/test_regress/t/t_func_noinl.v b/test_regress/t/t_func_noinl.v index 1f08b9af1..5631f30ab 100644 --- a/test_regress/t/t_func_noinl.v +++ b/test_regress/t/t_func_noinl.v @@ -10,25 +10,25 @@ module t (/*AUTOARG*/ ); input clk; - integer cyc = 0; - reg [63:0] crc; - reg [63:0] sum; + integer cyc = 0; + reg [63:0] crc; + reg [63:0] sum; wire [31:0] inp = crc[31:0]; - wire reset = (cyc < 5); + wire reset = (cyc < 5); /*AUTOWIRE*/ // Beginning of automatic wires (for undeclared instantiated-module outputs) - wire [31:0] outp; // From test of Test.v + wire [31:0] outp; // From test of Test.v // End of automatics Test test (/*AUTOINST*/ - // Outputs - .outp (outp[31:0]), - // Inputs - .reset (reset), - .clk (clk), - .inp (inp[31:0])); + // Outputs + .outp (outp[31:0]), + // Inputs + .reset (reset), + .clk (clk), + .inp (inp[31:0])); // Aggregate outputs into a single result vector wire [63:0] result = {32'h0, outp}; @@ -45,20 +45,20 @@ module t (/*AUTOARG*/ crc <= {crc[62:0], crc[63] ^ crc[2] ^ crc[0]}; sum <= result ^ {sum[62:0], sum[63] ^ sum[2] ^ sum[0]}; if (cyc==0) begin - // Setup - crc <= 64'h5aef0c8d_d70a4497; + // Setup + crc <= 64'h5aef0c8d_d70a4497; end else if (cyc<10) begin - sum <= 64'h0; + sum <= 64'h0; end else if (cyc<90) begin end else if (cyc==99) begin - $write("[%0t] cyc==%0d crc=%x sum=%x\n", $time, cyc, crc, sum); - if (crc !== 64'hc77bb9b3784ea091) $stop; - if (sum !== `EXPECTED_SUM) $stop; - $write("*-* All Finished *-*\n"); - $finish; + $write("[%0t] cyc==%0d crc=%x sum=%x\n", $time, cyc, crc, sum); + if (crc !== 64'hc77bb9b3784ea091) $stop; + if (sum !== `EXPECTED_SUM) $stop; + $write("*-* All Finished *-*\n"); + $finish; end end @@ -71,32 +71,32 @@ module Test (/*AUTOARG*/ reset, clk, inp ); - input reset; - input clk; - input [31:0] inp; - output [31:0] outp; + input reset; + input clk; + input [31:0] inp; + output [31:0] outp; function [31:0] no_inline_function; - input [31:0] var1; - input [31:0] var2; + input [31:0] var1; + input [31:0] var2; /*verilator no_inline_task*/ - reg [31*2:0] product1 ; - reg [31*2:0] product2 ; - integer i; - reg [31:0] tmp; + reg [31*2:0] product1 ; + reg [31*2:0] product2 ; + integer i; + reg [31:0] tmp; begin - product2 = {(31*2+1){1'b0}}; + product2 = {(31*2+1){1'b0}}; - for (i = 0; i < 32; i = i + 1) - if (var2[i]) begin - product1 = { {31*2+1-32{1'b0}}, var1} << i; - product2 = product2 ^ product1; - end - no_inline_function = 0; + for (i = 0; i < 32; i = i + 1) + if (var2[i]) begin + product1 = { {31*2+1-32{1'b0}}, var1} << i; + product2 = product2 ^ product1; + end + no_inline_function = 0; - for (i= 0; i < 31; i = i + 1 ) - no_inline_function[i+1] = no_inline_function[i] ^ product2[i] ^ var1[i]; + for (i= 0; i < 31; i = i + 1 ) + no_inline_function[i+1] = no_inline_function[i] ^ product2[i] ^ var1[i]; end endfunction @@ -105,11 +105,11 @@ module Test (/*AUTOARG*/ always @( posedge clk ) begin if( reset ) begin - outp <= 0; + outp <= 0; end else begin - inp_d <= inp; - outp <= no_inline_function(inp, inp_d); + inp_d <= inp; + outp <= no_inline_function(inp, inp_d); end end diff --git a/test_regress/t/t_func_numones.v b/test_regress/t/t_func_numones.v index d1ff279ea..2de8d7427 100644 --- a/test_regress/t/t_func_numones.v +++ b/test_regress/t/t_func_numones.v @@ -34,16 +34,16 @@ module t (clk); integer cyc; initial cyc=1; always @ (posedge clk) begin if (cyc!=0) begin - cyc <= cyc + 1; - if (cyc==1) begin - r32 <= 32'h12345678; - end - if (cyc==2) begin - if (w4 !== 1) $stop; - if (w5 !== 2) $stop; - $write("*-* All Finished *-*\n"); - $finish; - end + cyc <= cyc + 1; + if (cyc==1) begin + r32 <= 32'h12345678; + end + if (cyc==2) begin + if (w4 !== 1) $stop; + if (w5 !== 2) $stop; + $write("*-* All Finished *-*\n"); + $finish; + end end end diff --git a/test_regress/t/t_func_outfirst.v b/test_regress/t/t_func_outfirst.v index 68f6ee7a8..4b79becd2 100644 --- a/test_regress/t/t_func_outfirst.v +++ b/test_regress/t/t_func_outfirst.v @@ -16,9 +16,9 @@ module t (/*AUTOARG*/ ); input clk; - integer cyc = 0; - reg [63:0] crc; - reg [63:0] sum; + integer cyc = 0; + reg [63:0] crc; + reg [63:0] sum; // Take CRC data and apply to testblock inputs wire [`DDIFF_BITS-1:0] DDIFF_B = crc[`DDIFF_BITS-1:0]; @@ -26,16 +26,16 @@ module t (/*AUTOARG*/ /*AUTOWIRE*/ // Beginning of automatic wires (for undeclared instantiated-module outputs) - wire [`AOA_BITS-1:0] AOA_B; // From test of Test.v + wire [`AOA_BITS-1:0] AOA_B; // From test of Test.v // End of automatics Test test (/*AUTOINST*/ - // Outputs - .AOA_B (AOA_B[`AOA_BITS-1:0]), - // Inputs - .DDIFF_B (DDIFF_B[`DDIFF_BITS-1:0]), - .reset (reset), - .clk (clk)); + // Outputs + .AOA_B (AOA_B[`AOA_BITS-1:0]), + // Inputs + .DDIFF_B (DDIFF_B[`DDIFF_BITS-1:0]), + .reset (reset), + .clk (clk)); // Aggregate outputs into a single result vector wire [63:0] result = {56'h0, AOA_B}; @@ -49,23 +49,23 @@ module t (/*AUTOARG*/ crc <= {crc[62:0], crc[63] ^ crc[2] ^ crc[0]}; sum <= result ^ {sum[62:0], sum[63] ^ sum[2] ^ sum[0]}; if (cyc==0) begin - // Setup - crc <= 64'h5aef0c8d_d70a4497; - sum <= 64'h0; + // Setup + crc <= 64'h5aef0c8d_d70a4497; + sum <= 64'h0; end else if (cyc<10) begin - sum <= 64'h0; + sum <= 64'h0; end else if (cyc<90) begin end else if (cyc==99) begin - $write("[%0t] cyc==%0d crc=%x sum=%x\n", $time, cyc, crc, sum); - if (crc !== 64'hc77bb9b3784ea091) $stop; - // What checksum will we end up with (above print should match) + $write("[%0t] cyc==%0d crc=%x sum=%x\n", $time, cyc, crc, sum); + if (crc !== 64'hc77bb9b3784ea091) $stop; + // What checksum will we end up with (above print should match) `define EXPECTED_SUM 64'h3a74e9d34771ad93 - if (sum !== `EXPECTED_SUM) $stop; - $write("*-* All Finished *-*\n"); - $finish; + if (sum !== `EXPECTED_SUM) $stop; + $write("*-* All Finished *-*\n"); + $finish; end end @@ -88,10 +88,10 @@ module Test (/*AUTOARG*/ always @(posedge clk) begin if (reset) begin - AOA_B <= 8'h80; + AOA_B <= 8'h80; end else begin - AOA_B <= AOA_NEXT_B; + AOA_B <= AOA_NEXT_B; end end diff --git a/test_regress/t/t_func_outp.v b/test_regress/t/t_func_outp.v index cbaa5afeb..23f8f82dc 100644 --- a/test_regress/t/t_func_outp.v +++ b/test_regress/t/t_func_outp.v @@ -8,39 +8,39 @@ module t (clk); input clk; - reg [7:0] a,b; - wire [7:0] z; + reg [7:0] a,b; + wire [7:0] z; mytop u0 ( a, b, clk, z ); integer cyc; initial cyc=1; always @ (posedge clk) begin if (cyc!=0) begin - cyc <= cyc + 1; - //$write("%d %x\n", cyc, z); - if (cyc==1) begin - a <= 8'h07; - b <= 8'h20; - end - if (cyc==2) begin - a <= 8'h8a; - b <= 8'h12; - end - if (cyc==3) begin - if (z !== 8'hdf) $stop; - a <= 8'h71; - b <= 8'hb2; - end - if (cyc==4) begin - if (z !== 8'hed) $stop; - end - if (cyc==5) begin - if (z !== 8'h4d) $stop; - end - if (cyc==9) begin - $write("*-* All Finished *-*\n"); - $finish; - end + cyc <= cyc + 1; + //$write("%d %x\n", cyc, z); + if (cyc==1) begin + a <= 8'h07; + b <= 8'h20; + end + if (cyc==2) begin + a <= 8'h8a; + b <= 8'h12; + end + if (cyc==3) begin + if (z !== 8'hdf) $stop; + a <= 8'h71; + b <= 8'hb2; + end + if (cyc==4) begin + if (z !== 8'hed) $stop; + end + if (cyc==5) begin + if (z !== 8'h4d) $stop; + end + if (cyc==9) begin + $write("*-* All Finished *-*\n"); + $finish; + end end end @@ -61,10 +61,10 @@ module ftest( output reg [ 7:0 ] z ); - wire [7:0] zi; + wire [7:0] zi; inv u1 (.a(myadd(a,b)), - .z(zi)); + .z(zi)); always @ ( posedge clk ) begin diff --git a/test_regress/t/t_func_paramed.v b/test_regress/t/t_func_paramed.v index 158f78abe..b52c17812 100644 --- a/test_regress/t/t_func_paramed.v +++ b/test_regress/t/t_func_paramed.v @@ -16,37 +16,37 @@ module t (/*AUTOARG*/ wire [2:0] out_x; extractor #(4,3) extractor ( - // Outputs - .out (out_x), - // Inputs - .in (in_a), - .sel (sel)); + // Outputs + .out (out_x), + // Inputs + .in (in_a), + .sel (sel)); integer cyc; initial cyc=1; always @ (posedge clk) begin if (cyc!=0) begin - cyc <= cyc + 1; - //$write("%d %x %x %x\n", cyc, in_a, sel, out_x); - if (cyc==1) begin - in_a <= 12'b001_101_111_010; - sel <= 32'd0; - end - if (cyc==2) begin - sel <= 32'd1; - if (out_x != 3'b010) $stop; - end - if (cyc==3) begin - sel <= 32'd2; - if (out_x != 3'b111) $stop; - end - if (cyc==4) begin - sel <= 32'd3; - if (out_x != 3'b101) $stop; - end - if (cyc==9) begin - $write("*-* All Finished *-*\n"); - $finish; - end + cyc <= cyc + 1; + //$write("%d %x %x %x\n", cyc, in_a, sel, out_x); + if (cyc==1) begin + in_a <= 12'b001_101_111_010; + sel <= 32'd0; + end + if (cyc==2) begin + sel <= 32'd1; + if (out_x != 3'b010) $stop; + end + if (cyc==3) begin + sel <= 32'd2; + if (out_x != 3'b111) $stop; + end + if (cyc==4) begin + sel <= 32'd3; + if (out_x != 3'b101) $stop; + end + if (cyc==9) begin + $write("*-* All Finished *-*\n"); + $finish; + end end end endmodule @@ -62,19 +62,19 @@ module extractor (/*AUTOARG*/ input [IN_WIDTH*OUT_WIDTH-1:0] in; output [OUT_WIDTH-1:0] out; - input [31:0] sel; + input [31:0] sel; wire [OUT_WIDTH-1:0] out = selector(in,sel); function [OUT_WIDTH-1:0] selector; input [IN_WIDTH*OUT_WIDTH-1:0] inv; - input [31:0] selv; + input [31:0] selv; integer i; begin - selector = 0; - for (i=0; i0; log2=log2+1) - arg = (arg >> 1); + for(log2=0; arg>0; log2=log2+1) + arg = (arg >> 1); end endfunction always @ (posedge clk or negedge rst_n) if (!rst_n) begin - pos1 <= 0; - pos2 <= 0; + pos1 <= 0; + pos2 <= 0; end else begin - pos1 <= pos1 + 1; - pos2 <= pos2 + 1; + pos1 <= pos1 + 1; + pos2 <= pos2 + 1; end endmodule diff --git a/test_regress/t/t_func_public.v b/test_regress/t/t_func_public.v index 099e52da7..08549a602 100644 --- a/test_regress/t/t_func_public.v +++ b/test_regress/t/t_func_public.v @@ -13,16 +13,16 @@ module t (clk); integer cyc; initial cyc=1; always @ (posedge clk) begin if (cyc!=0) begin - cyc <= cyc + 1; - if (cyc==1) begin + cyc <= cyc + 1; + if (cyc==1) begin `ifdef verilator - $c("this->publicTop();"); + $c("this->publicTop();"); `endif - end - if (cyc==20) begin - $write("*-* All Finished *-*\n"); - $finish; - end + end + if (cyc==20) begin + $write("*-* All Finished *-*\n"); + $finish; + end end end @@ -42,13 +42,13 @@ module t (clk); endmodule module tpub ( - input clk, - input [31:0] i); + input clk, + input [31:0] i); reg [23:0] var_long; reg [59:0] var_quad; reg [71:0] var_wide; - reg var_bool; + reg var_bool; // verilator lint_off BLKANDNBLK reg [11:0] var_flop; @@ -62,62 +62,62 @@ module tpub ( integer cyc; initial cyc=1; always @ (posedge clk) begin if (cyc!=0) begin - cyc <= cyc + 1; - // cyc==1 is in top level - if (cyc==2) begin - publicNoArgs; - publicSetBool(1'b1); - publicSetLong(24'habca); - publicSetQuad(60'h4444_3333_2222); - publicSetWide(72'h12_5678_9123_1245_2352); - var_flop <= 12'habe; - end - if (cyc==3) begin - if (1'b1 != publicGetSetBool(1'b0)) $stop; - if (24'habca != publicGetSetLong(24'h1234)) $stop; - if (60'h4444_3333_2222 != publicGetSetQuad(60'h123_4567_89ab)) $stop; - if (72'h12_5678_9123_1245_2352 != publicGetSetWide(72'hac_abca_aaaa_bbbb_1234)) $stop; - end - if (cyc==4) begin - publicGetBool(got_bool); - if (1'b0 != got_bool) $stop; - publicGetLong(got_long); - if (24'h1234 != got_long) $stop; - publicGetQuad(got_quad); - if (60'h123_4567_89ab != got_quad) $stop; - publicGetWide(got_wide); - if (72'hac_abca_aaaa_bbbb_1234 != got_wide) $stop; - end - // + cyc <= cyc + 1; + // cyc==1 is in top level + if (cyc==2) begin + publicNoArgs; + publicSetBool(1'b1); + publicSetLong(24'habca); + publicSetQuad(60'h4444_3333_2222); + publicSetWide(72'h12_5678_9123_1245_2352); + var_flop <= 12'habe; + end + if (cyc==3) begin + if (1'b1 != publicGetSetBool(1'b0)) $stop; + if (24'habca != publicGetSetLong(24'h1234)) $stop; + if (60'h4444_3333_2222 != publicGetSetQuad(60'h123_4567_89ab)) $stop; + if (72'h12_5678_9123_1245_2352 != publicGetSetWide(72'hac_abca_aaaa_bbbb_1234)) $stop; + end + if (cyc==4) begin + publicGetBool(got_bool); + if (1'b0 != got_bool) $stop; + publicGetLong(got_long); + if (24'h1234 != got_long) $stop; + publicGetQuad(got_quad); + if (60'h123_4567_89ab != got_quad) $stop; + publicGetWide(got_wide); + if (72'hac_abca_aaaa_bbbb_1234 != got_wide) $stop; + end + // `ifdef VERILATOR_PUBLIC_TASKS - if (cyc==11) begin - $c("this->publicNoArgs();"); - $c("this->publicSetBool(true);"); - $c("this->publicSetLong(0x11bca);"); - $c("this->publicSetQuad(0x66655554444ULL);"); - $c("this->publicSetFlop(0x321);"); - //Unsupported: $c("WData w[3] = {0x12, 0x5678_9123, 0x1245_2352}; publicSetWide(w);"); - end - if (cyc==12) begin - $c("this->got_bool = this->publicGetSetBool(true);"); - $c("this->got_long = this->publicGetSetLong(0x11bca);"); - $c("this->got_quad = this->publicGetSetQuad(0xaaaabbbbccccULL);"); - end - if (cyc==13) begin - $c("{ bool gb; this->publicGetBool(gb); this->got_bool=gb; }"); - if (1'b1 != got_bool) $stop; - $c("this->publicGetLong(this->got_long);"); - if (24'h11bca != got_long) $stop; - $c("{ uint64_t qq; this->publicGetQuad(qq); this->got_quad=qq; }"); - if (60'haaaa_bbbb_cccc != got_quad) $stop; - $c("{ WData gw[3]; this->publicGetWide(gw); VL_ASSIGN_W(72,this->got_wide,gw); }"); - if (72'hac_abca_aaaa_bbbb_1234 != got_wide) $stop; - //Below doesn't work, because we're calling it inside the loop that sets var_flop - // if (12'h321 != var_flop) $stop; - end - if (cyc==14) begin - if ($c32("this->publicInstNum()") != i) $stop; - end + if (cyc==11) begin + $c("this->publicNoArgs();"); + $c("this->publicSetBool(true);"); + $c("this->publicSetLong(0x11bca);"); + $c("this->publicSetQuad(0x66655554444ULL);"); + $c("this->publicSetFlop(0x321);"); + //Unsupported: $c("WData w[3] = {0x12, 0x5678_9123, 0x1245_2352}; publicSetWide(w);"); + end + if (cyc==12) begin + $c("this->got_bool = this->publicGetSetBool(true);"); + $c("this->got_long = this->publicGetSetLong(0x11bca);"); + $c("this->got_quad = this->publicGetSetQuad(0xaaaabbbbccccULL);"); + end + if (cyc==13) begin + $c("{ bool gb; this->publicGetBool(gb); this->got_bool=gb; }"); + if (1'b1 != got_bool) $stop; + $c("this->publicGetLong(this->got_long);"); + if (24'h11bca != got_long) $stop; + $c("{ uint64_t qq; this->publicGetQuad(qq); this->got_quad=qq; }"); + if (60'haaaa_bbbb_cccc != got_quad) $stop; + $c("{ WData gw[3]; this->publicGetWide(gw); VL_ASSIGN_W(72,this->got_wide,gw); }"); + if (72'hac_abca_aaaa_bbbb_1234 != got_wide) $stop; + //Below doesn't work, because we're calling it inside the loop that sets var_flop + // if (12'h321 != var_flop) $stop; + end + if (cyc==14) begin + if ($c32("this->publicInstNum()") != i) $stop; + end `endif end end @@ -143,8 +143,8 @@ module tpub ( input [23:0] in_long; reg [23:0] not_long; begin - not_long = ~in_long; // Test that we can have local variables - var_long = ~not_long; + not_long = ~in_long; // Test that we can have local variables + var_long = ~not_long; end endtask @@ -194,8 +194,8 @@ module tpub ( // verilator public input in_bool; begin - publicGetSetBool = var_bool; - var_bool = in_bool; + publicGetSetBool = var_bool; + var_bool = in_bool; end endfunction @@ -203,8 +203,8 @@ module tpub ( // verilator public input [23:0] in_long; begin - publicGetSetLong = var_long; - var_long = in_long; + publicGetSetLong = var_long; + var_long = in_long; end endfunction @@ -212,8 +212,8 @@ module tpub ( // verilator public input [59:0] in_quad; begin - publicGetSetQuad = var_quad; - var_quad = in_quad; + publicGetSetQuad = var_quad; + var_quad = in_quad; end endfunction @@ -221,8 +221,8 @@ module tpub ( // Can't be public, as no wide return types in C++ input [71:0] in_wide; begin - publicGetSetWide = var_wide; - var_wide = in_wide; + publicGetSetWide = var_wide; + var_wide = in_wide; end endfunction diff --git a/test_regress/t/t_func_rand.v b/test_regress/t/t_func_rand.v index 5da1f012a..053ffe78d 100644 --- a/test_regress/t/t_func_rand.v +++ b/test_regress/t/t_func_rand.v @@ -20,9 +20,9 @@ module t (clk, Rand); input [7:0] idx; begin `ifdef verilator - QxRand32 = $c("this->QxRandTbl(", tbl, ",", idx, ")"); + QxRand32 = $c("this->QxRandTbl(", tbl, ",", idx, ")"); `else - QxRand32 = 32'hfeed0fad; + QxRand32 = 32'hfeed0fad; `endif end endfunction diff --git a/test_regress/t/t_func_range.v b/test_regress/t/t_func_range.v index c5a0cf3e0..3f1de54f6 100644 --- a/test_regress/t/t_func_range.v +++ b/test_regress/t/t_func_range.v @@ -25,11 +25,11 @@ module t (clk); input [`INT_RANGE] m; begin - copy_range = y; - stashb = b; - stasha = a; - stashn = n; - stashm = m; + copy_range = y; + stashb = b; + stasha = a; + stashn = n; + stashm = m; end endfunction @@ -37,27 +37,27 @@ module t (clk); parameter NUM_OF_REGS = 32; reg [NUM_OF_REGS*DATA_SIZE-1 : 0] memread_rf; - reg [DATA_SIZE-1:0] memread_rf_reg; + reg [DATA_SIZE-1:0] memread_rf_reg; always @(memread_rf) begin : memread_convert memread_rf_reg = copy_range('d0, DATA_SIZE-'d1, DATA_SIZE-'d1, memread_rf, - DATA_SIZE-'d1, DATA_SIZE-'d1); + DATA_SIZE-'d1, DATA_SIZE-'d1); end integer cyc; initial cyc=1; always @ (posedge clk) begin if (cyc!=0) begin - cyc <= cyc + 1; - if (cyc==1) begin - memread_rf = 512'haa; - end - if (cyc==3) begin - if (stashb != 'd15) $stop; - if (stasha != 'd15) $stop; - if (stashn != 'd15) $stop; - if (stashm != 'd15) $stop; - $write("*-* All Finished *-*\n"); - $finish; - end + cyc <= cyc + 1; + if (cyc==1) begin + memread_rf = 512'haa; + end + if (cyc==3) begin + if (stashb != 'd15) $stop; + if (stasha != 'd15) $stop; + if (stashn != 'd15) $stop; + if (stashm != 'd15) $stop; + $write("*-* All Finished *-*\n"); + $finish; + end end end diff --git a/test_regress/t/t_func_real_abs.v b/test_regress/t/t_func_real_abs.v index fd6c7c9a6..5f14de2f6 100644 --- a/test_regress/t/t_func_real_abs.v +++ b/test_regress/t/t_func_real_abs.v @@ -19,7 +19,7 @@ module t (/*AUTOARG*/); range_chk = 0; if ( last >= 0 ) begin if ( ABS(last - period) > cmp ) begin - range_chk = 1; + range_chk = 1; end end endfunction @@ -28,11 +28,11 @@ module t (/*AUTOARG*/); input num; real num; if (num > $rtoi(num)) - ceil = $rtoi(num) + 1; + ceil = $rtoi(num) + 1; else - // verilator lint_off REALCVT - ceil = num; - // verilator lint_on REALCVT + // verilator lint_off REALCVT + ceil = num; + // verilator lint_on REALCVT endfunction initial begin diff --git a/test_regress/t/t_func_real_param.v b/test_regress/t/t_func_real_param.v index dad6ec3b8..d446632ba 100644 --- a/test_regress/t/t_func_real_param.v +++ b/test_regress/t/t_func_real_param.v @@ -9,7 +9,7 @@ module t(); function real get_real_one; - input ignored; + input ignored; get_real_one = 1.1; endfunction @@ -18,10 +18,10 @@ module t(); generate initial begin - if (R_PARAM != 1.1) $stop; - if (R_PARAM_2 != 1'b1) $stop; - $write("*-* All Finished *-*\n"); - $finish; + if (R_PARAM != 1.1) $stop; + if (R_PARAM_2 != 1'b1) $stop; + $write("*-* All Finished *-*\n"); + $finish; end endgenerate diff --git a/test_regress/t/t_func_regfirst.v b/test_regress/t/t_func_regfirst.v index c45dfc614..3d868a17c 100644 --- a/test_regress/t/t_func_regfirst.v +++ b/test_regress/t/t_func_regfirst.v @@ -12,36 +12,36 @@ module t (clk); reg q; f6 f6 (/*AUTOINST*/ - // Outputs - .q (q), - // Inputs - .a (a[2:0]), - .b (b[2:0]), - .clk (clk)); + // Outputs + .q (q), + // Inputs + .a (a[2:0]), + .b (b[2:0]), + .clk (clk)); integer cyc; initial cyc=1; always @ (posedge clk) begin if (cyc!=0) begin - cyc <= cyc + 1; - if (cyc==1) begin - a <= 3'b000; - b <= 3'b100; - end - if (cyc==2) begin - a <= 3'b011; - b <= 3'b001; - if (q != 1'b0) $stop; - end - if (cyc==3) begin - a <= 3'b011; - b <= 3'b011; - if (q != 1'b0) $stop; - end - if (cyc==9) begin - if (q != 1'b1) $stop; - $write("*-* All Finished *-*\n"); - $finish; - end + cyc <= cyc + 1; + if (cyc==1) begin + a <= 3'b000; + b <= 3'b100; + end + if (cyc==2) begin + a <= 3'b011; + b <= 3'b001; + if (q != 1'b0) $stop; + end + if (cyc==3) begin + a <= 3'b011; + b <= 3'b011; + if (q != 1'b0) $stop; + end + if (cyc==9) begin + if (q != 1'b1) $stop; + $write("*-* All Finished *-*\n"); + $finish; + end end end @@ -49,22 +49,22 @@ endmodule module f6 (a, b, clk, q); input [2:0] a; - input [2:0] b; - input clk; - output q; - reg out; + input [2:0] b; + input clk; + output q; + reg out; function func6; - reg result; + reg result; input [5:0] src; begin - if (src[5:0] == 6'b011011) begin - result = 1'b1; - end - else begin - result = 1'b0; - end - func6 = result; + if (src[5:0] == 6'b011011) begin + result = 1'b1; + end + else begin + result = 1'b0; + end + func6 = result; end endfunction diff --git a/test_regress/t/t_func_return.v b/test_regress/t/t_func_return.v index 6732caf7b..93f8d9538 100644 --- a/test_regress/t/t_func_return.v +++ b/test_regress/t/t_func_return.v @@ -14,9 +14,9 @@ module t (/*AUTOARG*/ ); input clk; - integer cyc = 0; - reg [63:0] crc; - reg [63:0] sum; + integer cyc = 0; + reg [63:0] crc; + reg [63:0] sum; // Take CRC data and apply to testblock inputs wire [31:0] in = crc[31:0]; @@ -37,23 +37,23 @@ module t (/*AUTOARG*/ crc <= {crc[62:0], crc[63] ^ crc[2] ^ crc[0]}; sum <= result ^ {sum[62:0], sum[63] ^ sum[2] ^ sum[0]}; if (cyc==0) begin - // Setup - crc <= 64'h5aef0c8d_d70a4497; - sum <= 64'h0; + // Setup + crc <= 64'h5aef0c8d_d70a4497; + sum <= 64'h0; end else if (cyc<10) begin - sum <= 64'h0; + sum <= 64'h0; end else if (cyc<90) begin end else if (cyc==99) begin - $write("[%0t] cyc==%0d crc=%x sum=%x\n", $time, cyc, crc, sum); - if (crc !== 64'hc77bb9b3784ea091) $stop; - // What checksum will we end up with (above print should match) + $write("[%0t] cyc==%0d crc=%x sum=%x\n", $time, cyc, crc, sum); + if (crc !== 64'hc77bb9b3784ea091) $stop; + // What checksum will we end up with (above print should match) `define EXPECTED_SUM 64'hc918fa0aa882a206 - if (sum !== `EXPECTED_SUM) $stop; - $write("*-* All Finished *-*\n"); - $finish; + if (sum !== `EXPECTED_SUM) $stop; + $write("*-* All Finished *-*\n"); + $finish; end end diff --git a/test_regress/t/t_func_sum.v b/test_regress/t/t_func_sum.v index cf5c8b644..38d9689dd 100644 --- a/test_regress/t/t_func_sum.v +++ b/test_regress/t/t_func_sum.v @@ -10,24 +10,24 @@ module t (/*AUTOARG*/ ); input clk; - integer cyc = 0; - reg [63:0] crc; - reg [63:0] sum; + integer cyc = 0; + reg [63:0] crc; + reg [63:0] sum; wire [9:0] I1 = crc[9:0]; wire [9:0] I2 = crc[19:10]; /*AUTOWIRE*/ // Beginning of automatic wires (for undeclared instantiated-module outputs) - wire [9:0] S; // From test of Test.v + wire [9:0] S; // From test of Test.v // End of automatics Test test (/*AUTOINST*/ - // Outputs - .S (S[9:0]), - // Inputs - .I1 (I1[9:0]), - .I2 (I2[9:0])); + // Outputs + .S (S[9:0]), + // Inputs + .I1 (I1[9:0]), + .I2 (I2[9:0])); wire [63:0] result = {32'h0, 22'h0, S}; @@ -42,20 +42,20 @@ module t (/*AUTOARG*/ crc <= {crc[62:0], crc[63] ^ crc[2] ^ crc[0]}; sum <= result ^ {sum[62:0], sum[63] ^ sum[2] ^ sum[0]}; if (cyc==0) begin - // Setup - crc <= 64'h5aef0c8d_d70a4497; + // Setup + crc <= 64'h5aef0c8d_d70a4497; end else if (cyc<10) begin - sum <= 64'h0; + sum <= 64'h0; end else if (cyc<90) begin end else if (cyc==99) begin - $write("[%0t] cyc==%0d crc=%x sum=%x\n", $time, cyc, crc, sum); - if (crc !== 64'hc77bb9b3784ea091) $stop; - if (sum !== `EXPECTED_SUM) $stop; - $write("*-* All Finished *-*\n"); - $finish; + $write("[%0t] cyc==%0d crc=%x sum=%x\n", $time, cyc, crc, sum); + if (crc !== 64'hc77bb9b3784ea091) $stop; + if (sum !== `EXPECTED_SUM) $stop; + $write("*-* All Finished *-*\n"); + $finish; end end @@ -84,10 +84,10 @@ module Test (/*AUTOARG*/ task t2; input[9:0] In1,In2; output [9:0] Sum; - integer I; + integer I; begin - for (I=0;I<10;I=I+1) - t1(In1[I],In2[I],Sum[I]); + for (I=0;I<10;I=I+1) + t1(In1[I],In2[I],Sum[I]); end endtask endmodule diff --git a/test_regress/t/t_func_twocall.v b/test_regress/t/t_func_twocall.v index e6dcd1ee6..3181bf757 100644 --- a/test_regress/t/t_func_twocall.v +++ b/test_regress/t/t_func_twocall.v @@ -11,25 +11,25 @@ module t (clk); wire [61:59] ah = crc[5:3]; wire [61:59] bh = ~crc[4:2]; - wire [41:2] al = {crc,crc,crc,crc,crc}; - wire [41:2] bl = ~{crc[6:0],crc[6:0],crc[6:0],crc[6:0],crc[6:0],crc[6:2]}; - reg sel; + wire [41:2] al = {crc,crc,crc,crc,crc}; + wire [41:2] bl = ~{crc[6:0],crc[6:0],crc[6:0],crc[6:0],crc[6:0],crc[6:2]}; + reg sel; wire [61:28] q = ( sel - ? func(ah, al) - : func(bh, bl)); + ? func(ah, al) + : func(bh, bl)); function [61:28] func; - input [61:59] inh; - input [41:2] inl; - reg [42:28] func_mid; - reg carry; + input [61:59] inh; + input [41:2] inl; + reg [42:28] func_mid; + reg carry; begin - carry = &inl[27:2]; - func_mid = {1'b0,inl[41:28]} + {14'b0, carry}; - func[61:59] = inh + {2'b0, func_mid[42]}; - func[58:42] = {17{func_mid[41]}}; - func[41:28] = func_mid[41:28]; + carry = &inl[27:2]; + func_mid = {1'b0,inl[41:28]} + {14'b0, carry}; + func[61:59] = inh + {2'b0, func_mid[42]}; + func[58:42] = {17{func_mid[41]}}; + func[41:28] = func_mid[41:28]; end endfunction @@ -37,24 +37,24 @@ module t (clk); always @ (posedge clk) begin //$write("%d %x\n", cyc, q); if (cyc!=0) begin - cyc <= cyc + 1; - sel <= ~sel; - crc <= {crc[6:0], ~^ {crc[7],crc[5],crc[4],crc[3]}}; - if (cyc==1) begin - sel <= 1'b1; - crc <= 8'h12; - end - if (cyc==2) if (q!=34'h100000484) $stop; - if (cyc==3) if (q!=34'h37fffeddb) $stop; - if (cyc==4) if (q!=34'h080001212) $stop; - if (cyc==5) if (q!=34'h1fffff7ef) $stop; - if (cyc==6) if (q!=34'h200000848) $stop; - if (cyc==7) if (q!=34'h380001ebd) $stop; - if (cyc==8) if (q!=34'h07fffe161) $stop; - if (cyc==9) begin - $write("*-* All Finished *-*\n"); - $finish; - end + cyc <= cyc + 1; + sel <= ~sel; + crc <= {crc[6:0], ~^ {crc[7],crc[5],crc[4],crc[3]}}; + if (cyc==1) begin + sel <= 1'b1; + crc <= 8'h12; + end + if (cyc==2) if (q!=34'h100000484) $stop; + if (cyc==3) if (q!=34'h37fffeddb) $stop; + if (cyc==4) if (q!=34'h080001212) $stop; + if (cyc==5) if (q!=34'h1fffff7ef) $stop; + if (cyc==6) if (q!=34'h200000848) $stop; + if (cyc==7) if (q!=34'h380001ebd) $stop; + if (cyc==8) if (q!=34'h07fffe161) $stop; + if (cyc==9) begin + $write("*-* All Finished *-*\n"); + $finish; + end end end diff --git a/test_regress/t/t_func_under2.v b/test_regress/t/t_func_under2.v index 30d2515c6..7976de909 100644 --- a/test_regress/t/t_func_under2.v +++ b/test_regress/t/t_func_under2.v @@ -13,9 +13,9 @@ module t (/*AUTOARG*/ clk ); - input clk; + input clk; output integer val; - integer dbg_addr = 0; + integer dbg_addr = 0; function func1; input en; @@ -24,7 +24,7 @@ module t (/*AUTOARG*/ endfunction function func2; - input en; + input en; input [31:0] a; func2 = en && (a == 2); endfunction diff --git a/test_regress/t/t_func_wide.v b/test_regress/t/t_func_wide.v index ede40e84a..18884e285 100644 --- a/test_regress/t/t_func_wide.v +++ b/test_regress/t/t_func_wide.v @@ -7,22 +7,22 @@ module t (clk); input clk; - reg [43:0] mi; - wire [31:0] mo; + reg [43:0] mi; + wire [31:0] mo; muxtop um ( mi, mo); integer cyc; initial cyc=1; always @ (posedge clk) begin if (cyc!=0) begin - cyc <= cyc + 1; - if (cyc==1) begin - mi <= 44'h1234567890; - end - if (cyc==3) begin - if (mo !== 32'h12345678) $stop; - $write("*-* All Finished *-*\n"); - $finish; - end + cyc <= cyc + 1; + if (cyc==1) begin + mi <= 44'h1234567890; + end + if (cyc==3) begin + if (mo !== 32'h12345678) $stop; + $write("*-* All Finished *-*\n"); + $finish; + end end end diff --git a/test_regress/t/t_fuzz_eof_bad.v b/test_regress/t/t_fuzz_eof_bad.v index e82e286da..3b3591544 100644 --- a/test_regress/t/t_fuzz_eof_bad.v +++ b/test_regress/t/t_fuzz_eof_bad.v @@ -1,3 +1,3 @@ module a; - initial $lay(*Hello!=n"); + initial $lay(*Hello!=n"); endmodule diff --git a/test_regress/t/t_gantt_io_arm.dat b/test_regress/t/t_gantt_io_arm.dat index 23d79c253..7abda2023 100644 --- a/test_regress/t/t_gantt_io_arm.dat +++ b/test_regress/t/t_gantt_io_arm.dat @@ -3,45 +3,45 @@ VLPROF arg +verilator+prof+exec+start+1 VLPROF arg +verilator+prof+exec+window+2 VLPROF stat threads 2 VLPROF stat yields 51 -VLPROFPROC processor : 0 -VLPROFPROC model name : Phytium,FT-2500/128 -VLPROFPROC BogoMIPS : 100.00 -VLPROFPROC Features : fp asimd evtstrm aes pmull sha1 sha2 crc32 cpuid -VLPROFPROC CPU implementer : 0x70 +VLPROFPROC processor : 0 +VLPROFPROC model name : Phytium,FT-2500/128 +VLPROFPROC BogoMIPS : 100.00 +VLPROFPROC Features : fp asimd evtstrm aes pmull sha1 sha2 crc32 cpuid +VLPROFPROC CPU implementer : 0x70 VLPROFPROC CPU architecture: 8 -VLPROFPROC CPU variant : 0x1 -VLPROFPROC CPU part : 0x663 -VLPROFPROC CPU revision : 3 +VLPROFPROC CPU variant : 0x1 +VLPROFPROC CPU part : 0x663 +VLPROFPROC CPU revision : 3 VLPROFPROC -VLPROFPROC processor : 1 -VLPROFPROC model name : Phytium,FT-2500/128 -VLPROFPROC BogoMIPS : 100.00 -VLPROFPROC Features : fp asimd evtstrm aes pmull sha1 sha2 crc32 cpuid -VLPROFPROC CPU implementer : 0x70 +VLPROFPROC processor : 1 +VLPROFPROC model name : Phytium,FT-2500/128 +VLPROFPROC BogoMIPS : 100.00 +VLPROFPROC Features : fp asimd evtstrm aes pmull sha1 sha2 crc32 cpuid +VLPROFPROC CPU implementer : 0x70 VLPROFPROC CPU architecture: 8 -VLPROFPROC CPU variant : 0x1 -VLPROFPROC CPU part : 0x663 -VLPROFPROC CPU revision : 3 +VLPROFPROC CPU variant : 0x1 +VLPROFPROC CPU part : 0x663 +VLPROFPROC CPU revision : 3 VLPROFPROC -VLPROFPROC processor : 2 -VLPROFPROC model name : Phytium,FT-2500/128 -VLPROFPROC BogoMIPS : 100.00 -VLPROFPROC Features : fp asimd evtstrm aes pmull sha1 sha2 crc32 cpuid -VLPROFPROC CPU implementer : 0x70 +VLPROFPROC processor : 2 +VLPROFPROC model name : Phytium,FT-2500/128 +VLPROFPROC BogoMIPS : 100.00 +VLPROFPROC Features : fp asimd evtstrm aes pmull sha1 sha2 crc32 cpuid +VLPROFPROC CPU implementer : 0x70 VLPROFPROC CPU architecture: 8 -VLPROFPROC CPU variant : 0x1 -VLPROFPROC CPU part : 0x663 -VLPROFPROC CPU revision : 3 +VLPROFPROC CPU variant : 0x1 +VLPROFPROC CPU part : 0x663 +VLPROFPROC CPU revision : 3 VLPROFPROC -VLPROFPROC processor : 3 -VLPROFPROC model name : Phytium,FT-2500/128 -VLPROFPROC BogoMIPS : 100.00 -VLPROFPROC Features : fp asimd evtstrm aes pmull sha1 sha2 crc32 cpuid -VLPROFPROC CPU implementer : 0x70 +VLPROFPROC processor : 3 +VLPROFPROC model name : Phytium,FT-2500/128 +VLPROFPROC BogoMIPS : 100.00 +VLPROFPROC Features : fp asimd evtstrm aes pmull sha1 sha2 crc32 cpuid +VLPROFPROC CPU implementer : 0x70 VLPROFPROC CPU architecture: 8 -VLPROFPROC CPU variant : 0x1 -VLPROFPROC CPU part : 0x663 -VLPROFPROC CPU revision : 3 +VLPROFPROC CPU variant : 0x1 +VLPROFPROC CPU part : 0x663 +VLPROFPROC CPU revision : 3 VLPROFPROC VLPROFTHREAD 0 VLPROFEXEC EVAL_BEGIN 57709 diff --git a/test_regress/t/t_gate_array.v b/test_regress/t/t_gate_array.v index f9673c861..239d17495 100644 --- a/test_regress/t/t_gate_array.v +++ b/test_regress/t/t_gate_array.v @@ -10,9 +10,9 @@ module t (/*AUTOARG*/ ); input clk; - integer cyc = 0; - reg [63:0] crc; - reg [63:0] sum; + integer cyc = 0; + reg [63:0] crc; + reg [63:0] sum; // Take CRC data and apply to testblock inputs wire [7:0] a = crc[7:0]; @@ -20,16 +20,16 @@ module t (/*AUTOARG*/ /*AUTOWIRE*/ // Beginning of automatic wires (for undeclared instantiated-module outputs) - wire [63:0] out; // From test of Test.v + wire [63:0] out; // From test of Test.v // End of automatics Test test (/*AUTOINST*/ - // Outputs - .out (out[63:0]), - // Inputs - .clk (clk), - .a (a[7:0]), - .b (b[7:0])); + // Outputs + .out (out[63:0]), + // Inputs + .clk (clk), + .a (a[7:0]), + .b (b[7:0])); // Aggregate outputs into a single result vector wire [63:0] result = {out}; @@ -43,23 +43,23 @@ module t (/*AUTOARG*/ crc <= {crc[62:0], crc[63] ^ crc[2] ^ crc[0]}; sum <= result ^ {sum[62:0], sum[63] ^ sum[2] ^ sum[0]}; if (cyc==0) begin - // Setup - crc <= 64'h5aef0c8d_d70a4497; - sum <= 64'h0; + // Setup + crc <= 64'h5aef0c8d_d70a4497; + sum <= 64'h0; end else if (cyc<10) begin - sum <= 64'h0; + sum <= 64'h0; end else if (cyc<90) begin end else if (cyc==99) begin - $write("[%0t] cyc==%0d crc=%x sum=%x\n", $time, cyc, crc, sum); - if (crc !== 64'hc77bb9b3784ea091) $stop; - // What checksum will we end up with (above print should match) + $write("[%0t] cyc==%0d crc=%x sum=%x\n", $time, cyc, crc, sum); + if (crc !== 64'hc77bb9b3784ea091) $stop; + // What checksum will we end up with (above print should match) `define EXPECTED_SUM 64'h0908a1f2194d24ee - if (sum !== `EXPECTED_SUM) $stop; - $write("*-* All Finished *-*\n"); - $finish; + if (sum !== `EXPECTED_SUM) $stop; + $write("*-* All Finished *-*\n"); + $finish; end end diff --git a/test_regress/t/t_gate_elim.v b/test_regress/t/t_gate_elim.v index 910a0ff4c..a85443d10 100644 --- a/test_regress/t/t_gate_elim.v +++ b/test_regress/t/t_gate_elim.v @@ -35,42 +35,42 @@ module t (/*AUTOARG*/ $display("%b",{qa,qb,qc,qd,qe}); `endif if (cyc!=0) begin - cyc <= cyc + 1; - if (cyc==1) begin - b <= 1'b1; - end - if (cyc==2) begin - if (qa!=1'b1) $stop; - if (qb!=1'b0) $stop; - if (qd!=1'b0) $stop; - b <= 1'b0; - end - if (cyc==3) begin - if (qa!=1'b0) $stop; - if (qb!=1'b0) $stop; - if (qd!=1'b0) $stop; - if (qe!=1'b0) $stop; - b <= 1'b1; - end - if (cyc==4) begin - if (qa!=1'b1) $stop; - if (qb!=1'b0) $stop; - if (qd!=1'b0) $stop; - if (qe!=1'b1) $stop; - b <= 1'b0; - end - if (cyc==5) begin - $write("*-* All Finished *-*\n"); - $finish; - end + cyc <= cyc + 1; + if (cyc==1) begin + b <= 1'b1; + end + if (cyc==2) begin + if (qa!=1'b1) $stop; + if (qb!=1'b0) $stop; + if (qd!=1'b0) $stop; + b <= 1'b0; + end + if (cyc==3) begin + if (qa!=1'b0) $stop; + if (qb!=1'b0) $stop; + if (qd!=1'b0) $stop; + if (qe!=1'b0) $stop; + b <= 1'b1; + end + if (cyc==4) begin + if (qa!=1'b1) $stop; + if (qb!=1'b0) $stop; + if (qd!=1'b0) $stop; + if (qe!=1'b1) $stop; + b <= 1'b0; + end + if (cyc==5) begin + $write("*-* All Finished *-*\n"); + $finish; + end end end endmodule module ta ( - input vconst, - input b, - output reg q); + input vconst, + input b, + output reg q); always @ (/*AS*/b or vconst) begin q = vconst | b; @@ -78,9 +78,9 @@ module ta ( endmodule module tb ( - input vconst, - input clk, - output reg q); + input vconst, + input clk, + output reg q); always @ (posedge clk) begin q <= vconst; @@ -88,9 +88,9 @@ module tb ( endmodule module tc ( - input vconst, - input b, - output reg q); + input vconst, + input b, + output reg q); always @ (posedge vconst) begin q <= b; $stop; @@ -98,9 +98,9 @@ module tc ( endmodule module td ( - input vconst, - input b, - output reg q); + input vconst, + input b, + output reg q); always @ (/*AS*/vconst) begin q = vconst; @@ -108,11 +108,11 @@ module td ( endmodule module te ( - input clk, - input vconst, - input b, - output reg q); - reg qmid; + input clk, + input vconst, + input b, + output reg q); + reg qmid; always @ (posedge vconst or posedge clk) begin qmid <= b; end diff --git a/test_regress/t/t_gate_implicit.v b/test_regress/t/t_gate_implicit.v index 3e485ce34..0a1dd648e 100644 --- a/test_regress/t/t_gate_implicit.v +++ b/test_regress/t/t_gate_implicit.v @@ -10,24 +10,24 @@ module t (/*AUTOARG*/ ); input clk; - integer cyc = 0; - reg [63:0] crc; - reg [63:0] sum; + integer cyc = 0; + reg [63:0] crc; + reg [63:0] sum; /*AUTOWIRE*/ // Beginning of automatic wires (for undeclared instantiated-module outputs) - wire RBL2; // From t of Test.v + wire RBL2; // From t of Test.v // End of automatics - wire RWL1 = crc[2]; - wire RWL2 = crc[3]; + wire RWL1 = crc[2]; + wire RWL2 = crc[3]; Test t (/*AUTOINST*/ - // Outputs - .RBL2 (RBL2), - // Inputs - .RWL1 (RWL1), - .RWL2 (RWL2)); + // Outputs + .RBL2 (RBL2), + // Inputs + .RWL1 (RWL1), + .RWL2 (RWL2)); // Aggregate outputs into a single result vector wire [63:0] result = {63'h0, RBL2}; @@ -41,23 +41,23 @@ module t (/*AUTOARG*/ crc <= {crc[62:0], crc[63] ^ crc[2] ^ crc[0]}; sum <= result ^ {sum[62:0], sum[63] ^ sum[2] ^ sum[0]}; if (cyc==0) begin - // Setup - crc <= 64'h5aef0c8d_d70a4497; - sum <= 64'h0; + // Setup + crc <= 64'h5aef0c8d_d70a4497; + sum <= 64'h0; end else if (cyc<10) begin - sum <= 64'h0; + sum <= 64'h0; end else if (cyc<90) begin end else if (cyc==99) begin - $write("[%0t] cyc==%0d crc=%x sum=%x\n", $time, cyc, crc, sum); - if (crc !== 64'hc77bb9b3784ea091) $stop; - // What checksum will we end up with (above print should match) + $write("[%0t] cyc==%0d crc=%x sum=%x\n", $time, cyc, crc, sum); + if (crc !== 64'hc77bb9b3784ea091) $stop; + // What checksum will we end up with (above print should match) `define EXPECTED_SUM 64'hb6d6b86aa20a882a - if (sum !== `EXPECTED_SUM) $stop; - $write("*-* All Finished *-*\n"); - $finish; + if (sum !== `EXPECTED_SUM) $stop; + $write("*-* All Finished *-*\n"); + $finish; end end diff --git a/test_regress/t/t_gated_clk_1.v b/test_regress/t/t_gated_clk_1.v index 65c4a13e5..91b547259 100644 --- a/test_regress/t/t_gated_clk_1.v +++ b/test_regress/t/t_gated_clk_1.v @@ -41,15 +41,15 @@ module t (/*AUTOARG*/ always @(posedge clk) begin if (pc == 2'b11) begin - // Correct behaviour is that res should be lagging pc in the count - // by one cycle - if (res == 2'b10) begin - $write("*-* All Finished *-*\n"); - $finish; - end - else begin - $stop; - end + // Correct behaviour is that res should be lagging pc in the count + // by one cycle + if (res == 2'b10) begin + $write("*-* All Finished *-*\n"); + $finish; + end + else begin + $stop; + end end end diff --git a/test_regress/t/t_gen_alw.v b/test_regress/t/t_gen_alw.v index 8bd091b7f..21b953839 100644 --- a/test_regress/t/t_gen_alw.v +++ b/test_regress/t/t_gen_alw.v @@ -9,9 +9,9 @@ module t (/*AUTOARG*/ ); input clk; - integer cyc = 0; - reg [63:0] crc; - reg [63:0] sum; + integer cyc = 0; + reg [63:0] crc; + reg [63:0] sum; // Take CRC data and apply to testblock inputs wire [9:0] in = crc[9:0]; @@ -19,9 +19,9 @@ module t (/*AUTOARG*/ /*AUTOWIRE*/ Test test (/*AUTOINST*/ - // Inputs - .clk (clk), - .in (in[9:0])); + // Inputs + .clk (clk), + .in (in[9:0])); // Aggregate outputs into a single result vector wire [63:0] result = {64'h0}; @@ -35,22 +35,22 @@ module t (/*AUTOARG*/ crc <= {crc[62:0], crc[63] ^ crc[2] ^ crc[0]}; sum <= result ^ {sum[62:0], sum[63] ^ sum[2] ^ sum[0]}; if (cyc==0) begin - // Setup - crc <= 64'h5aef0c8d_d70a4497; + // Setup + crc <= 64'h5aef0c8d_d70a4497; end else if (cyc<10) begin - sum <= 64'h0; + sum <= 64'h0; end else if (cyc<90) begin end else if (cyc==99) begin - $write("[%0t] cyc==%0d crc=%x sum=%x\n", $time, cyc, crc, sum); - if (crc !== 64'hc77bb9b3784ea091) $stop; - // What checksum will we end up with (above print should match) + $write("[%0t] cyc==%0d crc=%x sum=%x\n", $time, cyc, crc, sum); + if (crc !== 64'hc77bb9b3784ea091) $stop; + // What checksum will we end up with (above print should match) `define EXPECTED_SUM 64'h0 - if (sum !== `EXPECTED_SUM) $stop; - $write("*-* All Finished *-*\n"); - $finish; + if (sum !== `EXPECTED_SUM) $stop; + $write("*-* All Finished *-*\n"); + $finish; end end @@ -67,7 +67,7 @@ module Test (/*AUTOARG*/ integer ai; always @* begin for (ai=0;ai<10;ai=ai+1) begin - a[ai]=in[ai]; + a[ai]=in[ai]; end end @@ -77,14 +77,14 @@ module Test (/*AUTOARG*/ generate genvar i; for (i=0; i<2; i=i+1) begin - always @(posedge clk) begin - for (j=0; j<10; j=j+1) begin - if (a[j]) - b[i][j] <= 1'b0; - else - b[i][j] <= 1'b1; - end - end + always @(posedge clk) begin + for (j=0; j<10; j=j+1) begin + if (a[j]) + b[i][j] <= 1'b0; + else + b[i][j] <= 1'b1; + end + end end endgenerate endmodule diff --git a/test_regress/t/t_gen_assign.v b/test_regress/t/t_gen_assign.v index 4528eebab..d3f3a0e05 100644 --- a/test_regress/t/t_gen_assign.v +++ b/test_regress/t/t_gen_assign.v @@ -16,14 +16,14 @@ module t (/*AUTOARG*/ reg [63:0] crc; reg [31:0] sum; - wire [8:0] Output; - wire [8:0] Input = crc[8:0]; + wire [8:0] Output; + wire [8:0] Input = crc[8:0]; assigns assigns (/*AUTOINST*/ - // Outputs - .Output (Output[8:0]), - // Inputs - .Input (Input[8:0])); + // Outputs + .Output (Output[8:0]), + // Inputs + .Input (Input[8:0])); always @ (posedge clk) begin `ifdef TEST_VERBOSE @@ -32,17 +32,17 @@ module t (/*AUTOARG*/ cyc <= cyc + 1; crc <= {crc[62:0], crc[63] ^ crc[2] ^ crc[0]}; if (cyc==0) begin - // Setup - crc <= 64'h5aef0c8d_d70a4497; - sum <= 32'h0; + // Setup + crc <= 64'h5aef0c8d_d70a4497; + sum <= 32'h0; end else if (cyc>10 && cyc<90) begin - sum <= {sum[30:0],sum[31]} ^ {23'h0, crc[8:0]}; + sum <= {sum[30:0],sum[31]} ^ {23'h0, crc[8:0]}; end else if (cyc==99) begin - if (sum !== 32'he8bbd130) $stop; - $write("*-* All Finished *-*\n"); - $finish; + if (sum !== 32'he8bbd130) $stop; + $write("*-* All Finished *-*\n"); + $finish; end end @@ -52,10 +52,10 @@ module assigns(Input, Output); input [8:0] Input; output [8:0] Output; - genvar i; + genvar i; generate for (i = 0; i < 8; i = i + 1) begin : ap - assign Output[(i>0) ? i-1 : 8] = Input[(i>0) ? i-1 : 8]; + assign Output[(i>0) ? i-1 : 8] = Input[(i>0) ? i-1 : 8]; end endgenerate endmodule diff --git a/test_regress/t/t_gen_cond_bitrange.v b/test_regress/t/t_gen_cond_bitrange.v index 57b7fd5ec..5a1ea06b9 100644 --- a/test_regress/t/t_gen_cond_bitrange.v +++ b/test_regress/t/t_gen_cond_bitrange.v @@ -33,11 +33,11 @@ module t (/*AUTOARG*/ always @(posedge clk) begin if (count == 1) begin - $write("*-* All Finished *-*\n"); - $finish; + $write("*-* All Finished *-*\n"); + $finish; end else begin - count = count + 1; + count = count + 1; end end @@ -63,60 +63,60 @@ module test_gen for (g = 0; g < `MAX_SIZE; g = g + 1) begin if ((g < SIZE) && MASK[g]) begin - always @(posedge clk) begin + always @(posedge clk) begin `ifdef TEST_VERBOSE - $write ("Logical AND generate if MASK [%1d] = %d\n", g, MASK[g]); + $write ("Logical AND generate if MASK [%1d] = %d\n", g, MASK[g]); `endif - if (g >= SIZE) begin - $stop; - end - end - end + if (g >= SIZE) begin + $stop; + end + end + end end endgenerate generate for (g = 0; g < `MAX_SIZE; g = g + 1) begin if (!((g >= SIZE) || ~MASK[g])) begin - always @(posedge clk) begin + always @(posedge clk) begin `ifdef TEST_VERBOSE - $write ("Logical OR generate if MASK [%1d] = %d\n", g, MASK[g]); + $write ("Logical OR generate if MASK [%1d] = %d\n", g, MASK[g]); `endif - if (g >= SIZE) begin - $stop; - end - end - end + if (g >= SIZE) begin + $stop; + end + end + end end endgenerate generate for (g = 0; g < `MAX_SIZE; g = g + 1) begin if (!((g < SIZE) -> ~MASK[g])) begin - always @(posedge clk) begin + always @(posedge clk) begin `ifdef TEST_VERBOSE - $write ("Logical infer generate if MASK [%1d] = %d\n", g, MASK[g]); + $write ("Logical infer generate if MASK [%1d] = %d\n", g, MASK[g]); `endif - if (g >= SIZE) begin - $stop; - end - end - end + if (g >= SIZE) begin + $stop; + end + end + end end endgenerate generate for (g = 0; g < `MAX_SIZE; g = g + 1) begin if ( g < SIZE ? MASK[g] : 1'b0) begin - always @(posedge clk) begin + always @(posedge clk) begin `ifdef TEST_VERBOSE - $write ("Conditional generate if MASK [%1d] = %d\n", g, MASK[g]); + $write ("Conditional generate if MASK [%1d] = %d\n", g, MASK[g]); `endif - if (g >= SIZE) begin - $stop; - end - end - end + if (g >= SIZE) begin + $stop; + end + end + end end endgenerate @@ -124,15 +124,15 @@ module test_gen generate for (g = 0; g < `MAX_SIZE; g = g + 1) begin if ( g >= SIZE ? 1'b0 : MASK[g]) begin - always @(posedge clk) begin + always @(posedge clk) begin `ifdef TEST_VERBOSE - $write ("Conditional generate if MASK [%1d] = %d\n", g, MASK[g]); + $write ("Conditional generate if MASK [%1d] = %d\n", g, MASK[g]); `endif - if (g >= SIZE) begin - $stop; - end - end - end + if (g >= SIZE) begin + $stop; + end + end + end end endgenerate diff --git a/test_regress/t/t_gen_cond_const.v b/test_regress/t/t_gen_cond_const.v index 870ee4f12..3b47a45fd 100644 --- a/test_regress/t/t_gen_cond_const.v +++ b/test_regress/t/t_gen_cond_const.v @@ -33,11 +33,11 @@ module t (/*AUTOARG*/ always @(posedge clk) begin if (count == 1) begin - $write("*-* All Finished *-*\n"); - $finish; + $write("*-* All Finished *-*\n"); + $finish; end else begin - count = count + 1; + count = count + 1; end end @@ -61,11 +61,11 @@ module test_gen // errors. generate if ((SIZE < 8'h04) && MASK[0]) begin - always @(posedge clk) begin + always @(posedge clk) begin `ifdef TEST_VERBOSE - $write ("Generate IF MASK[0] = %d\n", MASK[0]); + $write ("Generate IF MASK[0] = %d\n", MASK[0]); `endif - end + end end endgenerate diff --git a/test_regress/t/t_gen_defparam.v b/test_regress/t/t_gen_defparam.v index 4d8bd560c..c8a61a1a9 100644 --- a/test_regress/t/t_gen_defparam.v +++ b/test_regress/t/t_gen_defparam.v @@ -29,11 +29,11 @@ module m1 (output wire [31:0] o); generate if (W == 0) begin m2 m2 (.o(o)); - defparam m2.PAR2 = 8; + defparam m2.PAR2 = 8; end else begin m2 m2 (.o(o)); - defparam m2.PAR2 = 4; + defparam m2.PAR2 = 4; end endgenerate endmodule diff --git a/test_regress/t/t_gen_for.v b/test_regress/t/t_gen_for.v index 5ea4631ff..fb48c7a08 100644 --- a/test_regress/t/t_gen_for.v +++ b/test_regress/t/t_gen_for.v @@ -9,22 +9,22 @@ module t (/*AUTOARG*/ clk ); input clk; - integer cyc = 0; + integer cyc = 0; reg [7:0] crc; genvar g; - wire [7:0] out_p1; - wire [15:0] out_p2; - wire [7:0] out_p3; - wire [7:0] out_p4; + wire [7:0] out_p1; + wire [15:0] out_p2; + wire [7:0] out_p3; + wire [7:0] out_p4; paramed #(.WIDTH(8), .MODE(0)) p1 (.in(crc), .out(out_p1)); paramed #(.WIDTH(16), .MODE(1)) p2 (.in({crc,crc}), .out(out_p2)); paramed #(.WIDTH(8), .MODE(2)) p3 (.in(crc), .out(out_p3)); - gencase #(.MODE(3)) p4 (.in(crc), .out(out_p4)); + gencase #(.MODE(3)) p4 (.in(crc), .out(out_p4)); - wire [7:0] out_ef; + wire [7:0] out_ef; enflop #(.WIDTH(8)) enf (.a(crc), .q(out_ef), .oe_e1(1'b1), .clk(clk)); always @ (posedge clk) begin @@ -32,21 +32,21 @@ module t (/*AUTOARG*/ cyc <= cyc + 1; crc <= {crc[6:0], ~^ {crc[7],crc[5],crc[4],crc[3]}}; if (cyc==0) begin - // Setup - crc <= 8'hed; + // Setup + crc <= 8'hed; end else if (cyc==1) begin end else if (cyc==3) begin - if (out_p1 !== 8'h2d) $stop; - if (out_p2 !== 16'h2d2d) $stop; - if (out_p3 !== 8'h78) $stop; - if (out_p4 !== 8'h44) $stop; - if (out_ef !== 8'hda) $stop; + if (out_p1 !== 8'h2d) $stop; + if (out_p2 !== 16'h2d2d) $stop; + if (out_p3 !== 8'h78) $stop; + if (out_p4 !== 8'h44) $stop; + if (out_ef !== 8'hda) $stop; end else if (cyc==9) begin - $write("*-* All Finished *-*\n"); - $finish; + $write("*-* All Finished *-*\n"); + $finish; end end @@ -63,10 +63,10 @@ module gencase (/*AUTOARG*/ output [7:0] out; generate // : genblk1 begin - case (MODE) - 2: mbuf mc [7:0] (.q(out[7:0]), .a({in[5:0],in[7:6]})); - default: mbuf mc [7:0] (.q(out[7:0]), .a({in[3:0],in[3:0]})); - endcase + case (MODE) + 2: mbuf mc [7:0] (.q(out[7:0]), .a({in[5:0],in[7:6]})); + default: mbuf mc [7:0] (.q(out[7:0]), .a({in[3:0],in[3:0]})); + endcase end endgenerate @@ -102,40 +102,40 @@ module paramed (/*AUTOARG*/ generate endgenerate - genvar i; + genvar i; generate if (MODE==0) begin - // Flip bitorder, direct assign method - for (i=0; i= 0; i = i-1) begin: fnxtclk1 - fnxtclk fnxtclk1 - (.u(c[i]), - .reset(reset), - .clk(clk), - .w(d[i]) ); + fnxtclk fnxtclk1 + (.u(c[i]), + .reset(reset), + .clk(clk), + .w(d[i]) ); end endgenerate @@ -68,9 +68,9 @@ endmodule module fnxtclk (u, reset, clk, w ); input u; - input reset; - input clk; - output reg w; + input reset; + input clk; + output reg w; always @ (posedge clk or posedge reset) begin if (reset == 1'b1) begin diff --git a/test_regress/t/t_gen_for_shuffle.v b/test_regress/t/t_gen_for_shuffle.v index ad93479ff..85316549f 100644 --- a/test_regress/t/t_gen_for_shuffle.v +++ b/test_regress/t/t_gen_for_shuffle.v @@ -9,23 +9,23 @@ module t (/*AUTOARG*/ ); input clk; - integer cyc = 0; - reg [63:0] crc; - reg [63:0] sum; + integer cyc = 0; + reg [63:0] crc; + reg [63:0] sum; // Take CRC data and apply to testblock inputs wire [31:0] in = crc[31:0]; /*AUTOWIRE*/ // Beginning of automatic wires (for undeclared instantiated-module outputs) - wire [31:0] out; // From test of Test.v + wire [31:0] out; // From test of Test.v // End of automatics Test test (/*AUTOINST*/ - // Outputs - .out (out[31:0]), - // Inputs - .in (in[31:0])); + // Outputs + .out (out[31:0]), + // Inputs + .in (in[31:0])); // Aggregate outputs into a single result vector wire [63:0] result = {32'h0, out}; @@ -39,23 +39,23 @@ module t (/*AUTOARG*/ crc <= {crc[62:0], crc[63] ^ crc[2] ^ crc[0]}; sum <= result ^ {sum[62:0], sum[63] ^ sum[2] ^ sum[0]}; if (cyc==0) begin - // Setup - crc <= 64'h5aef0c8d_d70a4497; - sum <= 64'h0; + // Setup + crc <= 64'h5aef0c8d_d70a4497; + sum <= 64'h0; end else if (cyc<10) begin - sum <= 64'h0; + sum <= 64'h0; end else if (cyc<90) begin end else if (cyc==99) begin - $write("[%0t] cyc==%0d crc=%x sum=%x\n", $time, cyc, crc, sum); - if (crc !== 64'hc77bb9b3784ea091) $stop; - // What checksum will we end up with (above print should match) + $write("[%0t] cyc==%0d crc=%x sum=%x\n", $time, cyc, crc, sum); + if (crc !== 64'hc77bb9b3784ea091) $stop; + // What checksum will we end up with (above print should match) `define EXPECTED_SUM 64'h3e3a62edb61f8c7f - if (sum !== `EXPECTED_SUM) $stop; - $write("*-* All Finished *-*\n"); - $finish; + if (sum !== `EXPECTED_SUM) $stop; + $write("*-* All Finished *-*\n"); + $finish; end end @@ -71,10 +71,10 @@ module Test (/*AUTOARG*/ input [31:0] in; output [31:0] out; - genvar i; + genvar i; generate for (i=0; i<16; i=i+1) begin : gblk - assign out[i*2+1:i*2] = in[(30-i*2)+1:(30-i*2)]; + assign out[i*2+1:i*2] = in[(30-i*2)+1:(30-i*2)]; end endgenerate endmodule diff --git a/test_regress/t/t_gen_forif.v b/test_regress/t/t_gen_forif.v index 3ffaa7085..5e70a0ee3 100644 --- a/test_regress/t/t_gen_forif.v +++ b/test_regress/t/t_gen_forif.v @@ -10,7 +10,7 @@ module t (/*AUTOARG*/ ); input clk; - integer cyc = 0; + integer cyc = 0; reg [63:0] crc; reg [63:0] sum; @@ -20,12 +20,12 @@ module t (/*AUTOARG*/ wire [3:0] Result2; Testit testit (/*AUTOINST*/ - // Outputs - .Result (Result[3:0]), - .Result2 (Result2[3:0]), - // Inputs - .clk (clk), - .Value (Value[3:0])); + // Outputs + .Result (Result[3:0]), + .Result2 (Result2[3:0]), + // Inputs + .clk (clk), + .Value (Value[3:0])); always @ (posedge clk) begin `ifdef TEST_VERBOSE @@ -34,22 +34,22 @@ module t (/*AUTOARG*/ cyc <= cyc + 1; crc <= {crc[62:0], crc[63] ^ crc[2] ^ crc[0]}; sum <= {56'h0, Result, Result2} - ^ {sum[62:0], sum[63] ^ sum[2] ^ sum[0]}; + ^ {sum[62:0], sum[63] ^ sum[2] ^ sum[0]}; if (cyc==0) begin - // Setup - crc <= 64'h5aef0c8d_d70a4497; + // Setup + crc <= 64'h5aef0c8d_d70a4497; end else if (cyc<10) begin - sum <= 64'h0; + sum <= 64'h0; end else if (cyc<90) begin end else if (cyc==99) begin - $write("*-* All Finished *-*\n"); - $write("[%0t] cyc==%0d crc=%x %x\n", $time, cyc, crc, sum); - if (crc !== 64'hc77bb9b3784ea091) $stop; - if (sum !== 64'h4af37965592f64f9) $stop; - $finish; + $write("*-* All Finished *-*\n"); + $write("[%0t] cyc==%0d crc=%x %x\n", $time, cyc, crc, sum); + if (crc !== 64'hc77bb9b3784ea091) $stop; + if (sum !== 64'h4af37965592f64f9) $stop; + $finish; end end @@ -93,14 +93,14 @@ module Testit (clk, Value, Result, Result2); genvar i; generate for (i = 0; i < 4; i = i + 1) - begin : a - if ((i == 0) || (i == 2)) begin : gblk - Test_wrap1 test (clk, Value[i] , Result[i]); - end - else begin : gblk - Test_wrap2 test (clk, Value[i], Result[i]); - end - end + begin : a + if ((i == 0) || (i == 2)) begin : gblk + Test_wrap1 test (clk, Value[i] , Result[i]); + end + else begin : gblk + Test_wrap2 test (clk, Value[i], Result[i]); + end + end endgenerate assign Result2[0] = a[0].gblk.test.t.Internal; diff --git a/test_regress/t/t_gen_if.v b/test_regress/t/t_gen_if.v index bb1770742..3a3f8dc0c 100644 --- a/test_regress/t/t_gen_if.v +++ b/test_regress/t/t_gen_if.v @@ -19,16 +19,16 @@ module t(data_i, data_o, single); generate if (op_bits == 32) begin : general_case assign data_o = data_i; - // Test implicit signals - /* verilator lint_off IMPLICIT */ - assign imp = single; - /* verilator lint_on IMPLICIT */ + // Test implicit signals + /* verilator lint_off IMPLICIT */ + assign imp = single; + /* verilator lint_on IMPLICIT */ end else begin : special_case assign data_o = {{(32 -op_bits){1'b0}},data_i}; - /* verilator lint_off IMPLICIT */ - assign imp = single; - /* verilator lint_on IMPLICIT */ + /* verilator lint_off IMPLICIT */ + assign imp = single; + /* verilator lint_on IMPLICIT */ end endgenerate endmodule diff --git a/test_regress/t/t_gen_inc.v b/test_regress/t/t_gen_inc.v index dbe517bc6..1a0caf555 100644 --- a/test_regress/t/t_gen_inc.v +++ b/test_regress/t/t_gen_inc.v @@ -9,16 +9,16 @@ module t (/*AUTOARG*/ clk ); input clk; - integer cyc = 0; + integer cyc = 0; - genvar g; - integer i; + genvar g; + integer i; reg [31:0] v; reg [31:0] gen_pre_PLUSPLUS = 32'h0; reg [31:0] gen_pre_MINUSMINUS = 32'h0; - reg [31:0] gen_post_PLUSPLUS = 32'h0; + reg [31:0] gen_post_PLUSPLUS = 32'h0; reg [31:0] gen_post_MINUSMINUS = 32'h0; reg [31:0] gen_PLUSEQ = 32'h0; reg [31:0] gen_MINUSEQ = 32'h0; @@ -27,7 +27,7 @@ module t (/*AUTOARG*/ reg [31:0] gen_MODEQ = 32'h0; reg [31:0] gen_ANDEQ = 32'h0; reg [31:0] gen_OREQ = 32'h0; - reg [31:0] gen_XOREQ = 32'h0; + reg [31:0] gen_XOREQ = 32'h0; reg [31:0] gen_SLEFTEQ = 32'h0; reg [31:0] gen_SRIGHTEQ = 32'h0; reg [31:0] gen_SSRIGHTEQ = 32'h0; @@ -54,55 +54,55 @@ module t (/*AUTOARG*/ cyc <= cyc + 1; if (cyc == 3) begin `ifdef TEST_VERBOSE - $write("gen_pre_PLUSPLUS %b\n", gen_pre_PLUSPLUS); - $write("gen_pre_MINUSMINUS %b\n", gen_pre_MINUSMINUS); - $write("gen_post_PLUSPLUS %b\n", gen_post_PLUSPLUS); - $write("gen_post_MINUSMINUS %b\n", gen_post_MINUSMINUS); - $write("gen_PLUSEQ %b\n", gen_PLUSEQ); - $write("gen_MINUSEQ %b\n", gen_MINUSEQ); - $write("gen_TIMESEQ %b\n", gen_TIMESEQ); - $write("gen_DIVEQ %b\n", gen_DIVEQ); - $write("gen_MODEQ %b\n", gen_MODEQ); - $write("gen_ANDEQ %b\n", gen_ANDEQ); - $write("gen_OREQ %b\n", gen_OREQ); - $write("gen_XOREQ %b\n", gen_XOREQ); - $write("gen_SLEFTEQ %b\n", gen_SLEFTEQ); - $write("gen_SRIGHTEQ %b\n", gen_SRIGHTEQ); - $write("gen_SSRIGHTEQ %b\n", gen_SSRIGHTEQ); + $write("gen_pre_PLUSPLUS %b\n", gen_pre_PLUSPLUS); + $write("gen_pre_MINUSMINUS %b\n", gen_pre_MINUSMINUS); + $write("gen_post_PLUSPLUS %b\n", gen_post_PLUSPLUS); + $write("gen_post_MINUSMINUS %b\n", gen_post_MINUSMINUS); + $write("gen_PLUSEQ %b\n", gen_PLUSEQ); + $write("gen_MINUSEQ %b\n", gen_MINUSEQ); + $write("gen_TIMESEQ %b\n", gen_TIMESEQ); + $write("gen_DIVEQ %b\n", gen_DIVEQ); + $write("gen_MODEQ %b\n", gen_MODEQ); + $write("gen_ANDEQ %b\n", gen_ANDEQ); + $write("gen_OREQ %b\n", gen_OREQ); + $write("gen_XOREQ %b\n", gen_XOREQ); + $write("gen_SLEFTEQ %b\n", gen_SLEFTEQ); + $write("gen_SRIGHTEQ %b\n", gen_SRIGHTEQ); + $write("gen_SSRIGHTEQ %b\n", gen_SSRIGHTEQ); `endif - if (gen_pre_PLUSPLUS !== 32'b00000000000000011111111100000000) $stop; - if (gen_pre_MINUSMINUS !== 32'b00000000000000011111111100000000) $stop; - if (gen_post_PLUSPLUS !== 32'b00000000000000011111111100000000) $stop; - if (gen_post_MINUSMINUS!== 32'b00000000000000011111111100000000) $stop; - if (gen_PLUSEQ !== 32'b00000000000000010101010100000000) $stop; - if (gen_MINUSEQ !== 32'b00000000000000010101010100000000) $stop; - if (gen_TIMESEQ !== 32'b00000000000000010000000100000000) $stop; - if (gen_DIVEQ !== 32'b00000000000000010000000100000000) $stop; - if (gen_MODEQ !== 32'b00000000000000001000000000000000) $stop; - if (gen_ANDEQ !== 32'b00000000000000000000000010000000) $stop; - if (gen_OREQ !== 32'b00000000000000000000000000000010) $stop; - if (gen_XOREQ !== 32'b00000000000000000000000010000000) $stop; - if (gen_SLEFTEQ !== 32'b00000000000000000000000100000000) $stop; - if (gen_SRIGHTEQ !== 32'b00000000000000010000000000000000) $stop; - if (gen_SSRIGHTEQ !== 32'b00000000000000010000000000000000) $stop; + if (gen_pre_PLUSPLUS !== 32'b00000000000000011111111100000000) $stop; + if (gen_pre_MINUSMINUS !== 32'b00000000000000011111111100000000) $stop; + if (gen_post_PLUSPLUS !== 32'b00000000000000011111111100000000) $stop; + if (gen_post_MINUSMINUS!== 32'b00000000000000011111111100000000) $stop; + if (gen_PLUSEQ !== 32'b00000000000000010101010100000000) $stop; + if (gen_MINUSEQ !== 32'b00000000000000010101010100000000) $stop; + if (gen_TIMESEQ !== 32'b00000000000000010000000100000000) $stop; + if (gen_DIVEQ !== 32'b00000000000000010000000100000000) $stop; + if (gen_MODEQ !== 32'b00000000000000001000000000000000) $stop; + if (gen_ANDEQ !== 32'b00000000000000000000000010000000) $stop; + if (gen_OREQ !== 32'b00000000000000000000000000000010) $stop; + if (gen_XOREQ !== 32'b00000000000000000000000010000000) $stop; + if (gen_SLEFTEQ !== 32'b00000000000000000000000100000000) $stop; + if (gen_SRIGHTEQ !== 32'b00000000000000010000000000000000) $stop; + if (gen_SSRIGHTEQ !== 32'b00000000000000010000000000000000) $stop; - v=0; for (i=8; i<=16; ++i) v[i] = 1'b1; if (v !== 32'b00000000000000011111111100000000) $stop; - v=0; for (i=16; i>=8; --i) v[i] = 1'b1; if (v !== 32'b00000000000000011111111100000000) $stop; - v=0; for (i=8; i<=16; i++) v[i] = 1'b1; if (v !== 32'b00000000000000011111111100000000) $stop; - v=0; for (i=16; i>=8; i--) v[i] = 1'b1; if (v !== 32'b00000000000000011111111100000000) $stop; - v=0; for (i=8; i<=16; i+=2) v[i] = 1'b1; if (v !== 32'b00000000000000010101010100000000) $stop; - v=0; for (i=16; i>=8; i-=2) v[i] = 1'b1; if (v !== 32'b00000000000000010101010100000000) $stop; - v=0; for (i=8; i<=16; i*=2) v[i] = 1'b1; if (v !== 32'b00000000000000010000000100000000) $stop; - v=0; for (i=16; i>=8; i/=2) v[i] = 1'b1; if (v !== 32'b00000000000000010000000100000000) $stop; - v=0; for (i=15; i>8; i%=8) v[i] = 1'b1; if (v !== 32'b00000000000000001000000000000000) $stop; - v=0; for (i=7; i>4; i&=4) v[i] = 1'b1; if (v !== 32'b00000000000000000000000010000000) $stop; - v=0; for (i=1; i<=1; i|=2) v[i] = 1'b1; if (v !== 32'b00000000000000000000000000000010) $stop; - v=0; for (i=7; i==7; i^=2) v[i] = 1'b1; if (v !== 32'b00000000000000000000000010000000) $stop; - v=0; for (i=8; i<=16; i<<=2) v[i] =1'b1; if (v !== 32'b00000000000000000000000100000000) $stop; - v=0; for (i=16; i>=8; i>>=2) v[i] =1'b1; if (v !== 32'b00000000000000010000000000000000) $stop; - v=0; for (i=16; i>=8; i>>>=2) v[i]=1'b1; if (v !== 32'b00000000000000010000000000000000) $stop; - $write("*-* All Finished *-*\n"); - $finish; + v=0; for (i=8; i<=16; ++i) v[i] = 1'b1; if (v !== 32'b00000000000000011111111100000000) $stop; + v=0; for (i=16; i>=8; --i) v[i] = 1'b1; if (v !== 32'b00000000000000011111111100000000) $stop; + v=0; for (i=8; i<=16; i++) v[i] = 1'b1; if (v !== 32'b00000000000000011111111100000000) $stop; + v=0; for (i=16; i>=8; i--) v[i] = 1'b1; if (v !== 32'b00000000000000011111111100000000) $stop; + v=0; for (i=8; i<=16; i+=2) v[i] = 1'b1; if (v !== 32'b00000000000000010101010100000000) $stop; + v=0; for (i=16; i>=8; i-=2) v[i] = 1'b1; if (v !== 32'b00000000000000010101010100000000) $stop; + v=0; for (i=8; i<=16; i*=2) v[i] = 1'b1; if (v !== 32'b00000000000000010000000100000000) $stop; + v=0; for (i=16; i>=8; i/=2) v[i] = 1'b1; if (v !== 32'b00000000000000010000000100000000) $stop; + v=0; for (i=15; i>8; i%=8) v[i] = 1'b1; if (v !== 32'b00000000000000001000000000000000) $stop; + v=0; for (i=7; i>4; i&=4) v[i] = 1'b1; if (v !== 32'b00000000000000000000000010000000) $stop; + v=0; for (i=1; i<=1; i|=2) v[i] = 1'b1; if (v !== 32'b00000000000000000000000000000010) $stop; + v=0; for (i=7; i==7; i^=2) v[i] = 1'b1; if (v !== 32'b00000000000000000000000010000000) $stop; + v=0; for (i=8; i<=16; i<<=2) v[i] =1'b1; if (v !== 32'b00000000000000000000000100000000) $stop; + v=0; for (i=16; i>=8; i>>=2) v[i] =1'b1; if (v !== 32'b00000000000000010000000000000000) $stop; + v=0; for (i=16; i>=8; i>>>=2) v[i]=1'b1; if (v !== 32'b00000000000000010000000000000000) $stop; + $write("*-* All Finished *-*\n"); + $finish; end end diff --git a/test_regress/t/t_gen_index.v b/test_regress/t/t_gen_index.v index 810266adc..97d143c11 100644 --- a/test_regress/t/t_gen_index.v +++ b/test_regress/t/t_gen_index.v @@ -26,8 +26,8 @@ module t (/*AUTOARG*/ wire [`END-1:0] x; foo foo_i (.y (y), - .x (x), - .clk (clk)); + .x (x), + .clk (clk)); always @(posedge clk) begin $write("*-* All Finished *-*\n"); @@ -38,8 +38,8 @@ endmodule // t module foo(output wire [`END-1:0] y, - input wire [`END-1:0] x, - input wire clk); + input wire [`END-1:0] x, + input wire clk); function peek_bar; peek_bar = bar_inst[`START].i_bar.r; // this is ok @@ -50,8 +50,8 @@ module foo(output wire [`END-1:0] y, generate for (g = `START; g < `END; g = g + 1) begin: bar_inst bar i_bar(.x (x[g]), - .y (y[g]), - .clk (clk)); + .y (y[g]), + .clk (clk)); end endgenerate @@ -59,8 +59,8 @@ endmodule : foo module bar(output wire y, - input wire x, - input wire clk); + input wire x, + input wire clk); reg r = 0; assign y = r; diff --git a/test_regress/t/t_gen_intdot.v b/test_regress/t/t_gen_intdot.v index 16c509e8d..240672ccd 100644 --- a/test_regress/t/t_gen_intdot.v +++ b/test_regress/t/t_gen_intdot.v @@ -11,10 +11,10 @@ module t (/*AUTOARG*/ clk ); input clk; - integer cyc = 0; + integer cyc = 0; - wire out; - reg in; + wire out; + reg in; Genit g (.clk(clk), .value(in), .result(out)); @@ -22,21 +22,21 @@ module t (/*AUTOARG*/ //$write("[%0t] cyc==%0d %x %x\n", $time, cyc, in, out); cyc <= cyc + 1; if (cyc==0) begin - // Setup - in <= 1'b1; + // Setup + in <= 1'b1; end else if (cyc==1) begin - in <= 1'b0; + in <= 1'b0; end else if (cyc==2) begin - if (out != 1'b1) $stop; + if (out != 1'b1) $stop; end else if (cyc==3) begin - if (out != 1'b0) $stop; + if (out != 1'b0) $stop; end else if (cyc==9) begin - $write("*-* All Finished *-*\n"); - $finish; + $write("*-* All Finished *-*\n"); + $finish; end end @@ -101,12 +101,12 @@ module Genit (clk, value, result); generate for ( `ifdef WITH_FOR_GENVAR - genvar + genvar `endif - i = 0; i < 1; i = i + 1) - begin : foo - Test tt (clk, value, result); - end + i = 0; i < 1; i = i + 1) + begin : foo + Test tt (clk, value, result); + end endgenerate `else Test tt (clk, value, result); diff --git a/test_regress/t/t_gen_intdot2.v b/test_regress/t/t_gen_intdot2.v index 917b6223c..b496c4f05 100644 --- a/test_regress/t/t_gen_intdot2.v +++ b/test_regress/t/t_gen_intdot2.v @@ -11,9 +11,9 @@ module t (/*AUTOARG*/ clk ); input clk; - integer cyc = 0; + integer cyc = 0; - reg check; + reg check; initial check = 1'b0; Genit g (.clk(clk), .check(check)); @@ -21,15 +21,15 @@ module t (/*AUTOARG*/ //$write("[%0t] cyc==%0d %x %x\n", $time, cyc, check, out); cyc <= cyc + 1; if (cyc==0) begin - // Setup - check <= 1'b0; + // Setup + check <= 1'b0; end else if (cyc==1) begin - check <= 1'b1; + check <= 1'b1; end else if (cyc==9) begin - $write("*-* All Finished *-*\n"); - $finish; + $write("*-* All Finished *-*\n"); + $finish; end end @@ -52,7 +52,7 @@ module Genit ( input check); // ARRAY - One cellarray1[1:0] (); //cellarray[0..1][0..1] + One cellarray1[1:0] (); //cellarray[0..1][0..1] always @ (posedge clk) if (cellarray1[0].one !== 1'b1) $stop; always @ (posedge clk) if (cellarray1[1].one !== 1'b1) $stop; @@ -60,17 +60,17 @@ module Genit ( generate // genblk1 refers to the if's name, not the "generate" itself. if (1'b1) // IMPLIED begin: genblk1 - One ifcell1(); // genblk1.ifcell1 + One ifcell1(); // genblk1.ifcell1 else - One ifcell1(); // genblk1.ifcell1 + One ifcell1(); // genblk1.ifcell1 endgenerate // DISAGREEMENT on this naming always @ (posedge clk) if (genblk1.ifcell1.one !== 1'b1) $stop; generate begin : namedif2 - if (1'b1) - One ifcell2(); // namedif2.genblk1.ifcell2 + if (1'b1) + One ifcell2(); // namedif2.genblk1.ifcell2 end endgenerate // DISAGREEMENT on this naming @@ -78,19 +78,19 @@ module Genit ( generate if (1'b1) - begin : namedif3 - One ifcell3(); // namedif3.ifcell3 - end + begin : namedif3 + One ifcell3(); // namedif3.ifcell3 + end endgenerate always @ (posedge clk) if (namedif3.ifcell3.one !== 1'b1) $stop; // CASE generate begin : casecheck - case (1'b1) - 1'b1 : - One casecell10(); // genblk4.casecell10 - endcase + case (1'b1) + 1'b1 : + One casecell10(); // genblk4.casecell10 + endcase end endgenerate // DISAGREEMENT on this naming @@ -98,9 +98,9 @@ module Genit ( generate case (1'b1) - 1'b1 : begin : namedcase11 - One casecell11(); - end + 1'b1 : begin : namedcase11 + One casecell11(); + end endcase endgenerate always @ (posedge clk) if (namedcase11.casecell11.one !== 1'b1) $stop; @@ -110,8 +110,8 @@ module Genit ( generate begin : genfor - for (i = 0; i < 2; i = i + 1) - One cellfor20 (); // genfor.genblk1[0..1].cellfor20 + for (i = 0; i < 2; i = i + 1) + One cellfor20 (); // genfor.genblk1[0..1].cellfor20 end endgenerate // DISAGREEMENT on this naming @@ -121,32 +121,32 @@ module Genit ( // COMBO generate for (i = 0; i < 2; i = i + 1) - begin : namedfor21 - One cellfor21 (); // namedfor21[0..1].cellfor21 - end + begin : namedfor21 + One cellfor21 (); // namedfor21[0..1].cellfor21 + end endgenerate always @ (posedge clk) if (namedfor21[0].cellfor21.one !== 1'b1) $stop; always @ (posedge clk) if (namedfor21[1].cellfor21.one !== 1'b1) $stop; generate for (i = 0; i < 2; i = i + 1) - begin : namedfor30 - for (j = 0; j < 2; j = j + 1) - begin : forb30 - if (j == 0) - begin : forif30 - One cellfor30a (); // namedfor30[0..1].forb30[0].forif30.cellfor30a - end - else + begin : namedfor30 + for (j = 0; j < 2; j = j + 1) + begin : forb30 + if (j == 0) + begin : forif30 + One cellfor30a (); // namedfor30[0..1].forb30[0].forif30.cellfor30a + end + else `ifdef verilator - begin : forif30b + begin : forif30b `else - begin : forif30 // forif30 seems to work on some simulators, not verilator yet + begin : forif30 // forif30 seems to work on some simulators, not verilator yet `endif - One cellfor30b (); // namedfor30[0..1].forb30[1].forif30.cellfor30b - end - end - end + One cellfor30b (); // namedfor30[0..1].forb30[1].forif30.cellfor30b + end + end + end endgenerate always @ (posedge clk) if (namedfor30[0].forb30[0].forif30.cellfor30a.one !== 1'b1) $stop; always @ (posedge clk) if (namedfor30[1].forb30[0].forif30.cellfor30a.one !== 1'b1) $stop; diff --git a/test_regress/t/t_gen_local.v b/test_regress/t/t_gen_local.v index 3e42ecf26..782e74a70 100644 --- a/test_regress/t/t_gen_local.v +++ b/test_regress/t/t_gen_local.v @@ -9,27 +9,27 @@ module t (/*AUTOARG*/ clk ); input clk; - integer cyc = 0; + integer cyc = 0; localparam N = 31; - wire [31:0] vec; + wire [31:0] vec; generate genvar g; // bug461 begin : topgen - for (g=0; g10) begin `ifdef TEST_VERBOSE $display("%m: csub.clocal=%0d dlocal=%0d", csub.clocal, dlocal); `endif - if (csub.clocal !== n) $stop; - if (dlocal !== n) $stop; + if (csub.clocal !== n) $stop; + if (dlocal !== n) $stop; end if (cyc==99) begin - $write("*-* All Finished *-*\n"); - $finish; + $write("*-* All Finished *-*\n"); + $finish; end end endmodule diff --git a/test_regress/t/t_inst_first.v b/test_regress/t/t_inst_first.v index a1c7b7c42..05b876188 100644 --- a/test_regress/t/t_inst_first.v +++ b/test_regress/t/t_inst_first.v @@ -16,110 +16,110 @@ module t (/*AUTOARG*/ /*AUTOWIRE*/ // Beginning of automatic wires (for undeclared instantiated-module outputs) - wire o_com; // From b of t_inst_first_b.v - wire o_seq_d1r; // From b of t_inst_first_b.v + wire o_com; // From b of t_inst_first_b.v + wire o_seq_d1r; // From b of t_inst_first_b.v // End of automatics integer _mode; // initial _mode=0 reg na,nb,nc,nd,ne; wire ma,mb,mc,md,me; wire da,db,dc,dd,de; - reg [7:0] wa,wb,wc,wd,we; - wire [7:0] qa,qb,qc,qd,qe; + reg [7:0] wa,wb,wc,wd,we; + wire [7:0] qa,qb,qc,qd,qe; - wire [5:0] ra; - wire [4:0] rb; - wire [29:0] rc; - wire [63:0] rd; - reg [5:0] sa; - reg [4:0] sb; - reg [29:0] sc; - reg [63:0] sd; + wire [5:0] ra; + wire [4:0] rb; + wire [29:0] rc; + wire [63:0] rd; + reg [5:0] sa; + reg [4:0] sb; + reg [29:0] sc; + reg [63:0] sd; - reg _guard1; initial _guard1=0; + reg _guard1; initial _guard1=0; wire [104:0] r_wide = {ra,rb,rc,rd}; - reg _guard2; initial _guard2=0; - wire [98:0] r_wide0 = {rb,rc,rd}; - reg _guard3; initial _guard3=0; - wire [93:0] r_wide1 = {rc,rd}; - reg _guard4; initial _guard4=0; - wire [63:0] r_wide2 = {rd}; - reg _guard5; initial _guard5=0; + reg _guard2; initial _guard2=0; + wire [98:0] r_wide0 = {rb,rc,rd}; + reg _guard3; initial _guard3=0; + wire [93:0] r_wide1 = {rc,rd}; + reg _guard4; initial _guard4=0; + wire [63:0] r_wide2 = {rd}; + reg _guard5; initial _guard5=0; wire [168:0] r_wide3 = {ra,rb,rc,rd,rd}; - reg [127:0] _guard6; initial _guard6=0; + reg [127:0] _guard6; initial _guard6=0; t_inst_first_a a ( - .clk (clk), - // Outputs - .o_w5 ({ma,mb,mc,md,me}), - .o_w5_d1r ({da,db,dc,dd,de}), - .o_w40 ({qa,qb,qc,qd,qe}), - .o_w104 ({ra,rb,rc,rd}), - // Inputs - .i_w5 ({na,nb,nc,nd,ne}), - .i_w40 ({wa,wb,wc,wd,we}), - .i_w104 ({sa,sb,sc,sd}) - ); + .clk (clk), + // Outputs + .o_w5 ({ma,mb,mc,md,me}), + .o_w5_d1r ({da,db,dc,dd,de}), + .o_w40 ({qa,qb,qc,qd,qe}), + .o_w104 ({ra,rb,rc,rd}), + // Inputs + .i_w5 ({na,nb,nc,nd,ne}), + .i_w40 ({wa,wb,wc,wd,we}), + .i_w104 ({sa,sb,sc,sd}) + ); - reg i_seq; - reg i_com; + reg i_seq; + reg i_com; wire [15:14] o2_comhigh; t_inst_first_b b ( - .o2_com (o2_comhigh), - .i2_com ({i_com,~i_com}), - .wide_for_trace (128'h1234_5678_aaaa_bbbb_cccc_dddd), - .wide_for_trace_2 (_guard6 + 128'h1234_5678_aaaa_bbbb_cccc_dddd), - /*AUTOINST*/ - // Outputs - .o_seq_d1r (o_seq_d1r), - .o_com (o_com), - // Inputs - .clk (clk), - .i_seq (i_seq), - .i_com (i_com)); + .o2_com (o2_comhigh), + .i2_com ({i_com,~i_com}), + .wide_for_trace (128'h1234_5678_aaaa_bbbb_cccc_dddd), + .wide_for_trace_2 (_guard6 + 128'h1234_5678_aaaa_bbbb_cccc_dddd), + /*AUTOINST*/ + // Outputs + .o_seq_d1r (o_seq_d1r), + .o_com (o_com), + // Inputs + .clk (clk), + .i_seq (i_seq), + .i_com (i_com)); // surefire lint_off STMINI initial _mode = 0; always @ (posedge fastclk) begin if (_mode==1) begin - if (o_com !== ~i_com) $stop; - if (o2_comhigh !== {~i_com,i_com}) $stop; + if (o_com !== ~i_com) $stop; + if (o2_comhigh !== {~i_com,i_com}) $stop; end end always @ (posedge clk) begin //$write("[%0t] t_inst: MODE = %0x NA=%x MA=%x DA=%x\n", $time, _mode, - // {na,nb,nc,nd,ne}, {ma,mb,mc,md,me}, {da,db,dc,dd,de}); + // {na,nb,nc,nd,ne}, {ma,mb,mc,md,me}, {da,db,dc,dd,de}); $write("[%0t] t_inst: MODE = %0x IS=%x OS=%x\n", $time, _mode, i_seq, o_seq_d1r); if (_mode==0) begin - $write("[%0t] t_inst: Running\n", $time); - _mode<=1; - {na,nb,nc,nd,ne} <= 5'b10110; - {wa,wb,wc,wd,we} <= {8'ha, 8'hb, 8'hc, 8'hd, 8'he}; - {sa,sb,sc,sd} <= {6'hf, 5'h3, 30'h12345, 32'h0abc_abcd, 32'h7654_3210}; - // - i_seq <= 1'b1; - i_com <= 1'b1; + $write("[%0t] t_inst: Running\n", $time); + _mode<=1; + {na,nb,nc,nd,ne} <= 5'b10110; + {wa,wb,wc,wd,we} <= {8'ha, 8'hb, 8'hc, 8'hd, 8'he}; + {sa,sb,sc,sd} <= {6'hf, 5'h3, 30'h12345, 32'h0abc_abcd, 32'h7654_3210}; + // + i_seq <= 1'b1; + i_com <= 1'b1; end else if (_mode==1) begin - _mode<=2; - if ({ma,mb,mc,md,me} !== 5'b10110) $stop; - if ({qa,qb,qc,qd,qe} !== {8'ha,8'hb,8'hc,8'hd,8'he}) $stop; - if ({sa,sb,sc,sd} !== {6'hf, 5'h3, 30'h12345, 32'h0abc_abcd, 32'h7654_3210}) $stop; + _mode<=2; + if ({ma,mb,mc,md,me} !== 5'b10110) $stop; + if ({qa,qb,qc,qd,qe} !== {8'ha,8'hb,8'hc,8'hd,8'he}) $stop; + if ({sa,sb,sc,sd} !== {6'hf, 5'h3, 30'h12345, 32'h0abc_abcd, 32'h7654_3210}) $stop; end else if (_mode==2) begin - _mode<=3; - if ({da,db,dc,dd,de} !== 5'b10110) $stop; - if (o_seq_d1r !== ~i_seq) $stop; - // - $write("*-* All Finished *-*\n"); - $finish; + _mode<=3; + if ({da,db,dc,dd,de} !== 5'b10110) $stop; + if (o_seq_d1r !== ~i_seq) $stop; + // + $write("*-* All Finished *-*\n"); + $finish; end if (|{_guard1,_guard2,_guard3,_guard4,_guard5,_guard6}) begin - $write("Guard error %x %x %x %x %x\n",_guard1,_guard2,_guard3,_guard4,_guard5); - $stop; + $write("Guard error %x %x %x %x %x\n",_guard1,_guard2,_guard3,_guard4,_guard5); + $stop; end end diff --git a/test_regress/t/t_inst_first_a.v b/test_regress/t/t_inst_first_a.v index 4e2d6c35e..f347aff35 100644 --- a/test_regress/t/t_inst_first_a.v +++ b/test_regress/t/t_inst_first_a.v @@ -13,13 +13,13 @@ module t_inst_first_a (/*AUTOARG*/ input clk; - input [4:0] i_w5; - output [4:0] o_w5; - output [4:0] o_w5_d1r; - input [39:0] i_w40; - output [39:0] o_w40; - input [104:0] i_w104; - output [104:0] o_w104; + input [4:0] i_w5; + output [4:0] o_w5; + output [4:0] o_w5_d1r; + input [39:0] i_w40; + output [39:0] o_w40; + input [104:0] i_w104; + output [104:0] o_w104; wire [4:0] o_w5 = i_w5; wire [39:0] o_w40 = i_w40; @@ -27,7 +27,7 @@ module t_inst_first_a (/*AUTOARG*/ /*AUTOREG*/ // Beginning of automatic regs (for this module's undeclared outputs) - reg [4:0] o_w5_d1r; + reg [4:0] o_w5_d1r; // End of automatics always @ (posedge clk) begin diff --git a/test_regress/t/t_inst_first_b.v b/test_regress/t/t_inst_first_b.v index e60332429..ce2515ee0 100644 --- a/test_regress/t/t_inst_first_b.v +++ b/test_regress/t/t_inst_first_b.v @@ -14,12 +14,12 @@ module t_inst_first_b (/*AUTOARG*/ input clk; - input i_seq; - output o_seq_d1r; - input i_com; - output o_com; - input [1:0] i2_com; - output [1:0] o2_com; + input i_seq; + output o_seq_d1r; + input i_com; + output o_com; + input [1:0] i2_com; + output [1:0] o2_com; input [127:0] wide_for_trace; input [127:0] wide_for_trace_2; @@ -27,7 +27,7 @@ module t_inst_first_b (/*AUTOARG*/ // Beginning of automatic regs (for this module's undeclared outputs) // End of automatics - reg o_seq_d1r; + reg o_seq_d1r; always @ (posedge clk) begin o_seq_d1r <= ~i_seq; end diff --git a/test_regress/t/t_inst_implicit.v b/test_regress/t/t_inst_implicit.v index 5a3a407a5..53c205fad 100644 --- a/test_regress/t/t_inst_implicit.v +++ b/test_regress/t/t_inst_implicit.v @@ -14,9 +14,9 @@ module t (/*AUTOARG*/ wire [31:0] oe; Test test (/*AUTOINST*/ - // Outputs - .o (o[31:0]), - .oe (oe[31:0])); + // Outputs + .o (o[31:0]), + .oe (oe[31:0])); // Test loop always @ (posedge clk) begin @@ -38,12 +38,12 @@ endmodule module Test(o,oe); output [31:0] o; output [31:0] oe; - wire [31:0] xe; + wire [31:0] xe; assign xe[31:1] = 0; // verilator lint_off IMPLICIT // verilator lint_off WIDTH - subimp subimp(x, // x is implicit and one bit - xe[0]); // xe explicit one bit + subimp subimp(x, // x is implicit and one bit + xe[0]); // xe explicit one bit assign o = x; assign oe = xe; // verilator lint_on WIDTH diff --git a/test_regress/t/t_inst_mnpipe.v b/test_regress/t/t_inst_mnpipe.v index 1663dc88f..e97c4e9fd 100644 --- a/test_regress/t/t_inst_mnpipe.v +++ b/test_regress/t/t_inst_mnpipe.v @@ -24,18 +24,18 @@ module t (/*AUTOARG*/ cyc <= cyc + 1; crc <= {crc[6:0], ~^ {crc[7],crc[5],crc[4],crc[3]}}; if (cyc==0) begin - // Setup - crc <= 8'hed; - sum <= 3'h0; + // Setup + crc <= 8'hed; + sum <= 3'h0; end else if (cyc>10 && cyc<90) begin - sum <= {sum[1:0],sum[2]} ^ out; + sum <= {sum[1:0],sum[2]} ^ out; end else if (cyc==99) begin - if (crc !== 8'b01110000) $stop; - if (sum !== 3'h3) $stop; - $write("*-* All Finished *-*\n"); - $finish; + if (crc !== 8'b01110000) $stop; + if (sum !== 3'h3) $stop; + $write("*-* All Finished *-*\n"); + $finish; end end endmodule @@ -45,7 +45,7 @@ module dffn (q,d,clk); input [BITS-1:0] d; output reg [BITS-1:0] q; - input clk; + input clk; always @ (posedge clk) begin q <= d; @@ -58,7 +58,7 @@ module MxN_pipeline (in, out, clk); input [M-1:0] in; output [M-1:0] out; - input clk; + input clk; // Unsupported: Per-bit array instantiations with output connections to non-wires. //wire [M*(N-1):1] t; @@ -67,6 +67,6 @@ module MxN_pipeline (in, out, clk); wire [M*(N-1):1] w; wire [M*N:1] q; dffn #(M) p[N:1] (q,{w,in},clk); - assign {out,w} = q; + assign {out,w} = q; endmodule diff --git a/test_regress/t/t_inst_notunsized.v b/test_regress/t/t_inst_notunsized.v index d2fa6ff41..ced84654d 100644 --- a/test_regress/t/t_inst_notunsized.v +++ b/test_regress/t/t_inst_notunsized.v @@ -10,24 +10,24 @@ module t (/*AUTOARG*/ ); input clk; - integer cyc = 0; - reg [63:0] crc; - reg [63:0] sum; + integer cyc = 0; + reg [63:0] crc; + reg [63:0] sum; // Take CRC data and apply to testblock inputs wire [31:0] in = crc[31:0]; /*AUTOWIRE*/ // Beginning of automatic wires (for undeclared instantiated-module outputs) - wire [71:0] muxed; // From test of Test.v + wire [71:0] muxed; // From test of Test.v // End of automatics Test test (/*AUTOINST*/ - // Outputs - .muxed (muxed[71:0]), - // Inputs - .clk (clk), - .in (in[31:0])); + // Outputs + .muxed (muxed[71:0]), + // Inputs + .clk (clk), + .in (in[31:0])); // Aggregate outputs into a single result vector wire [63:0] result = {muxed[63:0]}; @@ -43,23 +43,23 @@ module t (/*AUTOARG*/ crc <= {crc[62:0], crc[63] ^ crc[2] ^ crc[0]}; sum <= result ^ {sum[62:0], sum[63] ^ sum[2] ^ sum[0]}; if (cyc==0) begin - // Setup - crc <= 64'h5aef0c8d_d70a4497; - sum <= 64'h0; + // Setup + crc <= 64'h5aef0c8d_d70a4497; + sum <= 64'h0; end else if (cyc<10) begin - sum <= 64'h0; + sum <= 64'h0; end else if (cyc<90) begin end else if (cyc==99) begin - $write("[%0t] cyc==%0d crc=%x sum=%x\n", $time, cyc, crc, sum); - if (crc !== 64'hc77bb9b3784ea091) $stop; - // What checksum will we end up with (above print should match) + $write("[%0t] cyc==%0d crc=%x sum=%x\n", $time, cyc, crc, sum); + if (crc !== 64'hc77bb9b3784ea091) $stop; + // What checksum will we end up with (above print should match) `define EXPECTED_SUM 64'h20050a66e7b253d1 - if (sum !== `EXPECTED_SUM) $stop; - $write("*-* All Finished *-*\n"); - $finish; + if (sum !== `EXPECTED_SUM) $stop; + $write("*-* All Finished *-*\n"); + $finish; end end @@ -75,19 +75,19 @@ module Test (/*AUTOARG*/ input [31:0] in; output [71:0] muxed; - wire [71:0] a = {in[7:0],~in[31:0],in[31:0]}; - wire [71:0] b = {~in[7:0],in[31:0],~in[31:0]}; + wire [71:0] a = {in[7:0],~in[31:0],in[31:0]}; + wire [71:0] b = {~in[7:0],in[31:0],~in[31:0]}; /*AUTOWIRE*/ Muxer muxer ( - .sa (0), - .sb (in[0]), - /*AUTOINST*/ - // Outputs - .muxed (muxed[71:0]), - // Inputs - .a (a[71:0]), - .b (b[71:0])); + .sa (0), + .sb (in[0]), + /*AUTOINST*/ + // Outputs + .muxed (muxed[71:0]), + // Inputs + .a (a[71:0]), + .b (b[71:0])); endmodule module Muxer (/*AUTOARG*/ @@ -96,16 +96,16 @@ module Muxer (/*AUTOARG*/ // Inputs sa, sb, a, b ); - input sa; - input sb; + input sa; + input sb; - output wire [71:0] muxed; + output wire [71:0] muxed; input [71:0] a; input [71:0] b; // Constification wasn't sizing with inlining and gave // unsized error on below // v - assign muxed = (({72{sa}} & a) - | ({72{sb}} & b)); + assign muxed = (({72{sa}} & a) + | ({72{sb}} & b)); endmodule diff --git a/test_regress/t/t_inst_signed.v b/test_regress/t/t_inst_signed.v index 39bdafa0d..8fbdc0adc 100644 --- a/test_regress/t/t_inst_signed.v +++ b/test_regress/t/t_inst_signed.v @@ -14,14 +14,14 @@ module t (/*AUTOARG*/ integer cyc; initial cyc = 0; wire signed [7:0] sgn_wide; - wire [7:0] unsgn_wide; + wire [7:0] unsgn_wide; // The instantiation will Z extend, not sign extend // verilator lint_off WIDTH sub sub (.clk, - .sgn(sgn_wide), .unsgn(unsgn_wide), - .iss(3'sh7), .isu(3'h7), - .ius(3'sh7), .iuu(3'h7)); + .sgn(sgn_wide), .unsgn(unsgn_wide), + .iss(3'sh7), .isu(3'h7), + .ius(3'sh7), .iuu(3'h7)); // verilator lint_on WIDTH always @ (posedge clk) begin @@ -32,25 +32,25 @@ module t (/*AUTOARG*/ if (unsgn_wide[2:0] != 3'h7) $stop; // Simulators differ here. if (sgn_wide !== 8'sbzzzzz111 // z-extension - NC - && sgn_wide !== 8'sb11111111) $stop; // sign extension - VCS + && sgn_wide !== 8'sb11111111) $stop; // sign extension - VCS if (unsgn_wide !== 8'sbzzzzz111 - && unsgn_wide!== 8'sb00000111) $stop; + && unsgn_wide!== 8'sb00000111) $stop; cyc <= cyc + 1; if (cyc==3) begin - $write("*-* All Finished *-*\n"); - $finish; + $write("*-* All Finished *-*\n"); + $finish; end end endmodule module sub ( - input clk, - output wire signed [2:0] sgn, - output wire [2:0] unsgn, - input signed [7:0] iss, - input signed [7:0] isu, - input [7:0] ius, - input [7:0] iuu); + input clk, + output wire signed [2:0] sgn, + output wire [2:0] unsgn, + input signed [7:0] iss, + input signed [7:0] isu, + input [7:0] ius, + input [7:0] iuu); assign sgn = 3'sh7; assign unsgn = 3'h7; always @ (posedge clk) begin diff --git a/test_regress/t/t_inst_slice.v b/test_regress/t/t_inst_slice.v index f05524451..2ce445b74 100644 --- a/test_regress/t/t_inst_slice.v +++ b/test_regress/t/t_inst_slice.v @@ -11,19 +11,19 @@ module t (/*AUTOARG*/ ); input clk; - integer cyc = 0; - reg [63:0] crc; - reg [63:0] sum; + integer cyc = 0; + reg [63:0] crc; + reg [63:0] sum; // Take CRC data and apply to testblock inputs wire [1:0] i = crc[1:0]; logic [1:0] o [13:10] ; Test test (/*AUTOINST*/ - // Outputs - .o (o/*[1:0].[3:0]*/), - // Inputs - .i (i[1:0])); + // Outputs + .o (o/*[1:0].[3:0]*/), + // Inputs + .i (i[1:0])); // Aggregate outputs into a single result vector wire [63:0] result = {32'h0, 6'h0,o[13], 6'h0,o[12], 6'h0,o[11], 6'h0,o[10]}; @@ -37,23 +37,23 @@ module t (/*AUTOARG*/ crc <= {crc[62:0], crc[63] ^ crc[2] ^ crc[0]}; sum <= result ^ {sum[62:0], sum[63] ^ sum[2] ^ sum[0]}; if (cyc==0) begin - // Setup - crc <= 64'h5aef0c8d_d70a4497; - sum <= '0; + // Setup + crc <= 64'h5aef0c8d_d70a4497; + sum <= '0; end else if (cyc<10) begin - sum <= '0; + sum <= '0; end else if (cyc<90) begin end else if (cyc==99) begin - $write("[%0t] cyc==%0d crc=%x sum=%x\n", $time, cyc, crc, sum); - if (crc !== 64'hc77bb9b3784ea091) $stop; - // What checksum will we end up with (above print should match) + $write("[%0t] cyc==%0d crc=%x sum=%x\n", $time, cyc, crc, sum); + if (crc !== 64'hc77bb9b3784ea091) $stop; + // What checksum will we end up with (above print should match) `define EXPECTED_SUM 64'hb42b2f48a0a9375a - if (sum !== `EXPECTED_SUM) $stop; - $write("*-* All Finished *-*\n"); - $finish; + if (sum !== `EXPECTED_SUM) $stop; + $write("*-* All Finished *-*\n"); + $finish; end end @@ -64,15 +64,15 @@ module Test output logic [1:0] o [3:0], //but this works //logic [N-1:0] o - input [1:0] i); + input [1:0] i); parameter N = 4; - logic [1:0] a [3:0]; initial a = '{2'h0,2'h1,2'h2,2'h3}; + logic [1:0] a [3:0]; initial a = '{2'h0,2'h1,2'h2,2'h3}; - sub sub [N-1:0] (.o (o), // many-to-many - .a (a), // many-to-many - .i (i)); // many-to-one + sub sub [N-1:0] (.o (o), // many-to-many + .a (a), // many-to-many + .i (i)); // many-to-one endmodule module sub diff --git a/test_regress/t/t_inst_sv.v b/test_regress/t/t_inst_sv.v index c69208500..d412b21a6 100644 --- a/test_regress/t/t_inst_sv.v +++ b/test_regress/t/t_inst_sv.v @@ -19,41 +19,41 @@ module t (/*AUTOARG*/ reg ionewire; wire oonewire; - wire [7:0] osizedreg; // From sub of t_inst_v2k_sub.v + wire [7:0] osizedreg; // From sub of t_inst_v2k_sub.v t_inst sub ( .osizedreg, .oonewire, // Inputs - .isizedwire (isizedwire[7:0]), + .isizedwire (isizedwire[7:0]), .* - //.ionewire (ionewire) + //.ionewire (ionewire) ); always @ (posedge clk) begin if (cyc!=0) begin - cyc <= cyc + 1; - if (cyc==1) begin - ionewire <= 1'b1; - isizedwire <= 8'd8; - end - if (cyc==2) begin - if (low != 2'b00) $stop; - if (high != 2'b11) $stop; - if (oonewire !== 1'b1) $stop; - if (isizedwire !== 8'd8) $stop; - end - if (cyc==3) begin - ionewire <= 1'b0; - isizedwire <= 8'd7; - end - if (cyc==4) begin - if (oonewire !== 1'b0) $stop; - if (isizedwire !== 8'd7) $stop; - $write("*-* All Finished *-*\n"); - $finish; - end + cyc <= cyc + 1; + if (cyc==1) begin + ionewire <= 1'b1; + isizedwire <= 8'd8; + end + if (cyc==2) begin + if (low != 2'b00) $stop; + if (high != 2'b11) $stop; + if (oonewire !== 1'b1) $stop; + if (isizedwire !== 8'd8) $stop; + end + if (cyc==3) begin + ionewire <= 1'b0; + isizedwire <= 8'd7; + end + if (cyc==4) begin + if (oonewire !== 1'b0) $stop; + if (isizedwire !== 8'd7) $stop; + $write("*-* All Finished *-*\n"); + $finish; + end end end endmodule diff --git a/test_regress/t/t_inst_tree.v b/test_regress/t/t_inst_tree.v index ea4ab1d3c..3533d8e76 100644 --- a/test_regress/t/t_inst_tree.v +++ b/test_regress/t/t_inst_tree.v @@ -13,7 +13,7 @@ module t (/*AUTOARG*/ integer cyc; initial cyc=1; // verilator lint_off GENCLK - reg printclk; + reg printclk; // verilator lint_on GENCLK ps ps (printclk); @@ -25,24 +25,24 @@ module t (/*AUTOARG*/ always @ (posedge clk) begin printclk <= 0; if (cyc!=0) begin - cyc <= cyc + 1; - if (cyc==1) begin - printclk <= 1'b1; - end - if (cyc==2) begin - a <= 8'b1; - end - if (cyc==3) begin - if (z !== 8'hf8) $stop; - //if (u.u1.u1.u1.u0.PARAM !== 1) $stop; - //if (u.u1.u1.u1.u1.PARAM !== 2) $stop; - //if (u.u0.u0.u0.u0.z !== 8'hfe) $stop; - //if (u.u0.u0.u0.u1.z !== 8'hff) $stop; - //if (u.u1.u1.u1.u0.z !== 8'h00) $stop; - //if (u.u1.u1.u1.u1.z !== 8'h01) $stop; - $write("*-* All Finished *-*\n"); - $finish; - end + cyc <= cyc + 1; + if (cyc==1) begin + printclk <= 1'b1; + end + if (cyc==2) begin + a <= 8'b1; + end + if (cyc==3) begin + if (z !== 8'hf8) $stop; + //if (u.u1.u1.u1.u0.PARAM !== 1) $stop; + //if (u.u1.u1.u1.u1.PARAM !== 2) $stop; + //if (u.u0.u0.u0.u0.z !== 8'hfe) $stop; + //if (u.u0.u0.u0.u1.z !== 8'hff) $stop; + //if (u.u1.u1.u1.u0.z !== 8'h00) $stop; + //if (u.u1.u1.u1.u1.z !== 8'h01) $stop; + $write("*-* All Finished *-*\n"); + $finish; + end end end diff --git a/test_regress/t/t_inst_v2k.v b/test_regress/t/t_inst_v2k.v index 6e60406c2..4e9e524b6 100644 --- a/test_regress/t/t_inst_v2k.v +++ b/test_regress/t/t_inst_v2k.v @@ -19,12 +19,12 @@ module t (/*AUTOARG*/ reg ionewire; `ifdef never_just_for_verilog_mode - wire oonewire; // From sub of t_inst_v2k__sub.v + wire oonewire; // From sub of t_inst_v2k__sub.v `endif - wire [7:0] osizedreg; // From sub of t_inst_v2k__sub.v - wire [1:0] tied; - wire [3:0] tied_also; + wire [7:0] osizedreg; // From sub of t_inst_v2k__sub.v + wire [1:0] tied; + wire [3:0] tied_also; hello hsub (.tied_also); @@ -32,32 +32,32 @@ module t (/*AUTOARG*/ t_inst_v2k__sub sub ( // Outputs - .osizedreg (osizedreg[7:0]), + .osizedreg (osizedreg[7:0]), // verilator lint_off IMPLICIT - .oonewire (oonewire), + .oonewire (oonewire), // verilator lint_on IMPLICIT - .tied (tied[1:0]), + .tied (tied[1:0]), // Inputs - .isizedwire (isizedwire[7:0]), - .ionewire (ionewire)); + .isizedwire (isizedwire[7:0]), + .ionewire (ionewire)); always @ (posedge clk) begin if (cyc!=0) begin - cyc <= cyc + 1; - if (cyc==1) begin - ionewire <= 1'b1; - isizedwire <= 8'd8; - end - if (cyc==2) begin - if (low != 2'b00) $stop; - if (high != 2'b11) $stop; - if (oonewire !== 1'b1) $stop; - if (isizedwire !== 8'd8) $stop; - if (tied != 2'b10) $stop; - if (tied_also != 4'b1010) $stop; - $write("*-* All Finished *-*\n"); - $finish; - end + cyc <= cyc + 1; + if (cyc==1) begin + ionewire <= 1'b1; + isizedwire <= 8'd8; + end + if (cyc==2) begin + if (low != 2'b00) $stop; + if (high != 2'b11) $stop; + if (oonewire !== 1'b1) $stop; + if (isizedwire !== 8'd8) $stop; + if (tied != 2'b10) $stop; + if (tied_also != 4'b1010) $stop; + $write("*-* All Finished *-*\n"); + $finish; + end end end diff --git a/test_regress/t/t_inst_wideconst.v b/test_regress/t/t_inst_wideconst.v index 42a535f88..b4cc2ec2d 100644 --- a/test_regress/t/t_inst_wideconst.v +++ b/test_regress/t/t_inst_wideconst.v @@ -12,56 +12,56 @@ module t (/*AUTOARG*/ input clk; integer cyc; initial cyc=1; - reg [41:0] aaa; - wire [41:0] bbb; + reg [41:0] aaa; + wire [41:0] bbb; // verilator public_module - wire [41:0] z_0; - wire [41:0] z_1; + wire [41:0] z_0; + wire [41:0] z_1; wide w_0( - .xxx( { {40{1'b0}},2'b11 } ), - .yyy( aaa[1:0] ), - .zzz( z_0 ) - ); + .xxx( { {40{1'b0}},2'b11 } ), + .yyy( aaa[1:0] ), + .zzz( z_0 ) + ); wide w_1( - .xxx( aaa ), - .yyy( 2'b10 ), - .zzz( z_1 ) - ); + .xxx( aaa ), + .yyy( 2'b10 ), + .zzz( z_1 ) + ); assign bbb= z_0 + z_1; always @ (posedge clk) begin if (cyc!=0) begin - cyc <= cyc + 1; - if (cyc==1) begin - aaa <= 42'b01; - end - if (cyc==2) begin - aaa <= 42'b10; - if (z_0 != 42'h4) $stop; - if (z_1 != 42'h3) $stop; - end - if (cyc==3) begin - if (z_0 != 42'h5) $stop; - if (z_1 != 42'h4) $stop; - end - if (cyc==4) begin - $write("*-* All Finished *-*\n"); - $finish; - end + cyc <= cyc + 1; + if (cyc==1) begin + aaa <= 42'b01; + end + if (cyc==2) begin + aaa <= 42'b10; + if (z_0 != 42'h4) $stop; + if (z_1 != 42'h3) $stop; + end + if (cyc==3) begin + if (z_0 != 42'h5) $stop; + if (z_1 != 42'h4) $stop; + end + if (cyc==4) begin + $write("*-* All Finished *-*\n"); + $finish; + end end end endmodule module wide ( - input [41:0] xxx, - input [1:0] yyy, - output [41:0] zzz - ); + input [41:0] xxx, + input [1:0] yyy, + output [41:0] zzz + ); // verilator public_module assign zzz = xxx+ { {40{1'b0}},yyy }; diff --git a/test_regress/t/t_interface1.v b/test_regress/t/t_interface1.v index 569222085..9d87f3a4c 100644 --- a/test_regress/t/t_interface1.v +++ b/test_regress/t/t_interface1.v @@ -21,15 +21,15 @@ module t (/*AUTOARG*/ ifc itop(); sub c1 (.isub(itop), - .i_value(4'h4)); + .i_value(4'h4)); always @ (posedge clk) begin cyc <= cyc + 1; if (cyc==20) begin - if (c1.i_value != 4) $stop; // 'Normal' crossref just for comparison - if (itop.value != 4) $stop; - $write("*-* All Finished *-*\n"); - $finish; + if (c1.i_value != 4) $stop; // 'Normal' crossref just for comparison + if (itop.value != 4) $stop; + $write("*-* All Finished *-*\n"); + $finish; end end endmodule diff --git a/test_regress/t/t_interface1_modport.v b/test_regress/t/t_interface1_modport.v index 42ec3a821..d2359b44e 100644 --- a/test_regress/t/t_interface1_modport.v +++ b/test_regress/t/t_interface1_modport.v @@ -23,16 +23,16 @@ module t (/*AUTOARG*/ ifc itop(); sub c1 (.isub(itop), - .i_value(4)); + .i_value(4)); always @ (posedge clk) begin cyc <= cyc + 1; if (cyc==20) begin - if (itop.value != 4) $stop; - itop.hidden_from_isub = 20; - if (itop.hidden_from_isub != 20) $stop; - $write("*-* All Finished *-*\n"); - $finish; + if (itop.value != 4) $stop; + itop.hidden_from_isub = 20; + if (itop.hidden_from_isub != 20) $stop; + $write("*-* All Finished *-*\n"); + $finish; end end endmodule diff --git a/test_regress/t/t_interface2.v b/test_regress/t/t_interface2.v index 799e7ec13..2c3df5550 100644 --- a/test_regress/t/t_interface2.v +++ b/test_regress/t/t_interface2.v @@ -14,19 +14,19 @@ module t (/*AUTOARG*/ counter_io c1_data(); counter_io c2_data(); - //counter_io c3_data; // IEEE illegal, and VCS doesn't allow non-() as it does with cells + //counter_io c3_data; // IEEE illegal, and VCS doesn't allow non-() as it does with cells counter_io c3_data(); counter_ansi c1 (.clkm(clk), - .c_data(c1_data), - .i_value(4'h1)); + .c_data(c1_data), + .i_value(4'h1)); counter_ansi c2 (.clkm(clk), - .c_data(c2_data), - .i_value(4'h2)); + .c_data(c2_data), + .i_value(4'h2)); `ifdef VERILATOR counter_ansi `else counter_nansi `endif - /**/ c3 (.clkm(clk), - .c_data(c3_data), - .i_value(4'h3)); + /**/ c3 (.clkm(clk), + .c_data(c3_data), + .i_value(4'h3)); initial begin c1_data.value = 4'h4; @@ -37,28 +37,28 @@ module t (/*AUTOARG*/ always @ (posedge clk) begin cyc <= cyc + 1; if (cyc<2) begin - c1_data.reset <= 1; - c2_data.reset <= 1; - c3_data.reset <= 1; + c1_data.reset <= 1; + c2_data.reset <= 1; + c3_data.reset <= 1; end if (cyc==2) begin - c1_data.reset <= 0; - c2_data.reset <= 0; - c3_data.reset <= 0; + c1_data.reset <= 0; + c2_data.reset <= 0; + c3_data.reset <= 0; end if (cyc==3) begin - if (c1_data.get_lcl() != 12345) $stop; + if (c1_data.get_lcl() != 12345) $stop; end if (cyc==20) begin - $write("[%0t] c1 cyc%0d: c1 %0x %0x c2 %0x %0x c3 %0x %0x\n", $time, cyc, - c1_data.value, c1_data.reset, - c2_data.value, c2_data.reset, - c3_data.value, c3_data.reset); - if (c1_data.value != 2) $stop; - if (c2_data.value != 3) $stop; - if (c3_data.value != 4) $stop; - $write("*-* All Finished *-*\n"); - $finish; + $write("[%0t] c1 cyc%0d: c1 %0x %0x c2 %0x %0x c3 %0x %0x\n", $time, cyc, + c1_data.value, c1_data.reset, + c2_data.value, c2_data.reset, + c3_data.value, c3_data.reset); + if (c1_data.value != 2) $stop; + if (c2_data.value != 3) $stop; + if (c3_data.value != 4) $stop; + $write("*-* All Finished *-*\n"); + $finish; end end endmodule diff --git a/test_regress/t/t_interface_array.v b/test_regress/t/t_interface_array.v index 41a4a571b..a847a0250 100644 --- a/test_regress/t/t_interface_array.v +++ b/test_regress/t/t_interface_array.v @@ -37,11 +37,11 @@ module t (/*AUTOARG*/ // Deferred link dotting with genvars generate - genvar i; + genvar i; for (i = 0; i < N-4; i++) begin : someLoop - assign ack_out[i] = a_in[i]; - assign foos[i].a = a_in[i]; - assign a_out[i] = foos[i].a; + assign ack_out[i] = a_in[i]; + assign foos[i].a = a_in[i]; + assign a_out[i] = foos[i].a; end endgenerate @@ -66,14 +66,14 @@ module t (/*AUTOARG*/ a_in <= a_in + { {N-1 {1'b0}}, 1'b1 }; if (ack_out != a_out) begin - $display("%%Error: Interface and non-interface paths do not match: 0b%b 0b%b", - ack_out, a_out); - $stop; + $display("%%Error: Interface and non-interface paths do not match: 0b%b 0b%b", + ack_out, a_out); + $stop; end if (& a_in) begin - $write("*-* All Finished *-*\n"); - $finish; + $write("*-* All Finished *-*\n"); + $finish; end end diff --git a/test_regress/t/t_interface_array2.v b/test_regress/t/t_interface_array2.v index 73ed3ecac..3d41e9451 100644 --- a/test_regress/t/t_interface_array2.v +++ b/test_regress/t/t_interface_array2.v @@ -41,12 +41,12 @@ module t .intf_inst(ifs[return_3()])); modify_interface m4 ( - .value(data[4]), - .intf_inst(ifs[4])); + .value(data[4]), + .intf_inst(ifs[4])); modify_interface m5 ( - .value(~ifs[4].logic_in_intf), - .intf_inst(ifs[5])); + .value(~ifs[4].logic_in_intf), + .intf_inst(ifs[5])); generate genvar j; diff --git a/test_regress/t/t_interface_array_modport.v b/test_regress/t/t_interface_array_modport.v index b63100f9a..5ed00a76f 100644 --- a/test_regress/t/t_interface_array_modport.v +++ b/test_regress/t/t_interface_array_modport.v @@ -28,10 +28,10 @@ module t (/*AUTOARG*/); foo_mod foo_mod ( - .foo (foos[2]), + .foo (foos[2]), .bars (bars) - //.foo (foos) - ); + //.foo (foos) + ); initial begin $write("*-* All Finished *-*\n"); diff --git a/test_regress/t/t_interface_arraymux.v b/test_regress/t/t_interface_arraymux.v index 261f154d9..382045fd3 100644 --- a/test_regress/t/t_interface_arraymux.v +++ b/test_regress/t/t_interface_arraymux.v @@ -23,11 +23,11 @@ interface the_intf outer_thing_t [M-1:0] things; logic valid; modport i ( - output things, - output valid); + output things, + output valid); modport t ( - input things, - input valid); + input things, + input valid); endinterface module ThingMuxOH @@ -61,7 +61,7 @@ module Thinker ( input logic clk, input logic reset, - input unique_id_t uids[0:N-1], + input unique_id_t uids[0:N-1], the_intf.t thing_inp, the_intf.i thing_out ); diff --git a/test_regress/t/t_interface_down.v b/test_regress/t/t_interface_down.v index 5925649f5..e37037367 100644 --- a/test_regress/t/t_interface_down.v +++ b/test_regress/t/t_interface_down.v @@ -24,23 +24,23 @@ module t (/*AUTOARG*/ ifc itop2b(); wrapper c1 (.isuba(itop1a), - .isubb(itop1b), - .i_valuea(14), - .i_valueb(15)); + .isubb(itop1b), + .i_valuea(14), + .i_valueb(15)); wrapper c2 (.isuba(itop2a), - .isubb(itop2b), - .i_valuea(24), - .i_valueb(25)); + .isubb(itop2b), + .i_valuea(24), + .i_valueb(25)); always @ (posedge clk) begin cyc <= cyc + 1; if (cyc==20) begin - if (itop1a.value != 14) $stop; - if (itop1b.value != 15) $stop; - if (itop2a.value != 24) $stop; - if (itop2b.value != 25) $stop; - $write("*-* All Finished *-*\n"); - $finish; + if (itop1a.value != 14) $stop; + if (itop1b.value != 15) $stop; + if (itop2a.value != 24) $stop; + if (itop2b.value != 25) $stop; + $write("*-* All Finished *-*\n"); + $finish; end end endmodule diff --git a/test_regress/t/t_interface_down_gen.v b/test_regress/t/t_interface_down_gen.v index 716d9bf71..fb65dae46 100644 --- a/test_regress/t/t_interface_down_gen.v +++ b/test_regress/t/t_interface_down_gen.v @@ -13,10 +13,10 @@ interface ifc; generate // Note block must be named per SystemVerilog 2005 if (MODE==1) begin : g - integer value; + integer value; end else if (MODE==2) begin : g - real value; + real value; end endgenerate endinterface @@ -35,23 +35,23 @@ module t (/*AUTOARG*/ ifc #(2) itop2b(); wrapper c1 (.isuba(itop1a), - .isubb(itop1b), - .i_valuea(14.1), - .i_valueb(15.2)); + .isubb(itop1b), + .i_valuea(14.1), + .i_valueb(15.2)); wrapper c2 (.isuba(itop2a), - .isubb(itop2b), - .i_valuea(24.3), - .i_valueb(25.4)); + .isubb(itop2b), + .i_valuea(24.3), + .i_valueb(25.4)); always @ (posedge clk) begin cyc <= cyc + 1; if (cyc==20) begin - if (itop1a.g.value != 14) $stop; - if (itop1b.g.value != 15) $stop; - if (itop2a.g.value != 24) $stop; - if (itop2b.g.value != 25) $stop; - $write("*-* All Finished *-*\n"); - $finish; + if (itop1a.g.value != 14) $stop; + if (itop1b.g.value != 15) $stop; + if (itop2a.g.value != 24) $stop; + if (itop2b.g.value != 25) $stop; + $write("*-* All Finished *-*\n"); + $finish; end end endmodule diff --git a/test_regress/t/t_interface_dups.v b/test_regress/t/t_interface_dups.v index 70de3f0c3..6a6925b7c 100644 --- a/test_regress/t/t_interface_dups.v +++ b/test_regress/t/t_interface_dups.v @@ -23,30 +23,30 @@ module t (/*AUTOARG*/ /*AUTOWIRE*/ // Beginning of automatic wires (for undeclared instantiated-module outputs) - logic din_ready; // From test of Test.v - logic [0:0] dout0_data; // From test of Test.v - logic dout0_valid; // From test of Test.v - logic [1:0] dout1_data; // From test of Test.v - logic dout1_valid; // From test of Test.v - logic [2:0] dout2_data; // From test of Test.v - logic dout2_valid; // From test of Test.v + logic din_ready; // From test of Test.v + logic [0:0] dout0_data; // From test of Test.v + logic dout0_valid; // From test of Test.v + logic [1:0] dout1_data; // From test of Test.v + logic dout1_valid; // From test of Test.v + logic [2:0] dout2_data; // From test of Test.v + logic dout2_valid; // From test of Test.v // End of automatics Test test (/*AUTOINST*/ - // Outputs - .din_ready (din_ready), - .dout0_valid (dout0_valid), - .dout0_data (dout0_data[0:0]), - .dout1_valid (dout1_valid), - .dout1_data (dout1_data[1:0]), - .dout2_valid (dout2_valid), - .dout2_data (dout2_data[2:0]), - // Inputs - .din_valid (din_valid), - .din_data (din_data[4:0]), - .dout0_ready (dout0_ready), - .dout1_ready (dout1_ready), - .dout2_ready (dout2_ready)); + // Outputs + .din_ready (din_ready), + .dout0_valid (dout0_valid), + .dout0_data (dout0_data[0:0]), + .dout1_valid (dout1_valid), + .dout1_data (dout1_data[1:0]), + .dout2_valid (dout2_valid), + .dout2_data (dout2_data[2:0]), + // Inputs + .din_valid (din_valid), + .din_data (din_data[4:0]), + .dout0_ready (dout0_ready), + .dout1_ready (dout1_ready), + .dout2_ready (dout2_ready)); // Aggregate outputs into a single result vector wire [63:0] result = {48'h0, din_ready, diff --git a/test_regress/t/t_interface_gen.v b/test_regress/t/t_interface_gen.v index f4f8511f3..6c7b88b66 100644 --- a/test_regress/t/t_interface_gen.v +++ b/test_regress/t/t_interface_gen.v @@ -25,21 +25,21 @@ module t (/*AUTOARG*/ ifc #(2) itopb(); sub #(1) ca (.isub(itopa), - .i_value(4)); + .i_value(4)); sub #(2) cb (.isub(itopb), - .i_value(5)); + .i_value(5)); always @ (posedge clk) begin cyc <= cyc + 1; if (cyc==1) begin - if (itopa.MODE != 1) $stop; - if (itopb.MODE != 2) $stop; + if (itopa.MODE != 1) $stop; + if (itopb.MODE != 2) $stop; end if (cyc==20) begin - if (itopa.get_value() != 4) $stop; - if (itopb.get_value() != 5) $stop; - $write("*-* All Finished *-*\n"); - $finish; + if (itopa.get_value() != 4) $stop; + if (itopb.get_value() != 5) $stop; + $write("*-* All Finished *-*\n"); + $finish; end end endmodule diff --git a/test_regress/t/t_interface_gen12.v b/test_regress/t/t_interface_gen12.v index bbf87fff1..aec45a9c0 100644 --- a/test_regress/t/t_interface_gen12.v +++ b/test_regress/t/t_interface_gen12.v @@ -9,7 +9,7 @@ module foo_module; generate for (genvar i = 0; i < 2; i = i + 1) begin : my_gen_block - logic baz; + logic baz; end endgenerate endmodule @@ -23,8 +23,8 @@ module t; initial begin bar.foo.my_gen_block[0].baz = 1; if (bar.foo.my_gen_block[0].baz) begin - $write("*-* All Finished *-*\n"); - $finish; + $write("*-* All Finished *-*\n"); + $finish; end end endmodule diff --git a/test_regress/t/t_interface_gen2.v b/test_regress/t/t_interface_gen2.v index 703a31a83..9ce2de2e1 100644 --- a/test_regress/t/t_interface_gen2.v +++ b/test_regress/t/t_interface_gen2.v @@ -18,9 +18,9 @@ module t (/*AUTOARG*/ ifc #(4) itopb(); sub ca (.isub(itopa), - .clk); + .clk); sub cb (.isub(itopb), - .clk); + .clk); always @ (posedge clk) begin `ifdef TEST_VERBOSE @@ -30,24 +30,24 @@ module t (/*AUTOARG*/ itopa.valuei <= cyc[1:0]; itopb.valuei <= cyc[3:0]; if (cyc==1) begin - if (itopa.WIDTH != 2) $stop; - if (itopb.WIDTH != 4) $stop; - if ($bits(itopa.valueo) != 2) $stop; - if ($bits(itopb.valueo) != 4) $stop; - if ($bits(itopa.out_modport.valueo) != 2) $stop; - if ($bits(itopb.out_modport.valueo) != 4) $stop; + if (itopa.WIDTH != 2) $stop; + if (itopb.WIDTH != 4) $stop; + if ($bits(itopa.valueo) != 2) $stop; + if ($bits(itopb.valueo) != 4) $stop; + if ($bits(itopa.out_modport.valueo) != 2) $stop; + if ($bits(itopb.out_modport.valueo) != 4) $stop; end if (cyc==4) begin - if (itopa.valueo != 2'b11) $stop; - if (itopb.valueo != 4'b0011) $stop; + if (itopa.valueo != 2'b11) $stop; + if (itopb.valueo != 4'b0011) $stop; end if (cyc==5) begin - if (itopa.valueo != 2'b00) $stop; - if (itopb.valueo != 4'b0100) $stop; + if (itopa.valueo != 2'b00) $stop; + if (itopb.valueo != 4'b0100) $stop; end if (cyc==20) begin - $write("*-* All Finished *-*\n"); - $finish; + $write("*-* All Finished *-*\n"); + $finish; end end endmodule diff --git a/test_regress/t/t_interface_gen3.v b/test_regress/t/t_interface_gen3.v index 7e8c92141..11f43c907 100644 --- a/test_regress/t/t_interface_gen3.v +++ b/test_regress/t/t_interface_gen3.v @@ -18,9 +18,9 @@ module t (/*AUTOARG*/ ifc #(4) itopb(); sub ca (.isub(itopa.out_modport), - .clk); + .clk); sub cb (.isub(itopb.out_modport), - .clk); + .clk); always @ (posedge clk) begin `ifdef TEST_VERBOSE @@ -30,24 +30,24 @@ module t (/*AUTOARG*/ itopa.valuei <= cyc[1:0]; itopb.valuei <= cyc[3:0]; if (cyc==1) begin - if (itopa.WIDTH != 2) $stop; - if (itopb.WIDTH != 4) $stop; - if ($bits(itopa.valueo) != 2) $stop; - if ($bits(itopb.valueo) != 4) $stop; - if ($bits(itopa.out_modport.valueo) != 2) $stop; - if ($bits(itopb.out_modport.valueo) != 4) $stop; + if (itopa.WIDTH != 2) $stop; + if (itopb.WIDTH != 4) $stop; + if ($bits(itopa.valueo) != 2) $stop; + if ($bits(itopb.valueo) != 4) $stop; + if ($bits(itopa.out_modport.valueo) != 2) $stop; + if ($bits(itopb.out_modport.valueo) != 4) $stop; end if (cyc==4) begin - if (itopa.valueo != 2'b11) $stop; - if (itopb.valueo != 4'b0011) $stop; + if (itopa.valueo != 2'b11) $stop; + if (itopb.valueo != 4'b0011) $stop; end if (cyc==5) begin - if (itopa.valueo != 2'b00) $stop; - if (itopb.valueo != 4'b0100) $stop; + if (itopa.valueo != 2'b00) $stop; + if (itopb.valueo != 4'b0100) $stop; end if (cyc==20) begin - $write("*-* All Finished *-*\n"); - $finish; + $write("*-* All Finished *-*\n"); + $finish; end end endmodule diff --git a/test_regress/t/t_interface_gen4.v b/test_regress/t/t_interface_gen4.v index 2c370310a..c8a1efe86 100644 --- a/test_regress/t/t_interface_gen4.v +++ b/test_regress/t/t_interface_gen4.v @@ -18,21 +18,21 @@ module t (/*AUTOARG*/ ifc #(2) itopb(); sub #(1) ca (.isub(itopa), - .i_value(4)); + .i_value(4)); sub #(2) cb (.isub(itopb), - .i_value(5)); + .i_value(5)); always @ (posedge clk) begin cyc <= cyc + 1; if (cyc==1) begin - if (itopa.MODE != 1) $stop; - if (itopb.MODE != 2) $stop; + if (itopa.MODE != 1) $stop; + if (itopb.MODE != 2) $stop; end if (cyc==20) begin - if (itopa.i != 4) $stop; - if (itopb.i != 5) $stop; - $write("*-* All Finished *-*\n"); - $finish; + if (itopa.i != 4) $stop; + if (itopb.i != 5) $stop; + $write("*-* All Finished *-*\n"); + $finish; end end endmodule @@ -54,6 +54,6 @@ interface ifc; parameter MODE = 0; // Commercial unsupported Xmrs into scopes within interfaces generate - integer i; + integer i; endgenerate endinterface diff --git a/test_regress/t/t_interface_gen6.v b/test_regress/t/t_interface_gen6.v index 4b7ef5dee..e6f41bc5e 100644 --- a/test_regress/t/t_interface_gen6.v +++ b/test_regress/t/t_interface_gen6.v @@ -26,27 +26,27 @@ module t(); generate begin - if (1) begin + if (1) begin intf #(.PARAM(2)) my_intf (); assign my_intf.val = '1; - end else begin + end else begin intf #(.PARAM(3)) my_intf (); assign my_intf.val = '0; - end + end end endgenerate generate begin - begin - if (1) begin + begin + if (1) begin intf #(.PARAM(2)) my_intf (); assign my_intf.val = '1; - end else begin + end else begin intf #(.PARAM(3)) my_intf (); assign my_intf.val = '0; - end - end + end + end end endgenerate diff --git a/test_regress/t/t_interface_gen7.v b/test_regress/t/t_interface_gen7.v index 3965e3602..1bf047801 100644 --- a/test_regress/t/t_interface_gen7.v +++ b/test_regress/t/t_interface_gen7.v @@ -26,38 +26,38 @@ module t(); generate genvar the_genvar; begin : ia - for (the_genvar = 0; the_genvar < 2; the_genvar++) begin : TestIf - begin + for (the_genvar = 0; the_genvar < 2; the_genvar++) begin : TestIf + begin assign my_intf[the_genvar].val = '1; t1 t (.mod_intf(my_intf[the_genvar])); - end - end + end + end end endgenerate generate genvar the_second_genvar; begin : ib - intf #(.PARAM(1)) my_intf [1:0] (); - for (the_second_genvar = 0; the_second_genvar < 2; the_second_genvar++) begin : TestIf - begin + intf #(.PARAM(1)) my_intf [1:0] (); + for (the_second_genvar = 0; the_second_genvar < 2; the_second_genvar++) begin : TestIf + begin assign my_intf[the_second_genvar].val = '1; t1 t (.mod_intf(my_intf[the_second_genvar])); - end - end + end + end end endgenerate generate genvar the_third_genvar; begin : ic - for (the_third_genvar = 0; the_third_genvar < 2; the_third_genvar++) begin : TestIf - begin - intf #(.PARAM(1)) my_intf [1:0] (); + for (the_third_genvar = 0; the_third_genvar < 2; the_third_genvar++) begin : TestIf + begin + intf #(.PARAM(1)) my_intf [1:0] (); assign my_intf[the_third_genvar].val = '1; t1 t (.mod_intf(my_intf[the_third_genvar])); - end - end + end + end end endgenerate diff --git a/test_regress/t/t_interface_modport.v b/test_regress/t/t_interface_modport.v index 162963511..a5cf58414 100644 --- a/test_regress/t/t_interface_modport.v +++ b/test_regress/t/t_interface_modport.v @@ -38,19 +38,19 @@ module t (/*AUTOARG*/ counter_if c4_data(); counter_ansi c1 (.clkm(clk), - .c_data(c1_data.counter_mp), - .i_value(4'h1)); + .c_data(c1_data.counter_mp), + .i_value(4'h1)); `ifdef VERILATOR counter_ansi `else counter_nansi `endif /**/ c2 (.clkm(clk), - .c_data(c2_data.counter_mp), - .i_value(4'h2)); + .c_data(c2_data.counter_mp), + .i_value(4'h2)); counter_ansi_m c3 (.clkm(clk), - .c_data(c3_data), - .i_value(4'h3)); + .c_data(c3_data), + .i_value(4'h3)); `ifdef VERILATOR counter_ansi_m `else counter_nansi_m `endif /**/ c4 (.clkm(clk), - .c_data(c4_data), - .i_value(4'h4)); + .c_data(c4_data), + .i_value(4'h4)); initial begin c1_data.value = 4'h4; @@ -62,29 +62,29 @@ module t (/*AUTOARG*/ always @ (posedge clk) begin cyc <= cyc + 1; if (cyc<2) begin - c1_data.reset <= 1; - c2_data.reset <= 1; - c3_data.reset <= 1; - c4_data.reset <= 1; + c1_data.reset <= 1; + c2_data.reset <= 1; + c3_data.reset <= 1; + c4_data.reset <= 1; end if (cyc==2) begin - c1_data.reset <= 0; - c2_data.reset <= 0; - c3_data.reset <= 0; - c4_data.reset <= 0; + c1_data.reset <= 0; + c2_data.reset <= 0; + c3_data.reset <= 0; + c4_data.reset <= 0; end if (cyc==20) begin - $write("[%0t] cyc%0d: c1 %0x %0x c2 %0x %0x c3 %0x %0x c4 %0x %0x\n", $time, cyc, - c1_data.value, c1_data.reset, - c2_data.value, c2_data.reset, - c3_data.value, c3_data.reset, - c4_data.value, c4_data.reset); - if (c1_data.value != 2) $stop; - if (c2_data.value != 3) $stop; - if (c3_data.value != 4) $stop; - if (c4_data.value != 5) $stop; - $write("*-* All Finished *-*\n"); - $finish; + $write("[%0t] cyc%0d: c1 %0x %0x c2 %0x %0x c3 %0x %0x c4 %0x %0x\n", $time, cyc, + c1_data.value, c1_data.reset, + c2_data.value, c2_data.reset, + c3_data.value, c3_data.reset, + c4_data.value, c4_data.reset); + if (c1_data.value != 2) $stop; + if (c2_data.value != 3) $stop; + if (c3_data.value != 4) $stop; + if (c4_data.value != 5) $stop; + $write("*-* All Finished *-*\n"); + $finish; end end endmodule diff --git a/test_regress/t/t_interface_modport_export.v b/test_regress/t/t_interface_modport_export.v index e00ec479f..1369556b7 100644 --- a/test_regress/t/t_interface_modport_export.v +++ b/test_regress/t/t_interface_modport_export.v @@ -12,19 +12,19 @@ interface test_if; extern function myfunc (input logic val); // Interface variable - logic data; + logic data; // Modport modport mp_e( export myfunc, - output data - ); + output data + ); // Modport modport mp_i( import myfunc, - output data - ); + output data + ); endinterface // test_if @@ -39,7 +39,7 @@ module t (/*AUTOARG*/ testmod_callee testmod_callee_i (.ie (i.mp_e)); testmod_caller testmod_caller_i (.clk (clk), - .ii (i.mp_i)); + .ii (i.mp_i)); endmodule @@ -50,7 +50,7 @@ module testmod_callee function automatic logic ie.myfunc (input logic val); begin - myfunc = (val == 1'b0); + myfunc = (val == 1'b0); end endfunction endmodule // testmod_caller @@ -65,11 +65,11 @@ module testmod_caller always @(posedge clk) begin ii.data = 1'b0; if (ii.myfunc (1'b0)) begin - $write("*-* All Finished *-*\n"); - $finish; + $write("*-* All Finished *-*\n"); + $finish; end else begin - $stop; + $stop; end end endmodule diff --git a/test_regress/t/t_interface_modport_import.v b/test_regress/t/t_interface_modport_import.v index 57363e22b..6fed88a03 100644 --- a/test_regress/t/t_interface_modport_import.v +++ b/test_regress/t/t_interface_modport_import.v @@ -9,17 +9,17 @@ interface test_if; // Interface variable - logic data; + logic data; // Modport modport mp( import myfunc, - output data - ); + output data + ); function automatic logic myfunc (input logic val); begin - myfunc = (val == 1'b0); + myfunc = (val == 1'b0); end endfunction @@ -35,7 +35,7 @@ module t (/*AUTOARG*/ test_if i (); testmod testmod_i (.clk (clk), - .i (i.mp)); + .i (i.mp)); endmodule @@ -49,11 +49,11 @@ module testmod always @(posedge clk) begin i.data = 1'b0; if (i.myfunc (1'b0)) begin - $write("*-* All Finished *-*\n"); - $finish; + $write("*-* All Finished *-*\n"); + $finish; end else begin - $stop; + $stop; end end endmodule diff --git a/test_regress/t/t_interface_param1.v b/test_regress/t/t_interface_param1.v index bed33ea78..30abd758d 100644 --- a/test_regress/t/t_interface_param1.v +++ b/test_regress/t/t_interface_param1.v @@ -12,7 +12,7 @@ module t (/*AUTOARG*/ ); input wire clk; - wire [31:0] result; + wire [31:0] result; test_if #(.id(3)) s(); sub_test U_SUB_TEST(s.a.b, result); // the line causing error endmodule : t @@ -34,14 +34,14 @@ interface test_if (); typedef struct packed { - logic a; + logic a; logic [31:0] b; } aType; aType a; typedef struct packed { - logic c; + logic c; logic [31:0] d; } bType; diff --git a/test_regress/t/t_interface_parameter_access.v b/test_regress/t/t_interface_parameter_access.v index 4bdd8c6ec..17f353a5c 100644 --- a/test_regress/t/t_interface_parameter_access.v +++ b/test_regress/t/t_interface_parameter_access.v @@ -9,15 +9,15 @@ interface test_if #(parameter integer FOO = 1); // Interface variable - logic data; + logic data; localparam integer BAR = FOO + 1; // Modport modport mp( import getFoo, - output data - ); + output data + ); function integer getFoo (); return FOO; @@ -31,16 +31,16 @@ endfunction module t (/*AUTOARG*/ - // Inputs - clk - ); + // Inputs + clk + ); input clk; test_if #( .FOO (identity(5)) ) the_interface (); test_if #( .FOO (identity(7)) ) array_interface [1:0] (); testmod testmod_i (.clk (clk), - .intf (the_interface), + .intf (the_interface), .intf_no_mp (the_interface), .intf_array (array_interface) ); @@ -52,15 +52,15 @@ module t (/*AUTOARG*/ initial begin if (THE_TOP_FOO != 5) begin $display("%%Error: THE_TOP_FOO = %0d", THE_TOP_FOO); - $stop; + $stop; end if (THE_TOP_FOO_BITS != 64) begin $display("%%Error: THE_TOP_FOO_BITS = %0d", THE_TOP_FOO_BITS); - $stop; + $stop; end if (THE_ARRAY_FOO != 7) begin $display("%%Error: THE_ARRAY_FOO = %0d", THE_ARRAY_FOO); - $stop; + $stop; end end @@ -85,7 +85,7 @@ module testmod always @(posedge clk) begin if (THE_FOO != 5) begin $display("%%Error: THE_FOO = %0d", THE_FOO); - $stop; + $stop; end if (THE_OTHER_FOO != 5) begin $display("%%Error: THE_OTHER_FOO = %0d", THE_OTHER_FOO); @@ -97,7 +97,7 @@ module testmod end if (intf.FOO != 5) begin $display("%%Error: intf.FOO = %0d", intf.FOO); - $stop; + $stop; end if (intf_no_mp.FOO != 5) begin $display("%%Error: intf_no_mp.FOO = %0d", intf_no_mp.FOO); @@ -109,7 +109,7 @@ module testmod end // if (i.getFoo() != 5) begin // $display("%%Error: i.getFoo() = %0d", i.getFoo()); - // $stop; + // $stop; // end if (THE_BAR != 6) begin $display("%%Error: THE_BAR = %0d", THE_BAR); @@ -125,7 +125,7 @@ module testmod end if (intf.BAR != 6) begin $display("%%Error: intf.BAR = %0d", intf.BAR); - $stop; + $stop; end if (intf_no_mp.BAR != 6) begin $display("%%Error: intf_no_mp.BAR = %0d", intf_no_mp.BAR); diff --git a/test_regress/t/t_interface_ref_trace.v b/test_regress/t/t_interface_ref_trace.v index 0f2577d47..13540e5c9 100644 --- a/test_regress/t/t_interface_ref_trace.v +++ b/test_regress/t/t_interface_ref_trace.v @@ -18,15 +18,15 @@ endinterface interface ifc (input logic clk, input integer cyc); - integer value; + integer value; struct_t the_struct; ifc_inner inner (.*); endinterface module t (/*AUTOARG*/ - // Inputs - clk - ); + // Inputs + clk + ); input clk; integer cyc = 0; @@ -52,10 +52,10 @@ module t (/*AUTOARG*/ always @ (posedge clk) begin cyc <= cyc + 1; if (cyc==20) begin - if (intf_1.value != 21) $stop; - if (intf_2.value != 22) $stop; - $write("*-* All Finished *-*\n"); - $finish; + if (intf_1.value != 21) $stop; + if (intf_2.value != 22) $stop; + $write("*-* All Finished *-*\n"); + $finish; end end endmodule @@ -99,9 +99,9 @@ module sub_all `endif ifc intf_in_sub_all ( - .clk(intf_one.clk), - .cyc(intf_one.cyc) - ); + .clk(intf_one.clk), + .cyc(intf_one.cyc) + ); assign intf_in_sub_all.value = intf_one.value + 1000; sub_check ac1 (.intf_for_check(intf_one)); diff --git a/test_regress/t/t_interface_star.v b/test_regress/t/t_interface_star.v index f8e3c9c25..76ef1ea20 100644 --- a/test_regress/t/t_interface_star.v +++ b/test_regress/t/t_interface_star.v @@ -21,9 +21,9 @@ module t (/*AUTOARG*/ always @ (posedge clk) begin cyc <= cyc + 1; if (cyc==20) begin - if (c_data.value != 12345) $stop; - $write("*-* All Finished *-*\n"); - $finish; + if (c_data.value != 12345) $stop; + $write("*-* All Finished *-*\n"); + $finish; end end endmodule diff --git a/test_regress/t/t_interface_twod.v b/test_regress/t/t_interface_twod.v index 76b8a9a77..b41b3435c 100644 --- a/test_regress/t/t_interface_twod.v +++ b/test_regress/t/t_interface_twod.v @@ -21,17 +21,17 @@ module t (/*AUTOARG*/ itop1b(); wrapper c1 (.isuba(itop1a), - .isubb(itop1b), - .i_valuea(14), - .i_valueb(15)); + .isubb(itop1b), + .i_valuea(14), + .i_valueb(15)); always @ (posedge clk) begin cyc <= cyc + 1; if (cyc==20) begin - if (itop1a.value != 14) $stop; - if (itop1b.value != 15) $stop; - $write("*-* All Finished *-*\n"); - $finish; + if (itop1a.value != 14) $stop; + if (itop1b.value != 15) $stop; + $write("*-* All Finished *-*\n"); + $finish; end end endmodule diff --git a/test_regress/t/t_langext_2.v b/test_regress/t/t_langext_2.v index feac45c88..30aa8b428 100644 --- a/test_regress/t/t_langext_2.v +++ b/test_regress/t/t_langext_2.v @@ -18,39 +18,39 @@ module t (/*AUTOARG*/ ); input clk; - reg [1:0] res; + reg [1:0] res; // Instantiate the test test test_i (/*AUTOINST*/ - // Outputs - .res (res), - // Inputs - .clk (clk), - .in (1'b1)); + // Outputs + .res (res), + // Inputs + .clk (clk), + .in (1'b1)); endmodule module test (// Outputs - res, - // Inputs - clk, - in + res, + // Inputs + clk, + in ); output [1:0] res; - input clk; - input in; + input clk; + input in; // This is a SystemVerilog 2009 only test generate genvar i; for (i=0; i<2; i=i+1) begin - always @(posedge clk) begin - unique0 case (i) - 0: res[0:0] <= in; - 1: res[1:1] <= in; - endcase - end + always @(posedge clk) begin + unique0 case (i) + 0: res[0:0] <= in; + 1: res[1:1] <= in; + endcase + end end endgenerate endmodule diff --git a/test_regress/t/t_leak.v b/test_regress/t/t_leak.v index 25ef75492..cca64710b 100644 --- a/test_regress/t/t_leak.v +++ b/test_regress/t/t_leak.v @@ -14,8 +14,8 @@ module t (clk); always @ (posedge clk) begin cyc <= cyc + 1; if (cyc==2) begin - // Not $finish; as we don't want a message to scroll by - $c("Verilated::threadContextp()->gotFinish(true);"); + // Not $finish; as we don't want a message to scroll by + $c("Verilated::threadContextp()->gotFinish(true);"); end end endmodule diff --git a/test_regress/t/t_lib_prot.v b/test_regress/t/t_lib_prot.v index d3dad3679..7da04b3ed 100644 --- a/test_regress/t/t_lib_prot.v +++ b/test_regress/t/t_lib_prot.v @@ -66,7 +66,7 @@ module t #(parameter GATED_CLK = 0) (/*AUTOARG*/ logic [15:0] s8x16up_3d_in[1:0][0:1][0:1]; logic [15:0] s8x16up_3d_out[1:0][0:1][0:1]; - wire clk_en = crc[0]; + wire clk_en = crc[0]; secret secret ( diff --git a/test_regress/t/t_lib_prot_secret.v b/test_regress/t/t_lib_prot_secret.v index c01d0f48e..7eeb7efca 100644 --- a/test_regress/t/t_lib_prot_secret.v +++ b/test_regress/t/t_lib_prot_secret.v @@ -43,7 +43,7 @@ module secret #(parameter GATED_CLK = 0) initial $display("created %m"); - logic the_clk; + logic the_clk; generate if (GATED_CLK != 0) begin: yes_gated_clock logic clk_en_latch /*verilator clock_enable*/; diff --git a/test_regress/t/t_lint_blksync_loop.v b/test_regress/t/t_lint_blksync_loop.v index dc707e7f6..c6564a957 100644 --- a/test_regress/t/t_lint_blksync_loop.v +++ b/test_regress/t/t_lint_blksync_loop.v @@ -14,31 +14,31 @@ module t (/*AUTOARG*/ /*AUTOINPUT*/ // Beginning of automatic inputs (from unused autoinst inputs) - input [31:0] data_in; // To sub of reg_1r1w.v - input [7:0] ra; // To sub of reg_1r1w.v - input rd; // To sub of reg_1r1w.v - input rst_l; // To sub of reg_1r1w.v - input [7:0] wa; // To sub of reg_1r1w.v - input wr; // To sub of reg_1r1w.v + input [31:0] data_in; // To sub of reg_1r1w.v + input [7:0] ra; // To sub of reg_1r1w.v + input rd; // To sub of reg_1r1w.v + input rst_l; // To sub of reg_1r1w.v + input [7:0] wa; // To sub of reg_1r1w.v + input wr; // To sub of reg_1r1w.v // End of automatics /*AUTOOUTPUT*/ // Beginning of automatic outputs (from unused autoinst outputs) - output [31:0] data_out; // From sub of reg_1r1w.v + output [31:0] data_out; // From sub of reg_1r1w.v // End of automatics reg_1r1w #(.WIDTH(32), .DEPTH(256), .ADRWID(8)) sub (/*AUTOINST*/ // Outputs - .data_out (data_out[31:0]), + .data_out (data_out[31:0]), // Inputs - .data_in (data_in[31:0]), - .ra (ra[7:0]), - .wa (wa[7:0]), - .wr (wr), - .rd (rd), - .clk (clk), - .rst_l (rst_l)); + .data_in (data_in[31:0]), + .ra (ra[7:0]), + .wa (wa[7:0]), + .wr (wr), + .rd (rd), + .clk (clk), + .rst_l (rst_l)); endmodule @@ -82,24 +82,24 @@ module reg_1r1w always @(posedge clk or negedge rst_l) begin if (!rst_l) begin - for (x=0; x> 1); + if (arg!=0) arg = arg - 1; + for (clog2_emulate=0; arg!=0; clog2_emulate=clog2_emulate+1) + arg = (arg >> 1); end endfunction endmodule diff --git a/test_regress/t/t_math_cmp.v b/test_regress/t/t_math_cmp.v index 203c39416..a142809d9 100644 --- a/test_regress/t/t_math_cmp.v +++ b/test_regress/t/t_math_cmp.v @@ -15,40 +15,40 @@ module t (/*AUTOARG*/ reg [2:0] index_b; prover #(4) p4 (/*AUTOINST*/ - // Inputs - .clk (clk), - .index_a (index_a), - .index_b (index_b)); + // Inputs + .clk (clk), + .index_a (index_a), + .index_b (index_b)); prover #(32) p32 (/*AUTOINST*/ - // Inputs - .clk (clk), - .index_a (index_a), - .index_b (index_b)); + // Inputs + .clk (clk), + .index_a (index_a), + .index_b (index_b)); prover #(63) p63 (/*AUTOINST*/ - // Inputs - .clk (clk), - .index_a (index_a), - .index_b (index_b)); + // Inputs + .clk (clk), + .index_a (index_a), + .index_b (index_b)); prover #(64) p64 (/*AUTOINST*/ - // Inputs - .clk (clk), - .index_a (index_a), - .index_b (index_b)); + // Inputs + .clk (clk), + .index_a (index_a), + .index_b (index_b)); prover #(72) p72 (/*AUTOINST*/ - // Inputs - .clk (clk), - .index_a (index_a), - .index_b (index_b)); + // Inputs + .clk (clk), + .index_a (index_a), + .index_b (index_b)); prover #(126) p126 (/*AUTOINST*/ - // Inputs - .clk (clk), - .index_a (index_a), - .index_b (index_b)); + // Inputs + .clk (clk), + .index_a (index_a), + .index_b (index_b)); prover #(128) p128 (/*AUTOINST*/ - // Inputs - .clk (clk), - .index_a (index_a), - .index_b (index_b)); + // Inputs + .clk (clk), + .index_a (index_a), + .index_b (index_b)); integer cyc; initial cyc = 0; initial index_a = 3'b0; @@ -61,8 +61,8 @@ module t (/*AUTOARG*/ always @ (posedge clk) begin cyc <= cyc + 1; if (cyc==99) begin - $write("*-* All Finished *-*\n"); - $finish; + $write("*-* All Finished *-*\n"); + $finish; end end @@ -80,25 +80,25 @@ module prover ( reg signed [WIDTH-1:0] as; reg signed [WIDTH-1:0] bs; - wire [WIDTH-1:0] b = bs; + wire [WIDTH-1:0] b = bs; // verilator lint_off LATCH always @* begin casez (index_a) - 3'd0: as = {(WIDTH){1'd0}}; // 0 - 3'd1: as = {{(WIDTH-1){1'd0}}, 1'b1}; // 1 - 3'd2: as = {1'b0, {(WIDTH-1){1'd0}}}; // 127 or equiv - 3'd3: as = {(WIDTH){1'd1}}; // -1 - 3'd4: as = {1'b1, {(WIDTH-1){1'd0}}}; // -128 or equiv - default: $stop; + 3'd0: as = {(WIDTH){1'd0}}; // 0 + 3'd1: as = {{(WIDTH-1){1'd0}}, 1'b1}; // 1 + 3'd2: as = {1'b0, {(WIDTH-1){1'd0}}}; // 127 or equiv + 3'd3: as = {(WIDTH){1'd1}}; // -1 + 3'd4: as = {1'b1, {(WIDTH-1){1'd0}}}; // -128 or equiv + default: $stop; endcase casez (index_b) - 3'd0: bs = {(WIDTH){1'd0}}; // 0 - 3'd1: bs = {{(WIDTH-1){1'd0}}, 1'b1}; // 1 - 3'd2: bs = {1'b0, {(WIDTH-1){1'd0}}}; // 127 or equiv - 3'd3: bs = {(WIDTH){1'd1}}; // -1 - 3'd4: bs = {1'b1, {(WIDTH-1){1'd0}}}; // -128 or equiv - default: $stop; + 3'd0: bs = {(WIDTH){1'd0}}; // 0 + 3'd1: bs = {{(WIDTH-1){1'd0}}, 1'b1}; // 1 + 3'd2: bs = {1'b0, {(WIDTH-1){1'd0}}}; // 127 or equiv + 3'd3: bs = {(WIDTH){1'd1}}; // -1 + 3'd4: bs = {1'b1, {(WIDTH-1){1'd0}}}; // -128 or equiv + default: $stop; endcase end // verilator lint_on LATCH @@ -122,16 +122,16 @@ module prover ( cyc <= cyc + 1; if (cyc>2) begin `ifdef TEST_VERBOSE - $write("results[%d][%d] = 8'b%b_%b_%b_%b_%b_%b_%b_%b;\n", - index_a, index_b, - gt, gts, gte, gtes, lt, lts, lte, ltes); + $write("results[%d][%d] = 8'b%b_%b_%b_%b_%b_%b_%b_%b;\n", + index_a, index_b, + gt, gts, gte, gtes, lt, lts, lte, ltes); `endif - exp = results[index_a][index_b]; - got = {gt, gts, gte, gtes, lt, lts, lte, ltes}; - if (exp !== got) begin - $display("%%Error: bad comparison width=%0d: %d/%d got=%b exp=%b", WIDTH, index_a,index_b,got, exp); - $stop; - end + exp = results[index_a][index_b]; + got = {gt, gts, gte, gtes, lt, lts, lte, ltes}; + if (exp !== got) begin + $display("%%Error: bad comparison width=%0d: %d/%d got=%b exp=%b", WIDTH, index_a,index_b,got, exp); + $stop; + end end end diff --git a/test_regress/t/t_math_concat.v b/test_regress/t/t_math_concat.v index a70ec1afa..e452078be 100644 --- a/test_regress/t/t_math_concat.v +++ b/test_regress/t/t_math_concat.v @@ -12,64 +12,64 @@ module t (/*AUTOARG*/ input clk; integer cyc; initial cyc=1; - reg [255:0] i; - wire [255:0] q; + reg [255:0] i; + wire [255:0] q; assign q = { - i[176],i[168],i[126],i[177],i[097],i[123],i[231],i[039], - i[156],i[026],i[001],i[052],i[005],i[240],i[157],i[048], - i[111],i[088],i[133],i[225],i[046],i[038],i[004],i[234], - i[115],i[008],i[069],i[099],i[137],i[130],i[255],i[122], - i[223],i[195],i[224],i[083],i[094],i[018],i[067],i[034], - i[221],i[105],i[104],i[107],i[053],i[066],i[020],i[174], - i[010],i[196],i[003],i[041],i[071],i[194],i[154],i[110], - i[186],i[210],i[040],i[044],i[243],i[236],i[239],i[183], - i[164],i[064],i[086],i[193],i[055],i[206],i[203],i[128], - i[190],i[233],i[023],i[022],i[135],i[108],i[061],i[139], - i[180],i[043],i[109],i[090],i[229],i[238],i[095],i[173], - i[208],i[054],i[025],i[024],i[148],i[079],i[246],i[142], - i[181],i[129],i[120],i[220],i[036],i[159],i[201],i[119], - i[216],i[152],i[175],i[138],i[242],i[143],i[101],i[035], - i[228],i[082],i[211],i[062],i[076],i[124],i[150],i[149], - i[235],i[227],i[250],i[134],i[068],i[032],i[060],i[144], - i[042],i[163],i[087],i[059],i[213],i[251],i[200],i[070], - i[145],i[204],i[249],i[191],i[127],i[247],i[106],i[017], - i[028],i[045],i[215],i[162],i[205],i[073],i[065],i[084], - i[153],i[158],i[085],i[197],i[212],i[114],i[096],i[118], - i[146],i[030],i[058],i[230],i[141],i[000],i[199],i[171], - i[182],i[185],i[021],i[016],i[033],i[237],i[015],i[112], - i[222],i[253],i[244],i[031],i[248],i[092],i[226],i[179], - i[189],i[056],i[132],i[116],i[072],i[184],i[027],i[002], - i[103],i[125],i[009],i[078],i[178],i[245],i[170],i[161], - i[102],i[047],i[192],i[012],i[057],i[207],i[187],i[151], - i[218],i[254],i[214],i[037],i[131],i[165],i[011],i[098], - i[169],i[209],i[167],i[202],i[100],i[172],i[147],i[013], - i[136],i[166],i[252],i[077],i[051],i[074],i[140],i[050], - i[217],i[198],i[081],i[091],i[075],i[121],i[188],i[219], - i[160],i[241],i[080],i[155],i[019],i[006],i[014],i[029], - i[089],i[049],i[113],i[232],i[007],i[117],i[063],i[093] - }; + i[176],i[168],i[126],i[177],i[097],i[123],i[231],i[039], + i[156],i[026],i[001],i[052],i[005],i[240],i[157],i[048], + i[111],i[088],i[133],i[225],i[046],i[038],i[004],i[234], + i[115],i[008],i[069],i[099],i[137],i[130],i[255],i[122], + i[223],i[195],i[224],i[083],i[094],i[018],i[067],i[034], + i[221],i[105],i[104],i[107],i[053],i[066],i[020],i[174], + i[010],i[196],i[003],i[041],i[071],i[194],i[154],i[110], + i[186],i[210],i[040],i[044],i[243],i[236],i[239],i[183], + i[164],i[064],i[086],i[193],i[055],i[206],i[203],i[128], + i[190],i[233],i[023],i[022],i[135],i[108],i[061],i[139], + i[180],i[043],i[109],i[090],i[229],i[238],i[095],i[173], + i[208],i[054],i[025],i[024],i[148],i[079],i[246],i[142], + i[181],i[129],i[120],i[220],i[036],i[159],i[201],i[119], + i[216],i[152],i[175],i[138],i[242],i[143],i[101],i[035], + i[228],i[082],i[211],i[062],i[076],i[124],i[150],i[149], + i[235],i[227],i[250],i[134],i[068],i[032],i[060],i[144], + i[042],i[163],i[087],i[059],i[213],i[251],i[200],i[070], + i[145],i[204],i[249],i[191],i[127],i[247],i[106],i[017], + i[028],i[045],i[215],i[162],i[205],i[073],i[065],i[084], + i[153],i[158],i[085],i[197],i[212],i[114],i[096],i[118], + i[146],i[030],i[058],i[230],i[141],i[000],i[199],i[171], + i[182],i[185],i[021],i[016],i[033],i[237],i[015],i[112], + i[222],i[253],i[244],i[031],i[248],i[092],i[226],i[179], + i[189],i[056],i[132],i[116],i[072],i[184],i[027],i[002], + i[103],i[125],i[009],i[078],i[178],i[245],i[170],i[161], + i[102],i[047],i[192],i[012],i[057],i[207],i[187],i[151], + i[218],i[254],i[214],i[037],i[131],i[165],i[011],i[098], + i[169],i[209],i[167],i[202],i[100],i[172],i[147],i[013], + i[136],i[166],i[252],i[077],i[051],i[074],i[140],i[050], + i[217],i[198],i[081],i[091],i[075],i[121],i[188],i[219], + i[160],i[241],i[080],i[155],i[019],i[006],i[014],i[029], + i[089],i[049],i[113],i[232],i[007],i[117],i[063],i[093] + }; always @ (posedge clk) begin if (cyc!=0) begin - cyc <= cyc + 1; + cyc <= cyc + 1; `ifdef TEST_VERBOSE - $write("%x %x\n", q, i); + $write("%x %x\n", q, i); `endif - if (cyc==1) begin - i <= 256'hed388e646c843d35de489bab2413d77045e0eb7642b148537491f3da147e7f26; - end - if (cyc==2) begin - i <= 256'h0e17c88f3d5fe51a982646c8e2bd68c3e236ddfddddbdad20a48e039c9f395b8; - if (q != 256'h697bad4b0cf2d7fa4ad22809293710bb67d1eb3131e8eb2135f2c7bd820baa84) $stop; - end - if (cyc==3) begin - if (q != 256'h320eda5078b3e942353d16dddc8b29fd773b4fcec8323612dadfb1fa483f602c) $stop; - end - if (cyc==4) begin - $write("*-* All Finished *-*\n"); - $finish; - end + if (cyc==1) begin + i <= 256'hed388e646c843d35de489bab2413d77045e0eb7642b148537491f3da147e7f26; + end + if (cyc==2) begin + i <= 256'h0e17c88f3d5fe51a982646c8e2bd68c3e236ddfddddbdad20a48e039c9f395b8; + if (q != 256'h697bad4b0cf2d7fa4ad22809293710bb67d1eb3131e8eb2135f2c7bd820baa84) $stop; + end + if (cyc==3) begin + if (q != 256'h320eda5078b3e942353d16dddc8b29fd773b4fcec8323612dadfb1fa483f602c) $stop; + end + if (cyc==4) begin + $write("*-* All Finished *-*\n"); + $finish; + end end end endmodule diff --git a/test_regress/t/t_math_concat0.v b/test_regress/t/t_math_concat0.v index 3ba29abb7..0f59bbcf0 100644 --- a/test_regress/t/t_math_concat0.v +++ b/test_regress/t/t_math_concat0.v @@ -9,28 +9,28 @@ module t (/*AUTOARG*/ ); input clk; - integer cyc = 0; - reg [63:0] crc; - reg [63:0] sum; + integer cyc = 0; + reg [63:0] crc; + reg [63:0] sum; // Take CRC data and apply to testblock inputs wire [15:0] in = crc[15:0]; /*AUTOWIRE*/ // Beginning of automatic wires (for undeclared instantiated-module outputs) - wire [15:0] outa; // From test of Test.v - wire [15:0] outb; // From test of Test.v - wire [15:0] outc; // From test of Test.v + wire [15:0] outa; // From test of Test.v + wire [15:0] outb; // From test of Test.v + wire [15:0] outc; // From test of Test.v // End of automatics Test test (/*AUTOINST*/ - // Outputs - .outa (outa[15:0]), - .outb (outb[15:0]), - .outc (outc[15:0]), - // Inputs - .clk (clk), - .in (in[15:0])); + // Outputs + .outa (outa[15:0]), + .outb (outb[15:0]), + .outc (outc[15:0]), + // Inputs + .clk (clk), + .in (in[15:0])); // Aggregate outputs into a single result vector wire [63:0] result = {16'h0, outa, outb, outc}; @@ -44,23 +44,23 @@ module t (/*AUTOARG*/ crc <= {crc[62:0], crc[63] ^ crc[2] ^ crc[0]}; sum <= result ^ {sum[62:0], sum[63] ^ sum[2] ^ sum[0]}; if (cyc==0) begin - // Setup - crc <= 64'h5aef0c8d_d70a4497; - sum <= 64'h0; + // Setup + crc <= 64'h5aef0c8d_d70a4497; + sum <= 64'h0; end else if (cyc<10) begin - sum <= 64'h0; + sum <= 64'h0; end else if (cyc<90) begin end else if (cyc==99) begin - $write("[%0t] cyc==%0d crc=%x sum=%x\n", $time, cyc, crc, sum); - if (crc !== 64'hc77bb9b3784ea091) $stop; - // What checksum will we end up with (above print should match) + $write("[%0t] cyc==%0d crc=%x sum=%x\n", $time, cyc, crc, sum); + if (crc !== 64'hc77bb9b3784ea091) $stop; + // What checksum will we end up with (above print should match) `define EXPECTED_SUM 64'h09be74b1b0f8c35d - if (sum !== `EXPECTED_SUM) $stop; - $write("*-* All Finished *-*\n"); - $finish; + if (sum !== `EXPECTED_SUM) $stop; + $write("*-* All Finished *-*\n"); + $finish; end end diff --git a/test_regress/t/t_math_concat64.v b/test_regress/t/t_math_concat64.v index 54f1ec601..e30f45a00 100644 --- a/test_regress/t/t_math_concat64.v +++ b/test_regress/t/t_math_concat64.v @@ -12,11 +12,11 @@ module t (/*AUTOARG*/ input clk; integer cyc; initial cyc=1; - reg [127:0] i; - wire [127:0] q1; - wire [127:0] q32; - wire [127:0] q64; - wire [63:0] q64_low; + reg [127:0] i; + wire [127:0] q1; + wire [127:0] q32; + wire [127:0] q64; + wire [63:0] q64_low; assign q1 = { i[24*4], i[25*4], i[26*4], i[27*4], i[28*4], i[29*4], i[30*4], i[31*4], @@ -94,38 +94,38 @@ module t (/*AUTOARG*/ always @ (posedge clk) begin if (cyc!=0) begin - cyc <= cyc + 1; + cyc <= cyc + 1; `ifdef TEST_VERBOSE - $write("%x %x\n", q1, i); + $write("%x %x\n", q1, i); `endif - if (cyc==1) begin - i <= 128'hed388e646c843d35de489bab2413d770; - end - if (cyc==2) begin - i <= 128'h0e17c88f3d5fe51a982646c8e2bd68c3; - if (q1 != 128'h06f0b17c6551e269e3ab07723b26fb10) $stop; - if (q1 != q32) $stop; - if (q1 != q64) $stop; - if (q1[63:0] != q64_low) $stop; - end - if (cyc==3) begin - i <= 128'he236ddfddddbdad20a48e039c9f395b8; - if (q1 != 128'h8c6f018c8a992c979a3e7859f29ac36d) $stop; - if (q1 != q32) $stop; - if (q1 != q64) $stop; - if (q1[63:0] != q64_low) $stop; - end - if (cyc==4) begin - i <= 128'h45e0eb7642b148537491f3da147e7f26; - if (q1 != 128'hf45fc07e4fa8524cf9571425f17f9ad7) $stop; - if (q1 != q32) $stop; - if (q1 != q64) $stop; - if (q1[63:0] != q64_low) $stop; - end - if (cyc==9) begin - $write("*-* All Finished *-*\n"); - $finish; - end + if (cyc==1) begin + i <= 128'hed388e646c843d35de489bab2413d770; + end + if (cyc==2) begin + i <= 128'h0e17c88f3d5fe51a982646c8e2bd68c3; + if (q1 != 128'h06f0b17c6551e269e3ab07723b26fb10) $stop; + if (q1 != q32) $stop; + if (q1 != q64) $stop; + if (q1[63:0] != q64_low) $stop; + end + if (cyc==3) begin + i <= 128'he236ddfddddbdad20a48e039c9f395b8; + if (q1 != 128'h8c6f018c8a992c979a3e7859f29ac36d) $stop; + if (q1 != q32) $stop; + if (q1 != q64) $stop; + if (q1[63:0] != q64_low) $stop; + end + if (cyc==4) begin + i <= 128'h45e0eb7642b148537491f3da147e7f26; + if (q1 != 128'hf45fc07e4fa8524cf9571425f17f9ad7) $stop; + if (q1 != q32) $stop; + if (q1 != q64) $stop; + if (q1[63:0] != q64_low) $stop; + end + if (cyc==9) begin + $write("*-* All Finished *-*\n"); + $finish; + end end end endmodule diff --git a/test_regress/t/t_math_cond_huge.v b/test_regress/t/t_math_cond_huge.v index f0e72273a..cff1f7099 100644 --- a/test_regress/t/t_math_cond_huge.v +++ b/test_regress/t/t_math_cond_huge.v @@ -10,284 +10,284 @@ module t (/*AUTOARG*/ ); input clk; - integer cyc = 0; - reg [63:0] crc; - reg [63:0] sum; + integer cyc = 0; + reg [63:0] crc; + reg [63:0] sum; // Take CRC data and apply to testblock inputs - wire [7:0] sel = crc[7:0]; + wire [7:0] sel = crc[7:0]; wire [255+3:0] in = {crc[2:0],crc,crc,crc,crc}; /*AUTOWIRE*/ // Beginning of automatic wires (for undeclared instantiated-module outputs) - wire [3:0] out; // From test of Test.v + wire [3:0] out; // From test of Test.v // End of automatics /* Test AUTO_TEMPLATE ( - .i\([0-9]+\) (in[\1 +:4]), + .i\([0-9]+\) (in[\1 +:4]), ); */ Test test (/*AUTOINST*/ - // Outputs - .out (out[3:0]), - // Inputs - .sel (sel[7:0]), - .i0 (in[0 +:4]), // Templated - .i1 (in[1 +:4]), // Templated - .i2 (in[2 +:4]), // Templated - .i3 (in[3 +:4]), // Templated - .i4 (in[4 +:4]), // Templated - .i5 (in[5 +:4]), // Templated - .i6 (in[6 +:4]), // Templated - .i7 (in[7 +:4]), // Templated - .i8 (in[8 +:4]), // Templated - .i9 (in[9 +:4]), // Templated - .i10 (in[10 +:4]), // Templated - .i11 (in[11 +:4]), // Templated - .i12 (in[12 +:4]), // Templated - .i13 (in[13 +:4]), // Templated - .i14 (in[14 +:4]), // Templated - .i15 (in[15 +:4]), // Templated - .i16 (in[16 +:4]), // Templated - .i17 (in[17 +:4]), // Templated - .i18 (in[18 +:4]), // Templated - .i19 (in[19 +:4]), // Templated - .i20 (in[20 +:4]), // Templated - .i21 (in[21 +:4]), // Templated - .i22 (in[22 +:4]), // Templated - .i23 (in[23 +:4]), // Templated - .i24 (in[24 +:4]), // Templated - .i25 (in[25 +:4]), // Templated - .i26 (in[26 +:4]), // Templated - .i27 (in[27 +:4]), // Templated - .i28 (in[28 +:4]), // Templated - .i29 (in[29 +:4]), // Templated - .i30 (in[30 +:4]), // Templated - .i31 (in[31 +:4]), // Templated - .i32 (in[32 +:4]), // Templated - .i33 (in[33 +:4]), // Templated - .i34 (in[34 +:4]), // Templated - .i35 (in[35 +:4]), // Templated - .i36 (in[36 +:4]), // Templated - .i37 (in[37 +:4]), // Templated - .i38 (in[38 +:4]), // Templated - .i39 (in[39 +:4]), // Templated - .i40 (in[40 +:4]), // Templated - .i41 (in[41 +:4]), // Templated - .i42 (in[42 +:4]), // Templated - .i43 (in[43 +:4]), // Templated - .i44 (in[44 +:4]), // Templated - .i45 (in[45 +:4]), // Templated - .i46 (in[46 +:4]), // Templated - .i47 (in[47 +:4]), // Templated - .i48 (in[48 +:4]), // Templated - .i49 (in[49 +:4]), // Templated - .i50 (in[50 +:4]), // Templated - .i51 (in[51 +:4]), // Templated - .i52 (in[52 +:4]), // Templated - .i53 (in[53 +:4]), // Templated - .i54 (in[54 +:4]), // Templated - .i55 (in[55 +:4]), // Templated - .i56 (in[56 +:4]), // Templated - .i57 (in[57 +:4]), // Templated - .i58 (in[58 +:4]), // Templated - .i59 (in[59 +:4]), // Templated - .i60 (in[60 +:4]), // Templated - .i61 (in[61 +:4]), // Templated - .i62 (in[62 +:4]), // Templated - .i63 (in[63 +:4]), // Templated - .i64 (in[64 +:4]), // Templated - .i65 (in[65 +:4]), // Templated - .i66 (in[66 +:4]), // Templated - .i67 (in[67 +:4]), // Templated - .i68 (in[68 +:4]), // Templated - .i69 (in[69 +:4]), // Templated - .i70 (in[70 +:4]), // Templated - .i71 (in[71 +:4]), // Templated - .i72 (in[72 +:4]), // Templated - .i73 (in[73 +:4]), // Templated - .i74 (in[74 +:4]), // Templated - .i75 (in[75 +:4]), // Templated - .i76 (in[76 +:4]), // Templated - .i77 (in[77 +:4]), // Templated - .i78 (in[78 +:4]), // Templated - .i79 (in[79 +:4]), // Templated - .i80 (in[80 +:4]), // Templated - .i81 (in[81 +:4]), // Templated - .i82 (in[82 +:4]), // Templated - .i83 (in[83 +:4]), // Templated - .i84 (in[84 +:4]), // Templated - .i85 (in[85 +:4]), // Templated - .i86 (in[86 +:4]), // Templated - .i87 (in[87 +:4]), // Templated - .i88 (in[88 +:4]), // Templated - .i89 (in[89 +:4]), // Templated - .i90 (in[90 +:4]), // Templated - .i91 (in[91 +:4]), // Templated - .i92 (in[92 +:4]), // Templated - .i93 (in[93 +:4]), // Templated - .i94 (in[94 +:4]), // Templated - .i95 (in[95 +:4]), // Templated - .i96 (in[96 +:4]), // Templated - .i97 (in[97 +:4]), // Templated - .i98 (in[98 +:4]), // Templated - .i99 (in[99 +:4]), // Templated - .i100 (in[100 +:4]), // Templated - .i101 (in[101 +:4]), // Templated - .i102 (in[102 +:4]), // Templated - .i103 (in[103 +:4]), // Templated - .i104 (in[104 +:4]), // Templated - .i105 (in[105 +:4]), // Templated - .i106 (in[106 +:4]), // Templated - .i107 (in[107 +:4]), // Templated - .i108 (in[108 +:4]), // Templated - .i109 (in[109 +:4]), // Templated - .i110 (in[110 +:4]), // Templated - .i111 (in[111 +:4]), // Templated - .i112 (in[112 +:4]), // Templated - .i113 (in[113 +:4]), // Templated - .i114 (in[114 +:4]), // Templated - .i115 (in[115 +:4]), // Templated - .i116 (in[116 +:4]), // Templated - .i117 (in[117 +:4]), // Templated - .i118 (in[118 +:4]), // Templated - .i119 (in[119 +:4]), // Templated - .i120 (in[120 +:4]), // Templated - .i121 (in[121 +:4]), // Templated - .i122 (in[122 +:4]), // Templated - .i123 (in[123 +:4]), // Templated - .i124 (in[124 +:4]), // Templated - .i125 (in[125 +:4]), // Templated - .i126 (in[126 +:4]), // Templated - .i127 (in[127 +:4]), // Templated - .i128 (in[128 +:4]), // Templated - .i129 (in[129 +:4]), // Templated - .i130 (in[130 +:4]), // Templated - .i131 (in[131 +:4]), // Templated - .i132 (in[132 +:4]), // Templated - .i133 (in[133 +:4]), // Templated - .i134 (in[134 +:4]), // Templated - .i135 (in[135 +:4]), // Templated - .i136 (in[136 +:4]), // Templated - .i137 (in[137 +:4]), // Templated - .i138 (in[138 +:4]), // Templated - .i139 (in[139 +:4]), // Templated - .i140 (in[140 +:4]), // Templated - .i141 (in[141 +:4]), // Templated - .i142 (in[142 +:4]), // Templated - .i143 (in[143 +:4]), // Templated - .i144 (in[144 +:4]), // Templated - .i145 (in[145 +:4]), // Templated - .i146 (in[146 +:4]), // Templated - .i147 (in[147 +:4]), // Templated - .i148 (in[148 +:4]), // Templated - .i149 (in[149 +:4]), // Templated - .i150 (in[150 +:4]), // Templated - .i151 (in[151 +:4]), // Templated - .i152 (in[152 +:4]), // Templated - .i153 (in[153 +:4]), // Templated - .i154 (in[154 +:4]), // Templated - .i155 (in[155 +:4]), // Templated - .i156 (in[156 +:4]), // Templated - .i157 (in[157 +:4]), // Templated - .i158 (in[158 +:4]), // Templated - .i159 (in[159 +:4]), // Templated - .i160 (in[160 +:4]), // Templated - .i161 (in[161 +:4]), // Templated - .i162 (in[162 +:4]), // Templated - .i163 (in[163 +:4]), // Templated - .i164 (in[164 +:4]), // Templated - .i165 (in[165 +:4]), // Templated - .i166 (in[166 +:4]), // Templated - .i167 (in[167 +:4]), // Templated - .i168 (in[168 +:4]), // Templated - .i169 (in[169 +:4]), // Templated - .i170 (in[170 +:4]), // Templated - .i171 (in[171 +:4]), // Templated - .i172 (in[172 +:4]), // Templated - .i173 (in[173 +:4]), // Templated - .i174 (in[174 +:4]), // Templated - .i175 (in[175 +:4]), // Templated - .i176 (in[176 +:4]), // Templated - .i177 (in[177 +:4]), // Templated - .i178 (in[178 +:4]), // Templated - .i179 (in[179 +:4]), // Templated - .i180 (in[180 +:4]), // Templated - .i181 (in[181 +:4]), // Templated - .i182 (in[182 +:4]), // Templated - .i183 (in[183 +:4]), // Templated - .i184 (in[184 +:4]), // Templated - .i185 (in[185 +:4]), // Templated - .i186 (in[186 +:4]), // Templated - .i187 (in[187 +:4]), // Templated - .i188 (in[188 +:4]), // Templated - .i189 (in[189 +:4]), // Templated - .i190 (in[190 +:4]), // Templated - .i191 (in[191 +:4]), // Templated - .i192 (in[192 +:4]), // Templated - .i193 (in[193 +:4]), // Templated - .i194 (in[194 +:4]), // Templated - .i195 (in[195 +:4]), // Templated - .i196 (in[196 +:4]), // Templated - .i197 (in[197 +:4]), // Templated - .i198 (in[198 +:4]), // Templated - .i199 (in[199 +:4]), // Templated - .i200 (in[200 +:4]), // Templated - .i201 (in[201 +:4]), // Templated - .i202 (in[202 +:4]), // Templated - .i203 (in[203 +:4]), // Templated - .i204 (in[204 +:4]), // Templated - .i205 (in[205 +:4]), // Templated - .i206 (in[206 +:4]), // Templated - .i207 (in[207 +:4]), // Templated - .i208 (in[208 +:4]), // Templated - .i209 (in[209 +:4]), // Templated - .i210 (in[210 +:4]), // Templated - .i211 (in[211 +:4]), // Templated - .i212 (in[212 +:4]), // Templated - .i213 (in[213 +:4]), // Templated - .i214 (in[214 +:4]), // Templated - .i215 (in[215 +:4]), // Templated - .i216 (in[216 +:4]), // Templated - .i217 (in[217 +:4]), // Templated - .i218 (in[218 +:4]), // Templated - .i219 (in[219 +:4]), // Templated - .i220 (in[220 +:4]), // Templated - .i221 (in[221 +:4]), // Templated - .i222 (in[222 +:4]), // Templated - .i223 (in[223 +:4]), // Templated - .i224 (in[224 +:4]), // Templated - .i225 (in[225 +:4]), // Templated - .i226 (in[226 +:4]), // Templated - .i227 (in[227 +:4]), // Templated - .i228 (in[228 +:4]), // Templated - .i229 (in[229 +:4]), // Templated - .i230 (in[230 +:4]), // Templated - .i231 (in[231 +:4]), // Templated - .i232 (in[232 +:4]), // Templated - .i233 (in[233 +:4]), // Templated - .i234 (in[234 +:4]), // Templated - .i235 (in[235 +:4]), // Templated - .i236 (in[236 +:4]), // Templated - .i237 (in[237 +:4]), // Templated - .i238 (in[238 +:4]), // Templated - .i239 (in[239 +:4]), // Templated - .i240 (in[240 +:4]), // Templated - .i241 (in[241 +:4]), // Templated - .i242 (in[242 +:4]), // Templated - .i243 (in[243 +:4]), // Templated - .i244 (in[244 +:4]), // Templated - .i245 (in[245 +:4]), // Templated - .i246 (in[246 +:4]), // Templated - .i247 (in[247 +:4]), // Templated - .i248 (in[248 +:4]), // Templated - .i249 (in[249 +:4]), // Templated - .i250 (in[250 +:4]), // Templated - .i251 (in[251 +:4]), // Templated - .i252 (in[252 +:4]), // Templated - .i253 (in[253 +:4]), // Templated - .i254 (in[254 +:4]), // Templated - .i255 (in[255 +:4])); // Templated + // Outputs + .out (out[3:0]), + // Inputs + .sel (sel[7:0]), + .i0 (in[0 +:4]), // Templated + .i1 (in[1 +:4]), // Templated + .i2 (in[2 +:4]), // Templated + .i3 (in[3 +:4]), // Templated + .i4 (in[4 +:4]), // Templated + .i5 (in[5 +:4]), // Templated + .i6 (in[6 +:4]), // Templated + .i7 (in[7 +:4]), // Templated + .i8 (in[8 +:4]), // Templated + .i9 (in[9 +:4]), // Templated + .i10 (in[10 +:4]), // Templated + .i11 (in[11 +:4]), // Templated + .i12 (in[12 +:4]), // Templated + .i13 (in[13 +:4]), // Templated + .i14 (in[14 +:4]), // Templated + .i15 (in[15 +:4]), // Templated + .i16 (in[16 +:4]), // Templated + .i17 (in[17 +:4]), // Templated + .i18 (in[18 +:4]), // Templated + .i19 (in[19 +:4]), // Templated + .i20 (in[20 +:4]), // Templated + .i21 (in[21 +:4]), // Templated + .i22 (in[22 +:4]), // Templated + .i23 (in[23 +:4]), // Templated + .i24 (in[24 +:4]), // Templated + .i25 (in[25 +:4]), // Templated + .i26 (in[26 +:4]), // Templated + .i27 (in[27 +:4]), // Templated + .i28 (in[28 +:4]), // Templated + .i29 (in[29 +:4]), // Templated + .i30 (in[30 +:4]), // Templated + .i31 (in[31 +:4]), // Templated + .i32 (in[32 +:4]), // Templated + .i33 (in[33 +:4]), // Templated + .i34 (in[34 +:4]), // Templated + .i35 (in[35 +:4]), // Templated + .i36 (in[36 +:4]), // Templated + .i37 (in[37 +:4]), // Templated + .i38 (in[38 +:4]), // Templated + .i39 (in[39 +:4]), // Templated + .i40 (in[40 +:4]), // Templated + .i41 (in[41 +:4]), // Templated + .i42 (in[42 +:4]), // Templated + .i43 (in[43 +:4]), // Templated + .i44 (in[44 +:4]), // Templated + .i45 (in[45 +:4]), // Templated + .i46 (in[46 +:4]), // Templated + .i47 (in[47 +:4]), // Templated + .i48 (in[48 +:4]), // Templated + .i49 (in[49 +:4]), // Templated + .i50 (in[50 +:4]), // Templated + .i51 (in[51 +:4]), // Templated + .i52 (in[52 +:4]), // Templated + .i53 (in[53 +:4]), // Templated + .i54 (in[54 +:4]), // Templated + .i55 (in[55 +:4]), // Templated + .i56 (in[56 +:4]), // Templated + .i57 (in[57 +:4]), // Templated + .i58 (in[58 +:4]), // Templated + .i59 (in[59 +:4]), // Templated + .i60 (in[60 +:4]), // Templated + .i61 (in[61 +:4]), // Templated + .i62 (in[62 +:4]), // Templated + .i63 (in[63 +:4]), // Templated + .i64 (in[64 +:4]), // Templated + .i65 (in[65 +:4]), // Templated + .i66 (in[66 +:4]), // Templated + .i67 (in[67 +:4]), // Templated + .i68 (in[68 +:4]), // Templated + .i69 (in[69 +:4]), // Templated + .i70 (in[70 +:4]), // Templated + .i71 (in[71 +:4]), // Templated + .i72 (in[72 +:4]), // Templated + .i73 (in[73 +:4]), // Templated + .i74 (in[74 +:4]), // Templated + .i75 (in[75 +:4]), // Templated + .i76 (in[76 +:4]), // Templated + .i77 (in[77 +:4]), // Templated + .i78 (in[78 +:4]), // Templated + .i79 (in[79 +:4]), // Templated + .i80 (in[80 +:4]), // Templated + .i81 (in[81 +:4]), // Templated + .i82 (in[82 +:4]), // Templated + .i83 (in[83 +:4]), // Templated + .i84 (in[84 +:4]), // Templated + .i85 (in[85 +:4]), // Templated + .i86 (in[86 +:4]), // Templated + .i87 (in[87 +:4]), // Templated + .i88 (in[88 +:4]), // Templated + .i89 (in[89 +:4]), // Templated + .i90 (in[90 +:4]), // Templated + .i91 (in[91 +:4]), // Templated + .i92 (in[92 +:4]), // Templated + .i93 (in[93 +:4]), // Templated + .i94 (in[94 +:4]), // Templated + .i95 (in[95 +:4]), // Templated + .i96 (in[96 +:4]), // Templated + .i97 (in[97 +:4]), // Templated + .i98 (in[98 +:4]), // Templated + .i99 (in[99 +:4]), // Templated + .i100 (in[100 +:4]), // Templated + .i101 (in[101 +:4]), // Templated + .i102 (in[102 +:4]), // Templated + .i103 (in[103 +:4]), // Templated + .i104 (in[104 +:4]), // Templated + .i105 (in[105 +:4]), // Templated + .i106 (in[106 +:4]), // Templated + .i107 (in[107 +:4]), // Templated + .i108 (in[108 +:4]), // Templated + .i109 (in[109 +:4]), // Templated + .i110 (in[110 +:4]), // Templated + .i111 (in[111 +:4]), // Templated + .i112 (in[112 +:4]), // Templated + .i113 (in[113 +:4]), // Templated + .i114 (in[114 +:4]), // Templated + .i115 (in[115 +:4]), // Templated + .i116 (in[116 +:4]), // Templated + .i117 (in[117 +:4]), // Templated + .i118 (in[118 +:4]), // Templated + .i119 (in[119 +:4]), // Templated + .i120 (in[120 +:4]), // Templated + .i121 (in[121 +:4]), // Templated + .i122 (in[122 +:4]), // Templated + .i123 (in[123 +:4]), // Templated + .i124 (in[124 +:4]), // Templated + .i125 (in[125 +:4]), // Templated + .i126 (in[126 +:4]), // Templated + .i127 (in[127 +:4]), // Templated + .i128 (in[128 +:4]), // Templated + .i129 (in[129 +:4]), // Templated + .i130 (in[130 +:4]), // Templated + .i131 (in[131 +:4]), // Templated + .i132 (in[132 +:4]), // Templated + .i133 (in[133 +:4]), // Templated + .i134 (in[134 +:4]), // Templated + .i135 (in[135 +:4]), // Templated + .i136 (in[136 +:4]), // Templated + .i137 (in[137 +:4]), // Templated + .i138 (in[138 +:4]), // Templated + .i139 (in[139 +:4]), // Templated + .i140 (in[140 +:4]), // Templated + .i141 (in[141 +:4]), // Templated + .i142 (in[142 +:4]), // Templated + .i143 (in[143 +:4]), // Templated + .i144 (in[144 +:4]), // Templated + .i145 (in[145 +:4]), // Templated + .i146 (in[146 +:4]), // Templated + .i147 (in[147 +:4]), // Templated + .i148 (in[148 +:4]), // Templated + .i149 (in[149 +:4]), // Templated + .i150 (in[150 +:4]), // Templated + .i151 (in[151 +:4]), // Templated + .i152 (in[152 +:4]), // Templated + .i153 (in[153 +:4]), // Templated + .i154 (in[154 +:4]), // Templated + .i155 (in[155 +:4]), // Templated + .i156 (in[156 +:4]), // Templated + .i157 (in[157 +:4]), // Templated + .i158 (in[158 +:4]), // Templated + .i159 (in[159 +:4]), // Templated + .i160 (in[160 +:4]), // Templated + .i161 (in[161 +:4]), // Templated + .i162 (in[162 +:4]), // Templated + .i163 (in[163 +:4]), // Templated + .i164 (in[164 +:4]), // Templated + .i165 (in[165 +:4]), // Templated + .i166 (in[166 +:4]), // Templated + .i167 (in[167 +:4]), // Templated + .i168 (in[168 +:4]), // Templated + .i169 (in[169 +:4]), // Templated + .i170 (in[170 +:4]), // Templated + .i171 (in[171 +:4]), // Templated + .i172 (in[172 +:4]), // Templated + .i173 (in[173 +:4]), // Templated + .i174 (in[174 +:4]), // Templated + .i175 (in[175 +:4]), // Templated + .i176 (in[176 +:4]), // Templated + .i177 (in[177 +:4]), // Templated + .i178 (in[178 +:4]), // Templated + .i179 (in[179 +:4]), // Templated + .i180 (in[180 +:4]), // Templated + .i181 (in[181 +:4]), // Templated + .i182 (in[182 +:4]), // Templated + .i183 (in[183 +:4]), // Templated + .i184 (in[184 +:4]), // Templated + .i185 (in[185 +:4]), // Templated + .i186 (in[186 +:4]), // Templated + .i187 (in[187 +:4]), // Templated + .i188 (in[188 +:4]), // Templated + .i189 (in[189 +:4]), // Templated + .i190 (in[190 +:4]), // Templated + .i191 (in[191 +:4]), // Templated + .i192 (in[192 +:4]), // Templated + .i193 (in[193 +:4]), // Templated + .i194 (in[194 +:4]), // Templated + .i195 (in[195 +:4]), // Templated + .i196 (in[196 +:4]), // Templated + .i197 (in[197 +:4]), // Templated + .i198 (in[198 +:4]), // Templated + .i199 (in[199 +:4]), // Templated + .i200 (in[200 +:4]), // Templated + .i201 (in[201 +:4]), // Templated + .i202 (in[202 +:4]), // Templated + .i203 (in[203 +:4]), // Templated + .i204 (in[204 +:4]), // Templated + .i205 (in[205 +:4]), // Templated + .i206 (in[206 +:4]), // Templated + .i207 (in[207 +:4]), // Templated + .i208 (in[208 +:4]), // Templated + .i209 (in[209 +:4]), // Templated + .i210 (in[210 +:4]), // Templated + .i211 (in[211 +:4]), // Templated + .i212 (in[212 +:4]), // Templated + .i213 (in[213 +:4]), // Templated + .i214 (in[214 +:4]), // Templated + .i215 (in[215 +:4]), // Templated + .i216 (in[216 +:4]), // Templated + .i217 (in[217 +:4]), // Templated + .i218 (in[218 +:4]), // Templated + .i219 (in[219 +:4]), // Templated + .i220 (in[220 +:4]), // Templated + .i221 (in[221 +:4]), // Templated + .i222 (in[222 +:4]), // Templated + .i223 (in[223 +:4]), // Templated + .i224 (in[224 +:4]), // Templated + .i225 (in[225 +:4]), // Templated + .i226 (in[226 +:4]), // Templated + .i227 (in[227 +:4]), // Templated + .i228 (in[228 +:4]), // Templated + .i229 (in[229 +:4]), // Templated + .i230 (in[230 +:4]), // Templated + .i231 (in[231 +:4]), // Templated + .i232 (in[232 +:4]), // Templated + .i233 (in[233 +:4]), // Templated + .i234 (in[234 +:4]), // Templated + .i235 (in[235 +:4]), // Templated + .i236 (in[236 +:4]), // Templated + .i237 (in[237 +:4]), // Templated + .i238 (in[238 +:4]), // Templated + .i239 (in[239 +:4]), // Templated + .i240 (in[240 +:4]), // Templated + .i241 (in[241 +:4]), // Templated + .i242 (in[242 +:4]), // Templated + .i243 (in[243 +:4]), // Templated + .i244 (in[244 +:4]), // Templated + .i245 (in[245 +:4]), // Templated + .i246 (in[246 +:4]), // Templated + .i247 (in[247 +:4]), // Templated + .i248 (in[248 +:4]), // Templated + .i249 (in[249 +:4]), // Templated + .i250 (in[250 +:4]), // Templated + .i251 (in[251 +:4]), // Templated + .i252 (in[252 +:4]), // Templated + .i253 (in[253 +:4]), // Templated + .i254 (in[254 +:4]), // Templated + .i255 (in[255 +:4])); // Templated // Aggregate outputs into a single result vector wire [63:0] result = {60'h0, out}; @@ -304,20 +304,20 @@ module t (/*AUTOARG*/ crc <= {crc[62:0], crc[63] ^ crc[2] ^ crc[0]}; sum <= result ^ {sum[62:0], sum[63] ^ sum[2] ^ sum[0]}; if (cyc==0) begin - // Setup - crc <= 64'h5aef0c8d_d70a4497; + // Setup + crc <= 64'h5aef0c8d_d70a4497; end else if (cyc<10) begin - sum <= 64'h0; + sum <= 64'h0; end else if (cyc<90) begin end else if (cyc==99) begin - $write("[%0t] cyc==%0d crc=%x sum=%x\n", $time, cyc, crc, sum); - if (crc !== 64'hc77bb9b3784ea091) $stop; - if (sum !== `EXPECTED_SUM) $stop; - $write("*-* All Finished *-*\n"); - $finish; + $write("[%0t] cyc==%0d crc=%x sum=%x\n", $time, cyc, crc, sum); + if (crc !== 64'hc77bb9b3784ea091) $stop; + if (sum !== `EXPECTED_SUM) $stop; + $write("*-* All Finished *-*\n"); + $finish; end end diff --git a/test_regress/t/t_math_const.v b/test_regress/t/t_math_const.v index 8580a714c..79b0b65fc 100644 --- a/test_regress/t/t_math_const.v +++ b/test_regress/t/t_math_const.v @@ -24,11 +24,11 @@ module t (/*AUTOARG*/ reg [31:0] win; // Test casting is proper on narrow->wide->narrow conversions // verilator lint_off WIDTH - wire [49:0] wider = ({18'h0, win} | (1'b1<<32)) - 50'h111; - wire [31:0] wider2 = ({win} | (1'b1<<32)) - 50'd111; + wire [49:0] wider = ({18'h0, win} | (1'b1<<32)) - 50'h111; + wire [31:0] wider2 = ({win} | (1'b1<<32)) - 50'd111; // verilator lint_on WIDTH - wire [31:0] narrow = wider[31:0]; - wire [31:0] narrow2 = wider2[31:0]; + wire [31:0] narrow = wider[31:0]; + wire [31:0] narrow2 = wider2[31:0]; // surefire lint_off ASWEMB // surefire lint_off ASWCMB @@ -39,105 +39,105 @@ module t (/*AUTOARG*/ integer cyc; initial cyc=1; always @ (posedge clk) begin if (cyc!=0) begin - cyc <= cyc + 1; - if (cyc==1) begin - $write("[%0t] t_const: Running\n", $time); + cyc <= cyc + 1; + if (cyc==1) begin + $write("[%0t] t_const: Running\n", $time); - con1 = 4_0'h1000_0010; // Odd but legal _ in width - con2 = 40'h10_0000_0010; - con3 = con1 + 40'h10_1100_0101; - if (con1[31:0]!== 32'h1000_0010 || con1[39:32]!==0) $stop; - $display("%x %x %x\n", con2, con2[31:0], con2[39:32]); - if (con2[31:0]!== 32'h10 || con2[39:32]!==8'h10) $stop; - if (con3[31:0]!==32'h2100_0111 || con3[39:32]!==8'h10) $stop; + con1 = 4_0'h1000_0010; // Odd but legal _ in width + con2 = 40'h10_0000_0010; + con3 = con1 + 40'h10_1100_0101; + if (con1[31:0]!== 32'h1000_0010 || con1[39:32]!==0) $stop; + $display("%x %x %x\n", con2, con2[31:0], con2[39:32]); + if (con2[31:0]!== 32'h10 || con2[39:32]!==8'h10) $stop; + if (con3[31:0]!==32'h2100_0111 || con3[39:32]!==8'h10) $stop; - // verilator lint_off WIDTH - con1 = 10'h10 + 40'h80_1100_0131; - // verilator lint_on WIDTH - con2 = 40'h80_0000_0000 + 40'h13_7543_0107; - if (con1[31:0]!== 32'h1100_0141 || con1[39:32]!==8'h80) $stop; - if (con2[31:0]!== 32'h7543_0107 || con2[39:32]!==8'h93) $stop; + // verilator lint_off WIDTH + con1 = 10'h10 + 40'h80_1100_0131; + // verilator lint_on WIDTH + con2 = 40'h80_0000_0000 + 40'h13_7543_0107; + if (con1[31:0]!== 32'h1100_0141 || con1[39:32]!==8'h80) $stop; + if (con2[31:0]!== 32'h7543_0107 || con2[39:32]!==8'h93) $stop; - // verilator lint_off WIDTH + // verilator lint_off WIDTH conw3 = 94'h000a_5010_4020_3030_2040_1050; - // verilator lint_on WIDTH - if (conw3[31:00]!== 32'h2040_1050 || - conw3[63:32]!== 32'h4020_3030 || - conw3[95:64]!== 32'h000a_5010 || - conw3[128:96]!==33'h0) $stop; - $display("%x... %x\n", conw3[15:0], ~| conw3[15:0]); - if ((~| conw3[15:0]) !== 1'h0) $stop; - if ((~& conw3[15:0]) !== 1'h1) $stop; + // verilator lint_on WIDTH + if (conw3[31:00]!== 32'h2040_1050 || + conw3[63:32]!== 32'h4020_3030 || + conw3[95:64]!== 32'h000a_5010 || + conw3[128:96]!==33'h0) $stop; + $display("%x... %x\n", conw3[15:0], ~| conw3[15:0]); + if ((~| conw3[15:0]) !== 1'h0) $stop; + if ((~& conw3[15:0]) !== 1'h1) $stop; - // verilator lint_off WIDTH + // verilator lint_off WIDTH conw4 = 112'h7010_602a_5030_4040_3050_2060_1070; - // verilator lint_on WIDTH - if (conw4[31:00]!== 32'h2060_1070 || - conw4[63:32]!== 32'h4040_3050 || - conw4[95:64]!== 32'h602a_5030 || - conw4[127:96]!==32'h7010) $stop; + // verilator lint_on WIDTH + if (conw4[31:00]!== 32'h2060_1070 || + conw4[63:32]!== 32'h4040_3050 || + conw4[95:64]!== 32'h602a_5030 || + conw4[127:96]!==32'h7010) $stop; // conw4 = 144'h7000_7000_7010_602a_5030_4040_3050_2060_1070; - w32 = 12; - win <= 12; - if ((32'hffff0000 >> w32) != 32'h 000ffff0) $stop; + w32 = 12; + win <= 12; + if ((32'hffff0000 >> w32) != 32'h 000ffff0) $stop; - con__ascii = "abcdefghijklmnop"; - if ( con__ascii !== {"abcd","efgh","ijkl","mnop"}) $stop; - con__ascii = "abcdefghijklm"; - if ( con__ascii !== {24'h0,"a","bcde","fghi","jklm"}) $stop; + con__ascii = "abcdefghijklmnop"; + if ( con__ascii !== {"abcd","efgh","ijkl","mnop"}) $stop; + con__ascii = "abcdefghijklm"; + if ( con__ascii !== {24'h0,"a","bcde","fghi","jklm"}) $stop; - if ( 3'dx !== 3'hx) $stop; + if ( 3'dx !== 3'hx) $stop; - // Wide decimal - if ( 94'd12345678901234567890123456789 != 94'h27e41b3246bec9b16e398115) $stop; - if (-94'sd123456789012345678901234567 != 94'h3f99e1020ea70d57d360b479) $stop; + // Wide decimal + if ( 94'd12345678901234567890123456789 != 94'h27e41b3246bec9b16e398115) $stop; + if (-94'sd123456789012345678901234567 != 94'h3f99e1020ea70d57d360b479) $stop; - // Increments - w32 = 12; w32++; if (w32 != 13) $stop; - w32 = 12; ++w32; if (w32 != 13) $stop; - w32 = 12; w32--; if (w32 != 11) $stop; - w32 = 12; --w32; if (w32 != 11) $stop; - w32 = 12; w32 += 2; if (w32 != 14) $stop; - w32 = 12; w32 -= 2; if (w32 != 10) $stop; - w32 = 12; w32 *= 2; if (w32 != 24) $stop; - w32 = 12; w32 /= 2; if (w32 != 6) $stop; - w32 = 12; w32 &= 6; if (w32 != 4) $stop; - w32 = 12; w32 |= 15; if (w32 != 15) $stop; - w32 = 12; w32 ^= 15; if (w32 != 3) $stop; - w32 = 12; w32 >>= 1; if (w32 != 6) $stop; - w32 = 12; w32 >>>= 1; if (w32 != 6) $stop; - w32 = 12; w32 <<= 1; if (w32 != 24) $stop; - w32 = 12; w32 %= 5; if (w32 != 2) $stop; + // Increments + w32 = 12; w32++; if (w32 != 13) $stop; + w32 = 12; ++w32; if (w32 != 13) $stop; + w32 = 12; w32--; if (w32 != 11) $stop; + w32 = 12; --w32; if (w32 != 11) $stop; + w32 = 12; w32 += 2; if (w32 != 14) $stop; + w32 = 12; w32 -= 2; if (w32 != 10) $stop; + w32 = 12; w32 *= 2; if (w32 != 24) $stop; + w32 = 12; w32 /= 2; if (w32 != 6) $stop; + w32 = 12; w32 &= 6; if (w32 != 4) $stop; + w32 = 12; w32 |= 15; if (w32 != 15) $stop; + w32 = 12; w32 ^= 15; if (w32 != 3) $stop; + w32 = 12; w32 >>= 1; if (w32 != 6) $stop; + w32 = 12; w32 >>>= 1; if (w32 != 6) $stop; + w32 = 12; w32 <<= 1; if (w32 != 24) $stop; + w32 = 12; w32 %= 5; if (w32 != 2) $stop; - // Increments - v32[1] = 12; v32[1]++; if (v32[1] != 13) $stop; - v32[1] = 12; ++v32[1]; if (v32[1] != 13) $stop; - v32[1] = 12; v32[1]--; if (v32[1] != 11) $stop; - v32[1] = 12; --v32[1]; if (v32[1] != 11) $stop; - v32[1] = 12; v32[1] += 2; if (v32[1] != 14) $stop; - v32[1] = 12; v32[1] -= 2; if (v32[1] != 10) $stop; - v32[1] = 12; v32[1] *= 2; if (v32[1] != 24) $stop; - v32[1] = 12; v32[1] /= 2; if (v32[1] != 6) $stop; - v32[1] = 12; v32[1] &= 6; if (v32[1] != 4) $stop; - v32[1] = 12; v32[1] |= 15; if (v32[1] != 15) $stop; - v32[1] = 12; v32[1] ^= 15; if (v32[1] != 3) $stop; - v32[1] = 12; v32[1] >>= 1; if (v32[1] != 6) $stop; - v32[1] = 12; v32[1] <<= 1; if (v32[1] != 24) $stop; - end - if (cyc==2) begin - win <= 32'h123123; - if (narrow !== 32'hfffffefb) $stop; - if (narrow2 !== 32'hffffff9d) $stop; - end - if (cyc==3) begin - if (narrow !== 32'h00123012) $stop; - if (narrow2 !== 32'h001230b4) $stop; - end - if (cyc==10) begin - $write("*-* All Finished *-*\n"); - $finish; - end + // Increments + v32[1] = 12; v32[1]++; if (v32[1] != 13) $stop; + v32[1] = 12; ++v32[1]; if (v32[1] != 13) $stop; + v32[1] = 12; v32[1]--; if (v32[1] != 11) $stop; + v32[1] = 12; --v32[1]; if (v32[1] != 11) $stop; + v32[1] = 12; v32[1] += 2; if (v32[1] != 14) $stop; + v32[1] = 12; v32[1] -= 2; if (v32[1] != 10) $stop; + v32[1] = 12; v32[1] *= 2; if (v32[1] != 24) $stop; + v32[1] = 12; v32[1] /= 2; if (v32[1] != 6) $stop; + v32[1] = 12; v32[1] &= 6; if (v32[1] != 4) $stop; + v32[1] = 12; v32[1] |= 15; if (v32[1] != 15) $stop; + v32[1] = 12; v32[1] ^= 15; if (v32[1] != 3) $stop; + v32[1] = 12; v32[1] >>= 1; if (v32[1] != 6) $stop; + v32[1] = 12; v32[1] <<= 1; if (v32[1] != 24) $stop; + end + if (cyc==2) begin + win <= 32'h123123; + if (narrow !== 32'hfffffefb) $stop; + if (narrow2 !== 32'hffffff9d) $stop; + end + if (cyc==3) begin + if (narrow !== 32'h00123012) $stop; + if (narrow2 !== 32'h001230b4) $stop; + end + if (cyc==10) begin + $write("*-* All Finished *-*\n"); + $finish; + end end end diff --git a/test_regress/t/t_math_div.v b/test_regress/t/t_math_div.v index 9c023a1e5..644f06939 100644 --- a/test_regress/t/t_math_div.v +++ b/test_regress/t/t_math_div.v @@ -11,16 +11,16 @@ module t (/*AUTOARG*/ input clk; - reg [255:0] a; - reg [60:0] divisor; - reg [60:0] qq; - reg [60:0] rq; - reg [60:0] qq4; - reg [60:0] rq4; - reg [60:0] qq5; - reg [60:0] rq5; - reg signed [60:0] qqs; - reg signed [60:0] rqs; + reg [255:0] a; + reg [60:0] divisor; + reg [60:0] qq; + reg [60:0] rq; + reg [60:0] qq4; + reg [60:0] rq4; + reg [60:0] qq5; + reg [60:0] rq5; + reg signed [60:0] qqs; + reg signed [60:0] rqs; always @* begin qq = a[60:0] / divisor; @@ -36,80 +36,80 @@ module t (/*AUTOARG*/ integer cyc; initial cyc=1; always @ (posedge clk) begin if (cyc!=0) begin - cyc <= cyc + 1; - //$write("%d: %x %x %x %x\n", cyc, qq, rq, qqs, rqs); - if (cyc==1) begin - a <= 256'hed388e646c843d35de489bab2413d77045e0eb7642b148537491f3da147e7f26; - divisor <= 61'h12371; - a[60] <= 1'b0; divisor[60] <= 1'b0; // Unsigned - end - if (cyc > 1) begin - if (qq4 != {2'b0, a[60:2]}) $stop; - if (rq4 != {59'h0, a[1:0]}) $stop; - end - if (cyc==2) begin - a <= 256'h0e17c88f3d5fe51a982646c8e2bd68c3e236ddfddddbdad20a48e039c9f395b8; - divisor <= 61'h1238123771; - a[60] <= 1'b0; divisor[60] <= 1'b0; // Unsigned - if (qq!==61'h00000403ad81c0da) $stop; - if (rq!==61'h00000000000090ec) $stop; - if (qqs!==61'h00000403ad81c0da) $stop; - if (rqs!==61'h00000000000090ec) $stop; - if (qq4 != 61'h01247cf6851f9fc9) $stop; - if (rq4 != 61'h0000000000000002) $stop; - end - if (cyc==3) begin - a <= 256'h0e17c88f00d5fe51a982646c8002bd68c3e236ddfd00ddbdad20a48e00f395b8; - divisor <= 61'hf1b; - a[60] <= 1'b1; divisor[60] <= 1'b0; // Signed - if (qq!==61'h000000000090832e) $stop; - if (rq!==61'h0000000334becc6a) $stop; - if (qqs!==61'h000000000090832e) $stop; - if (rqs!==61'h0000000334becc6a) $stop; - if (qq4 != 61'h0292380e727ce56e) $stop; - if (rq4 != 61'h0000000000000000) $stop; - end - if (cyc==4) begin - a[60] <= 1'b0; divisor[60] <= 1'b1; // Signed - if (qq!==61'h0001eda37cca1be8) $stop; - if (rq!==61'h0000000000000c40) $stop; - if (qqs!==61'h1fffcf5187c76510) $stop; - if (rqs!==61'h1ffffffffffffd08) $stop; - if (qq4 != 61'h07482923803ce56e) $stop; - if (rq4 != 61'h0000000000000000) $stop; - end - if (cyc==5) begin - a[60] <= 1'b1; divisor[60] <= 1'b1; // Signed - if (qq!==61'h0000000000000000) $stop; - if (rq!==61'h0d20a48e00f395b8) $stop; - if (qqs!==61'h0000000000000000) $stop; - if (rqs!==61'h0d20a48e00f395b8) $stop; - end - if (cyc==6) begin - if (qq!==61'h0000000000000001) $stop; - if (rq!==61'h0d20a48e00f3869d) $stop; - if (qqs!==61'h0000000000000000) $stop; - if (rqs!==61'h1d20a48e00f395b8) $stop; - end - // Div by zero - if (cyc==9) begin - divisor <= 61'd0; - end - if (cyc==10) begin + cyc <= cyc + 1; + //$write("%d: %x %x %x %x\n", cyc, qq, rq, qqs, rqs); + if (cyc==1) begin + a <= 256'hed388e646c843d35de489bab2413d77045e0eb7642b148537491f3da147e7f26; + divisor <= 61'h12371; + a[60] <= 1'b0; divisor[60] <= 1'b0; // Unsigned + end + if (cyc > 1) begin + if (qq4 != {2'b0, a[60:2]}) $stop; + if (rq4 != {59'h0, a[1:0]}) $stop; + end + if (cyc==2) begin + a <= 256'h0e17c88f3d5fe51a982646c8e2bd68c3e236ddfddddbdad20a48e039c9f395b8; + divisor <= 61'h1238123771; + a[60] <= 1'b0; divisor[60] <= 1'b0; // Unsigned + if (qq!==61'h00000403ad81c0da) $stop; + if (rq!==61'h00000000000090ec) $stop; + if (qqs!==61'h00000403ad81c0da) $stop; + if (rqs!==61'h00000000000090ec) $stop; + if (qq4 != 61'h01247cf6851f9fc9) $stop; + if (rq4 != 61'h0000000000000002) $stop; + end + if (cyc==3) begin + a <= 256'h0e17c88f00d5fe51a982646c8002bd68c3e236ddfd00ddbdad20a48e00f395b8; + divisor <= 61'hf1b; + a[60] <= 1'b1; divisor[60] <= 1'b0; // Signed + if (qq!==61'h000000000090832e) $stop; + if (rq!==61'h0000000334becc6a) $stop; + if (qqs!==61'h000000000090832e) $stop; + if (rqs!==61'h0000000334becc6a) $stop; + if (qq4 != 61'h0292380e727ce56e) $stop; + if (rq4 != 61'h0000000000000000) $stop; + end + if (cyc==4) begin + a[60] <= 1'b0; divisor[60] <= 1'b1; // Signed + if (qq!==61'h0001eda37cca1be8) $stop; + if (rq!==61'h0000000000000c40) $stop; + if (qqs!==61'h1fffcf5187c76510) $stop; + if (rqs!==61'h1ffffffffffffd08) $stop; + if (qq4 != 61'h07482923803ce56e) $stop; + if (rq4 != 61'h0000000000000000) $stop; + end + if (cyc==5) begin + a[60] <= 1'b1; divisor[60] <= 1'b1; // Signed + if (qq!==61'h0000000000000000) $stop; + if (rq!==61'h0d20a48e00f395b8) $stop; + if (qqs!==61'h0000000000000000) $stop; + if (rqs!==61'h0d20a48e00f395b8) $stop; + end + if (cyc==6) begin + if (qq!==61'h0000000000000001) $stop; + if (rq!==61'h0d20a48e00f3869d) $stop; + if (qqs!==61'h0000000000000000) $stop; + if (rqs!==61'h1d20a48e00f395b8) $stop; + end + // Div by zero + if (cyc==9) begin + divisor <= 61'd0; + end + if (cyc==10) begin `ifdef verilator - if (qq !== {61{1'b0}}) $stop; - if (rq !== {61{1'b0}}) $stop; + if (qq !== {61{1'b0}}) $stop; + if (rq !== {61{1'b0}}) $stop; `else - if (qq !== {61{1'bx}}) $stop; - if (rq !== {61{1'bx}}) $stop; + if (qq !== {61{1'bx}}) $stop; + if (rq !== {61{1'bx}}) $stop; `endif - if ({16{1'bx}} !== 16'd1/16'd0) $stop; // No div by zero errors - if ({16{1'bx}} !== 16'd1%16'd0) $stop; // No div by zero errors - end - if (cyc==19) begin - $write("*-* All Finished *-*\n"); - $finish; - end + if ({16{1'bx}} !== 16'd1/16'd0) $stop; // No div by zero errors + if ({16{1'bx}} !== 16'd1%16'd0) $stop; // No div by zero errors + end + if (cyc==19) begin + $write("*-* All Finished *-*\n"); + $finish; + end end end endmodule diff --git a/test_regress/t/t_math_divw.v b/test_regress/t/t_math_divw.v index 0bb952bd7..d85b3d7ff 100644 --- a/test_regress/t/t_math_divw.v +++ b/test_regress/t/t_math_divw.v @@ -18,57 +18,57 @@ module t (/*AUTOARG*/ reg bad; initial begin bad=0; - c96(96'h0_0000_0000_0000_0000, 96'h8_8888_8888_8888_8888, 96'h0_0000_0000_0000_0000, 96'h0); - c96(96'h8_8888_8888_8888_8888, 96'h0_0000_0000_0000_0000, 96'h0_0000_0000_0000_0000, 96'h0); - c96(96'h8_8888_8888_8888_8888, 96'h0_0000_0000_0000_0002, 96'h4_4444_4444_4444_4444, 96'h0); - c96(96'h8_8888_8888_8888_8888, 96'h0_2000_0000_0000_0000, 96'h0_0000_0000_0000_0044, 96'h0_0888_8888_8888_8888); - c96(96'h8_8888_8888_8888_8888, 96'h8_8888_8888_8888_8888, 96'h0_0000_0000_0000_0001, 96'h0); - c96(96'h8_8888_8888_8888_8888, 96'h8_8888_8888_8888_8889, 96'h0_0000_0000_0000_0000, 96'h8_8888_8888_8888_8888); - c96(96'h1_0000_0000_8eba_434a, 96'h0_0000_0000_0000_0001, 96'h1_0000_0000_8eba_434a, 96'h0); + c96(96'h0_0000_0000_0000_0000, 96'h8_8888_8888_8888_8888, 96'h0_0000_0000_0000_0000, 96'h0); + c96(96'h8_8888_8888_8888_8888, 96'h0_0000_0000_0000_0000, 96'h0_0000_0000_0000_0000, 96'h0); + c96(96'h8_8888_8888_8888_8888, 96'h0_0000_0000_0000_0002, 96'h4_4444_4444_4444_4444, 96'h0); + c96(96'h8_8888_8888_8888_8888, 96'h0_2000_0000_0000_0000, 96'h0_0000_0000_0000_0044, 96'h0_0888_8888_8888_8888); + c96(96'h8_8888_8888_8888_8888, 96'h8_8888_8888_8888_8888, 96'h0_0000_0000_0000_0001, 96'h0); + c96(96'h8_8888_8888_8888_8888, 96'h8_8888_8888_8888_8889, 96'h0_0000_0000_0000_0000, 96'h8_8888_8888_8888_8888); + c96(96'h1_0000_0000_8eba_434a, 96'h0_0000_0000_0000_0001, 96'h1_0000_0000_8eba_434a, 96'h0); - c96(96'h0003, 96'h0002, 96'h0001, 96'h0001); - c96(96'h0003, 96'h0003, 96'h0001, 96'h0000); - c96(96'h0003, 96'h0004, 96'h0000, 96'h0003); - c96(96'h0000, 96'hffff, 96'h0000, 96'h0000); - c96(96'hffff, 96'h0001, 96'hffff, 96'h0000); - c96(96'hffff, 96'hffff, 96'h0001, 96'h0000); - c96(96'hffff, 96'h0003, 96'h5555, 96'h0000); - c96(96'hffff_ffff, 96'h0001, 96'hffff_ffff, 96'h0000); - c96(96'hffff_ffff, 96'hffff, 96'h0001_0001, 96'h0000); - c96(96'hfffe_ffff, 96'hffff, 96'h0000_ffff, 96'hfffe); - c96(96'h1234_5678, 96'h9abc, 96'h0000_1e1e, 96'h2c70); - c96(96'h0000_0000, 96'h0001_0000, 96'h0000, 96'h0000_0000); - c96(96'h0007_0000, 96'h0003_0000, 96'h0002, 96'h0001_0000); - c96(96'h0007_0005, 96'h0003_0000, 96'h0002, 96'h0001_0005); - c96(96'h0006_0000, 96'h0002_0000, 96'h0003, 96'h0000_0000); - c96(96'h8000_0001, 96'h4000_7000, 96'h0001, 96'h3fff_9001); - c96(96'hbcde_789a, 96'hbcde_789a, 96'h0001, 96'h0000_0000); - c96(96'hbcde_789b, 96'hbcde_789a, 96'h0001, 96'h0000_0001); - c96(96'hbcde_7899, 96'hbcde_789a, 96'h0000, 96'hbcde_7899); - c96(96'hffff_ffff, 96'hffff_ffff, 96'h0001, 96'h0000_0000); - c96(96'hffff_ffff, 96'h0001_0000, 96'hffff, 96'h0000_ffff); - c96(96'h0123_4567_89ab, 96'h0001_0000, 96'h0123_4567, 96'h0000_89ab); - c96(96'h8000_fffe_0000, 96'h8000_ffff, 96'h0000_ffff, 96'h7fff_ffff); - c96(96'h8000_0000_0003, 96'h2000_0000_0001, 96'h0003, 96'h2000_0000_0000); + c96(96'h0003, 96'h0002, 96'h0001, 96'h0001); + c96(96'h0003, 96'h0003, 96'h0001, 96'h0000); + c96(96'h0003, 96'h0004, 96'h0000, 96'h0003); + c96(96'h0000, 96'hffff, 96'h0000, 96'h0000); + c96(96'hffff, 96'h0001, 96'hffff, 96'h0000); + c96(96'hffff, 96'hffff, 96'h0001, 96'h0000); + c96(96'hffff, 96'h0003, 96'h5555, 96'h0000); + c96(96'hffff_ffff, 96'h0001, 96'hffff_ffff, 96'h0000); + c96(96'hffff_ffff, 96'hffff, 96'h0001_0001, 96'h0000); + c96(96'hfffe_ffff, 96'hffff, 96'h0000_ffff, 96'hfffe); + c96(96'h1234_5678, 96'h9abc, 96'h0000_1e1e, 96'h2c70); + c96(96'h0000_0000, 96'h0001_0000, 96'h0000, 96'h0000_0000); + c96(96'h0007_0000, 96'h0003_0000, 96'h0002, 96'h0001_0000); + c96(96'h0007_0005, 96'h0003_0000, 96'h0002, 96'h0001_0005); + c96(96'h0006_0000, 96'h0002_0000, 96'h0003, 96'h0000_0000); + c96(96'h8000_0001, 96'h4000_7000, 96'h0001, 96'h3fff_9001); + c96(96'hbcde_789a, 96'hbcde_789a, 96'h0001, 96'h0000_0000); + c96(96'hbcde_789b, 96'hbcde_789a, 96'h0001, 96'h0000_0001); + c96(96'hbcde_7899, 96'hbcde_789a, 96'h0000, 96'hbcde_7899); + c96(96'hffff_ffff, 96'hffff_ffff, 96'h0001, 96'h0000_0000); + c96(96'hffff_ffff, 96'h0001_0000, 96'hffff, 96'h0000_ffff); + c96(96'h0123_4567_89ab, 96'h0001_0000, 96'h0123_4567, 96'h0000_89ab); + c96(96'h8000_fffe_0000, 96'h8000_ffff, 96'h0000_ffff, 96'h7fff_ffff); + c96(96'h8000_0000_0003, 96'h2000_0000_0001, 96'h0003, 96'h2000_0000_0000); - c96(96'hffff_ffff_0000_0000, 96'h0001_0000_0000, 96'hffff_ffff, 96'h0000_0000_0000); - c96(96'hffff_ffff_0000_0000, 96'hffff_0000_0000, 96'h0001_0001, 96'h0000_0000_0000); - c96(96'hfffe_ffff_0000_0000, 96'hffff_0000_0000, 96'h0000_ffff, 96'hfffe_0000_0000); - c96(96'h1234_5678_0000_0000, 96'h9abc_0000_0000, 96'h0000_1e1e, 96'h2c70_0000_0000); + c96(96'hffff_ffff_0000_0000, 96'h0001_0000_0000, 96'hffff_ffff, 96'h0000_0000_0000); + c96(96'hffff_ffff_0000_0000, 96'hffff_0000_0000, 96'h0001_0001, 96'h0000_0000_0000); + c96(96'hfffe_ffff_0000_0000, 96'hffff_0000_0000, 96'h0000_ffff, 96'hfffe_0000_0000); + c96(96'h1234_5678_0000_0000, 96'h9abc_0000_0000, 96'h0000_1e1e, 96'h2c70_0000_0000); - c96(96'h0000_0000_0000_0000, 96'h0001_0000_0000_0000, 96'h0000, 96'h0000_0000_0000_0000); - c96(96'h0007_0000_0000_0000, 96'h0003_0000_0000_0000, 96'h0002, 96'h0001_0000_0000_0000); - c96(96'h0007_0005_0000_0000, 96'h0003_0000_0000_0000, 96'h0002, 96'h0001_0005_0000_0000); - c96(96'h0006_0000_0000_0000, 96'h0002_0000_0000_0000, 96'h0003, 96'h0000_0000_0000_0000); - c96(96'h8000_0001_0000_0000, 96'h4000_7000_0000_0000, 96'h0001, 96'h3fff_9001_0000_0000); - c96(96'hbcde_789a_0000_0000, 96'hbcde_789a_0000_0000, 96'h0001, 96'h0000_0000_0000_0000); - c96(96'hbcde_789b_0000_0000, 96'hbcde_789a_0000_0000, 96'h0001, 96'h0000_0001_0000_0000); - c96(96'hbcde_7899_0000_0000, 96'hbcde_789a_0000_0000, 96'h0000, 96'hbcde_7899_0000_0000); - c96(96'hffff_ffff_0000_0000, 96'hffff_ffff_0000_0000, 96'h0001, 96'h0000_0000_0000_0000); - c96(96'hffff_ffff_0000_0000, 96'h0001_0000_0000_0000, 96'hffff, 96'h0000_ffff_0000_0000); - c96(96'h7fff_8000_0000_0000, 96'h8000_0000_0001, 96'h0000_fffe, 96'h7fff_ffff_0002); - c96(96'h8000_0000_fffe_0000, 96'h8000_0000_ffff, 96'h0000_ffff, 96'h7fff_ffff_ffff); - c96(96'h0008_8888_8888_8888_8888, 96'h0002_0000_0000_0000, 96'h0004_4444, 96'h0000_8888_8888_8888); + c96(96'h0000_0000_0000_0000, 96'h0001_0000_0000_0000, 96'h0000, 96'h0000_0000_0000_0000); + c96(96'h0007_0000_0000_0000, 96'h0003_0000_0000_0000, 96'h0002, 96'h0001_0000_0000_0000); + c96(96'h0007_0005_0000_0000, 96'h0003_0000_0000_0000, 96'h0002, 96'h0001_0005_0000_0000); + c96(96'h0006_0000_0000_0000, 96'h0002_0000_0000_0000, 96'h0003, 96'h0000_0000_0000_0000); + c96(96'h8000_0001_0000_0000, 96'h4000_7000_0000_0000, 96'h0001, 96'h3fff_9001_0000_0000); + c96(96'hbcde_789a_0000_0000, 96'hbcde_789a_0000_0000, 96'h0001, 96'h0000_0000_0000_0000); + c96(96'hbcde_789b_0000_0000, 96'hbcde_789a_0000_0000, 96'h0001, 96'h0000_0001_0000_0000); + c96(96'hbcde_7899_0000_0000, 96'hbcde_789a_0000_0000, 96'h0000, 96'hbcde_7899_0000_0000); + c96(96'hffff_ffff_0000_0000, 96'hffff_ffff_0000_0000, 96'h0001, 96'h0000_0000_0000_0000); + c96(96'hffff_ffff_0000_0000, 96'h0001_0000_0000_0000, 96'hffff, 96'h0000_ffff_0000_0000); + c96(96'h7fff_8000_0000_0000, 96'h8000_0000_0001, 96'h0000_fffe, 96'h7fff_ffff_0002); + c96(96'h8000_0000_fffe_0000, 96'h8000_0000_ffff, 96'h0000_ffff, 96'h7fff_ffff_ffff); + c96(96'h0008_8888_8888_8888_8888, 96'h0002_0000_0000_0000, 96'h0004_4444, 96'h0000_8888_8888_8888); if (bad) $stop; $write("*-* All Finished *-*\n"); @@ -97,21 +97,21 @@ module t (/*AUTOARG*/ gotq = u/v; gotr = u%v; if (gotq != expq && v!=0) begin - bad = 1; + bad = 1; end if (gotr != expr && v!=0) begin - bad = 1; + bad = 1; end if (bad `ifdef TEST_VERBOSE - || 1 + || 1 `endif - ) begin - $write(" %x /u %x = got %x exp %x %% got %x exp %x", u,v,gotq,expq,gotr,expr); - // Test for v=0 to prevent Xs causing grief - if (gotq != expq && v!=0) $write(" BADQ"); - if (gotr != expr && v!=0) $write(" BADR"); - $write("\n"); + ) begin + $write(" %x /u %x = got %x exp %x %% got %x exp %x", u,v,gotq,expq,gotr,expr); + // Test for v=0 to prevent Xs causing grief + if (gotq != expq && v!=0) $write(" BADQ"); + if (gotr != expr && v!=0) $write(" BADR"); + $write("\n"); end endtask @@ -125,21 +125,21 @@ module t (/*AUTOARG*/ gotq = u/v; gotr = u%v; if (gotq != expq && v!=0) begin - bad = 1; + bad = 1; end if (gotr != expr && v!=0) begin - bad = 1; + bad = 1; end if (bad `ifdef TEST_VERBOSE - || 1 + || 1 `endif - ) begin - $write(" %x /s %x = got %x exp %x %% got %x exp %x", u,v,gotq,expq,gotr,expr); - // Test for v=0 to prevent Xs causing grief - if (gotq != expq && v!=0) $write(" BADQ"); - if (gotr != expr && v!=0) $write(" BADR"); - $write("\n"); + ) begin + $write(" %x /s %x = got %x exp %x %% got %x exp %x", u,v,gotq,expq,gotr,expr); + // Test for v=0 to prevent Xs causing grief + if (gotq != expq && v!=0) $write(" BADQ"); + if (gotr != expr && v!=0) $write(" BADR"); + $write("\n"); end endtask diff --git a/test_regress/t/t_math_eq.v b/test_regress/t/t_math_eq.v index 1ab0e9495..c1b5a8ae6 100644 --- a/test_regress/t/t_math_eq.v +++ b/test_regress/t/t_math_eq.v @@ -10,24 +10,24 @@ module t (/*AUTOARG*/ ); input clk; - integer cyc = 0; - reg [63:0] crc; - reg [63:0] sum; + integer cyc = 0; + reg [63:0] crc; + reg [63:0] sum; // Take CRC data and apply to testblock inputs wire [31:0] in = crc[31:0]; /*AUTOWIRE*/ // Beginning of automatic wires (for undeclared instantiated-module outputs) - wire [3:0] out; // From test of Test.v + wire [3:0] out; // From test of Test.v // End of automatics Test test (/*AUTOINST*/ - // Outputs - .out (out[3:0]), - // Inputs - .clk (clk), - .in (in[31:0])); + // Outputs + .out (out[3:0]), + // Inputs + .clk (clk), + .in (in[31:0])); // Aggregate outputs into a single result vector wire [63:0] result = {60'h0, out}; @@ -44,20 +44,20 @@ module t (/*AUTOARG*/ crc <= {crc[62:0], crc[63] ^ crc[2] ^ crc[0]}; sum <= result ^ {sum[62:0], sum[63] ^ sum[2] ^ sum[0]}; if (cyc==0) begin - // Setup - crc <= 64'h5aef0c8d_d70a4497; + // Setup + crc <= 64'h5aef0c8d_d70a4497; end else if (cyc<10) begin - sum <= 64'h0; + sum <= 64'h0; end else if (cyc<90) begin end else if (cyc==99) begin - $write("[%0t] cyc==%0d crc=%x sum=%x\n", $time, cyc, crc, sum); - if (crc !== 64'hc77bb9b3784ea091) $stop; - if (sum !== `EXPECTED_SUM) $stop; - $write("*-* All Finished *-*\n"); - $finish; + $write("[%0t] cyc==%0d crc=%x sum=%x\n", $time, cyc, crc, sum); + if (crc !== 64'hc77bb9b3784ea091) $stop; + if (sum !== `EXPECTED_SUM) $stop; + $write("*-* All Finished *-*\n"); + $finish; end end @@ -74,19 +74,19 @@ module Test (/*AUTOARG*/ input [31:0] in; output [3:0] out; - assign out[0] = in[3:0] ==? 4'b1001; - assign out[1] = in[3:0] !=? 4'b1001; - assign out[2] = in[3:0] ==? 4'bx01x; - assign out[3] = in[3:0] !=? 4'bx01x; + assign out[0] = in[3:0] ==? 4'b1001; + assign out[1] = in[3:0] !=? 4'b1001; + assign out[2] = in[3:0] ==? 4'bx01x; + assign out[3] = in[3:0] !=? 4'bx01x; wire signed [3:0] ins = in[3:0]; wire signed [3:0] outs; - assign outs[0] = ins ==? 4'sb1001; - assign outs[1] = ins !=? 4'sb1001; - assign outs[2] = ins ==? 4'sbx01x; - assign outs[3] = ins !=? 4'sbx01x; + assign outs[0] = ins ==? 4'sb1001; + assign outs[1] = ins !=? 4'sb1001; + assign outs[2] = ins ==? 4'sbx01x; + assign outs[3] = ins !=? 4'sbx01x; always_comb if (out != outs) $stop; diff --git a/test_regress/t/t_math_equal.v b/test_regress/t/t_math_equal.v index 54968a263..dee162e01 100644 --- a/test_regress/t/t_math_equal.v +++ b/test_regress/t/t_math_equal.v @@ -13,14 +13,14 @@ module t (/*AUTOARG*/ integer _mode; - reg _guard1; + reg _guard1; reg [127:0] r_wide0; - reg _guard2; + reg _guard2; wire [63:0] r_wide1; - reg _guard3; - reg _guard4; - reg _guard5; - reg _guard6; + reg _guard3; + reg _guard4; + reg _guard5; + reg _guard6; assign r_wide1 = r_wide0[127:64]; @@ -29,45 +29,45 @@ module t (/*AUTOARG*/ always @ (posedge clk) begin if (_mode==0) begin - $write("[%0t] t_equal: Running\n", $time); - _guard1 <= 0; - _guard2 <= 0; - _guard3 <= 0; - _guard4 <= 0; - _guard5 <= 0; - _guard6 <= 0; + $write("[%0t] t_equal: Running\n", $time); + _guard1 <= 0; + _guard2 <= 0; + _guard3 <= 0; + _guard4 <= 0; + _guard5 <= 0; + _guard6 <= 0; - _mode<=1; - r_wide0 <= {32'h aa111111,32'hbb222222,32'hcc333333,32'hdd444444}; + _mode<=1; + r_wide0 <= {32'h aa111111,32'hbb222222,32'hcc333333,32'hdd444444}; end else if (_mode==1) begin - _mode<=2; - // - if (5'd10 != 5'b1010) $stop; - if (5'd10 != 5'd10) $stop; - if (5'd10 != 5'd1_0) $stop; - if (5'd10 != 5'ha) $stop; - if (5'd10 != 5'o12) $stop; - if (5'd10 != 5'o1_2) $stop; - if (5'd10 != 5'B 1010) $stop; - if (5'd10 != 5'B 10_10) $stop; - if (5'd10 != 5'D10) $stop; - if (5'd10 != 5'H a) $stop; - if (5'd10 != 5 'O 12) $stop; - if (24'h29cbb8 != 24'o12345670) $stop; - if (24'h29__cbb8 != 24'o123456__70) $stop; - if (6'b111xxx !== 6'o7x) $stop; - if (6'b111??? !== 6'o7?) $stop; - if (6'b111zzz !== 6'o7z) $stop; - // - if (r_wide0 !== {32'haa111111,32'hbb222222,32'hcc333333,32'hdd444444}) $stop; - if (r_wide1 !== {32'haa111111,32'hbb222222}) $stop; - if (|{_guard1,_guard2,_guard3,_guard4,_guard5,_guard6}) begin - $write("Guard error %x %x %x %x %x\n",_guard1,_guard2,_guard3,_guard4,_guard5); - $stop; - end - $write("*-* All Finished *-*\n"); - $finish; + _mode<=2; + // + if (5'd10 != 5'b1010) $stop; + if (5'd10 != 5'd10) $stop; + if (5'd10 != 5'd1_0) $stop; + if (5'd10 != 5'ha) $stop; + if (5'd10 != 5'o12) $stop; + if (5'd10 != 5'o1_2) $stop; + if (5'd10 != 5'B 1010) $stop; + if (5'd10 != 5'B 10_10) $stop; + if (5'd10 != 5'D10) $stop; + if (5'd10 != 5'H a) $stop; + if (5'd10 != 5 'O 12) $stop; + if (24'h29cbb8 != 24'o12345670) $stop; + if (24'h29__cbb8 != 24'o123456__70) $stop; + if (6'b111xxx !== 6'o7x) $stop; + if (6'b111??? !== 6'o7?) $stop; + if (6'b111zzz !== 6'o7z) $stop; + // + if (r_wide0 !== {32'haa111111,32'hbb222222,32'hcc333333,32'hdd444444}) $stop; + if (r_wide1 !== {32'haa111111,32'hbb222222}) $stop; + if (|{_guard1,_guard2,_guard3,_guard4,_guard5,_guard6}) begin + $write("Guard error %x %x %x %x %x\n",_guard1,_guard2,_guard3,_guard4,_guard5); + $stop; + end + $write("*-* All Finished *-*\n"); + $finish; end end diff --git a/test_regress/t/t_math_imm.v b/test_regress/t/t_math_imm.v index e5019a4b0..d5884e806 100644 --- a/test_regress/t/t_math_imm.v +++ b/test_regress/t/t_math_imm.v @@ -23,9 +23,9 @@ module t (/*AUTOARG*/ /*AUTOWIRE*/ // Beginning of automatic wires (for undeclared instantiated-module outputs) - wire [63:0] HighLogicImm; // From example of example.v - wire [63:0] LogicImm; // From example of example.v - wire [63:0] LowLogicImm; // From example of example.v + wire [63:0] HighLogicImm; // From example of example.v + wire [63:0] LogicImm; // From example of example.v + wire [63:0] LowLogicImm; // From example of example.v // End of automatics wire [5:0] LowMaskSel_Top = crc[5:0]; @@ -34,43 +34,43 @@ module t (/*AUTOARG*/ wire [5:0] HighMaskSel_Bot = crc[5:0]+{4'b0,crc[7:6]}; example example (/*AUTOINST*/ - // Outputs - .LogicImm (LogicImm[63:0]), - .LowLogicImm (LowLogicImm[63:0]), - .HighLogicImm (HighLogicImm[63:0]), - // Inputs - .LowMaskSel_Top (LowMaskSel_Top[5:0]), - .HighMaskSel_Top (HighMaskSel_Top[5:0]), - .LowMaskSel_Bot (LowMaskSel_Bot[5:0]), - .HighMaskSel_Bot (HighMaskSel_Bot[5:0])); + // Outputs + .LogicImm (LogicImm[63:0]), + .LowLogicImm (LowLogicImm[63:0]), + .HighLogicImm (HighLogicImm[63:0]), + // Inputs + .LowMaskSel_Top (LowMaskSel_Top[5:0]), + .HighMaskSel_Top (HighMaskSel_Top[5:0]), + .LowMaskSel_Bot (LowMaskSel_Bot[5:0]), + .HighMaskSel_Bot (HighMaskSel_Bot[5:0])); always @ (posedge clk) begin cyc <= cyc + 1; crc <= {crc[6:0], ~^ {crc[7],crc[5],crc[4],crc[3]}}; `ifdef TEST_VERBOSE $write("[%0t] cyc==%0d crc=%b %d.%d,%d.%d -> %x.%x -> %x\n", $time, cyc, crc, - LowMaskSel_Top, HighMaskSel_Top, LowMaskSel_Bot, HighMaskSel_Bot, - LowLogicImm, HighLogicImm, LogicImm); + LowMaskSel_Top, HighMaskSel_Top, LowMaskSel_Bot, HighMaskSel_Bot, + LowLogicImm, HighLogicImm, LogicImm); `endif if (cyc==0) begin - // Single case - crc <= 8'h0; - sum <= 64'h0; + // Single case + crc <= 8'h0; + sum <= 64'h0; end else if (cyc==1) begin - // Setup - crc <= 8'hed; - sum <= 64'h0; + // Setup + crc <= 8'hed; + sum <= 64'h0; end else if (cyc<90) begin - sum <= {sum[62:0],sum[63]} ^ LogicImm; + sum <= {sum[62:0],sum[63]} ^ LogicImm; end else if (cyc==99) begin - $write("[%0t] cyc==%0d crc=%b %x\n", $time, cyc, crc, sum); - if (crc !== 8'b00111000) $stop; - if (sum !== 64'h58743ffa61e41075) $stop; - $write("*-* All Finished *-*\n"); - $finish; + $write("[%0t] cyc==%0d crc=%b %x\n", $time, cyc, crc, sum); + if (crc !== 8'b00111000) $stop; + if (sum !== 64'h58743ffa61e41075) $stop; + $write("*-* All Finished *-*\n"); + $finish; end end @@ -84,27 +84,27 @@ module example (/*AUTOARG*/ ); input [5:0] LowMaskSel_Top, HighMaskSel_Top; - input [5:0] LowMaskSel_Bot, HighMaskSel_Bot; + input [5:0] LowMaskSel_Bot, HighMaskSel_Bot; output [63:0] LogicImm; - output [63:0] LowLogicImm, HighLogicImm; + output [63:0] LowLogicImm, HighLogicImm; - wire [63:0] LowLogicImm, HighLogicImm; + wire [63:0] LowLogicImm, HighLogicImm; /* verilator lint_off UNSIGNED */ /* verilator lint_off CMPCONST */ - genvar i; + genvar i; generate for (i=0;i<64;i=i+1) begin : MaskVal - if (i >= 32) begin - assign LowLogicImm[i] = (LowMaskSel_Top <= i[5:0]); - assign HighLogicImm[i] = (HighMaskSel_Top >= i[5:0]); - end - else begin - assign LowLogicImm[i] = (LowMaskSel_Bot <= i[5:0]); - assign HighLogicImm[i] = (HighMaskSel_Bot >= i[5:0]); - end + if (i >= 32) begin + assign LowLogicImm[i] = (LowMaskSel_Top <= i[5:0]); + assign HighLogicImm[i] = (HighMaskSel_Top >= i[5:0]); + end + else begin + assign LowLogicImm[i] = (LowMaskSel_Bot <= i[5:0]); + assign HighLogicImm[i] = (HighMaskSel_Bot >= i[5:0]); + end end endgenerate /* verilator lint_on UNSIGNED */ diff --git a/test_regress/t/t_math_imm2.v b/test_regress/t/t_math_imm2.v index 4a0bff5d3..57476f385 100644 --- a/test_regress/t/t_math_imm2.v +++ b/test_regress/t/t_math_imm2.v @@ -18,24 +18,24 @@ module t_math_imm2 (/*AUTOARG*/ LowMaskSel_Top, HighMaskSel_Top, LowMaskSel_Bot, HighMaskSel_Bot ); input [4:0] LowMaskSel_Top, HighMaskSel_Top; - input [4:0] LowMaskSel_Bot, HighMaskSel_Bot; + input [4:0] LowMaskSel_Bot, HighMaskSel_Bot; output [63:0] LogicImm; output [63:0] LowLogicImm, HighLogicImm; /* verilator lint_off UNSIGNED */ /* verilator lint_off CMPCONST */ - genvar i; + genvar i; generate for (i=0;i<64;i=i+1) begin : MaskVal - if (i >= 32) begin - assign LowLogicImm[i] = (LowMaskSel_Top <= i[4:0]); - assign HighLogicImm[i] = (HighMaskSel_Top >= i[4:0]); - end - else begin - assign LowLogicImm[i] = (LowMaskSel_Bot <= i[4:0]); - assign HighLogicImm[i] = (HighMaskSel_Bot >= i[4:0]); - end + if (i >= 32) begin + assign LowLogicImm[i] = (LowMaskSel_Top <= i[4:0]); + assign HighLogicImm[i] = (HighMaskSel_Top >= i[4:0]); + end + else begin + assign LowLogicImm[i] = (LowMaskSel_Bot <= i[4:0]); + assign HighLogicImm[i] = (HighMaskSel_Bot >= i[4:0]); + end end endgenerate diff --git a/test_regress/t/t_math_mul.v b/test_regress/t/t_math_mul.v index a63ceb249..65d92878a 100644 --- a/test_regress/t/t_math_mul.v +++ b/test_regress/t/t_math_mul.v @@ -27,12 +27,12 @@ module t (/*AUTOARG*/ crc <= {crc[62:0], crc[63] ^ crc[2] ^ crc[0]}; sum <= {sum[62:0], sum[63]^sum[2]^sum[0]} ^ {out2,out1}; if (cyc==1) begin - // Setup - crc <= 64'h00000000_00000097; - sum <= 64'h0; + // Setup + crc <= 64'h00000000_00000097; + sum <= 64'h0; end else if (cyc==90) begin - if (sum !== 64'he396068aba3898a2) $stop; + if (sum !== 64'he396068aba3898a2) $stop; end else if (cyc==91) begin end @@ -43,8 +43,8 @@ module t (/*AUTOARG*/ else if (cyc==94) begin end else if (cyc==99) begin - $write("*-* All Finished *-*\n"); - $finish; + $write("*-* All Finished *-*\n"); + $finish; end end diff --git a/test_regress/t/t_math_pick.v b/test_regress/t/t_math_pick.v index 9f8aa5c17..0908ed8a1 100644 --- a/test_regress/t/t_math_pick.v +++ b/test_regress/t/t_math_pick.v @@ -10,27 +10,27 @@ module t (/*AUTOARG*/ ); input clk; - integer cyc = 0; - reg [63:0] crc; - reg [63:0] sum; + integer cyc = 0; + reg [63:0] crc; + reg [63:0] sum; // Take CRC data and apply to testblock inputs - wire pick1 = crc[0]; + wire pick1 = crc[0]; wire [13:0][1:0] data1 = crc[27+1:1]; wire [3:0][2:0][1:0] data2 = crc[23+29:29]; /*AUTOWIRE*/ // Beginning of automatic wires (for undeclared instantiated-module outputs) - logic [15:0] [1:0] datao; // From test of Test.v + logic [15:0] [1:0] datao; // From test of Test.v // End of automatics Test test (/*AUTOINST*/ - // Outputs - .datao (datao/*[15:0][1:0]*/), - // Inputs - .pick1 (pick1), - .data1 (data1/*[13:0][1:0]*/), - .data2 (data2/*[2:0][3:0][1:0]*/)); + // Outputs + .datao (datao/*[15:0][1:0]*/), + // Inputs + .pick1 (pick1), + .data1 (data1/*[13:0][1:0]*/), + .data2 (data2/*[2:0][3:0][1:0]*/)); // Aggregate outputs into a single result vector wire [63:0] result = {32'h0, datao}; @@ -44,23 +44,23 @@ module t (/*AUTOARG*/ crc <= {crc[62:0], crc[63] ^ crc[2] ^ crc[0]}; sum <= result ^ {sum[62:0], sum[63] ^ sum[2] ^ sum[0]}; if (cyc==0) begin - // Setup - crc <= 64'h5aef0c8d_d70a4497; - sum <= 64'h0; + // Setup + crc <= 64'h5aef0c8d_d70a4497; + sum <= 64'h0; end else if (cyc<10) begin - sum <= 64'h0; + sum <= 64'h0; end else if (cyc<90) begin end else if (cyc==99) begin - $write("[%0t] cyc==%0d crc=%x sum=%x\n", $time, cyc, crc, sum); - if (crc !== 64'hc77bb9b3784ea091) $stop; - // What checksum will we end up with (above print should match) + $write("[%0t] cyc==%0d crc=%x sum=%x\n", $time, cyc, crc, sum); + if (crc !== 64'hc77bb9b3784ea091) $stop; + // What checksum will we end up with (above print should match) `define EXPECTED_SUM 64'h3ff4bf0e6407b281 - if (sum !== `EXPECTED_SUM) $stop; - $write("*-* All Finished *-*\n"); - $finish; + if (sum !== `EXPECTED_SUM) $stop; + $write("*-* All Finished *-*\n"); + $finish; end end @@ -68,10 +68,10 @@ endmodule module Test ( - input logic pick1, - input logic [13:0] [1:0] data1, // 14 x 2 = 28 bits + input logic pick1, + input logic [13:0] [1:0] data1, // 14 x 2 = 28 bits input logic [ 3:0] [2:0] [1:0] data2, // 4 x 3 x 2 = 24 bits - output logic [15:0] [1:0] datao // 16 x 2 = 32 bits + output logic [15:0] [1:0] datao // 16 x 2 = 32 bits ); // verilator lint_off WIDTH always_comb datao[13: 0] // 28 bits diff --git a/test_regress/t/t_math_pow.v b/test_regress/t/t_math_pow.v index 3afbf8433..dd18f3085 100644 --- a/test_regress/t/t_math_pow.v +++ b/test_regress/t/t_math_pow.v @@ -30,76 +30,76 @@ module t (/*AUTOARG*/ integer cyc; initial cyc=1; always @ (posedge clk) begin if (cyc!=0) begin - cyc <= cyc + 1; + cyc <= cyc + 1; `ifdef TEST_VERBOSE - $write("%0x %x %x\n", cyc, p, shifted); + $write("%0x %x %x\n", cyc, p, shifted); `endif - // Constant versions - `checkh(61'h1 ** 21'h31, 61'h1); - `checkh(61'h2 ** 21'h10, 61'h10000); - `checkh(61'd10 ** 21'h3, 61'h3e8); - `checkh(61'h3 ** 21'h7, 61'h88b); + // Constant versions + `checkh(61'h1 ** 21'h31, 61'h1); + `checkh(61'h2 ** 21'h10, 61'h10000); + `checkh(61'd10 ** 21'h3, 61'h3e8); + `checkh(61'h3 ** 21'h7, 61'h88b); `ifndef VCS - `checkh(61'h7ab3811219 ** 21'ha6e30, 61'h01ea58c703687e81); + `checkh(61'h7ab3811219 ** 21'ha6e30, 61'h01ea58c703687e81); `endif - if (cyc==1) begin - a <= 61'h0; - b <= 21'h0; - end - if (cyc==2) begin - a <= 61'h0; - b <= 21'h3; - end - if (cyc==3) begin - a <= 61'h1; - b <= 21'h31; - end - if (cyc==4) begin - a <= 61'h2; - b <= 21'h10; - end - if (cyc==5) begin - a <= 61'd10; - b <= 21'd3; - end - if (cyc==6) begin - a <= 61'd3; - b <= 21'd7; - end - if (cyc==7) begin - a <= 61'h7ab3811219; - b <= 21'ha6e30; - end - if (cyc==9) begin - $write("*-* All Finished *-*\n"); - $finish; - end + if (cyc==1) begin + a <= 61'h0; + b <= 21'h0; + end + if (cyc==2) begin + a <= 61'h0; + b <= 21'h3; + end + if (cyc==3) begin + a <= 61'h1; + b <= 21'h31; + end + if (cyc==4) begin + a <= 61'h2; + b <= 21'h10; + end + if (cyc==5) begin + a <= 61'd10; + b <= 21'd3; + end + if (cyc==6) begin + a <= 61'd3; + b <= 21'd7; + end + if (cyc==7) begin + a <= 61'h7ab3811219; + b <= 21'ha6e30; + end + if (cyc==9) begin + $write("*-* All Finished *-*\n"); + $finish; + end end case (cyc) - 32'd00: ; - 32'd01: ; - 32'd02: ; // 0^x is indeterminate - 32'd03: ; // 0^x is indeterminate - 32'd04: `checkh(p, 61'h1); - 32'd05: `checkh(p, 61'h10000); - 32'd06: `checkh(p, 61'h3e8); - 32'd07: `checkh(p, 61'h88b); - 32'd08: `checkh(p, 61'h01ea58c703687e81); - 32'd09: `checkh(p, 61'h01ea58c703687e81); - default: $stop; + 32'd00: ; + 32'd01: ; + 32'd02: ; // 0^x is indeterminate + 32'd03: ; // 0^x is indeterminate + 32'd04: `checkh(p, 61'h1); + 32'd05: `checkh(p, 61'h10000); + 32'd06: `checkh(p, 61'h3e8); + 32'd07: `checkh(p, 61'h88b); + 32'd08: `checkh(p, 61'h01ea58c703687e81); + 32'd09: `checkh(p, 61'h01ea58c703687e81); + default: $stop; endcase case (cyc) - 32'd00: ; - 32'd01: ; - 32'd02: `checkh(shifted, 61'h0000000000000001); - 32'd03: `checkh(shifted, 61'h0000000000000008); - 32'd04: `checkh(shifted, 61'h0002000000000000); - 32'd05: `checkh(shifted, 61'h0000000000010000); - 32'd06: `checkh(shifted, 61'h0000000000000008); - 32'd07: `checkh(shifted, 61'h0000000000000080); - 32'd08: `checkh(shifted, 61'h0000000000000000); - 32'd09: `checkh(shifted, 61'h0000000000000000); - default: $stop; + 32'd00: ; + 32'd01: ; + 32'd02: `checkh(shifted, 61'h0000000000000001); + 32'd03: `checkh(shifted, 61'h0000000000000008); + 32'd04: `checkh(shifted, 61'h0002000000000000); + 32'd05: `checkh(shifted, 61'h0000000000010000); + 32'd06: `checkh(shifted, 61'h0000000000000008); + 32'd07: `checkh(shifted, 61'h0000000000000080); + 32'd08: `checkh(shifted, 61'h0000000000000000); + 32'd09: `checkh(shifted, 61'h0000000000000000); + default: $stop; endcase end endmodule diff --git a/test_regress/t/t_math_pow2.v b/test_regress/t/t_math_pow2.v index 9ecc6fd91..7cd74413e 100644 --- a/test_regress/t/t_math_pow2.v +++ b/test_regress/t/t_math_pow2.v @@ -10,15 +10,15 @@ module t (/*AUTOARG*/ ); input clk; - integer cyc = 0; - reg [63:0] crc; - reg [63:0] sum; + integer cyc = 0; + reg [63:0] crc; + reg [63:0] sum; // Aggregate outputs into a single result vector - //wire [31:0] pow32b = {24'h0,crc[15:8]}**crc[7:0]; // Overflows - wire [3:0] pow4b = crc[7:4] ** crc[3:0]; - wire [31:0] pow2 = 2 ** crc[3:0]; // Optimizes to shift - wire [63:0] result = {pow2, 28'h0, pow4b}; + //wire [31:0] pow32b = {24'h0,crc[15:8]}**crc[7:0]; // Overflows + wire [3:0] pow4b = crc[7:4] ** crc[3:0]; + wire [31:0] pow2 = 2 ** crc[3:0]; // Optimizes to shift + wire [63:0] result = {pow2, 28'h0, pow4b}; // Test loop always @ (posedge clk) begin @@ -29,22 +29,22 @@ module t (/*AUTOARG*/ crc <= {crc[62:0], crc[63] ^ crc[2] ^ crc[0]}; sum <= result ^ {sum[62:0], sum[63] ^ sum[2] ^ sum[0]}; if (cyc==0) begin - // Setup - crc <= 64'h5aef0c8d_d70a4497; - sum <= 64'h0; + // Setup + crc <= 64'h5aef0c8d_d70a4497; + sum <= 64'h0; end else if (cyc<10) begin - sum <= 64'h0; + sum <= 64'h0; end else if (cyc<90) begin end else if (cyc==99) begin - $write("[%0t] cyc==%0d crc=%x sum=%x\n", $time, cyc, crc, sum); - if (crc !== 64'hc77bb9b3784ea091) $stop; + $write("[%0t] cyc==%0d crc=%x sum=%x\n", $time, cyc, crc, sum); + if (crc !== 64'hc77bb9b3784ea091) $stop; `define EXPECTED_SUM 64'h056ea1c5a63aff6a - if (sum !== `EXPECTED_SUM) $stop; - $write("*-* All Finished *-*\n"); - $finish; + if (sum !== `EXPECTED_SUM) $stop; + $write("*-* All Finished *-*\n"); + $finish; end end diff --git a/test_regress/t/t_math_pow3.v b/test_regress/t/t_math_pow3.v index 785e05382..e16d50a07 100644 --- a/test_regress/t/t_math_pow3.v +++ b/test_regress/t/t_math_pow3.v @@ -25,27 +25,27 @@ module t (/*AUTOARG*/); $display("64'big ** 1 = %0x expect %0x", 64'h8765432187654321 ** 1, 64'h8765432187654321); $display("\n"); - `checkh( (64'b1111 ** 64'b1110), 64'h67b6cfc1b29a21); - `checkh( (-4'd1 ** -4'sd2), 4'h0); //bug730 - `checkh( (-4'd1 ** -4'd2), 4'h1); - `checkh( (4'd15 ** 4'd14), 4'h1); + `checkh( (64'b1111 ** 64'b1110), 64'h67b6cfc1b29a21); + `checkh( (-4'd1 ** -4'sd2), 4'h0); //bug730 + `checkh( (-4'd1 ** -4'd2), 4'h1); + `checkh( (4'd15 ** 4'd14), 4'h1); `checkh( (64'h8765432187654321 ** 4'h1), 64'h8765432187654321); `checkh((-8'sh3 ** 8'h3) , 8'he5 ); // a**b (-27) - `checkh((-8'sh1 ** 8'h2) , 8'h1 ); // -1^odd=-1, -1^even=1 + `checkh((-8'sh1 ** 8'h2) , 8'h1 ); // -1^odd=-1, -1^even=1 `checkh((-8'sh1 ** 8'h3) , 8'hff ); // -1^odd=-1, -1^even=1 - `checkh(( 8'h0 ** 8'h3) , 8'h0 ); // 0 - `checkh(( 8'h1 ** 8'h3) , 8'h1 ); // 1 + `checkh(( 8'h0 ** 8'h3) , 8'h0 ); // 0 + `checkh(( 8'h1 ** 8'h3) , 8'h1 ); // 1 `checkh(( 8'h3 ** 8'h3) , 8'h1b ); // a**b (27) `checkh(( 8'sh3 ** 8'h3) , 8'h1b ); // a**b (27) `checkh(( 8'h6 ** 8'h3) , 8'hd8 ); // a**b (216) `checkh(( 8'sh6 ** 8'h3) , 8'hd8 ); // a**b (216) `checkh((-8'sh3 ** 8'sh3), 8'he5 ); // a**b - `checkh((-8'sh1 ** 8'sh2), 8'h1 ); // -1^odd=-1, -1^even=1 + `checkh((-8'sh1 ** 8'sh2), 8'h1 ); // -1^odd=-1, -1^even=1 `checkh((-8'sh1 ** 8'sh3), 8'hff ); // -1^odd=-1, -1^even=1 - `checkh(( 8'h0 ** 8'sh3), 8'h0 ); // 0 - `checkh(( 8'h1 ** 8'sh3), 8'h1 ); // 1 + `checkh(( 8'h0 ** 8'sh3), 8'h0 ); // 0 + `checkh(( 8'h1 ** 8'sh3), 8'h1 ); // 1 `checkh(( 8'h3 ** 8'sh3), 8'h1b ); // a**b (27) `checkh(( 8'sh3 ** 8'sh3), 8'h1b ); // a**b (27) `checkh(( 8'h6 ** 8'sh3), 8'hd8 ); // a**b (216) diff --git a/test_regress/t/t_math_pow4.v b/test_regress/t/t_math_pow4.v index a7488e610..fc032c2d4 100644 --- a/test_regress/t/t_math_pow4.v +++ b/test_regress/t/t_math_pow4.v @@ -10,15 +10,15 @@ module t (/*AUTOARG*/ ); input clk; - integer cyc = 0; + integer cyc = 0; wire [31:0] y; - reg a; + reg a; test004 sub (/*AUTOINST*/ - // Outputs - .y (y[31:0]), - // Inputs - .a (a)); + // Outputs + .y (y[31:0]), + // Inputs + .a (a)); // Test loop always @ (posedge clk) begin @@ -27,18 +27,18 @@ module t (/*AUTOARG*/ `endif cyc <= cyc + 1; if (cyc==0) begin - a <= 0; + a <= 0; end else if (cyc==1) begin - a <= 1; - if (y != 32'h0) $stop; + a <= 1; + if (y != 32'h0) $stop; end else if (cyc==2) begin - if (y != 32'h010000ff) $stop; + if (y != 32'h010000ff) $stop; end else if (cyc==99) begin - $write("*-* All Finished *-*\n"); - $finish; + $write("*-* All Finished *-*\n"); + $finish; end end diff --git a/test_regress/t/t_math_pow5.v b/test_regress/t/t_math_pow5.v index 3fe06f5e0..f51b99395 100644 --- a/test_regress/t/t_math_pow5.v +++ b/test_regress/t/t_math_pow5.v @@ -37,38 +37,38 @@ module t (/*AUTOARG*/ integer cyc; initial cyc=1; always @ (posedge clk) begin if (cyc!=0) begin - cyc <= cyc + 1; + cyc <= cyc + 1; `ifdef TEST_VERBOSE - $write("%d %x %x %x %x\n", cyc, left, right, outu, outs); + $write("%d %x %x %x %x\n", cyc, left, right, outu, outs); `endif - if (cyc==1) begin - left <= 68'h1; - right <= '0; - end - if (cyc==2) begin - if (outu != 68'h1) $stop; - if (outs != 68'h1) $stop; - end - if (cyc==3) begin - left <= 68'he_12345678_9abcdef0; - right <= 68'h3; - end - if (cyc==4) begin - if (outu != 68'hcee3cb96ce96cf000) $stop; - if (outs != 68'hcee3cb96ce96cf000) $stop; - end - if (cyc==5) begin - left <= 68'he_12345678_9abcdef0; - right <= 68'h5_6789abcd_ef012345; - end - if (cyc==6) begin - if (outu != 68'h0) $stop; - if (outs != 68'h0) $stop; - end - if (cyc==9) begin - $write("*-* All Finished *-*\n"); - $finish; - end + if (cyc==1) begin + left <= 68'h1; + right <= '0; + end + if (cyc==2) begin + if (outu != 68'h1) $stop; + if (outs != 68'h1) $stop; + end + if (cyc==3) begin + left <= 68'he_12345678_9abcdef0; + right <= 68'h3; + end + if (cyc==4) begin + if (outu != 68'hcee3cb96ce96cf000) $stop; + if (outs != 68'hcee3cb96ce96cf000) $stop; + end + if (cyc==5) begin + left <= 68'he_12345678_9abcdef0; + right <= 68'h5_6789abcd_ef012345; + end + if (cyc==6) begin + if (outu != 68'h0) $stop; + if (outs != 68'h0) $stop; + end + if (cyc==9) begin + $write("*-* All Finished *-*\n"); + $finish; + end end end endmodule diff --git a/test_regress/t/t_math_precedence.v b/test_regress/t/t_math_precedence.v index 46a6b8d3a..85d2f48f5 100644 --- a/test_regress/t/t_math_precedence.v +++ b/test_regress/t/t_math_precedence.v @@ -10,40 +10,40 @@ module t (/*AUTOARG*/ ); input clk; - integer cyc = 0; - reg [63:0] crc; - reg [63:0] sum; + integer cyc = 0; + reg [63:0] crc; + reg [63:0] sum; - wire [1:0] a = crc[1 +: 2]; - wire [1:0] b = crc[3 +: 2]; - wire [1:0] c = crc[5 +: 2]; - wire [1:0] d = crc[7 +: 2]; - wire [1:0] e = crc[9 +: 2]; - wire [1:0] f = crc[11+: 2]; - wire [1:0] g = crc[13+: 2]; + wire [1:0] a = crc[1 +: 2]; + wire [1:0] b = crc[3 +: 2]; + wire [1:0] c = crc[5 +: 2]; + wire [1:0] d = crc[7 +: 2]; + wire [1:0] e = crc[9 +: 2]; + wire [1:0] f = crc[11+: 2]; + wire [1:0] g = crc[13+: 2]; - // left () [] :: . - // unary + - ! ~ & ~& | ~| ^ ~^ ^~ ++ -- (unary) - // left ** - // left * / % - // left + - (binary) - // left << >> <<< >>> - // left < <= > >= inside dist - // left == != === !== ==? !=? - // left & (binary) - // left ^ ~^ ^~ (binary) - // left | (binary) - // left && - // left || - // left ? : - // right -> - // none = += -= *= /= %= &= ^= |= <<= >>= <<<= >>>= := :/ <= - // {} {{}} concatenation + // left () [] :: . + // unary + - ! ~ & ~& | ~| ^ ~^ ^~ ++ -- (unary) + // left ** + // left * / % + // left + - (binary) + // left << >> <<< >>> + // left < <= > >= inside dist + // left == != === !== ==? !=? + // left & (binary) + // left ^ ~^ ^~ (binary) + // left | (binary) + // left && + // left || + // left ? : + // right -> + // none = += -= *= /= %= &= ^= |= <<= >>= <<<= >>>= := :/ <= + // {} {{}} concatenation - wire [1:0] bnz = (b==2'b0) ? 2'b11 : b; - wire [1:0] cnz = (c==2'b0) ? 2'b11 : c; - wire [1:0] dnz = (d==2'b0) ? 2'b11 : d; - wire [1:0] enz = (e==2'b0) ? 2'b11 : e; + wire [1:0] bnz = (b==2'b0) ? 2'b11 : b; + wire [1:0] cnz = (c==2'b0) ? 2'b11 : c; + wire [1:0] dnz = (d==2'b0) ? 2'b11 : d; + wire [1:0] enz = (e==2'b0) ? 2'b11 : e; // verilator lint_off WIDTH // Do a few in each group @@ -81,26 +81,26 @@ module t (/*AUTOARG*/ function [1:0] pow (input [1:0] x, input [1:0] y); casez ({x,y}) - 4'b00_??: pow = 2'b00; - 4'b01_00: pow = 2'b01; - 4'b01_01: pow = 2'b01; - 4'b01_10: pow = 2'b01; - 4'b01_11: pow = 2'b01; - 4'b10_00: pow = 2'b01; - 4'b10_01: pow = 2'b10; - 4'b10_10: pow = 2'b00; - 4'b10_11: pow = 2'b00; - 4'b11_00: pow = 2'b01; - 4'b11_01: pow = 2'b11; - 4'b11_10: pow = 2'b01; - 4'b11_11: pow = 2'b11; + 4'b00_??: pow = 2'b00; + 4'b01_00: pow = 2'b01; + 4'b01_01: pow = 2'b01; + 4'b01_10: pow = 2'b01; + 4'b01_11: pow = 2'b01; + 4'b10_00: pow = 2'b01; + 4'b10_01: pow = 2'b10; + 4'b10_10: pow = 2'b00; + 4'b10_11: pow = 2'b00; + 4'b11_00: pow = 2'b01; + 4'b11_01: pow = 2'b11; + 4'b11_10: pow = 2'b01; + 4'b11_11: pow = 2'b11; endcase endfunction // Aggregate outputs into a single result vector wire [63:0] result = {12'h0, - x11,x10,x9,x8,x7,x6,x5,x4,x3,x2,x1, - o15,o14,o13,o12,o11,o10,o9,o8,o7,o6,o5,o4,o3,o2,o1}; + x11,x10,x9,x8,x7,x6,x5,x4,x3,x2,x1, + o15,o14,o13,o12,o11,o10,o9,o8,o7,o6,o5,o4,o3,o2,o1}; // Test loop always @ (posedge clk) begin @@ -139,23 +139,23 @@ module t (/*AUTOARG*/ crc <= {crc[62:0], crc[63] ^ crc[2] ^ crc[0]}; sum <= result ^ {sum[62:0], sum[63] ^ sum[2] ^ sum[0]}; if (cyc==0) begin - // Setup - crc <= 64'h5aef0c8d_d70a4497; - sum <= 64'h0; + // Setup + crc <= 64'h5aef0c8d_d70a4497; + sum <= 64'h0; end else if (cyc<10) begin - sum <= 64'h0; + sum <= 64'h0; end else if (cyc<90) begin end else if (cyc==99) begin - $write("[%0t] cyc==%0d crc=%x sum=%x\n", $time, cyc, crc, sum); - if (crc !== 64'hc77bb9b3784ea091) $stop; - // What checksum will we end up with (above print should match) + $write("[%0t] cyc==%0d crc=%x sum=%x\n", $time, cyc, crc, sum); + if (crc !== 64'hc77bb9b3784ea091) $stop; + // What checksum will we end up with (above print should match) `define EXPECTED_SUM 64'h2756ea365ec7520e - if (sum !== `EXPECTED_SUM) $stop; - $write("*-* All Finished *-*\n"); - $finish; + if (sum !== `EXPECTED_SUM) $stop; + $write("*-* All Finished *-*\n"); + $finish; end end diff --git a/test_regress/t/t_math_repl.v b/test_regress/t/t_math_repl.v index 43b57e044..e36b15d49 100644 --- a/test_regress/t/t_math_repl.v +++ b/test_regress/t/t_math_repl.v @@ -15,7 +15,7 @@ module t (/*AUTOARG*/ reg [63:0] rf; reg [63:0] rf2; reg [63:0] biu; - reg b; + reg b; always @* begin rf[63:32] = biu[63:32] & {32{b}}; @@ -26,85 +26,85 @@ module t (/*AUTOARG*/ reg [31:0] src1, src0, sr, mask; wire [31:0] dualasr - = ((| src1[31:4]) - ? {{16{src0[31]}}, {16{src0[15]}}} - : ( ( sr & {2{mask[31:16]}}) - | ( {{16{src0[31]}}, {16{src0[15]}}} - & {2{~mask[31:16]}}))); + = ((| src1[31:4]) + ? {{16{src0[31]}}, {16{src0[15]}}} + : ( ( sr & {2{mask[31:16]}}) + | ( {{16{src0[31]}}, {16{src0[15]}}} + & {2{~mask[31:16]}}))); wire [31:0] sl_mask - = (32'hffffffff << src1[4:0]); + = (32'hffffffff << src1[4:0]); wire [31:0] sr_mask - = {sl_mask[0], sl_mask[1], - sl_mask[2], sl_mask[3], sl_mask[4], + = {sl_mask[0], sl_mask[1], + sl_mask[2], sl_mask[3], sl_mask[4], sl_mask[5], sl_mask[6], sl_mask[7], - sl_mask[8], sl_mask[9], + sl_mask[8], sl_mask[9], sl_mask[10], sl_mask[11], - sl_mask[12], sl_mask[13], sl_mask[14], + sl_mask[12], sl_mask[13], sl_mask[14], sl_mask[15], sl_mask[16], - sl_mask[17], sl_mask[18], sl_mask[19], + sl_mask[17], sl_mask[18], sl_mask[19], sl_mask[20], sl_mask[21], - sl_mask[22], sl_mask[23], sl_mask[24], + sl_mask[22], sl_mask[23], sl_mask[24], sl_mask[25], sl_mask[26], - sl_mask[27], sl_mask[28], sl_mask[29], + sl_mask[27], sl_mask[28], sl_mask[29], sl_mask[30], sl_mask[31]}; wire [95:0] widerep = {2{({2{({2{ {b,b}, {b,{2{b}}}, {{2{b}},b}, {2{({2{b}})}} }})}})}}; - wire [1:0] w = {2{b}}; + wire [1:0] w = {2{b}}; always @ (posedge clk) begin if (cyc!=0) begin - cyc <= cyc + 1; + cyc <= cyc + 1; `ifdef TEST_VERBOSE - $write("cyc=%0d d=%x %x %x %x %x %x %x\n", cyc, b, rf, rf2, dualasr, sl_mask, sr_mask, widerep); + $write("cyc=%0d d=%x %x %x %x %x %x %x\n", cyc, b, rf, rf2, dualasr, sl_mask, sr_mask, widerep); `endif - if (cyc==1) begin - biu <= 64'h12451282_abadee00; - b <= 1'b0; - src1 <= 32'h00000001; - src0 <= 32'h9a4f1235; - sr <= 32'h0f19f567; - mask <= 32'h7af07ab4; - end - if (cyc==2) begin - biu <= 64'h12453382_abad8801; - b <= 1'b1; - if (rf != 64'h0) $stop; - if (rf2 != 64'h00000000ffffffff) $stop; - src1 <= 32'h0010000f; - src0 <= 32'h028aa336; - sr <= 32'h42ad0377; - mask <= 32'h1ab3b906; - if (dualasr != 32'h8f1f7060) $stop; - if (sl_mask != 32'hfffffffe) $stop; - if (sr_mask != 32'h7fffffff) $stop; - if (widerep != '0) $stop; - end - if (cyc==3) begin - biu <= 64'h12422382_77ad8802; - b <= 1'b1; - if (rf != 64'h12453382ffffffff) $stop; - if (rf2 != 64'h1245338200000000) $stop; - src1 <= 32'h0000000f; - src0 <= 32'h5c158f71; - sr <= 32'h7076c40a; - mask <= 32'h33eb3d44; - if (dualasr != 32'h0000ffff) $stop; - if (sl_mask != 32'hffff8000) $stop; - if (sr_mask != 32'h0001ffff) $stop; - if (widerep != '1) $stop; - end - if (cyc==4) begin - if (rf != 64'h12422382ffffffff) $stop; - if (rf2 != 64'h1242238200000000) $stop; - if (dualasr != 32'h3062cc1e) $stop; - if (sl_mask != 32'hffff8000) $stop; - if (sr_mask != 32'h0001ffff) $stop; - $write("*-* All Finished *-*\n"); - if (widerep != '1) $stop; - $finish; - end + if (cyc==1) begin + biu <= 64'h12451282_abadee00; + b <= 1'b0; + src1 <= 32'h00000001; + src0 <= 32'h9a4f1235; + sr <= 32'h0f19f567; + mask <= 32'h7af07ab4; + end + if (cyc==2) begin + biu <= 64'h12453382_abad8801; + b <= 1'b1; + if (rf != 64'h0) $stop; + if (rf2 != 64'h00000000ffffffff) $stop; + src1 <= 32'h0010000f; + src0 <= 32'h028aa336; + sr <= 32'h42ad0377; + mask <= 32'h1ab3b906; + if (dualasr != 32'h8f1f7060) $stop; + if (sl_mask != 32'hfffffffe) $stop; + if (sr_mask != 32'h7fffffff) $stop; + if (widerep != '0) $stop; + end + if (cyc==3) begin + biu <= 64'h12422382_77ad8802; + b <= 1'b1; + if (rf != 64'h12453382ffffffff) $stop; + if (rf2 != 64'h1245338200000000) $stop; + src1 <= 32'h0000000f; + src0 <= 32'h5c158f71; + sr <= 32'h7076c40a; + mask <= 32'h33eb3d44; + if (dualasr != 32'h0000ffff) $stop; + if (sl_mask != 32'hffff8000) $stop; + if (sr_mask != 32'h0001ffff) $stop; + if (widerep != '1) $stop; + end + if (cyc==4) begin + if (rf != 64'h12422382ffffffff) $stop; + if (rf2 != 64'h1242238200000000) $stop; + if (dualasr != 32'h3062cc1e) $stop; + if (sl_mask != 32'hffff8000) $stop; + if (sr_mask != 32'h0001ffff) $stop; + $write("*-* All Finished *-*\n"); + if (widerep != '1) $stop; + $finish; + end end end endmodule diff --git a/test_regress/t/t_math_reverse.v b/test_regress/t/t_math_reverse.v index f8b6b8a20..15ee7de62 100644 --- a/test_regress/t/t_math_reverse.v +++ b/test_regress/t/t_math_reverse.v @@ -53,31 +53,31 @@ module t (/*AUTOARG*/ always @ (posedge clk) begin if (cyc!=0) begin - cyc<=cyc+1; - //$write("cyc=%0d crc=%x r=%x\n", cyc, crc, bitrev); - crc <= {crc[6:0], ~^ {crc[7],crc[5],crc[4],crc[3]}}; - if (cyc==1) begin - crc <= 8'hed; - end - if (cyc==2 && bitrev!=8'hb7) $stop; - if (cyc==3 && bitrev!=8'h5b) $stop; - if (cyc==4 && bitrev!=8'h2d) $stop; - if (cyc==5 && bitrev!=8'h16) $stop; - if (cyc==6 && bitrev!=8'h8b) $stop; - if (cyc==7 && bitrev!=8'hc5) $stop; - if (cyc==8 && bitrev!=8'he2) $stop; - if (cyc==9 && bitrev!=8'hf1) $stop; - if (bitrevb != bitrev) $stop; - if (cyc==3 && bitrevr!=8'hb7) $stop; - if (cyc==4 && bitrevr!=8'h5b) $stop; - if (cyc==5 && bitrevr!=8'h2d) $stop; - if (cyc==6 && bitrevr!=8'h16) $stop; - if (cyc==7 && bitrevr!=8'h8b) $stop; - if (cyc==8 && bitrevr!=8'hc5) $stop; - if (cyc==9) begin - $write("*-* All Finished *-*\n"); - $finish; - end + cyc<=cyc+1; + //$write("cyc=%0d crc=%x r=%x\n", cyc, crc, bitrev); + crc <= {crc[6:0], ~^ {crc[7],crc[5],crc[4],crc[3]}}; + if (cyc==1) begin + crc <= 8'hed; + end + if (cyc==2 && bitrev!=8'hb7) $stop; + if (cyc==3 && bitrev!=8'h5b) $stop; + if (cyc==4 && bitrev!=8'h2d) $stop; + if (cyc==5 && bitrev!=8'h16) $stop; + if (cyc==6 && bitrev!=8'h8b) $stop; + if (cyc==7 && bitrev!=8'hc5) $stop; + if (cyc==8 && bitrev!=8'he2) $stop; + if (cyc==9 && bitrev!=8'hf1) $stop; + if (bitrevb != bitrev) $stop; + if (cyc==3 && bitrevr!=8'hb7) $stop; + if (cyc==4 && bitrevr!=8'h5b) $stop; + if (cyc==5 && bitrevr!=8'h2d) $stop; + if (cyc==6 && bitrevr!=8'h16) $stop; + if (cyc==7 && bitrevr!=8'h8b) $stop; + if (cyc==8 && bitrevr!=8'hc5) $stop; + if (cyc==9) begin + $write("*-* All Finished *-*\n"); + $finish; + end end end endmodule diff --git a/test_regress/t/t_math_shift_rep.v b/test_regress/t/t_math_shift_rep.v index d7e1ad0ec..edfcf059e 100644 --- a/test_regress/t/t_math_shift_rep.v +++ b/test_regress/t/t_math_shift_rep.v @@ -11,9 +11,9 @@ module t (/*AUTOARG*/ input clk; - integer cyc = 0; - reg [63:0] crc; - reg [63:0] sum; + integer cyc = 0; + reg [63:0] crc; + reg [63:0] sum; //bug765; disappears if add this wire //wire [7:0] a = (crc[7] ? {7'b0,crc[0]} : crc[7:0]); // favor low values @@ -21,14 +21,14 @@ module t (/*AUTOARG*/ /*AUTOWIRE*/ // Beginning of automatic wires (for undeclared instantiated-module outputs) - wire [15:0] y; // From test of Test.v + wire [15:0] y; // From test of Test.v // End of automatics Test test (/*AUTOINST*/ - // Outputs - .y (y[15:0]), - // Inputs - .a (a[7:0])); + // Outputs + .y (y[15:0]), + // Inputs + .a (a[7:0])); // Aggregate outputs into a single result vector wire [63:0] result = {48'h0, y}; @@ -42,23 +42,23 @@ module t (/*AUTOARG*/ crc <= {crc[62:0], crc[63] ^ crc[2] ^ crc[0]}; sum <= result ^ {sum[62:0], sum[63] ^ sum[2] ^ sum[0]}; if (cyc==0) begin - // Setup - crc <= 64'h5aef0c8d_d70a4497; - sum <= 64'h0; + // Setup + crc <= 64'h5aef0c8d_d70a4497; + sum <= 64'h0; end else if (cyc<10) begin - sum <= 64'h0; + sum <= 64'h0; end else if (cyc<90) begin end else if (cyc==99) begin - $write("[%0t] cyc==%0d crc=%x sum=%x\n", $time, cyc, crc, sum); - if (crc !== 64'hc77bb9b3784ea091) $stop; - // What checksum will we end up with (above print should match) + $write("[%0t] cyc==%0d crc=%x sum=%x\n", $time, cyc, crc, sum); + if (crc !== 64'hc77bb9b3784ea091) $stop; + // What checksum will we end up with (above print should match) `define EXPECTED_SUM 64'h0 - if (sum !== `EXPECTED_SUM) $stop; - $write("*-* All Finished *-*\n"); - $finish; + if (sum !== `EXPECTED_SUM) $stop; + $write("*-* All Finished *-*\n"); + $finish; end end diff --git a/test_regress/t/t_math_shift_sel.v b/test_regress/t/t_math_shift_sel.v index 3a78512b4..569f3b170 100644 --- a/test_regress/t/t_math_shift_sel.v +++ b/test_regress/t/t_math_shift_sel.v @@ -10,25 +10,25 @@ module t (/*AUTOARG*/ ); input clk; - integer cyc = 0; - reg [63:0] crc; - reg [63:0] sum; + integer cyc = 0; + reg [63:0] crc; + reg [63:0] sum; // Take CRC data and apply to testblock inputs wire [106:0] in = {~crc[42:0], crc[63:0]}; /*AUTOWIRE*/ // Beginning of automatic wires (for undeclared instantiated-module outputs) - wire [7:0] out1; // From test of Test.v - wire [7:0] out2; // From test of Test.v + wire [7:0] out1; // From test of Test.v + wire [7:0] out2; // From test of Test.v // End of automatics Test test (/*AUTOINST*/ - // Outputs - .out1 (out1[7:0]), - .out2 (out2[7:0]), - // Inputs - .in (in[106:0])); + // Outputs + .out1 (out1[7:0]), + .out2 (out2[7:0]), + // Inputs + .in (in[106:0])); // Aggregate outputs into a single result vector wire [63:0] result = {48'h0, out1, out1}; @@ -42,23 +42,23 @@ module t (/*AUTOARG*/ crc <= {crc[62:0], crc[63] ^ crc[2] ^ crc[0]}; sum <= result ^ {sum[62:0], sum[63] ^ sum[2] ^ sum[0]}; if (cyc==0) begin - // Setup - crc <= 64'h5aef0c8d_d70a4497; - sum <= '0; + // Setup + crc <= 64'h5aef0c8d_d70a4497; + sum <= '0; end else if (cyc<10) begin - sum <= '0; + sum <= '0; end else if (cyc<90) begin end else if (cyc==99) begin - $write("[%0t] cyc==%0d crc=%x sum=%x\n", $time, cyc, crc, sum); - if (crc !== 64'hc77bb9b3784ea091) $stop; - // What checksum will we end up with (above print should match) + $write("[%0t] cyc==%0d crc=%x sum=%x\n", $time, cyc, crc, sum); + if (crc !== 64'hc77bb9b3784ea091) $stop; + // What checksum will we end up with (above print should match) `define EXPECTED_SUM 64'hc746017202a24ecc - if (sum !== `EXPECTED_SUM) $stop; - $write("*-* All Finished *-*\n"); - $finish; + if (sum !== `EXPECTED_SUM) $stop; + $write("*-* All Finished *-*\n"); + $finish; end end @@ -81,8 +81,8 @@ module Test (/*AUTOARG*/ // verilator lint_off WIDTH // Better written as onibble[99 +: 8]. Verilator will convert it. - wire [7:0] out1 = (in >>> 99) & 255; + wire [7:0] out1 = (in >>> 99) & 255; // verilator lint_on WIDTH - wire [7:0] out2 = in[106:99]; + wire [7:0] out2 = in[106:99]; endmodule diff --git a/test_regress/t/t_math_shiftrs.v b/test_regress/t/t_math_shiftrs.v index d89c637dd..1622ebbdb 100644 --- a/test_regress/t/t_math_shiftrs.v +++ b/test_regress/t/t_math_shiftrs.v @@ -13,45 +13,45 @@ module t (/*AUTOARG*/ integer cyc; initial cyc=1; reg signed [64+15:0] data; - integer i; - integer b; + integer i; + integer b; reg signed [64+15:0] srs; always @ (posedge clk) begin if (cyc!=0) begin - cyc <= cyc + 1; - if (cyc==2) begin - data <= 80'h0; - data[75] <= 1'b1; - data[10] <= 1'b1; - end - if (cyc==3) begin - for (i=0; i<85; i=i+1) begin - srs = data>>>i; - //$write (" %x >>> %d == %x\n",data,i,srs); - for (b=0; b<80; b=b+1) begin - if (srs[b] != (b==(75-i) || b==(10-i))) $stop; - end - end - end - if (cyc==10) begin - data <= 80'h0; - data[79] <= 1'b1; - data[10] <= 1'b1; - end - if (cyc==12) begin - for (i=0; i<85; i=i+1) begin - srs = data>>>i; - //$write (" %x >>> %d == %x\n",data,i,srs); - for (b=0; b<80; b=b+1) begin - if (srs[b] != (b>=(79-i) || b==(10-i))) $stop; - end - end - end - if (cyc==20) begin - $write("*-* All Finished *-*\n"); - $finish; - end + cyc <= cyc + 1; + if (cyc==2) begin + data <= 80'h0; + data[75] <= 1'b1; + data[10] <= 1'b1; + end + if (cyc==3) begin + for (i=0; i<85; i=i+1) begin + srs = data>>>i; + //$write (" %x >>> %d == %x\n",data,i,srs); + for (b=0; b<80; b=b+1) begin + if (srs[b] != (b==(75-i) || b==(10-i))) $stop; + end + end + end + if (cyc==10) begin + data <= 80'h0; + data[79] <= 1'b1; + data[10] <= 1'b1; + end + if (cyc==12) begin + for (i=0; i<85; i=i+1) begin + srs = data>>>i; + //$write (" %x >>> %d == %x\n",data,i,srs); + for (b=0; b<80; b=b+1) begin + if (srs[b] != (b>=(79-i) || b==(10-i))) $stop; + end + end + end + if (cyc==20) begin + $write("*-* All Finished *-*\n"); + $finish; + end end end endmodule diff --git a/test_regress/t/t_math_signed.v b/test_regress/t/t_math_signed.v index 9bdc5d362..7adf78026 100644 --- a/test_regress/t/t_math_signed.v +++ b/test_regress/t/t_math_signed.v @@ -22,13 +22,13 @@ module t (/*AUTOARG*/ by_width #(96) w96 (.clk(clk)); by_width #(97) w97 (.clk(clk)); - reg signed [15:0] a; - reg signed [4:0] b; + reg signed [15:0] a; + reg signed [4:0] b; - reg signed [15:0] sr,srs,sl,sls; + reg signed [15:0] sr,srs,sl,sls; - reg [15:0] b_s; - reg [15:0] b_us; + reg [15:0] b_s; + reg [15:0] b_us; task check_s(input signed [7:0] i, input [7:0] expval); //$display("check_s %x\n", i); @@ -45,8 +45,8 @@ module t (/*AUTOARG*/ sl = a<>>4; // Signed - b_us = b[4:0]>>>4; // Unsigned, due to extract + b_s = b>>>4; // Signed + b_us = b[4:0]>>>4; // Unsigned, due to extract check_s ( 3'b111, 8'h07); check_s (3'sb111, 8'hff); check_us( 3'b111, 8'h07); @@ -61,10 +61,10 @@ module t (/*AUTOARG*/ end integer i; initial begin - if ((-1 >>> 3) != -1) $stop; // Decimals are signed + if ((-1 >>> 3) != -1) $stop; // Decimals are signed // verilator lint_off WIDTH - if ((3'b111 >>> 3) != 0) $stop; // Based numbers are unsigned - if ((3'sb111 >>> 3) != -1) $stop; // Signed based numbers + if ((3'b111 >>> 3) != 0) $stop; // Based numbers are unsigned + if ((3'sb111 >>> 3) != -1) $stop; // Signed based numbers // verilator lint_on WIDTH if ( (3'sb000 > 3'sb000)) $stop; if (!(3'sb000 > 3'sb111)) $stop; @@ -106,71 +106,71 @@ module t (/*AUTOARG*/ $write("%x %x %x %x %x %x %x\n", cyc, sr,srs,sl,sls, b_s,b_us); `endif case (cyc) - 0: begin - a <= 16'sh8b1b; b <= 5'sh1f; // -1 - end - 1: begin - // Check spaces in constants - a <= 16 'sh 8b1b; b <= 5'sh01; // -1 - end - 2: begin - a <= 16'sh8b1b; b <= 5'sh1e; // shift AMOUNT is really unsigned - if (ucyc / 1 != 32'd2) $stop; - if (ucyc / 2 != 32'd1) $stop; - if (ucyc * 1 != 32'd2) $stop; - if (ucyc * 2 != 32'd4) $stop; - if (ucyc * 3 != 32'd6) $stop; - if (cyc * 32'sd1 != 32'sd2) $stop; - if (cyc * 32'sd2 != 32'sd4) $stop; - if (cyc * 32'sd3 != 32'sd6) $stop; - end - 3: begin - a <= 16'sh0048; b <= 5'sh1f; - if (ucyc * 1 != 32'd3) $stop; - if (ucyc * 2 != 32'd6) $stop; - if (ucyc * 3 != 32'd9) $stop; - if (ucyc * 4 != 32'd12) $stop; - if (cyc * 32'sd1 != 32'sd3) $stop; - if (cyc * 32'sd2 != 32'sd6) $stop; - if (cyc * 32'sd3 != 32'sd9) $stop; - end - 4: begin - a <= 16'sh4154; b <= 5'sh02; - end - 5: begin - a <= 16'shc3e8; b <= 5'sh12; - end - 6: begin - a <= 16'sh488b; b <= 5'sh02; - end - 9: begin - $write("*-* All Finished *-*\n"); - $finish; - end - default: ; + 0: begin + a <= 16'sh8b1b; b <= 5'sh1f; // -1 + end + 1: begin + // Check spaces in constants + a <= 16 'sh 8b1b; b <= 5'sh01; // -1 + end + 2: begin + a <= 16'sh8b1b; b <= 5'sh1e; // shift AMOUNT is really unsigned + if (ucyc / 1 != 32'd2) $stop; + if (ucyc / 2 != 32'd1) $stop; + if (ucyc * 1 != 32'd2) $stop; + if (ucyc * 2 != 32'd4) $stop; + if (ucyc * 3 != 32'd6) $stop; + if (cyc * 32'sd1 != 32'sd2) $stop; + if (cyc * 32'sd2 != 32'sd4) $stop; + if (cyc * 32'sd3 != 32'sd6) $stop; + end + 3: begin + a <= 16'sh0048; b <= 5'sh1f; + if (ucyc * 1 != 32'd3) $stop; + if (ucyc * 2 != 32'd6) $stop; + if (ucyc * 3 != 32'd9) $stop; + if (ucyc * 4 != 32'd12) $stop; + if (cyc * 32'sd1 != 32'sd3) $stop; + if (cyc * 32'sd2 != 32'sd6) $stop; + if (cyc * 32'sd3 != 32'sd9) $stop; + end + 4: begin + a <= 16'sh4154; b <= 5'sh02; + end + 5: begin + a <= 16'shc3e8; b <= 5'sh12; + end + 6: begin + a <= 16'sh488b; b <= 5'sh02; + end + 9: begin + $write("*-* All Finished *-*\n"); + $finish; + end + default: ; endcase case (cyc) - 0: ; - 1: if ({sr,srs,sl,sls,b_s,b_us}!==96'sh0000_ffff_0000_0000_ffff_0001) $stop; - 2: if ({sr,srs,sl,sls,b_s,b_us}!==96'sh458d_c58d_1636_1636_0000_0000) $stop; - 3: if ({sr,srs,sl,sls,b_s,b_us}!==96'sh0000_ffff_0000_0000_ffff_0001) $stop; - 4: if ({sr,srs,sl,sls,b_s,b_us}!==96'sh0000_0000_0000_0000_ffff_0001) $stop; - 5: if ({sr,srs,sl,sls,b_s,b_us}!==96'sh1055_1055_0550_0550_0000_0000) $stop; - 6: if ({sr,srs,sl,sls,b_s,b_us}!==96'sh0000_ffff_0000_0000_ffff_0001) $stop; - 7: if ({sr,srs,sl,sls,b_s,b_us}!==96'sh1222_1222_222c_222c_0000_0000) $stop; - 8: ; - 9: ; + 0: ; + 1: if ({sr,srs,sl,sls,b_s,b_us}!==96'sh0000_ffff_0000_0000_ffff_0001) $stop; + 2: if ({sr,srs,sl,sls,b_s,b_us}!==96'sh458d_c58d_1636_1636_0000_0000) $stop; + 3: if ({sr,srs,sl,sls,b_s,b_us}!==96'sh0000_ffff_0000_0000_ffff_0001) $stop; + 4: if ({sr,srs,sl,sls,b_s,b_us}!==96'sh0000_0000_0000_0000_ffff_0001) $stop; + 5: if ({sr,srs,sl,sls,b_s,b_us}!==96'sh1055_1055_0550_0550_0000_0000) $stop; + 6: if ({sr,srs,sl,sls,b_s,b_us}!==96'sh0000_ffff_0000_0000_ffff_0001) $stop; + 7: if ({sr,srs,sl,sls,b_s,b_us}!==96'sh1222_1222_222c_222c_0000_0000) $stop; + 8: ; + 9: ; endcase end endmodule module by_width ( - input clk - ); - parameter WIDTH=1; + input clk + ); + parameter WIDTH=1; - reg signed i1; + reg signed i1; reg signed [62:0] i63; reg signed [64:0] i65; @@ -188,19 +188,19 @@ module by_width ( i63 <= {63{cyc[0]}}; i65 <= {65{cyc[0]}}; case (cyc) - 1: begin - if (i1extp != {WIDTH{1'b0}}) $stop; - if (i1ext != {WIDTH{1'b0}}) $stop; - if (i63ext != {WIDTH{1'b0}}) $stop; - if (i65ext != {WIDTH{1'b0}}) $stop; - end - 2: begin - if (i1extp != {WIDTH{1'b1}}) $stop; - if (i1ext != {WIDTH{1'b1}}) $stop; - if (i63ext != {WIDTH{1'b1}}) $stop; - if (i65ext != {WIDTH{1'b1}}) $stop; - end - default: ; + 1: begin + if (i1extp != {WIDTH{1'b0}}) $stop; + if (i1ext != {WIDTH{1'b0}}) $stop; + if (i63ext != {WIDTH{1'b0}}) $stop; + if (i65ext != {WIDTH{1'b0}}) $stop; + end + 2: begin + if (i1extp != {WIDTH{1'b1}}) $stop; + if (i1ext != {WIDTH{1'b1}}) $stop; + if (i63ext != {WIDTH{1'b1}}) $stop; + if (i65ext != {WIDTH{1'b1}}) $stop; + end + default: ; endcase end endmodule diff --git a/test_regress/t/t_math_signed2.v b/test_regress/t/t_math_signed2.v index 41337b3d7..edfb02686 100644 --- a/test_regress/t/t_math_signed2.v +++ b/test_regress/t/t_math_signed2.v @@ -32,7 +32,7 @@ module t (/*AUTOARG*/ `endif // delay line shift for (k=31;k>0;k=k-1) begin - delay_minmax[k] = delay_minmax[k-1]; + delay_minmax[k] = delay_minmax[k-1]; end delay_minmax[0] = filtered_data; `ifdef TEST_VERBOSE @@ -47,21 +47,21 @@ module t (/*AUTOARG*/ $write("min init: %d\n", min); `endif for(k=0;k<32;k=k+1) begin - if ((delay_minmax[k]) > $signed(max)) - max = delay_minmax[k]; - if ((delay_minmax[k]) < $signed(min)) - min = delay_minmax[k]; + if ((delay_minmax[k]) > $signed(max)) + max = delay_minmax[k]; + if ((delay_minmax[k]) < $signed(min)) + min = delay_minmax[k]; end `ifdef TEST_VERBOSE $write("max: %d\n", max); $write("min: %d\n", min); `endif if (min == 127) begin - $stop; + $stop; end else if (filtered_data >= -61) begin - $write("*-* All Finished *-*\n"); - $finish; + $write("*-* All Finished *-*\n"); + $finish; end end endmodule diff --git a/test_regress/t/t_math_signed3.v b/test_regress/t/t_math_signed3.v index 3deed359d..fcc602242 100644 --- a/test_regress/t/t_math_signed3.v +++ b/test_regress/t/t_math_signed3.v @@ -11,40 +11,40 @@ module t (/*AUTOARG*/); // verilator lint_off WIDTH wire [1:0] bug729_au = ~0; wire signed [1:0] bug729_as = ~0; - wire [2:0] bug729_b = ~0; + wire [2:0] bug729_b = ~0; // the $signed output is unsigned because the input is unsigned; the signedness does not change. - wire [0:0] bug729_yuu = $signed(2'b11) == 3'b111; //1'b0 - wire [0:0] bug729_ysu = $signed(2'SB11) == 3'b111; //1'b0 - wire [0:0] bug729_yus = $signed(2'b11) == 3'sb111; //1'b1 - wire [0:0] bug729_yss = $signed(2'sb11) == 3'sb111; //1'b1 - wire [0:0] bug729_zuu = 2'sb11 == 3'b111; //1'b0 - wire [0:0] bug729_zsu = 2'sb11 == 3'b111; //1'b0 - wire [0:0] bug729_zus = 2'sb11 == 3'sb111; //1'b1 - wire [0:0] bug729_zss = 2'sb11 == 3'sb111; //1'b1 + wire [0:0] bug729_yuu = $signed(2'b11) == 3'b111; //1'b0 + wire [0:0] bug729_ysu = $signed(2'SB11) == 3'b111; //1'b0 + wire [0:0] bug729_yus = $signed(2'b11) == 3'sb111; //1'b1 + wire [0:0] bug729_yss = $signed(2'sb11) == 3'sb111; //1'b1 + wire [0:0] bug729_zuu = 2'sb11 == 3'b111; //1'b0 + wire [0:0] bug729_zsu = 2'sb11 == 3'b111; //1'b0 + wire [0:0] bug729_zus = 2'sb11 == 3'sb111; //1'b1 + wire [0:0] bug729_zss = 2'sb11 == 3'sb111; //1'b1 - wire [3:0] bug733_a = 4'b0010; - wire [3:0] bug733_yu = $signed(|bug733_a); // 4'b1111 note | is always unsigned + wire [3:0] bug733_a = 4'b0010; + wire [3:0] bug733_yu = $signed(|bug733_a); // 4'b1111 note | is always unsigned wire signed [3:0] bug733_ys = $signed(|bug733_a); // 4'b1111 - wire [3:0] bug733_zu = $signed(2'b11); // 4'b1111 + wire [3:0] bug733_zu = $signed(2'b11); // 4'b1111 wire signed [3:0] bug733_zs = $signed(2'sb11); // 4'b1111 // When RHS of assignment is fewer bits than lhs, RHS sign or zero extends based on RHS's sign - wire [3:0] bug733_qu = 2'sb11; // 4'b1111 + wire [3:0] bug733_qu = 2'sb11; // 4'b1111 wire signed [3:0] bug733_qs = 2'sb11; // 4'b1111 reg signed [32:0] bug349_s; reg signed [32:0] bug349_u; wire signed [1:0] sb11 = 2'sb11; - wire [3:0] subout_u; + wire [3:0] subout_u; sub sub (.a(2'sb11), .z(subout_u)); initial `checkh(subout_u, 4'b1111); - wire [5:0] cond_a = 1'b1 ? 3'sb111 : 5'sb11111; + wire [5:0] cond_a = 1'b1 ? 3'sb111 : 5'sb11111; initial `checkh(cond_a, 6'b111111); - wire [5:0] cond_b = 1'b0 ? 3'sb111 : 5'sb11111; + wire [5:0] cond_b = 1'b0 ? 3'sb111 : 5'sb11111; initial `checkh(cond_b, 6'b111111); initial begin @@ -81,13 +81,13 @@ module t (/*AUTOARG*/); `checkh(bug349_s,33'he); case (2'sb11) - 4'b1111: ; - default: $stop; + 4'b1111: ; + default: $stop; endcase case (sb11) - 4'b1111: ; - default: $stop; + 4'b1111: ; + default: $stop; endcase $write("*-* All Finished *-*\n"); @@ -96,6 +96,6 @@ module t (/*AUTOARG*/); endmodule module sub (input [3:0] a, - output [3:0] z); + output [3:0] z); assign z = a; endmodule diff --git a/test_regress/t/t_math_signed4.v b/test_regress/t/t_math_signed4.v index 0cec8a318..31021e729 100644 --- a/test_regress/t/t_math_signed4.v +++ b/test_regress/t/t_math_signed4.v @@ -113,9 +113,9 @@ module t (/*AUTOARG*/); // If any part of case is real, all is real case (22) - 22.0: ; - 22.1: $stop; - default: $stop; + 22.0: ; + 22.1: $stop; + default: $stop; endcase // bug759 diff --git a/test_regress/t/t_math_signed5.v b/test_regress/t/t_math_signed5.v index c6ea2cb32..b4c2b9ca0 100644 --- a/test_regress/t/t_math_signed5.v +++ b/test_regress/t/t_math_signed5.v @@ -21,18 +21,18 @@ reg signed [3:0] w4_s; reg signed [4:0] w5_s; - reg [2:0] w3_u; - reg [3:0] w4_u; - reg [4:0] w5_u; - reg [5:0] w6_u; - reg [15:0] w16a_u; - reg [15:0] w16_u; - reg [31:0] w32_u; - real r; + reg [2:0] w3_u; + reg [3:0] w4_u; + reg [4:0] w5_u; + reg [5:0] w6_u; + reg [15:0] w16a_u; + reg [15:0] w16_u; + reg [31:0] w32_u; + real r; reg signed [4:0] bug754_a; - integer i; + integer i; //verilator lint_off WIDTH wire a = (5'b0 == (5'sb11111 >>> 3'd7)); @@ -53,7 +53,7 @@ //====================================================================== - if ((-1 >>> 3) != -1) $stop; // Decimals are signed + if ((-1 >>> 3) != -1) $stop; // Decimals are signed i = 3'sb111 >>> 3; `checkh(i, -1); diff --git a/test_regress/t/t_math_signed7.v b/test_regress/t/t_math_signed7.v index 0ed55b0b0..6cadf344f 100644 --- a/test_regress/t/t_math_signed7.v +++ b/test_regress/t/t_math_signed7.v @@ -19,26 +19,26 @@ module t (/*AUTOARG*/ reg aaa_ltu, aaa_lts; always @(posedge clk) begin - in_op1 = 4'sb1110; - in_op2 = 4'b0010; - aaa_ltu = in_op1 < in_op2; - // bug999 - aaa_lts = $signed(in_op1) < $signed(in_op2); - `checkh (aaa_ltu, 1'b0); - `checkh (aaa_lts, 1'b1); + in_op1 = 4'sb1110; + in_op2 = 4'b0010; + aaa_ltu = in_op1 < in_op2; + // bug999 + aaa_lts = $signed(in_op1) < $signed(in_op2); + `checkh (aaa_ltu, 1'b0); + `checkh (aaa_lts, 1'b1); end generate if (1) begin always @(posedge clk) begin - in_op1 = 4'sb1110; - in_op2 = 4'b0010; - alu_ltu = in_op1 < in_op2; - // bug999 - alu_lts = $signed(in_op1) < $signed(in_op2); - `checkh (alu_ltu, 1'b0); - `checkh (alu_lts, 1'b1); - $write("*-* All Finished *-*\n"); - $finish; + in_op1 = 4'sb1110; + in_op2 = 4'b0010; + alu_ltu = in_op1 < in_op2; + // bug999 + alu_lts = $signed(in_op1) < $signed(in_op2); + `checkh (alu_ltu, 1'b0); + `checkh (alu_lts, 1'b1); + $write("*-* All Finished *-*\n"); + $finish; end end endgenerate diff --git a/test_regress/t/t_math_signed_wire.v b/test_regress/t/t_math_signed_wire.v index 0f0d3fc62..806044ddd 100644 --- a/test_regress/t/t_math_signed_wire.v +++ b/test_regress/t/t_math_signed_wire.v @@ -31,8 +31,8 @@ module t (/*AUTOARG*/ endmodule module Test1 (output [7:0] au); - wire [7:0] b; - wire signed [3:0] c; + wire [7:0] b; + wire signed [3:0] c; // verilator lint_off WIDTH assign c=-1; // 'hf @@ -43,8 +43,8 @@ endmodule module Test2 (output [7:0] as); - wire signed [7:0] b; - wire signed [3:0] c; + wire signed [7:0] b; + wire signed [3:0] c; // verilator lint_off WIDTH assign c=-1; // 'hf diff --git a/test_regress/t/t_math_svl.v b/test_regress/t/t_math_svl.v index 5858e5b80..04d808141 100644 --- a/test_regress/t/t_math_svl.v +++ b/test_regress/t/t_math_svl.v @@ -15,14 +15,14 @@ module t (/*AUTOARG*/ reg [49:0] q; reg [79:0] w; reg [4:0] lc; - reg lo; - reg l0; + reg lo; + reg l0; reg [5:0] qc; - reg qo; - reg q0; + reg qo; + reg q0; reg [6:0] wc; - reg wo; - reg w0; + reg wo; + reg w0; always @* begin lc = $countones(l); @@ -66,73 +66,73 @@ module t (/*AUTOARG*/ always @ (posedge clk) begin if (cyc!=0) begin - cyc <= cyc + 1; - //$write("%d %x %d %x %x %x %d %x %x %x %d %x %x\n", - // cyc, l, lc, lo, l0, q,qc,qo,q0, w,wc,wo,w0); - if (cyc_com != cyc_com) $stop; - if (cyc_d1 != cyc-1) $stop; - if (cyc==1) begin - l <= 16'b0; - q <= 50'h0; - w <= 80'h0; - end - if (cyc==2) begin - l <= ~16'b0; - q <= ~50'h0; - w <= ~80'h0; - // - if ({lc,lo,l0} != {5'd0,1'b0,1'b1}) $stop; - if ({qc,qo,q0} != {6'd0,1'b0,1'b1}) $stop; - if ({wc,wo,w0} != {7'd0,1'b0,1'b1}) $stop; - end - if (cyc==3) begin - l <= 16'b0010110010110111; - q <= 50'h01_1111_0001; - w <= 80'h0100_0000_0f00_00f0_0000; - // - if ({lc,lo,l0} != {5'd16,1'b0,1'b0}) $stop; - if ({qc,qo,q0} != {6'd50,1'b0,1'b0}) $stop; - if ({wc,wo,w0} != {7'd80,1'b0,1'b0}) $stop; - end - if (cyc==4) begin - l <= 16'b0000010000000000; - q <= 50'h1_0000_0000; - w <= 80'h010_00000000_00000000; - // - if ({lc,lo,l0} != {5'd9,1'b0,1'b0}) $stop; - if ({qc,qo,q0} != {6'd6,1'b0,1'b0}) $stop; - if ({wc,wo,w0} != {7'd9,1'b0,1'b0}) $stop; - end - if (cyc==5) begin - l <= 16'b0000000100000000; - q <= 50'h8000_0000_0000; - w <= 80'h10_00000000_00000000; - // - if ({lc,lo,l0} != {5'd1,1'b1,1'b1}) $stop; - if ({qc,qo,q0} != {6'd1,1'b1,1'b1}) $stop; - if ({wc,wo,w0} != {7'd1,1'b1,1'b1}) $stop; - end - if (cyc==6) begin - l <= 16'b0000100100000000; - q <= 50'h01_00000100; - w <= 80'h01_00000100_00000000; - // - if ({lc,lo,l0} != {5'd1,1'b1,1'b1}) $stop; - if ({qc,qo,q0} != {6'd1,1'b1,1'b1}) $stop; - if ({wc,wo,w0} != {7'd1,1'b1,1'b1}) $stop; - end - if (cyc==7) begin - // - if ({lc,lo,l0} != {5'd2,1'b0,1'b0}) $stop; - if ({qc,qo,q0} != {6'd2,1'b0,1'b0}) $stop; - if ({wc,wo,w0} != {7'd2,1'b0,1'b0}) $stop; - end - if (cyc==8) begin - end - if (cyc==9) begin - $write("*-* All Finished *-*\n"); - $finish; - end + cyc <= cyc + 1; + //$write("%d %x %d %x %x %x %d %x %x %x %d %x %x\n", + // cyc, l, lc, lo, l0, q,qc,qo,q0, w,wc,wo,w0); + if (cyc_com != cyc_com) $stop; + if (cyc_d1 != cyc-1) $stop; + if (cyc==1) begin + l <= 16'b0; + q <= 50'h0; + w <= 80'h0; + end + if (cyc==2) begin + l <= ~16'b0; + q <= ~50'h0; + w <= ~80'h0; + // + if ({lc,lo,l0} != {5'd0,1'b0,1'b1}) $stop; + if ({qc,qo,q0} != {6'd0,1'b0,1'b1}) $stop; + if ({wc,wo,w0} != {7'd0,1'b0,1'b1}) $stop; + end + if (cyc==3) begin + l <= 16'b0010110010110111; + q <= 50'h01_1111_0001; + w <= 80'h0100_0000_0f00_00f0_0000; + // + if ({lc,lo,l0} != {5'd16,1'b0,1'b0}) $stop; + if ({qc,qo,q0} != {6'd50,1'b0,1'b0}) $stop; + if ({wc,wo,w0} != {7'd80,1'b0,1'b0}) $stop; + end + if (cyc==4) begin + l <= 16'b0000010000000000; + q <= 50'h1_0000_0000; + w <= 80'h010_00000000_00000000; + // + if ({lc,lo,l0} != {5'd9,1'b0,1'b0}) $stop; + if ({qc,qo,q0} != {6'd6,1'b0,1'b0}) $stop; + if ({wc,wo,w0} != {7'd9,1'b0,1'b0}) $stop; + end + if (cyc==5) begin + l <= 16'b0000000100000000; + q <= 50'h8000_0000_0000; + w <= 80'h10_00000000_00000000; + // + if ({lc,lo,l0} != {5'd1,1'b1,1'b1}) $stop; + if ({qc,qo,q0} != {6'd1,1'b1,1'b1}) $stop; + if ({wc,wo,w0} != {7'd1,1'b1,1'b1}) $stop; + end + if (cyc==6) begin + l <= 16'b0000100100000000; + q <= 50'h01_00000100; + w <= 80'h01_00000100_00000000; + // + if ({lc,lo,l0} != {5'd1,1'b1,1'b1}) $stop; + if ({qc,qo,q0} != {6'd1,1'b1,1'b1}) $stop; + if ({wc,wo,w0} != {7'd1,1'b1,1'b1}) $stop; + end + if (cyc==7) begin + // + if ({lc,lo,l0} != {5'd2,1'b0,1'b0}) $stop; + if ({qc,qo,q0} != {6'd2,1'b0,1'b0}) $stop; + if ({wc,wo,w0} != {7'd2,1'b0,1'b0}) $stop; + end + if (cyc==8) begin + end + if (cyc==9) begin + $write("*-* All Finished *-*\n"); + $finish; + end end end diff --git a/test_regress/t/t_math_svl2.v b/test_regress/t/t_math_svl2.v index 022f62911..ccd1a1c7a 100644 --- a/test_regress/t/t_math_svl2.v +++ b/test_regress/t/t_math_svl2.v @@ -14,27 +14,27 @@ module t (/*AUTOARG*/ integer cyc; initial cyc=1; always @ (posedge clk) begin if (cyc!=0) begin - cyc <= cyc + 1; - if (cyc==1) begin - // New number format - if ('0 !== {66{1'b0}}) $stop; - if ('1 !== {66{1'b1}}) $stop; - if ('x !== {66{1'bx}}) $stop; - if ('z !== {66{1'bz}}) $stop; -`ifndef NC // NC-Verilog 5.50-s09 chokes on this test - if ("\v" != 8'd11) $stop; - if ("\f" != 8'd12) $stop; - if ("\a" != 8'd7) $stop; - if ("\x9a" != 8'h9a) $stop; - if ("\xf1" != 8'hf1) $stop; + cyc <= cyc + 1; + if (cyc==1) begin + // New number format + if ('0 !== {66{1'b0}}) $stop; + if ('1 !== {66{1'b1}}) $stop; + if ('x !== {66{1'bx}}) $stop; + if ('z !== {66{1'bz}}) $stop; +`ifndef NC // NC-Verilog 5.50-s09 chokes on this test + if ("\v" != 8'd11) $stop; + if ("\f" != 8'd12) $stop; + if ("\a" != 8'd7) $stop; + if ("\x9a" != 8'h9a) $stop; + if ("\xf1" != 8'hf1) $stop; `endif - end - if (cyc==8) begin - end - if (cyc==9) begin - $write("*-* All Finished *-*\n"); - $finish; - end + end + if (cyc==8) begin + end + if (cyc==9) begin + $write("*-* All Finished *-*\n"); + $finish; + end end end diff --git a/test_regress/t/t_math_swap.v b/test_regress/t/t_math_swap.v index e59e1c5d8..b32d88b28 100644 --- a/test_regress/t/t_math_swap.v +++ b/test_regress/t/t_math_swap.v @@ -10,34 +10,34 @@ module t (/*AUTOARG*/ ); input clk; - integer cyc = 0; - reg [63:0] crc; - reg [63:0] sum; + integer cyc = 0; + reg [63:0] crc; + reg [63:0] sum; // Take CRC data and apply to testblock inputs wire [31:0] Operand1 = crc[31:0]; wire [15:0] Operand2 = crc[47:32]; - wire Unsigned = crc[48]; - reg rst; + wire Unsigned = crc[48]; + reg rst; parameter wl = 16; /*AUTOWIRE*/ // Beginning of automatic wires (for undeclared instantiated-module outputs) - wire [wl-1:0] Quotient; // From test of Test.v - wire [wl-1:0] Remainder; // From test of Test.v + wire [wl-1:0] Quotient; // From test of Test.v + wire [wl-1:0] Remainder; // From test of Test.v // End of automatics Test test (/*AUTOINST*/ - // Outputs - .Quotient (Quotient[wl-1:0]), - .Remainder (Remainder[wl-1:0]), - // Inputs - .Operand1 (Operand1[wl*2-1:0]), - .Operand2 (Operand2[wl-1:0]), - .clk (clk), - .rst (rst), - .Unsigned (Unsigned)); + // Outputs + .Quotient (Quotient[wl-1:0]), + .Remainder (Remainder[wl-1:0]), + // Inputs + .Operand1 (Operand1[wl*2-1:0]), + .Operand2 (Operand2[wl-1:0]), + .clk (clk), + .rst (rst), + .Unsigned (Unsigned)); // Aggregate outputs into a single result vector wire [63:0] result = {32'h0, Quotient, Remainder}; @@ -52,26 +52,26 @@ module t (/*AUTOARG*/ `endif cyc <= cyc + 1; if (cyc < 20 || test.Iteration==4'd15) begin - crc <= {crc[62:0], crc[63] ^ crc[2] ^ crc[0]}; + crc <= {crc[62:0], crc[63] ^ crc[2] ^ crc[0]}; end sum <= result ^ {sum[62:0], sum[63] ^ sum[2] ^ sum[0]}; if (cyc==0) begin - // Setup - crc <= 64'h5aef0c8d_d70a4497; - rst <= 1'b1; + // Setup + crc <= 64'h5aef0c8d_d70a4497; + rst <= 1'b1; end else if (cyc<20) begin - sum <= 64'h0; - rst <= 1'b0; + sum <= 64'h0; + rst <= 1'b0; end else if (cyc<90) begin end else if (cyc==99) begin - $write("[%0t] cyc==%0d crc=%x sum=%x\n", $time, cyc, crc, sum); - if (crc !== 64'h8dd70a44972ad809) $stop; - if (sum !== `EXPECTED_SUM) $stop; - $write("*-* All Finished *-*\n"); - $finish; + $write("[%0t] cyc==%0d crc=%x sum=%x\n", $time, cyc, crc, sum); + if (crc !== 64'h8dd70a44972ad809) $stop; + if (sum !== `EXPECTED_SUM) $stop; + $write("*-* All Finished *-*\n"); + $finish; end end @@ -88,32 +88,32 @@ module Test(clk, rst, Operand1, Operand2, Unsigned, Quotient, Remainder); reg Cy, Overflow, Sign1, Sign2, Zero, Negative; reg [wl-1:0] ah,al,Quotient, Remainder; - reg [3:0] Iteration; + reg [3:0] Iteration; reg [wl-1:0] sub_quot,op; - reg ah_ext; + reg ah_ext; - reg [1:0] a,b,c,d,e; + reg [1:0] a,b,c,d,e; always @(posedge clk) begin if (!rst) begin - {a,b,c,d,e} = Operand1[9:0]; - {a,b,c,d,e} = {e,d,c,b,a}; - if (a != Operand1[1:0]) $stop; - if (b != Operand1[3:2]) $stop; - if (c != Operand1[5:4]) $stop; - if (d != Operand1[7:6]) $stop; - if (e != Operand1[9:8]) $stop; + {a,b,c,d,e} = Operand1[9:0]; + {a,b,c,d,e} = {e,d,c,b,a}; + if (a != Operand1[1:0]) $stop; + if (b != Operand1[3:2]) $stop; + if (c != Operand1[5:4]) $stop; + if (d != Operand1[7:6]) $stop; + if (e != Operand1[9:8]) $stop; end end always @(posedge clk) begin if (rst) begin - Iteration <= 0; + Iteration <= 0; Quotient <= 0; Remainder <= 0; end else begin - if (Iteration == 0) begin + if (Iteration == 0) begin {ah,al} = Operand1; op = Operand2; Cy = 0; @@ -121,44 +121,44 @@ module Test(clk, rst, Operand1, Operand2, Unsigned, Quotient, Remainder); Sign1 = (~Unsigned)&ah[wl-1]; Sign2 = (~Unsigned)&(ah[wl-1]^op[wl-1]); if (Sign1) {ah,al} = -{ah,al}; - end + end `define BUG1 `ifdef BUG1 - {ah_ext,ah,al} = {ah,al,Cy}; + {ah_ext,ah,al} = {ah,al,Cy}; `else - ah_ext = ah[15]; - ah[15:1] = ah[14:0]; - ah[0] = al[15]; - al[15:1] = al[14:0]; - al[0] = Cy; + ah_ext = ah[15]; + ah[15:1] = ah[14:0]; + ah[0] = al[15]; + al[15:1] = al[14:0]; + al[0] = Cy; `endif `ifdef TEST_VERBOSE - $display("%x %x %x %x %x %x %x %x %x", - Iteration, ah, al, Quotient, Remainder, Overflow, ah_ext, sub_quot, Cy); + $display("%x %x %x %x %x %x %x %x %x", + Iteration, ah, al, Quotient, Remainder, Overflow, ah_ext, sub_quot, Cy); `endif - {Cy,sub_quot} = (~Unsigned)&op[wl-1]? {ah_ext,ah}+op : {ah_ext,ah} - {1'b1,op}; - if (Cy) - begin + {Cy,sub_quot} = (~Unsigned)&op[wl-1]? {ah_ext,ah}+op : {ah_ext,ah} - {1'b1,op}; + if (Cy) + begin {ah_ext,ah} = {1'b0,sub_quot}; - end - if (Iteration != 15 ) - begin + end + if (Iteration != 15 ) + begin if (ah_ext) Overflow = 1; - end - else - begin + end + else + begin if (al[14] && ~Unsigned) Overflow = 1; Quotient <= Sign2 ? -{al[14:0],Cy} : {al[14:0],Cy}; Remainder <= Sign1 ? -ah : ah; if (Overflow) - begin - Quotient <= Sign2 ? 16'h8001 : {Unsigned,{15{1'b1}}}; - Remainder <= Unsigned ? 16'hffff : 16'h8000; - Zero = 1; - Negative = 1; - end - end - Iteration <= Iteration + 1; // Count number of times this instruction is repeated + begin + Quotient <= Sign2 ? 16'h8001 : {Unsigned,{15{1'b1}}}; + Remainder <= Unsigned ? 16'hffff : 16'h8000; + Zero = 1; + Negative = 1; + end + end + Iteration <= Iteration + 1; // Count number of times this instruction is repeated end end diff --git a/test_regress/t/t_math_trig.v b/test_regress/t/t_math_trig.v index 61204358c..91e9d3066 100644 --- a/test_regress/t/t_math_trig.v +++ b/test_regress/t/t_math_trig.v @@ -13,53 +13,53 @@ module t (/*AUTOARG*/ input clk; real r, r2; - integer cyc = 0; + integer cyc = 0; task check(integer line, real got, real ex); if (got != ex) begin if ((got > ex ? got - ex : ex - got) > 0.000001) begin - $display("%%Error: Line %0d: Bad result, got=%0.99g expect=%0.99g",line,got,ex); - $stop; - end + $display("%%Error: Line %0d: Bad result, got=%0.99g expect=%0.99g",line,got,ex); + $stop; + end end endtask initial begin // Check constant propagation // Note $abs is not defined in SystemVerilog (as of 2012) - check(`__LINE__, $ceil(-1.2), -1); - check(`__LINE__, $ceil(1.2), 2); - check(`__LINE__, $exp(1.2), 3.3201169227365472380597566370852291584014892578125); - check(`__LINE__, $exp(0.0), 1); - check(`__LINE__, $exp(-1.2), 0.301194211912202136627314530414878390729427337646484375); - check(`__LINE__, $floor(-1.2), -2); - check(`__LINE__, $floor(1.2), 1); - check(`__LINE__, $ln(1.2), 0.1823215567939545922460098381634452380239963531494140625); - //check(`__LINE__, $ln(0), 0); // Bad value - //check(`__LINE__, $ln(-1.2), 0); // Bad value - check(`__LINE__, $log10(1.2), 0.07918124604762481755226843915806966833770275115966796875); - //check(`__LINE__, $log10(0), 0); // Bad value - //check(`__LINE__, $log10(-1.2), 0); - check(`__LINE__, $pow(2.3,1.2), 2.71689843249914897427288451581262052059173583984375); - check(`__LINE__, $pow(2.3,-1.2), 0.368066758785732861536388327294844202697277069091796875); - //check(`__LINE__, $pow(-2.3,1.2),0); // Bad value - check(`__LINE__, $sqrt(1.2), 1.095445115010332148841598609578795731067657470703125); - //check(`__LINE__, $sqrt(-1.2), 0); // Bad value + check(`__LINE__, $ceil(-1.2), -1); + check(`__LINE__, $ceil(1.2), 2); + check(`__LINE__, $exp(1.2), 3.3201169227365472380597566370852291584014892578125); + check(`__LINE__, $exp(0.0), 1); + check(`__LINE__, $exp(-1.2), 0.301194211912202136627314530414878390729427337646484375); + check(`__LINE__, $floor(-1.2), -2); + check(`__LINE__, $floor(1.2), 1); + check(`__LINE__, $ln(1.2), 0.1823215567939545922460098381634452380239963531494140625); + //check(`__LINE__, $ln(0), 0); // Bad value + //check(`__LINE__, $ln(-1.2), 0); // Bad value + check(`__LINE__, $log10(1.2), 0.07918124604762481755226843915806966833770275115966796875); + //check(`__LINE__, $log10(0), 0); // Bad value + //check(`__LINE__, $log10(-1.2), 0); + check(`__LINE__, $pow(2.3,1.2), 2.71689843249914897427288451581262052059173583984375); + check(`__LINE__, $pow(2.3,-1.2), 0.368066758785732861536388327294844202697277069091796875); + //check(`__LINE__, $pow(-2.3,1.2),0); // Bad value + check(`__LINE__, $sqrt(1.2), 1.095445115010332148841598609578795731067657470703125); + //check(`__LINE__, $sqrt(-1.2), 0); // Bad value check(`__LINE__, ((1.5)**(1.25)), 1.660023); - check(`__LINE__, $acos (0.2), 1.369438406); // Arg1 is -1..1 - check(`__LINE__, $acosh(1.2), 0.622362503); - check(`__LINE__, $asin (0.2), 0.201357920); // Arg1 is -1..1 - check(`__LINE__, $asinh(1.2), 1.015973134); - check(`__LINE__, $atan (0.2), 0.197395559); - check(`__LINE__, $atan2(0.2,2.3), 0.086738338); // Arg1 is -1..1 - check(`__LINE__, $atanh(0.2), 0.202732554); // Arg1 is -1..1 - check(`__LINE__, $cos (1.2), 0.362357754); - check(`__LINE__, $cosh (1.2), 1.810655567); - check(`__LINE__, $hypot(1.2,2.3), 2.594224354); - check(`__LINE__, $sin (1.2), 0.932039085); - check(`__LINE__, $sinh (1.2), 1.509461355); - check(`__LINE__, $tan (1.2), 2.572151622); - check(`__LINE__, $tanh (1.2), 0.833654607); + check(`__LINE__, $acos (0.2), 1.369438406); // Arg1 is -1..1 + check(`__LINE__, $acosh(1.2), 0.622362503); + check(`__LINE__, $asin (0.2), 0.201357920); // Arg1 is -1..1 + check(`__LINE__, $asinh(1.2), 1.015973134); + check(`__LINE__, $atan (0.2), 0.197395559); + check(`__LINE__, $atan2(0.2,2.3), 0.086738338); // Arg1 is -1..1 + check(`__LINE__, $atanh(0.2), 0.202732554); // Arg1 is -1..1 + check(`__LINE__, $cos (1.2), 0.362357754); + check(`__LINE__, $cosh (1.2), 1.810655567); + check(`__LINE__, $hypot(1.2,2.3), 2.594224354); + check(`__LINE__, $sin (1.2), 0.932039085); + check(`__LINE__, $sinh (1.2), 1.509461355); + check(`__LINE__, $tan (1.2), 2.572151622); + check(`__LINE__, $tanh (1.2), 0.833654607); end real sum_ceil; @@ -96,58 +96,58 @@ module t (/*AUTOARG*/ if (cyc==0) begin end else if (cyc<90) begin - // Setup - sum_ceil += 1.0+$ceil(r); - sum_exp += 1.0+$exp(r); - sum_floor += 1.0+$floor(r); - if (r > 0.0) sum_ln += 1.0+$ln(r); - if (r > 0.0) sum_log10 += 1.0+$log10(r); - // Pow requires if arg1<0 then arg1 integral - sum_pow1 += 1.0+$pow(2.3,r); - if (r >= 0.0) sum_pow2 += 1.0+$pow(r,2.3); - if (r >= 0.0) sum_sqrt += 1.0+$sqrt(r); + // Setup + sum_ceil += 1.0+$ceil(r); + sum_exp += 1.0+$exp(r); + sum_floor += 1.0+$floor(r); + if (r > 0.0) sum_ln += 1.0+$ln(r); + if (r > 0.0) sum_log10 += 1.0+$log10(r); + // Pow requires if arg1<0 then arg1 integral + sum_pow1 += 1.0+$pow(2.3,r); + if (r >= 0.0) sum_pow2 += 1.0+$pow(r,2.3); + if (r >= 0.0) sum_sqrt += 1.0+$sqrt(r); - if (r>=-1.0 && r<=1.0) sum_acos += 1.0+$acos (r); - if (r>=1.0) sum_acosh += 1.0+$acosh(r); - if (r>=-1.0 && r<=1.0) sum_asin += 1.0+$asin (r); - sum_asinh += 1.0+$asinh(r); - sum_atan += 1.0+$atan (r); - if (r>=-1.0 && r<=1.0) sum_atan2 += 1.0+$atan2(r,2.3); - if (r>=-1.0 && r<=1.0) sum_atanh += 1.0+$atanh(r); - sum_cos += 1.0+$cos (r); - sum_cosh += 1.0+$cosh (r); - sum_hypot += 1.0+$hypot(r,2.3); - sum_sin += 1.0+$sin (r); - sum_sinh += 1.0+$sinh (r); - sum_tan += 1.0+$tan (r); - sum_tanh += 1.0+$tanh (r); + if (r>=-1.0 && r<=1.0) sum_acos += 1.0+$acos (r); + if (r>=1.0) sum_acosh += 1.0+$acosh(r); + if (r>=-1.0 && r<=1.0) sum_asin += 1.0+$asin (r); + sum_asinh += 1.0+$asinh(r); + sum_atan += 1.0+$atan (r); + if (r>=-1.0 && r<=1.0) sum_atan2 += 1.0+$atan2(r,2.3); + if (r>=-1.0 && r<=1.0) sum_atanh += 1.0+$atanh(r); + sum_cos += 1.0+$cos (r); + sum_cosh += 1.0+$cosh (r); + sum_hypot += 1.0+$hypot(r,2.3); + sum_sin += 1.0+$sin (r); + sum_sinh += 1.0+$sinh (r); + sum_tan += 1.0+$tan (r); + sum_tanh += 1.0+$tanh (r); end else if (cyc==99) begin - check (`__LINE__, sum_ceil, 85); - check (`__LINE__, sum_exp, 608.06652950); - check (`__LINE__, sum_floor, 4); - check (`__LINE__, sum_ln, 55.830941633); - check (`__LINE__, sum_log10, 46.309585076); - check (`__LINE__, sum_pow1, 410.98798177); - check (`__LINE__, sum_pow2, 321.94765689); - check (`__LINE__, sum_sqrt, 92.269677253); - check (`__LINE__, sum_acos, 53.986722862); - check (`__LINE__, sum_acosh, 72.685208498); - check (`__LINE__, sum_asin, 21); - check (`__LINE__, sum_asinh, 67.034973416); - check (`__LINE__, sum_atan, 75.511045389); - check (`__LINE__, sum_atan2, 21); - check (`__LINE__, sum_atanh, 0); - check (`__LINE__, sum_cos, 72.042023124); - check (`__LINE__, sum_cosh, 1054.0178222); - check (`__LINE__, sum_hypot, 388.92858406); - check (`__LINE__, sum_sin, 98.264184989); + check (`__LINE__, sum_ceil, 85); + check (`__LINE__, sum_exp, 608.06652950); + check (`__LINE__, sum_floor, 4); + check (`__LINE__, sum_ln, 55.830941633); + check (`__LINE__, sum_log10, 46.309585076); + check (`__LINE__, sum_pow1, 410.98798177); + check (`__LINE__, sum_pow2, 321.94765689); + check (`__LINE__, sum_sqrt, 92.269677253); + check (`__LINE__, sum_acos, 53.986722862); + check (`__LINE__, sum_acosh, 72.685208498); + check (`__LINE__, sum_asin, 21); + check (`__LINE__, sum_asinh, 67.034973416); + check (`__LINE__, sum_atan, 75.511045389); + check (`__LINE__, sum_atan2, 21); + check (`__LINE__, sum_atanh, 0); + check (`__LINE__, sum_cos, 72.042023124); + check (`__LINE__, sum_cosh, 1054.0178222); + check (`__LINE__, sum_hypot, 388.92858406); + check (`__LINE__, sum_sin, 98.264184989); check (`__LINE__, sum_sinh, -356.9512927); - check (`__LINE__, sum_tan, 1.7007946043); - check (`__LINE__, sum_tanh, 79.003199681); + check (`__LINE__, sum_tan, 1.7007946043); + check (`__LINE__, sum_tanh, 79.003199681); - $write("*-* All Finished *-*\n"); - $finish; + $write("*-* All Finished *-*\n"); + $finish; end end endmodule diff --git a/test_regress/t/t_math_vgen.v b/test_regress/t/t_math_vgen.v index ca2ec8bd6..0111649c0 100644 --- a/test_regress/t/t_math_vgen.v +++ b/test_regress/t/t_math_vgen.v @@ -11,7 +11,7 @@ module t (/*AUTOARG*/ input clk; integer cyc; initial cyc=1; - reg check; initial check = 1'b0; + reg check; initial check = 1'b0; // verilator lint_off WIDTH @@ -21,13 +21,13 @@ module t (/*AUTOARG*/ reg [ 58:0] W0101; //=0000000FFFFFFFF always @(posedge clk) begin if (cyc==1) begin - W0095 = ((2'h3)); - W0101 = ({27'h0,({16{(W0095)}})}); + W0095 = ((2'h3)); + W0101 = ({27'h0,({16{(W0095)}})}); end end always @(posedge clk) begin if (cyc==2) begin - if ((W0101) != (59'h0FFFFFFFF)) if (check) $stop; + if ((W0101) != (59'h0FFFFFFFF)) if (check) $stop; end end @@ -41,9 +41,9 @@ module t (/*AUTOARG*/ end always @(posedge clk) begin if (cyc==2) begin - // Width violation, but still... - if (((-W1243) < 32'h01) != (1'h0)) if (check) $stop; - if (({32{W1243}} < 32'h01) != (1'h0)) if (check) $stop; + // Width violation, but still... + if (((-W1243) < 32'h01) != (1'h0)) if (check) $stop; + if (({32{W1243}} < 32'h01) != (1'h0)) if (check) $stop; end end @@ -52,31 +52,31 @@ module t (/*AUTOARG*/ reg [ 0:0] W0344; //=0 always @(posedge clk) begin if (cyc==1) begin - W0344 = 1'b0; + W0344 = 1'b0; end end always @(posedge clk) begin if (cyc==2) begin - if ((W0344) != (1'h0)) if (check) $stop; - if (({116{(((- 95'h7FFFFFFFFFFFFFFFFFFFFFFF) ^ 95'h7FFFFFFFFFFFFFFFFFFFFFFF ) == ({94'h0,W0344}))}})) if (check) $stop; + if ((W0344) != (1'h0)) if (check) $stop; + if (({116{(((- 95'h7FFFFFFFFFFFFFFFFFFFFFFF) ^ 95'h7FFFFFFFFFFFFFFFFFFFFFFF ) == ({94'h0,W0344}))}})) if (check) $stop; end end //============================================================ reg [ 63:0] W0372; //=FFFFFFFFFFFFFFFF - reg [118:0] W0420; //=7FFFFFFFFFFFFFFFFFFFFFFFFFFFFF - reg [115:0] W0421; //=00000000000000000000000000000 + reg [118:0] W0420; //=7FFFFFFFFFFFFFFFFFFFFFFFFFFFFF + reg [115:0] W0421; //=00000000000000000000000000000 always @(posedge clk) begin if (cyc==1) begin - W0372 = ({64{((1'h1))}}); - W0421 = 116'h0; - W0420 = ({119{((W0372) <= (W0372))}}); + W0372 = ({64{((1'h1))}}); + W0421 = 116'h0; + W0420 = ({119{((W0372) <= (W0372))}}); end end always @(posedge clk) begin if (cyc==2) begin - if ((W0420[(- (W0421[115:110]))]) != (1'h1)) if (check) $stop; + if ((W0420[(- (W0421[115:110]))]) != (1'h1)) if (check) $stop; end end @@ -84,46 +84,46 @@ module t (/*AUTOARG*/ // gcc_2_96_bug reg [ 31:0] W0161; //=FFFFFFFF - reg [ 62:0] W0217; //=0000000000000000 - reg [ 53:0] W0219; //=00000000000000 + reg [ 62:0] W0217; //=0000000000000000 + reg [ 53:0] W0219; //=00000000000000 always @(posedge clk) begin if (cyc==1) begin - W0161 = 32'hFFFFFFFF; - W0217 = 63'h0; - W0219 = 54'h0; + W0161 = 32'hFFFFFFFF; + W0217 = 63'h0; + W0219 = 54'h0; end end always @(posedge clk) begin if (cyc==2) begin - if ((W0161) != (32'hFFFFFFFF)) if (check) $stop; - if (((- (W0161)) & ((W0217[62:31]) & ({25'h0,(W0219[53:47])}))) != (32'h00000000)) if (check) $stop; + if ((W0161) != (32'hFFFFFFFF)) if (check) $stop; + if (((- (W0161)) & ((W0217[62:31]) & ({25'h0,(W0219[53:47])}))) != (32'h00000000)) if (check) $stop; end end //============================================================ reg [119:0] W0592; //=000000000000000000000000000000 - reg [ 7:0] W0593; //=70 + reg [ 7:0] W0593; //=70 always @(posedge clk) begin if (cyc==1) begin - W0593 = (((8'h90)) * ((8'hFF))); + W0593 = (((8'h90)) * ((8'hFF))); W0592 = 120'h000000000000000000000000000000; end end always @(posedge clk) begin if (cyc==2) begin - if (((W0592[119:9]) >> ((W0593))) != (111'h0000000000000000000000000000)) if (check) $stop; + if (((W0592[119:9]) >> ((W0593))) != (111'h0000000000000000000000000000)) if (check) $stop; end end //============================================================ reg [127:0] WA1063 ; //=00000000000000000000000000000001 - reg [ 34:0] WA1064 /*verilator public*/; //=7FFFFFFFF - reg [ 62:0] WA1065 ; //=0000000000000000 - reg [ 89:0] WA1066 /*verilator public*/; //=00000000000000000000001 - reg [ 34:0] WA1067 ; //=7FFFFFFFF - reg [111:0] WA1068; + reg [ 34:0] WA1064 /*verilator public*/; //=7FFFFFFFF + reg [ 62:0] WA1065 ; //=0000000000000000 + reg [ 89:0] WA1066 /*verilator public*/; //=00000000000000000000001 + reg [ 34:0] WA1067 ; //=7FFFFFFFF + reg [111:0] WA1068; always @(check) begin WA1067 = (~ (35'h0)); @@ -134,23 +134,23 @@ module t (/*AUTOARG*/ end always @(posedge clk) begin if (cyc==2) begin - if ((WA1063[(WA1064[(WA1065[((5'h04) | (5'h0))+:4])+:3])+:112]) != 112'h0) if (check) $stop; + if ((WA1063[(WA1064[(WA1065[((5'h04) | (5'h0))+:4])+:3])+:112]) != 112'h0) if (check) $stop; end end //============================================================ reg [127:0] WB1063 ; //=00000000000000000000000000000001 - reg [ 34:0] WB1064 /*verilator public*/; //=7FFFFFFFF - reg [ 62:0] WB1065 ; //=0000000000000000 - reg [ 89:0] WB1066 /*verilator public*/; //=00000000000000000000001 - reg [ 34:0] WB1067 ; //=7FFFFFFFF - reg [111:0] WB1068; + reg [ 34:0] WB1064 /*verilator public*/; //=7FFFFFFFF + reg [ 62:0] WB1065 ; //=0000000000000000 + reg [ 89:0] WB1066 /*verilator public*/; //=00000000000000000000001 + reg [ 34:0] WB1067 ; //=7FFFFFFFF + reg [111:0] WB1068; always @(posedge clk) begin if (cyc==1) begin - WB1067 = (~ (35'h0)); - WB1066 = (90'h00000000000000000000001); + WB1067 = (~ (35'h0)); + WB1066 = (90'h00000000000000000000001); end if (cyc==2) WB1065 <= (WB1066[89:27]); if (cyc==3) WB1064 <= (WB1067); @@ -159,8 +159,8 @@ module t (/*AUTOARG*/ end always @(posedge clk) begin if (cyc==9) begin - if (WB1068 != 112'h0) if (check) $stop; - if ((WB1063[(WB1064[(WB1065[((5'h04) | (5'h0))+:4])+:3])+:112]) != 112'h0) if (check) $stop; + if (WB1068 != 112'h0) if (check) $stop; + if ((WB1063[(WB1064[(WB1065[((5'h04) | (5'h0))+:4])+:3])+:112]) != 112'h0) if (check) $stop; end end @@ -295,14 +295,14 @@ module t (/*AUTOARG*/ always @ (posedge clk) begin if (cyc!=0) begin - cyc <= cyc + 1; - if (cyc==18) begin - check <= 1'b1; - end - if (cyc==20) begin - $write("*-* All Finished *-*\n"); - $finish; - end + cyc <= cyc + 1; + if (cyc==18) begin + check <= 1'b1; + end + if (cyc==20) begin + $write("*-* All Finished *-*\n"); + $finish; + end end end endmodule diff --git a/test_regress/t/t_math_vliw.v b/test_regress/t/t_math_vliw.v index 42ba7ff86..4aa2d26e1 100644 --- a/test_regress/t/t_math_vliw.v +++ b/test_regress/t/t_math_vliw.v @@ -23,82 +23,82 @@ module t (/*AUTOARG*/ wire [223:0] bxiouf; vliw vliw ( - // Outputs - .bxiouf (bxiouf), - // Inputs - .mglehy (mglehy[255:0]), - .drricx (drricx[215:0]), - .apqrli (apqrli[15:0]), - .szlfpf (szlfpf[2:0]), - .dzosui (dzosui[15:0]), - .zndrba (zndrba[31:0])); + // Outputs + .bxiouf (bxiouf), + // Inputs + .mglehy (mglehy[255:0]), + .drricx (drricx[215:0]), + .apqrli (apqrli[15:0]), + .szlfpf (szlfpf[2:0]), + .dzosui (dzosui[15:0]), + .zndrba (zndrba[31:0])); always @ (posedge clk) begin cyc <= cyc + 1; crc <= {crc[6:0], ~^ {crc[7],crc[5],crc[4],crc[3]}}; if (cyc==0) begin - // Setup - crc <= 8'hed; - sum <= 224'h0; + // Setup + crc <= 8'hed; + sum <= 224'h0; end else if (cyc<90) begin - //$write("[%0t] cyc==%0d BXI=%x\n", $time, cyc, bxiouf); - sum <= {sum[222:0],sum[223]} ^ bxiouf; + //$write("[%0t] cyc==%0d BXI=%x\n", $time, cyc, bxiouf); + sum <= {sum[222:0],sum[223]} ^ bxiouf; end else if (cyc==99) begin - $write("[%0t] cyc==%0d crc=%b %x\n", $time, cyc, crc, sum); - if (crc !== 8'b01110000) $stop; - if (sum !== 224'h1fdff998855c3c38d467e28124847831f9ad6d4a09f2801098f032a8) $stop; - $write("*-* All Finished *-*\n"); - $finish; + $write("[%0t] cyc==%0d crc=%b %x\n", $time, cyc, crc, sum); + if (crc !== 8'b01110000) $stop; + if (sum !== 224'h1fdff998855c3c38d467e28124847831f9ad6d4a09f2801098f032a8) $stop; + $write("*-* All Finished *-*\n"); + $finish; end end endmodule module vliw ( - input[255:0] mglehy, - input[215:0] drricx, - input[15:0] apqrli, - input[2:0] szlfpf, - input[15:0] dzosui, - input[31:0] zndrba, - output wire [223:0] bxiouf - ); + input[255:0] mglehy, + input[215:0] drricx, + input[15:0] apqrli, + input[2:0] szlfpf, + input[15:0] dzosui, + input[31:0] zndrba, + output wire [223:0] bxiouf + ); wire [463:0] zhknfc = ({29{~apqrli}} & {mglehy, drricx[215:8]}) - | ({29{apqrli}} & {mglehy[247:0], drricx}); + | ({29{apqrli}} & {mglehy[247:0], drricx}); wire [335:0] umntwz = ({21{~dzosui}} & zhknfc[463:128]) - | ({21{dzosui}} & zhknfc[335:0]); + | ({21{dzosui}} & zhknfc[335:0]); wire [335:0] viuvoc = umntwz << {szlfpf, 4'b0000}; wire [223:0] rzyeut = viuvoc[335:112]; assign bxiouf = {rzyeut[7:0], - rzyeut[15:8], - rzyeut[23:16], - rzyeut[31:24], - rzyeut[39:32], - rzyeut[47:40], - rzyeut[55:48], - rzyeut[63:56], - rzyeut[71:64], - rzyeut[79:72], - rzyeut[87:80], - rzyeut[95:88], - rzyeut[103:96], - rzyeut[111:104], - rzyeut[119:112], - rzyeut[127:120], - rzyeut[135:128], - rzyeut[143:136], - rzyeut[151:144], - rzyeut[159:152], - rzyeut[167:160], - rzyeut[175:168], - rzyeut[183:176], - rzyeut[191:184], - rzyeut[199:192], - rzyeut[207:200], - rzyeut[215:208], - rzyeut[223:216]}; + rzyeut[15:8], + rzyeut[23:16], + rzyeut[31:24], + rzyeut[39:32], + rzyeut[47:40], + rzyeut[55:48], + rzyeut[63:56], + rzyeut[71:64], + rzyeut[79:72], + rzyeut[87:80], + rzyeut[95:88], + rzyeut[103:96], + rzyeut[111:104], + rzyeut[119:112], + rzyeut[127:120], + rzyeut[135:128], + rzyeut[143:136], + rzyeut[151:144], + rzyeut[159:152], + rzyeut[167:160], + rzyeut[175:168], + rzyeut[183:176], + rzyeut[191:184], + rzyeut[199:192], + rzyeut[207:200], + rzyeut[215:208], + rzyeut[223:216]}; endmodule diff --git a/test_regress/t/t_mem.v b/test_regress/t/t_mem.v index 8a6ce3e30..ea9d7dfce 100644 --- a/test_regress/t/t_mem.v +++ b/test_regress/t/t_mem.v @@ -15,7 +15,7 @@ module t (/*AUTOARG*/ // [16] is SV syntax for [0:15] reg [7:0] memory8_16 [16]; - reg m_we; + reg m_we; reg [3:1] m_addr; reg [15:0] m_data; @@ -23,8 +23,8 @@ module t (/*AUTOARG*/ // Load instructions from cache memory8_16[{m_addr,1'd0}] <= 8'hfe; if (m_we) begin - {memory8_16[{m_addr,1'd1}], - memory8_16[{m_addr,1'd0}]} <= m_data; + {memory8_16[{m_addr,1'd1}], + memory8_16[{m_addr,1'd0}]} <= m_data; end end @@ -39,30 +39,30 @@ module t (/*AUTOARG*/ always @ (posedge clk) begin m_we <= 0; if (cyc!=0) begin - cyc <= cyc + 1; - if (cyc==1) begin - m_we <= 1'b1; - m_addr <= 3'd2; - m_data <= 16'h55_44; - end - if (cyc==2) begin - m_we <= 1'b1; - m_addr <= 3'd3; - m_data <= 16'h77_66; - end - if (cyc==3) begin - m_we <= 0; // Check we really don't write this - m_addr <= 3'd3; - m_data <= 16'h0bad; - end - if (cyc==5) begin - if (memory8_16_4 != 8'h44) $stop; - if (memory8_16_5 != 8'h55) $stop; - if (memory8_16[6] != 8'hfe) $stop; - if (memory8_16[7] != 8'h77) $stop; - $write("*-* All Finished *-*\n"); - $finish; - end + cyc <= cyc + 1; + if (cyc==1) begin + m_we <= 1'b1; + m_addr <= 3'd2; + m_data <= 16'h55_44; + end + if (cyc==2) begin + m_we <= 1'b1; + m_addr <= 3'd3; + m_data <= 16'h77_66; + end + if (cyc==3) begin + m_we <= 0; // Check we really don't write this + m_addr <= 3'd3; + m_data <= 16'h0bad; + end + if (cyc==5) begin + if (memory8_16_4 != 8'h44) $stop; + if (memory8_16_5 != 8'h55) $stop; + if (memory8_16[6] != 8'hfe) $stop; + if (memory8_16[7] != 8'h77) $stop; + $write("*-* All Finished *-*\n"); + $finish; + end end end diff --git a/test_regress/t/t_mem_banks.v b/test_regress/t/t_mem_banks.v index b810ca532..0f438eaea 100644 --- a/test_regress/t/t_mem_banks.v +++ b/test_regress/t/t_mem_banks.v @@ -6,68 +6,68 @@ module t (/*AUTOARG*/); - reg [5:0] addr; + reg [5:0] addr; parameter BANKS = 6; parameter ROWS = 8; - wire [2:0] bank; - wire [2:0] row; + wire [2:0] bank; + wire [2:0] row; - integer a; - integer used[BANKS][ROWS]; + integer a; + integer used[BANKS][ROWS]; // Test loop initial begin for (a = 0; a < BANKS*ROWS; ++a) begin - addr[5:0] = a[5:0]; - hash (addr, bank, row); - used [bank][row] ++; - if (used [bank][row] > 1) begin - $write ("Error: Hash failed addr=%x bank=%x row=%x\n", addr, bank, row); - end + addr[5:0] = a[5:0]; + hash (addr, bank, row); + used [bank][row] ++; + if (used [bank][row] > 1) begin + $write ("Error: Hash failed addr=%x bank=%x row=%x\n", addr, bank, row); + end end $write("*-* All Finished *-*\n"); $finish; end task hash (input [5:0] addr, - output [2:0] bank, - output [2:0] row); + output [2:0] bank, + output [2:0] row); reg [1:0] third; reg [1:0] fourth; third = {addr[5], addr[4]}; fourth = {addr[3] ^ addr[1], - addr[2] ^ addr[0]}; + addr[2] ^ addr[0]}; case (third) - 2'h0: - case (fourth) - 2'h0: begin bank = 3'h0; row = {1'h0, addr[1:0]}; end - 2'h1: begin bank = 3'h1; row = {1'h0, addr[1:0]}; end - 2'h2: begin bank = 3'h2; row = {1'h0, addr[1:0]}; end - 2'h3: begin bank = 3'h3; row = {1'h0, addr[1:0]}; end - endcase + 2'h0: + case (fourth) + 2'h0: begin bank = 3'h0; row = {1'h0, addr[1:0]}; end + 2'h1: begin bank = 3'h1; row = {1'h0, addr[1:0]}; end + 2'h2: begin bank = 3'h2; row = {1'h0, addr[1:0]}; end + 2'h3: begin bank = 3'h3; row = {1'h0, addr[1:0]}; end + endcase - 2'h1: - case (fourth) - 2'h0: begin bank = 3'h0; row = {1'h1, addr[1:0]}; end - 2'h1: begin bank = 3'h1; row = {1'h1, addr[1:0]}; end - 2'h2: begin bank = 3'h4; row = {1'h0, addr[1:0]}; end - 2'h3: begin bank = 3'h5; row = {1'h0, addr[1:0]}; end - endcase + 2'h1: + case (fourth) + 2'h0: begin bank = 3'h0; row = {1'h1, addr[1:0]}; end + 2'h1: begin bank = 3'h1; row = {1'h1, addr[1:0]}; end + 2'h2: begin bank = 3'h4; row = {1'h0, addr[1:0]}; end + 2'h3: begin bank = 3'h5; row = {1'h0, addr[1:0]}; end + endcase - 2'h2: - case (fourth) - 2'h0: begin bank = 3'h2; row = {1'h1, addr[1:0]}; end - 2'h1: begin bank = 3'h3; row = {1'h1, addr[1:0]}; end - 2'h2: begin bank = 3'h4; row = {1'h1, addr[1:0]}; end - 2'h3: begin bank = 3'h5; row = {1'h1, addr[1:0]}; end - endcase + 2'h2: + case (fourth) + 2'h0: begin bank = 3'h2; row = {1'h1, addr[1:0]}; end + 2'h1: begin bank = 3'h3; row = {1'h1, addr[1:0]}; end + 2'h2: begin bank = 3'h4; row = {1'h1, addr[1:0]}; end + 2'h3: begin bank = 3'h5; row = {1'h1, addr[1:0]}; end + endcase - 2'h3: $stop; + 2'h3: $stop; endcase endtask endmodule diff --git a/test_regress/t/t_mem_fifo.v b/test_regress/t/t_mem_fifo.v index d4bdc2425..e76ec783a 100644 --- a/test_regress/t/t_mem_fifo.v +++ b/test_regress/t/t_mem_fifo.v @@ -14,50 +14,50 @@ module t (/*AUTOARG*/ integer cyc; initial cyc = 0; reg [63:0] crc; - wire [65:0] outData; // From fifo of fifo.v - wire [15:0] inData = crc[15:0]; - wire [1:0] inWordPtr = crc[17:16]; - wire wrEn = crc[20]; - wire [1:0] wrPtr = crc[33:32]; - wire [1:0] rdPtr = crc[34:33]; + wire [65:0] outData; // From fifo of fifo.v + wire [15:0] inData = crc[15:0]; + wire [1:0] inWordPtr = crc[17:16]; + wire wrEn = crc[20]; + wire [1:0] wrPtr = crc[33:32]; + wire [1:0] rdPtr = crc[34:33]; fifo fifo ( - // Outputs - .outData (outData[65:0]), - // Inputs - .clk (clk), - .inWordPtr (inWordPtr[1:0]), - .inData (inData[15:0]), - .rdPtr (rdPtr), - .wrPtr (wrPtr), - .wrEn (wrEn)); + // Outputs + .outData (outData[65:0]), + // Inputs + .clk (clk), + .inWordPtr (inWordPtr[1:0]), + .inData (inData[15:0]), + .rdPtr (rdPtr), + .wrPtr (wrPtr), + .wrEn (wrEn)); always @ (posedge clk) begin //$write("[%0t] cyc==%0d crc=%b q=%x\n", $time, cyc, crc, outData); cyc <= cyc + 1; crc <= {crc[62:0], crc[63] ^ crc[2] ^ crc[0]}; if (cyc==0) begin - // Setup - crc <= 64'h5aef0c8d_d70a4497; + // Setup + crc <= 64'h5aef0c8d_d70a4497; end else if (cyc==90) begin - if (outData[63:0] != 64'hd9bcbc276f0984ea) $stop; + if (outData[63:0] != 64'hd9bcbc276f0984ea) $stop; end else if (cyc==91) begin - if (outData[63:0] != 64'hef77cd9b13a866f0) $stop; + if (outData[63:0] != 64'hef77cd9b13a866f0) $stop; end else if (cyc==92) begin - if (outData[63:0] != 64'h2750cd9b13a866f0) $stop; + if (outData[63:0] != 64'h2750cd9b13a866f0) $stop; end else if (cyc==93) begin - if (outData[63:0] != 64'h4ea0bc276f0984ea) $stop; + if (outData[63:0] != 64'h4ea0bc276f0984ea) $stop; end else if (cyc==94) begin - if (outData[63:0] != 64'h9d41bc276f0984ea) $stop; + if (outData[63:0] != 64'h9d41bc276f0984ea) $stop; end else if (cyc==99) begin - $write("*-* All Finished *-*\n"); - $finish; + $write("*-* All Finished *-*\n"); + $finish; end end @@ -78,32 +78,32 @@ module fifo (/*AUTOARG*/ `define PTRBITSM2 (fifoDepthLog2-1) input clk; - input [1:0] inWordPtr; + input [1:0] inWordPtr; input [15:0] inData; input [`PTRBITSM1:0] wrPtr; input [`PTRBITSM1:0] rdPtr; output [65:0] outData; - input wrEn; + input wrEn; reg [65:0] outData; // verilator lint_off VARHIDDEN // verilator lint_off LITENDIAN - reg [65:0] fifo[0:fifoDepth-1]; + reg [65:0] fifo[0:fifoDepth-1]; // verilator lint_on LITENDIAN // verilator lint_on VARHIDDEN - //reg [65:0] temp; + //reg [65:0] temp; always @(posedge clk) begin //$write ("we=%x PT=%x ID=%x D=%x\n", wrEn, wrPtr[`PTRBITSM2:0], {1'b0,~inWordPtr,4'b0}, inData[15:0]); if (wrEn) begin - fifo[ wrPtr[`PTRBITSM2:0] ][{1'b0,~inWordPtr,4'b0}+:16] <= inData[15:0]; - // Equivelent to: - //temp = fifo[ wrPtr[`PTRBITSM2:0] ]; - //temp [{1'b0,~inWordPtr,4'b0}+:16] = inData[15:0]; - //fifo[ wrPtr[`PTRBITSM2:0] ] <= temp; + fifo[ wrPtr[`PTRBITSM2:0] ][{1'b0,~inWordPtr,4'b0}+:16] <= inData[15:0]; + // Equivelent to: + //temp = fifo[ wrPtr[`PTRBITSM2:0] ]; + //temp [{1'b0,~inWordPtr,4'b0}+:16] = inData[15:0]; + //fifo[ wrPtr[`PTRBITSM2:0] ] <= temp; end outData <= fifo[rdPtr[`PTRBITSM2:0]]; end diff --git a/test_regress/t/t_mem_file.v b/test_regress/t/t_mem_file.v index 9284d9fba..8d9dacb09 100644 --- a/test_regress/t/t_mem_file.v +++ b/test_regress/t/t_mem_file.v @@ -14,39 +14,39 @@ module t (/*AUTOARG*/ reg [63:0] crc; reg [63:0] sum; - wire r1_en /*verilator public*/ = crc[12]; - wire [1:0] r1_ad /*verilator public*/ = crc[9:8]; - wire r2_en /*verilator public*/ = 1'b1; - wire [1:0] r2_ad /*verilator public*/ = crc[11:10]; - wire w1_en /*verilator public*/ = crc[5]; - wire [1:0] w1_a /*verilator public*/ = crc[1:0]; - wire [63:0] w1_d /*verilator public*/ = {2{crc[63:32]}}; - wire w2_en /*verilator public*/ = crc[4]; - wire [1:0] w2_a /*verilator public*/ = crc[3:2]; - wire [63:0] w2_d /*verilator public*/ = {2{~crc[63:32]}}; + wire r1_en /*verilator public*/ = crc[12]; + wire [1:0] r1_ad /*verilator public*/ = crc[9:8]; + wire r2_en /*verilator public*/ = 1'b1; + wire [1:0] r2_ad /*verilator public*/ = crc[11:10]; + wire w1_en /*verilator public*/ = crc[5]; + wire [1:0] w1_a /*verilator public*/ = crc[1:0]; + wire [63:0] w1_d /*verilator public*/ = {2{crc[63:32]}}; + wire w2_en /*verilator public*/ = crc[4]; + wire [1:0] w2_a /*verilator public*/ = crc[3:2]; + wire [63:0] w2_d /*verilator public*/ = {2{~crc[63:32]}}; /*AUTOWIRE*/ // Beginning of automatic wires (for undeclared instantiated-module outputs) - wire [63:0] r1_d_d2r; // From file of file.v - wire [63:0] r2_d_d2r; // From file of file.v + wire [63:0] r1_d_d2r; // From file of file.v + wire [63:0] r2_d_d2r; // From file of file.v // End of automatics file file (/*AUTOINST*/ - // Outputs - .r1_d_d2r (r1_d_d2r[63:0]), - .r2_d_d2r (r2_d_d2r[63:0]), - // Inputs - .clk (clk), - .r1_en (r1_en), - .r1_ad (r1_ad[1:0]), - .r2_en (r2_en), - .r2_ad (r2_ad[1:0]), - .w1_en (w1_en), - .w1_a (w1_a[1:0]), - .w1_d (w1_d[63:0]), - .w2_en (w2_en), - .w2_a (w2_a[1:0]), - .w2_d (w2_d[63:0])); + // Outputs + .r1_d_d2r (r1_d_d2r[63:0]), + .r2_d_d2r (r2_d_d2r[63:0]), + // Inputs + .clk (clk), + .r1_en (r1_en), + .r1_ad (r1_ad[1:0]), + .r2_en (r2_en), + .r2_ad (r2_ad[1:0]), + .w1_en (w1_en), + .w1_a (w1_a[1:0]), + .w1_d (w1_d[63:0]), + .w2_en (w2_en), + .w2_a (w2_a[1:0]), + .w2_d (w2_d[63:0])); always @ (posedge clk) begin //$write("[%0t] cyc==%0d EN=%b%b%b%b R0=%x R1=%x\n", $time, cyc, r1_en,r2_en,w1_en,w2_en, r1_d_d2r, r2_d_d2r); @@ -54,21 +54,21 @@ module t (/*AUTOARG*/ crc <= {crc[62:0], crc[63] ^ crc[2] ^ crc[0]}; sum <= {r1_d_d2r ^ r2_d_d2r} ^ {sum[62:0], sum[63] ^ sum[2] ^ sum[0]}; if (cyc==0) begin - // Setup - crc <= 64'h5aef0c8d_d70a4497; + // Setup + crc <= 64'h5aef0c8d_d70a4497; end else if (cyc<10) begin - // We've manually verified all X's are out of the design by this point - sum <= 64'h0; + // We've manually verified all X's are out of the design by this point + sum <= 64'h0; end else if (cyc<90) begin end else if (cyc==99) begin - $write("*-* All Finished *-*\n"); - $write("[%0t] cyc==%0d crc=%x %x\n", $time, cyc, crc, sum); - if (crc !== 64'hc77bb9b3784ea091) $stop; - if (sum !== 64'h5e9ea8c33a97f81e) $stop; - $finish; + $write("*-* All Finished *-*\n"); + $write("[%0t] cyc==%0d crc=%x %x\n", $time, cyc, crc, sum); + if (crc !== 64'hc77bb9b3784ea091) $stop; + if (sum !== 64'h5e9ea8c33a97f81e) $stop; + $finish; end end @@ -81,18 +81,18 @@ module file (/*AUTOARG*/ clk, r1_en, r1_ad, r2_en, r2_ad, w1_en, w1_a, w1_d, w2_en, w2_a, w2_d ); - input clk; - input r1_en; - input [1:0] r1_ad; + input clk; + input r1_en; + input [1:0] r1_ad; output [63:0] r1_d_d2r; - input r2_en; - input [1:0] r2_ad; + input r2_en; + input [1:0] r2_ad; output [63:0] r2_d_d2r; - input w1_en; - input [1:0] w1_a; + input w1_en; + input [1:0] w1_a; input [63:0] w1_d; - input w2_en; - input [1:0] w2_a; + input w2_en; + input [1:0] w2_a; input [63:0] w2_d; /*AUTOWIRE*/ @@ -100,26 +100,26 @@ module file (/*AUTOARG*/ // End of automatics /*AUTOREG*/ // Beginning of automatic regs (for this module's undeclared outputs) - reg [63:0] r1_d_d2r; - reg [63:0] r2_d_d2r; + reg [63:0] r1_d_d2r; + reg [63:0] r2_d_d2r; // End of automatics // Writes - wire [3:0] m_w1_onehotwe = ({4{w1_en}} & (4'b1 << w1_a)); - wire [3:0] m_w2_onehotwe = ({4{w2_en}} & (4'b1 << w2_a)); + wire [3:0] m_w1_onehotwe = ({4{w1_en}} & (4'b1 << w1_a)); + wire [3:0] m_w2_onehotwe = ({4{w2_en}} & (4'b1 << w2_a)); - wire [63:0] rg0_wrdat = m_w1_onehotwe[0] ? w1_d : w2_d; - wire [63:0] rg1_wrdat = m_w1_onehotwe[1] ? w1_d : w2_d; - wire [63:0] rg2_wrdat = m_w1_onehotwe[2] ? w1_d : w2_d; - wire [63:0] rg3_wrdat = m_w1_onehotwe[3] ? w1_d : w2_d; + wire [63:0] rg0_wrdat = m_w1_onehotwe[0] ? w1_d : w2_d; + wire [63:0] rg1_wrdat = m_w1_onehotwe[1] ? w1_d : w2_d; + wire [63:0] rg2_wrdat = m_w1_onehotwe[2] ? w1_d : w2_d; + wire [63:0] rg3_wrdat = m_w1_onehotwe[3] ? w1_d : w2_d; - wire [3:0] m_w_onehotwe = m_w1_onehotwe | m_w2_onehotwe; + wire [3:0] m_w_onehotwe = m_w1_onehotwe | m_w2_onehotwe; // Storage - reg [63:0] m_rg0_r; - reg [63:0] m_rg1_r; - reg [63:0] m_rg2_r; - reg [63:0] m_rg3_r; + reg [63:0] m_rg0_r; + reg [63:0] m_rg1_r; + reg [63:0] m_rg2_r; + reg [63:0] m_rg3_r; always @ (posedge clk) begin if (m_w_onehotwe[0]) m_rg0_r <= rg0_wrdat; @@ -129,9 +129,9 @@ module file (/*AUTOARG*/ end // Reads - reg [1:0] m_r1_ad_d1r; - reg [1:0] m_r2_ad_d1r; - reg [1:0] m_ren_d1r; + reg [1:0] m_r1_ad_d1r; + reg [1:0] m_r2_ad_d1r; + reg [1:0] m_ren_d1r; always @ (posedge clk) begin if (r1_en) m_r1_ad_d1r <= r1_ad; @@ -140,23 +140,23 @@ module file (/*AUTOARG*/ end // Scheme1: shift... - wire [3:0] m_r1_onehot_d1 = (4'b1 << m_r1_ad_d1r); + wire [3:0] m_r1_onehot_d1 = (4'b1 << m_r1_ad_d1r); // Scheme2: bit mask - reg [3:0] m_r2_onehot_d1; + reg [3:0] m_r2_onehot_d1; always @* begin m_r2_onehot_d1 = 4'd0; m_r2_onehot_d1[m_r2_ad_d1r] = 1'b1; end - wire [63:0] m_r1_d_d1 = (({64{m_r1_onehot_d1[0]}} & m_rg0_r) | - ({64{m_r1_onehot_d1[1]}} & m_rg1_r) | - ({64{m_r1_onehot_d1[2]}} & m_rg2_r) | - ({64{m_r1_onehot_d1[3]}} & m_rg3_r)); + wire [63:0] m_r1_d_d1 = (({64{m_r1_onehot_d1[0]}} & m_rg0_r) | + ({64{m_r1_onehot_d1[1]}} & m_rg1_r) | + ({64{m_r1_onehot_d1[2]}} & m_rg2_r) | + ({64{m_r1_onehot_d1[3]}} & m_rg3_r)); - wire [63:0] m_r2_d_d1 = (({64{m_r2_onehot_d1[0]}} & m_rg0_r) | - ({64{m_r2_onehot_d1[1]}} & m_rg1_r) | - ({64{m_r2_onehot_d1[2]}} & m_rg2_r) | - ({64{m_r2_onehot_d1[3]}} & m_rg3_r)); + wire [63:0] m_r2_d_d1 = (({64{m_r2_onehot_d1[0]}} & m_rg0_r) | + ({64{m_r2_onehot_d1[1]}} & m_rg1_r) | + ({64{m_r2_onehot_d1[2]}} & m_rg2_r) | + ({64{m_r2_onehot_d1[3]}} & m_rg3_r)); always @ (posedge clk) begin if (m_ren_d1r[0]) r1_d_d2r <= m_r1_d_d1; diff --git a/test_regress/t/t_mem_first.v b/test_regress/t/t_mem_first.v index 8db61242b..372032a77 100644 --- a/test_regress/t/t_mem_first.v +++ b/test_regress/t/t_mem_first.v @@ -10,7 +10,7 @@ module t (/*AUTOARG*/ ); input clk; - integer _mode; initial _mode = 0; + integer _mode; initial _mode = 0; // verilator lint_off LITENDIAN reg [7:0] mem_narrow [0:31]; //surefire lint_off_line RD_WRT WRTWRT NBAJAM @@ -27,79 +27,79 @@ module t (/*AUTOARG*/ // Must take LSBs into account in bit extract widths. wire [15:14] sixt = 2'b10; // surefire lint_off_line ASWCBB wire [16:14] sixt2 = 3'b110; // surefire lint_off_line ASWCBB - wire [3:0] sixfrom = 13; - wire [4:0] sixfrom2 = 16; - wire sixtext = sixt[sixfrom]; - wire sixtext2 = sixt2[sixfrom2]; + wire [3:0] sixfrom = 13; + wire [4:0] sixfrom2 = 16; + wire sixtext = sixt[sixfrom]; + wire sixtext2 = sixt2[sixfrom2]; // Non-power of 2 memory overwriting checks - reg [2:0] np2_mem [5:0] /*verilator public*/; - reg [2:0] np2_guard [7:6] /*verilator public*/; + reg [2:0] np2_mem [5:0] /*verilator public*/; + reg [2:0] np2_guard [7:6] /*verilator public*/; - integer i; + integer i; always @ (posedge clk) begin if (_mode!=0) begin - wrd0[0] = 32'h1; - // - for (i=0; i<32; i=i+1) begin //surefire lint_off_line STMFOR - mem_narrow[i] = i[7:0]; - mem_wide[i] = {i[7:0],70'hfeed}; - end - // - for (i=0; i<32; i=i+1) begin //surefire lint_off_line STMFOR - if (mem_narrow[i] !== i[7:0]) $stop; - if (mem_wide[i] !== {i[7:0],70'hfeed}) $stop; - end - // - vec_wide <= 0; - // - np2_guard[6] = 0; - np2_guard[7] = 0; - // - $write("selout %b %b %b\n", selout, sixtext, sixtext2); + wrd0[0] = 32'h1; + // + for (i=0; i<32; i=i+1) begin //surefire lint_off_line STMFOR + mem_narrow[i] = i[7:0]; + mem_wide[i] = {i[7:0],70'hfeed}; + end + // + for (i=0; i<32; i=i+1) begin //surefire lint_off_line STMFOR + if (mem_narrow[i] !== i[7:0]) $stop; + if (mem_wide[i] !== {i[7:0],70'hfeed}) $stop; + end + // + vec_wide <= 0; + // + np2_guard[6] = 0; + np2_guard[7] = 0; + // + $write("selout %b %b %b\n", selout, sixtext, sixtext2); end if (_mode == 1) begin - _mode <= 2; - // - i=0; - mem_dly_narrow[0] <= ~i[7:0]; - mem_dly_wide[0] <= {~i[7:0],70'hface}; - i=1; - mem_dly_narrow[i] <= ~i[7:0]; - mem_dly_wide[i] <= {~i[7:0],70'hface}; - // - for (i=0; i<16; i=i+1) begin //surefire lint_off_line STMFOR - // verilator lint_off width - np2_mem[i] = i[2:0]; // surefire lint_off_line ASWSBB - // verilator lint_on width - if (np2_guard[6]!=0 || np2_guard[7]!=0) $stop; - end - // verilator lint_off SELRANGE - if (np2_mem[6] !== np2_mem[7]) begin - $write("Mem[6]!=Mem[7] during randomize...\n"); - //$stop; // Random value, so this can happen - end - // verilator lint_on SELRANGE - //if (np2_mem[8] !== np2_mem[9]) $stop; // Enhancement: Illegal indexes, make sure map to X's - // - vec_wide[32:31] <= 2'b11; - vec_wide[34] <= 1'b1; - $display("%x",vec_wide); + _mode <= 2; + // + i=0; + mem_dly_narrow[0] <= ~i[7:0]; + mem_dly_wide[0] <= {~i[7:0],70'hface}; + i=1; + mem_dly_narrow[i] <= ~i[7:0]; + mem_dly_wide[i] <= {~i[7:0],70'hface}; + // + for (i=0; i<16; i=i+1) begin //surefire lint_off_line STMFOR + // verilator lint_off width + np2_mem[i] = i[2:0]; // surefire lint_off_line ASWSBB + // verilator lint_on width + if (np2_guard[6]!=0 || np2_guard[7]!=0) $stop; + end + // verilator lint_off SELRANGE + if (np2_mem[6] !== np2_mem[7]) begin + $write("Mem[6]!=Mem[7] during randomize...\n"); + //$stop; // Random value, so this can happen + end + // verilator lint_on SELRANGE + //if (np2_mem[8] !== np2_mem[9]) $stop; // Enhancement: Illegal indexes, make sure map to X's + // + vec_wide[32:31] <= 2'b11; + vec_wide[34] <= 1'b1; + $display("%x",vec_wide); end if (_mode == 2) begin - _mode <= 3; - // - for (i=0; i<2; i=i+1) begin //surefire lint_off_line STMFOR - if (mem_dly_narrow[i] !== ~i[7:0]) $stop; - if (mem_dly_wide[i] !== {~i[7:0],70'hface}) $stop; - end - // - //$write ("VW %x %x\n", vec_wide[34:32], vec_wide[31:0]); - if (vec_wide != {4'b101_1,31'd0}) $stop; - // - $write("*-* All Finished *-*\n"); - $finish; + _mode <= 3; + // + for (i=0; i<2; i=i+1) begin //surefire lint_off_line STMFOR + if (mem_dly_narrow[i] !== ~i[7:0]) $stop; + if (mem_dly_wide[i] !== {~i[7:0],70'hface}) $stop; + end + // + //$write ("VW %x %x\n", vec_wide[34:32], vec_wide[31:0]); + if (vec_wide != {4'b101_1,31'd0}) $stop; + // + $write("*-* All Finished *-*\n"); + $finish; end _mode <= _mode + 1; end diff --git a/test_regress/t/t_mem_func.v b/test_regress/t/t_mem_func.v index c9c1077a9..86cd1f7b2 100644 --- a/test_regress/t/t_mem_func.v +++ b/test_regress/t/t_mem_func.v @@ -10,27 +10,27 @@ module t (/*AUTOARG*/ ); input clk; - integer cyc = 0; - reg [63:0] crc; - reg [63:0] sum; + integer cyc = 0; + reg [63:0] crc; + reg [63:0] sum; /*AUTOWIRE*/ // Beginning of automatic wires (for undeclared instantiated-module outputs) - wire [2:0] q; // From test of Test.v + wire [2:0] q; // From test of Test.v // End of automatics Test test ( - // Outputs - .q (q[2:0]), - // Inputs - .clk (clk), - .reset_l (crc[0]), - .enable (crc[2]), - .q_var0 (crc[19:10]), - .q_var2 (crc[29:20]), - .q_var4 (crc[39:30]), - .q_var6 (crc[49:40]) - /*AUTOINST*/); + // Outputs + .q (q[2:0]), + // Inputs + .clk (clk), + .reset_l (crc[0]), + .enable (crc[2]), + .q_var0 (crc[19:10]), + .q_var2 (crc[29:20]), + .q_var4 (crc[39:30]), + .q_var6 (crc[49:40]) + /*AUTOINST*/); // Aggregate outputs into a single result vector wire [63:0] result = {61'h0,q}; @@ -44,21 +44,21 @@ module t (/*AUTOARG*/ crc <= {crc[62:0], crc[63] ^ crc[2] ^ crc[0]}; sum <= result ^ {sum[62:0], sum[63] ^ sum[2] ^ sum[0]}; if (cyc==0) begin - // Setup - crc <= 64'h5aef0c8d_d70a4497; + // Setup + crc <= 64'h5aef0c8d_d70a4497; end else if (cyc<10) begin - sum <= 64'h0; + sum <= 64'h0; end else if (cyc<90) begin end else if (cyc==99) begin - $write("[%0t] cyc==%0d crc=%x sum=%x\n", $time, cyc, crc, sum); - if (crc !== 64'hc77bb9b3784ea091) $stop; + $write("[%0t] cyc==%0d crc=%x sum=%x\n", $time, cyc, crc, sum); + if (crc !== 64'hc77bb9b3784ea091) $stop; `define EXPECTED_SUM 64'h58b162c58d6e35ba - if (sum !== `EXPECTED_SUM) $stop; - $write("*-* All Finished *-*\n"); - $finish; + if (sum !== `EXPECTED_SUM) $stop; + $write("*-* All Finished *-*\n"); + $finish; end end endmodule @@ -78,7 +78,7 @@ module Test output reg [2:0] q ); - reg [7:0] p1_r [6:0]; + reg [7:0] p1_r [6:0]; always @(posedge clk) begin if (!reset_l) begin @@ -103,8 +103,8 @@ module Test q = 0; bd = 0; for (idx=0; idx<7; idx=idx+1) begin - q = idx+1; - bd = bd + p1_r[idx]; + q = idx+1; + bd = bd + p1_r[idx]; end end @@ -113,10 +113,10 @@ module Test input [9:0] p0, p1, p2, p3; reg [9:0] p[3:0]; begin - p[0] = p0; - p[1] = p1; - p[2] = p2; - p[3] = p3; + p[0] = p0; + p[1] = p1; + p[2] = p2; + p[3] = p3; p1_r[0] <= p[0]; p1_r[1] <= p[1]; end diff --git a/test_regress/t/t_mem_iforder.v b/test_regress/t/t_mem_iforder.v index 93e35744a..32b56f4a6 100644 --- a/test_regress/t/t_mem_iforder.v +++ b/test_regress/t/t_mem_iforder.v @@ -15,42 +15,42 @@ module t (/*AUTOARG*/ reg [63:0] crc; reg [31:0] sum; - wire [15:0] out0; - wire [15:0] out1; - wire [15:0] inData = crc[15:0]; - wire wr0a = crc[16]; - wire wr0b = crc[17]; - wire wr1a = crc[18]; - wire wr1b = crc[19]; + wire [15:0] out0; + wire [15:0] out1; + wire [15:0] inData = crc[15:0]; + wire wr0a = crc[16]; + wire wr0b = crc[17]; + wire wr1a = crc[18]; + wire wr1b = crc[19]; fifo fifo ( - // Outputs - .out0 (out0[15:0]), - .out1 (out1[15:0]), - // Inputs - .clk (clk), - .wr0a (wr0a), - .wr0b (wr0b), - .wr1a (wr1a), - .wr1b (wr1b), - .inData (inData[15:0])); + // Outputs + .out0 (out0[15:0]), + .out1 (out1[15:0]), + // Inputs + .clk (clk), + .wr0a (wr0a), + .wr0b (wr0b), + .wr1a (wr1a), + .wr1b (wr1b), + .inData (inData[15:0])); always @ (posedge clk) begin //$write("[%0t] cyc==%0d crc=%x q=%x\n", $time, cyc, crc, sum); cyc <= cyc + 1; crc <= {crc[62:0], crc[63] ^ crc[2] ^ crc[0]}; if (cyc==0) begin - // Setup - crc <= 64'h5aef0c8d_d70a4497; - sum <= 32'h0; + // Setup + crc <= 64'h5aef0c8d_d70a4497; + sum <= 32'h0; end else if (cyc>10 && cyc<90) begin - sum <= {sum[30:0],sum[31]} ^ {out1, out0}; + sum <= {sum[30:0],sum[31]} ^ {out1, out0}; end else if (cyc==99) begin - if (sum !== 32'he8bbd130) $stop; - $write("*-* All Finished *-*\n"); - $finish; + if (sum !== 32'he8bbd130) $stop; + $write("*-* All Finished *-*\n"); + $finish; end end @@ -64,39 +64,39 @@ module fifo (/*AUTOARG*/ ); input clk; - input wr0a; - input wr0b; - input wr1a; - input wr1b; + input wr0a; + input wr0b; + input wr1a; + input wr1b; input [15:0] inData; output [15:0] out0; output [15:0] out1; - reg [15:0] mem [1:0]; - reg [15:0] memtemp2 [1:0]; - reg [15:0] memtemp3 [1:0]; + reg [15:0] mem [1:0]; + reg [15:0] memtemp2 [1:0]; + reg [15:0] memtemp3 [1:0]; - assign out0 = {mem[0] ^ memtemp2[0]}; - assign out1 = {mem[1] ^ memtemp3[1]}; + assign out0 = {mem[0] ^ memtemp2[0]}; + assign out1 = {mem[1] ^ memtemp3[1]}; always @(posedge clk) begin // These mem assignments must be done in order after processing if (wr0a) begin - memtemp2[0] <= inData; - mem[0] <= inData; + memtemp2[0] <= inData; + mem[0] <= inData; end if (wr0b) begin - memtemp3[0] <= inData; - mem[0] <= ~inData; + memtemp3[0] <= inData; + mem[0] <= ~inData; end if (wr1a) begin - memtemp3[1] <= inData; - mem[1] <= inData; + memtemp3[1] <= inData; + mem[1] <= inData; end if (wr1b) begin - memtemp2[1] <= inData; - mem[1] <= ~inData; + memtemp2[1] <= inData; + mem[1] <= ~inData; end end diff --git a/test_regress/t/t_mem_multi_io.v b/test_regress/t/t_mem_multi_io.v index e94b9860a..cd753cffa 100644 --- a/test_regress/t/t_mem_multi_io.v +++ b/test_regress/t/t_mem_multi_io.v @@ -20,7 +20,7 @@ module t (/*AUTOARG*/ initial begin for (int i = 0; i < 8; i++) begin - arr[i] = 0; + arr[i] = 0; end end @@ -30,7 +30,7 @@ module t (/*AUTOARG*/ $stop; end for (int i = 0; i < 7; ++i) begin - arr[i+1] <= arr[i]; + arr[i+1] <= arr[i]; end arr[0] <= arr[0] + 1; end @@ -48,14 +48,14 @@ module has_array ( always @(posedge clk) begin cyc <= cyc + 1; if (arri[0] == 10 && cyc == 10) begin - $write("*-* All Finished *-*\n"); - $finish; + $write("*-* All Finished *-*\n"); + $finish; end end always @(posedge clk) begin for (integer i = 0; i < 7; ++i) begin - arro[i+1] <= arro[i]; + arro[i+1] <= arro[i]; end arro[0] = arro[0] + 2; end diff --git a/test_regress/t/t_mem_multi_io3.v b/test_regress/t/t_mem_multi_io3.v index a7624c047..1e4d7434d 100644 --- a/test_regress/t/t_mem_multi_io3.v +++ b/test_regress/t/t_mem_multi_io3.v @@ -6,41 +6,41 @@ module t ( - input logic clk, - input logic daten, - input logic [8:0] datval, + input logic clk, + input logic daten, + input logic [8:0] datval, output logic signed [3:0][3:0][35:0] datao ); - logic signed [3:0][3:0][3:0][8:0] datat; + logic signed [3:0][3:0][3:0][8:0] datat; - genvar i; + genvar i; generate for (i=0; i<4; i++)begin - testio dut(.clk(clk), .arr3d_in(datat[i]), .arr2d_out(datao[i])); + testio dut(.clk(clk), .arr3d_in(datat[i]), .arr2d_out(datao[i])); end endgenerate genvar j; generate for (i=0; i<4; i++) begin - for (j=0; j<4; j++) begin - always_comb datat[i][j][0] = daten ? 9'h0 : datval; - always_comb datat[i][j][1] = daten ? 9'h1 : datval; - always_comb datat[i][j][2] = daten ? 9'h2 : datval; - always_comb datat[i][j][3] = daten ? 9'h3 : datval; - end + for (j=0; j<4; j++) begin + always_comb datat[i][j][0] = daten ? 9'h0 : datval; + always_comb datat[i][j][1] = daten ? 9'h1 : datval; + always_comb datat[i][j][2] = daten ? 9'h2 : datval; + always_comb datat[i][j][3] = daten ? 9'h3 : datval; + end end endgenerate endmodule module testio ( - input clk, + input clk, input logic signed [3:0] [3:0] [8:0] arr3d_in, - output logic signed [3:0] [35:0] arr2d_out + output logic signed [3:0] [35:0] arr2d_out ); - logic signed [3:0] [35:0] ar2d_out_pre; + logic signed [3:0] [35:0] ar2d_out_pre; always_comb ar2d_out_pre[0][35:0] = {arr3d_in[0][0][8:0], arr3d_in[0][1][8:0], arr3d_in[0][2][8:0], arr3d_in[0][3][8:0]}; always_comb ar2d_out_pre[0][35:0] = {arr3d_in[0][0][8:0], arr3d_in[0][1][8:0], arr3d_in[0][2][8:0], arr3d_in[0][3][8:0]}; @@ -49,7 +49,7 @@ module testio always_ff @(posedge clk) begin if (clk) - arr2d_out <= ar2d_out_pre; + arr2d_out <= ar2d_out_pre; end endmodule diff --git a/test_regress/t/t_mem_multidim.v b/test_regress/t/t_mem_multidim.v index 3d09878cc..9f68b4d5d 100644 --- a/test_regress/t/t_mem_multidim.v +++ b/test_regress/t/t_mem_multidim.v @@ -33,67 +33,67 @@ module t (/*AUTOARG*/ initial begin for (i0=0; i0<3; i0=i0+1) begin - for (i1=1; i1<4; i1=i1+1) begin - imem[i0[1:0]] [i1[1:0]] = i1; - for (i2=2; i2<6; i2=i2+1) begin - memw[i0[1:0]] [i1[1:0]] [i2[2:0]] = {56'hfe_fee0_fee0_fee0_,4'b0,i0[3:0],i1[3:0],i2[3:0]}; - memn[i0[1:0]] [i1[1:0]] [i2[2:0]] = 8'b1000_0001; - end - end + for (i1=1; i1<4; i1=i1+1) begin + imem[i0[1:0]] [i1[1:0]] = i1; + for (i2=2; i2<6; i2=i2+1) begin + memw[i0[1:0]] [i1[1:0]] [i2[2:0]] = {56'hfe_fee0_fee0_fee0_,4'b0,i0[3:0],i1[3:0],i2[3:0]}; + memn[i0[1:0]] [i1[1:0]] [i2[2:0]] = 8'b1000_0001; + end + end end end reg [71:0] wread; - reg wreadb; + reg wreadb; always @ (posedge clk) begin //$write("cyc==%0d crc=%x i[%d][%d][%d] nar=%x wide=%x\n",cyc, crc, index0,index1,index2, narrow, wide); cyc <= cyc + 1; if (cyc==0) begin - // Setup - crc <= 64'h5aef0c8d_d70a4497; - narrow <= 8'h0; - wide <= 72'h0; - index0 <= 2'b0; - index1 <= 2'b0; - index2 <= 3'b0; + // Setup + crc <= 64'h5aef0c8d_d70a4497; + narrow <= 8'h0; + wide <= 72'h0; + index0 <= 2'b0; + index1 <= 2'b0; + index2 <= 3'b0; end else if (cyc<90) begin - index0 <= crc[1:0]; - index1 <= crc[3:2]; - index2 <= crc[6:4]; - crc <= {crc[62:0], crc[63] ^ crc[2] ^ crc[0]}; + index0 <= crc[1:0]; + index1 <= crc[3:2]; + index2 <= crc[6:4]; + crc <= {crc[62:0], crc[63] ^ crc[2] ^ crc[0]}; - // We never read past bounds, or get unspecific results - // We also never read lowest indexes, as writing outside of range may corrupt them - if (index0>=0+1 && index0<=2 && index1>=1+1 /*&& index1<=3 CMPCONST*/ && index2>=2+1 && index2<=5) begin - narrow <= ({narrow[6:0], narrow[7]^narrow[0]} - ^ {memn[index0][index1][index2]}); - wread = memw[index0][index1][index2]; - wreadb = memw[index0][index1][index2][2]; - wide <= ({wide[70:0], wide[71]^wide[2]^wide[0]} ^ wread); - //$write("Get memw[%d][%d][%d] -> %x\n",index0,index1,index2, wread); - end - // We may write past bounds of memory - memn[index0][index1][index2] [crc[10:8]+:3] <= crc[2:0]; - memn[index0][index1][index2] <= {~crc[6:0],crc[7]}; - memw[index0][index1][index2] <= {~crc[7:0],crc}; - //$write("Set memw[%d][%d][%d] <= %x\n",index0,index1,index2, {~crc[7:0],crc}); - cstyle[cyc[0]] <= cyc[2:0]; - if (cyc>20) if (cstyle[~cyc[0]] != (cyc[2:0]-3'b1)) $stop; + // We never read past bounds, or get unspecific results + // We also never read lowest indexes, as writing outside of range may corrupt them + if (index0>=0+1 && index0<=2 && index1>=1+1 /*&& index1<=3 CMPCONST*/ && index2>=2+1 && index2<=5) begin + narrow <= ({narrow[6:0], narrow[7]^narrow[0]} + ^ {memn[index0][index1][index2]}); + wread = memw[index0][index1][index2]; + wreadb = memw[index0][index1][index2][2]; + wide <= ({wide[70:0], wide[71]^wide[2]^wide[0]} ^ wread); + //$write("Get memw[%d][%d][%d] -> %x\n",index0,index1,index2, wread); + end + // We may write past bounds of memory + memn[index0][index1][index2] [crc[10:8]+:3] <= crc[2:0]; + memn[index0][index1][index2] <= {~crc[6:0],crc[7]}; + memw[index0][index1][index2] <= {~crc[7:0],crc}; + //$write("Set memw[%d][%d][%d] <= %x\n",index0,index1,index2, {~crc[7:0],crc}); + cstyle[cyc[0]] <= cyc[2:0]; + if (cyc>20) if (cstyle[~cyc[0]] != (cyc[2:0]-3'b1)) $stop; end else if (cyc==90) begin - memn[0][1][3] <= memn[0][1][3] ^ 8'ha8; + memn[0][1][3] <= memn[0][1][3] ^ 8'ha8; end else if (cyc==91) begin end else if (cyc==99) begin - $write("[%0t] cyc==%0d crc=%x nar=%x wide=%x\n", $time, cyc, crc, narrow, wide); - if (crc != 64'h65e3bddcd9bc2750) $stop; - if (narrow != 8'hca) $stop; - if (wide != 72'h4edafed31ba6873f73) $stop; - $write("*-* All Finished *-*\n"); - $finish; + $write("[%0t] cyc==%0d crc=%x nar=%x wide=%x\n", $time, cyc, crc, narrow, wide); + if (crc != 64'h65e3bddcd9bc2750) $stop; + if (narrow != 8'hca) $stop; + if (wide != 72'h4edafed31ba6873f73) $stop; + $write("*-* All Finished *-*\n"); + $finish; end end diff --git a/test_regress/t/t_mem_multiwire.v b/test_regress/t/t_mem_multiwire.v index c031b44ce..24a53f502 100644 --- a/test_regress/t/t_mem_multiwire.v +++ b/test_regress/t/t_mem_multiwire.v @@ -22,12 +22,12 @@ module t (/*AUTOARG*/ generate for (g0=0; g0<3; g0=g0+1) begin - for (g1=1; g1<4; g1=g1+1) begin - inst inst (.q(array[g0[1:0]] [g1[1:0]]), - .cyc(cyc), - .i0(g0[1:0]), - .i1(g1[1:0])); - end + for (g1=1; g1<4; g1=g1+1) begin + inst inst (.q(array[g0[1:0]] [g1[1:0]]), + .cyc(cyc), + .i0(g0[1:0]), + .i1(g1[1:0])); + end end endgenerate @@ -35,17 +35,17 @@ module t (/*AUTOARG*/ //$write("cyc==%0d\n",cyc); cyc <= cyc + 1; if (cyc==2) begin - if (array[2][1] !== 8'h92) $stop; - for (i0=0; i0<3; i0=i0+1) begin - for (i1=1; i1<4; i1=i1+1) begin - //$write(" array[%0d][%0d] == 8'h%x\n",i0,i1,array[i0[1:0]] [i1[1:0]]); - if (array[i0[1:0]] [i1[1:0]] != {i0[1:0], i1[1:0], cyc[3:0]}) $stop; - end - end + if (array[2][1] !== 8'h92) $stop; + for (i0=0; i0<3; i0=i0+1) begin + for (i1=1; i1<4; i1=i1+1) begin + //$write(" array[%0d][%0d] == 8'h%x\n",i0,i1,array[i0[1:0]] [i1[1:0]]); + if (array[i0[1:0]] [i1[1:0]] != {i0[1:0], i1[1:0], cyc[3:0]}) $stop; + end + end end else if (cyc==9) begin - $write("*-* All Finished *-*\n"); - $finish; + $write("*-* All Finished *-*\n"); + $finish; end end @@ -59,14 +59,14 @@ module inst (/*AUTOARG*/ ); output reg [7:0] q; input [31:0] cyc; - input [1:0] i0; - input [1:0] i1; + input [1:0] i0; + input [1:0] i1; inst2 inst2 (/*AUTOINST*/ - // Inputs - .cyc (cyc[31:0]), - .i0 (i0[1:0]), - .i1 (i1[1:0])); + // Inputs + .cyc (cyc[31:0]), + .i0 (i0[1:0]), + .i1 (i1[1:0])); always @* begin q = {i0, i1, cyc[3:0]}; @@ -79,8 +79,8 @@ module inst2 (/*AUTOARG*/ ); /*verilator no_inline_module*/ // So we'll get a CELL under a GENFOR, without inlining input [31:0] cyc; - input [1:0] i0; - input [1:0] i1; + input [1:0] i0; + input [1:0] i1; initial begin if (cyc==32'h1) $write("[%0t] i0=%d i1=%d\n", $time, i0, i1); end diff --git a/test_regress/t/t_mem_packed.v b/test_regress/t/t_mem_packed.v index 2a90a7462..eb570fc5a 100644 --- a/test_regress/t/t_mem_packed.v +++ b/test_regress/t/t_mem_packed.v @@ -31,7 +31,7 @@ module t (/*AUTOARG*/ initial begin for (i0=0; i0<5; i0=i0+1) begin - arr[i0] = 1 << (i0[1:0]*2); + arr[i0] = 1 << (i0[1:0]*2); end end @@ -40,21 +40,21 @@ module t (/*AUTOARG*/ always @ (posedge clk) begin cyc <= cyc + 1; if (cyc==0) begin - // Setup - sum <= 0; - sum_w <= 0; + // Setup + sum <= 0; + sum_w <= 0; end else if (cyc >= 10 && cyc < 14) begin - sum <= sum + arr[cyc-10]; + sum <= sum + arr[cyc-10]; - sum_w <= sum_w + arr_w[cyc-10]; + sum_w <= sum_w + arr_w[cyc-10]; end else if (cyc==99) begin - $write("[%0t] cyc==%0d sum=%x\n", $time, cyc, sum); - if (sum != 8'h55) $stop; - if (sum != sum_w) $stop; - $write("*-* All Finished *-*\n"); - $finish; + $write("[%0t] cyc==%0d sum=%x\n", $time, cyc, sum); + if (sum != 8'h55) $stop; + if (sum != sum_w) $stop; + $write("*-* All Finished *-*\n"); + $finish; end end @@ -69,26 +69,26 @@ module t (/*AUTOARG*/ logic [31:0] last_data_out; always @ (posedge clk) begin if (cyc <= 2) begin - data_in[0][0] <= 0; - data_in[0][1] <= 0; - data_in[0][2] <= 0; - data_in2[0][0] <= 0; - data_in2[0][1] <= 0; - data_in2[0][2] <= 0; + data_in[0][0] <= 0; + data_in[0][1] <= 0; + data_in[0][2] <= 0; + data_in2[0][0] <= 0; + data_in2[0][1] <= 0; + data_in2[0][2] <= 0; end else if (cyc > 2 && cyc < 99) begin - data_in[0][0] <= data_in[0][0] + 1; - data_in[0][1] <= data_in[0][1] + 1; - data_in[0][2] <= data_in[0][2] + 1; - data_in2[0][0] <= data_in2[0][0] + 1; - data_in2[0][1] <= data_in2[0][1] + 1; - data_in2[0][2] <= data_in2[0][2] + 1; - last_data_out <= data_out; + data_in[0][0] <= data_in[0][0] + 1; + data_in[0][1] <= data_in[0][1] + 1; + data_in[0][2] <= data_in[0][2] + 1; + data_in2[0][0] <= data_in2[0][0] + 1; + data_in2[0][1] <= data_in2[0][1] + 1; + data_in2[0][2] <= data_in2[0][2] + 1; + last_data_out <= data_out; `ifdef TEST_VERBOSE - $write("data_out %0x %0x\n", data_out, last_data_out); + $write("data_out %0x %0x\n", data_out, last_data_out); `endif - if (cyc > 4 && data_out != last_data_out + 3) $stop; - if (cyc > 4 && data_out != data_out2) $stop; + if (cyc > 4 && data_out != last_data_out + 3) $stop; + if (cyc > 4 && data_out != data_out2) $stop; end end @@ -130,13 +130,13 @@ module t (/*AUTOARG*/ initial begin for (int i=0; i<4; i=i+2) begin for (int j=0; j<8; j=j+2) begin - vld[0][0][i][j] = 2'b00; - vld[0][0][i+1][j+1] = 2'b00; - vld2[i][j] = 2'b00; - vld2[i+1][j+1] = 2'b00; - not_rhs[i][j] = i[1:0]; - not_rhs[i+1][j+1] = i[1:0]; - end + vld[0][0][i][j] = 2'b00; + vld[0][0][i+1][j+1] = 2'b00; + vld2[i][j] = 2'b00; + vld2[i+1][j+1] = 2'b00; + not_rhs[i][j] = i[1:0]; + not_rhs[i+1][j+1] = i[1:0]; + end end end @@ -147,15 +147,15 @@ module t (/*AUTOARG*/ expect_cyc <= expect_cyc + 1; for (int i=0; i<4; i=i+1) begin for (int j=0; j<8; j=j+1) begin - vld[0][0][i][j] <= vld[0][0][i][j] + 1; - vld2[i][j] <= vld2[i][j] + 1; - if (not_rhs[i][j] != ~not_lhs[i][j]) $stop; - not_rhs[i][j] <= not_rhs[i][j] + 1; - end + vld[0][0][i][j] <= vld[0][0][i][j] + 1; + vld2[i][j] <= vld2[i][j] + 1; + if (not_rhs[i][j] != ~not_lhs[i][j]) $stop; + not_rhs[i][j] <= not_rhs[i][j] + 1; + end end if (cyc % 8 == 0) begin - vld[0][0][0][0] <= vld[0][0][0][0] - 1; - vld2[0][0] <= vld2[0][0] - 1; + vld[0][0][0][0] <= vld[0][0][0][0] - 1; + vld2[0][0] <= vld2[0][0] - 1; end if (expect_cyc < 8 && !vld_xor) $stop; else if (expect_cyc > 7 && vld_xor) $stop; diff --git a/test_regress/t/t_mem_shift.v b/test_regress/t/t_mem_shift.v index a2e84d6cf..af523b4fe 100644 --- a/test_regress/t/t_mem_shift.v +++ b/test_regress/t/t_mem_shift.v @@ -14,20 +14,20 @@ module t (/*AUTOARG*/ integer cyc; initial cyc = 0; reg [63:0] crc; - integer i; - reg [63:0] mem [7:0]; + integer i; + reg [63:0] mem [7:0]; always @ (posedge clk) begin if (cyc==1) begin - for (i=0; i<8; i=i+1) begin - mem[i] <= 64'h0; - end + for (i=0; i<8; i=i+1) begin + mem[i] <= 64'h0; + end end else begin - mem[0] <= crc; - for (i=1; i<8; i=i+1) begin - mem[i] <= mem[i-1]; - end + mem[0] <= crc; + for (i=1; i<8; i=i+1) begin + mem[i] <= mem[i-1]; + end end end @@ -38,14 +38,14 @@ module t (/*AUTOARG*/ cyc <= cyc + 1; crc <= {crc[62:0], crc[63] ^ crc[2] ^ crc[0]}; if (cyc==0) begin - // Setup - crc <= 64'h5aef0c8d_d70a4497; + // Setup + crc <= 64'h5aef0c8d_d70a4497; end else if (cyc==90) begin - if (outData != 64'h1265e3bddcd9bc27) $stop; + if (outData != 64'h1265e3bddcd9bc27) $stop; end else if (cyc==91) begin - if (outData != 64'h24cbc77bb9b3784e) $stop; + if (outData != 64'h24cbc77bb9b3784e) $stop; end else if (cyc==92) begin end @@ -54,8 +54,8 @@ module t (/*AUTOARG*/ else if (cyc==94) begin end else if (cyc==99) begin - $write("*-* All Finished *-*\n"); - $finish; + $write("*-* All Finished *-*\n"); + $finish; end end diff --git a/test_regress/t/t_mem_slice.v b/test_regress/t/t_mem_slice.v index fe084c1e3..66aa61509 100644 --- a/test_regress/t/t_mem_slice.v +++ b/test_regress/t/t_mem_slice.v @@ -29,7 +29,7 @@ module t (/*AUTOARG*/ logic [8:0][1:0] command_A4; logic [8:0][1:0] command_B4; - logic [8:0] pipe1 [7:0]; + logic [8:0] pipe1 [7:0]; logic [8:0] pipe1_input; integer cyc; @@ -62,19 +62,19 @@ module t (/*AUTOARG*/ cyc = 0; use_AnB = 0; for (int i = 0; i < 7; ++i) begin - command_A[i] = 2'b00; - command_B[i] = 2'b11; - command_A2[i] = 2'b00; - command_B2[i] = 2'b11; - pipe1_input = 9'b0; + command_A[i] = 2'b00; + command_B[i] = 2'b11; + command_A2[i] = 2'b00; + command_B2[i] = 2'b11; + pipe1_input = 9'b0; end for (int i = 0; i < 2; ++i) begin - for (int j = 0; j < 3; ++j) begin - for (int k = 0; k < 4; ++k) begin - command_A3[i][j][k] = 2'b00; - command_B3[i][j][k] = 2'b11; - end - end + for (int j = 0; j < 3; ++j) begin + for (int k = 0; k < 4; ++k) begin + command_A3[i][j][k] = 2'b00; + command_B3[i][j][k] = 2'b11; + end + end end end @@ -82,42 +82,42 @@ module t (/*AUTOARG*/ use_AnB <= ~use_AnB; cyc <= cyc + 1; if (use_AnB) begin - if (active_command[3] != 2'b00) begin - $stop; - end - if (active_command2[3] != 2'b00) begin - $stop; - end - if (active_command3[0][1][2] != 2'b00) begin - $stop; - end + if (active_command[3] != 2'b00) begin + $stop; + end + if (active_command2[3] != 2'b00) begin + $stop; + end + if (active_command3[0][1][2] != 2'b00) begin + $stop; + end end if (!use_AnB) begin - if (active_command[3] != 2'b11) begin - $stop; - end - if (active_command2[3] != 2'b11) begin - $stop; - end + if (active_command[3] != 2'b11) begin + $stop; + end + if (active_command2[3] != 2'b11) begin + $stop; + end end end logic [8:0] last_pipe; always @(posedge clk) begin if (cyc < 3) begin - last_pipe <= pipe1[0]; + last_pipe <= pipe1[0]; end else begin - if (last_pipe + 1 != pipe1[0]) begin - $stop; - end - else begin - last_pipe <= pipe1[0]; - end + if (last_pipe + 1 != pipe1[0]) begin + $stop; + end + else begin + last_pipe <= pipe1[0]; + end end if (cyc > 10) begin - $write("*-* All Finished *-*\n"); - $finish; + $write("*-* All Finished *-*\n"); + $finish; end end diff --git a/test_regress/t/t_mem_slice_conc_bad.v b/test_regress/t/t_mem_slice_conc_bad.v index cca91bb24..07b9bc4c2 100644 --- a/test_regress/t/t_mem_slice_conc_bad.v +++ b/test_regress/t/t_mem_slice_conc_bad.v @@ -14,17 +14,17 @@ module t (/*AUTOARG*/ ); input clk; - integer cyc = 0; - reg [63:0] crc; - reg [63:0] sum; + integer cyc = 0; + reg [63:0] crc; + reg [63:0] sum; // Take CRC data and apply to testblock inputs - wire rst; - data_t iii_in = crc[5:0]; - data_t jjj_in = crc[11:6]; - data_t iii_out; - data_t jjj_out; - logic [1:0] ctl0 = crc[63:62]; + wire rst; + data_t iii_in = crc[5:0]; + data_t jjj_in = crc[11:6]; + data_t iii_out; + data_t jjj_out; + logic [1:0] ctl0 = crc[63:62]; aaa aaa (.*); @@ -40,26 +40,26 @@ module t (/*AUTOARG*/ crc <= {crc[62:0], crc[63] ^ crc[2] ^ crc[0]}; sum <= result ^ {sum[62:0], sum[63] ^ sum[2] ^ sum[0]}; if (cyc==0) begin - // Setup - crc <= 64'h5aef0c8d_d70a4497; - sum <= 64'h0; - rst <= 1'b0; + // Setup + crc <= 64'h5aef0c8d_d70a4497; + sum <= 64'h0; + rst <= 1'b0; end else if (cyc<10) begin - sum <= 64'h0; - rst <= 1'b1; + sum <= 64'h0; + rst <= 1'b1; end else if (cyc<90) begin - rst <= 1'b0; + rst <= 1'b0; end else if (cyc==99) begin - $write("[%0t] cyc==%0d crc=%x sum=%x\n", $time, cyc, crc, sum); - if (crc !== 64'hc77bb9b3784ea091) $stop; - // What checksum will we end up with (above print should match) + $write("[%0t] cyc==%0d crc=%x sum=%x\n", $time, cyc, crc, sum); + if (crc !== 64'hc77bb9b3784ea091) $stop; + // What checksum will we end up with (above print should match) `define EXPECTED_SUM 64'h4afe43fb79d7b71e - if (sum !== `EXPECTED_SUM) $stop; - $write("*-* All Finished *-*\n"); - $finish; + if (sum !== `EXPECTED_SUM) $stop; + $write("*-* All Finished *-*\n"); + $finish; end end @@ -75,24 +75,24 @@ module bbb input logic rst ); - genvar i; + genvar i; generate for (i=0; i<2; i++) begin: PPP - always_ff @(posedge clk) begin - if (rst) begin - ggg_out[i] <= 6'b0; - end - else begin - if (ctl[i][0]) begin - if (ctl[i][1]) begin - ggg_out[i] <= ~ggg_in[i]; - end else begin - ggg_out[i] <= ggg_in[i]; - end - end - end - end + always_ff @(posedge clk) begin + if (rst) begin + ggg_out[i] <= 6'b0; + end + else begin + if (ctl[i][0]) begin + if (ctl[i][1]) begin + ggg_out[i] <= ~ggg_in[i]; + end else begin + ggg_out[i] <= ggg_in[i]; + end + end + end + end end endgenerate @@ -111,9 +111,9 @@ module aaa // Below is a bug; {} concat isn't used to make arrays bbb bbb ( - .ggg_in ({jjj_in, iii_in}), - .ggg_out ({jjj_out, iii_out}), - .ctl ({{1'b1,ctl0[1]}, {1'b0,ctl0[0]}}), + .ggg_in ({jjj_in, iii_in}), + .ggg_out ({jjj_out, iii_out}), + .ctl ({{1'b1,ctl0[1]}, {1'b0,ctl0[0]}}), .*); endmodule diff --git a/test_regress/t/t_mem_twoedge.v b/test_regress/t/t_mem_twoedge.v index 8d4f48303..c180efbd4 100644 --- a/test_regress/t/t_mem_twoedge.v +++ b/test_regress/t/t_mem_twoedge.v @@ -10,30 +10,30 @@ module t (/*AUTOARG*/ ); input clk; - integer cyc = 0; - reg [63:0] crc; - reg [63:0] sum; + integer cyc = 0; + reg [63:0] crc; + reg [63:0] sum; // verilator lint_off MULTIDRIVEN /*AUTOWIRE*/ // Beginning of automatic wires (for undeclared instantiated-module outputs) - wire [31:0] out; // From test of Test.v - wire [15:0] out2; // From test of Test.v + wire [31:0] out; // From test of Test.v + wire [15:0] out2; // From test of Test.v // End of automatics // verilator lint_on MULTIDRIVEN Test test ( - .en (crc[21:20]), - .a1 (crc[19:18]), - .a0 (crc[17:16]), - .d1 (crc[15:8]), - .d0 (crc[7:0]), - /*AUTOINST*/ - // Outputs - .out (out[31:0]), - .out2 (out2[15:0]), - // Inputs - .clk (clk)); + .en (crc[21:20]), + .a1 (crc[19:18]), + .a0 (crc[17:16]), + .d1 (crc[15:8]), + .d0 (crc[7:0]), + /*AUTOINST*/ + // Outputs + .out (out[31:0]), + .out2 (out2[15:0]), + // Inputs + .clk (clk)); // Aggregate outputs into a single result vector wire [63:0] result = {out2, 16'h0, out}; @@ -52,25 +52,25 @@ module t (/*AUTOARG*/ crc <= {crc[62:0], crc[63] ^ crc[2] ^ crc[0]}; sum <= result ^ {sum[62:0], sum[63] ^ sum[2] ^ sum[0]}; if (cyc==0) begin - // Setup - crc <= 64'h5aef0c8d_d70a4497; - sum <= 64'h0; - test.clear(); + // Setup + crc <= 64'h5aef0c8d_d70a4497; + sum <= 64'h0; + test.clear(); end else if (cyc<10) begin - sum <= 64'h0; - test.clear(); + sum <= 64'h0; + test.clear(); end else if (cyc<90) begin end else if (cyc==99) begin - $write("[%0t] cyc==%0d crc=%x sum=%x\n", $time, cyc, crc, sum); - if (crc !== 64'hc77bb9b3784ea091) $stop; - // What checksum will we end up with (above print should match) + $write("[%0t] cyc==%0d crc=%x sum=%x\n", $time, cyc, crc, sum); + if (crc !== 64'hc77bb9b3784ea091) $stop; + // What checksum will we end up with (above print should match) `define EXPECTED_SUM 64'hc68a94a34ec970aa - if (sum !== `EXPECTED_SUM) $stop; - $write("*-* All Finished *-*\n"); - $finish; + if (sum !== `EXPECTED_SUM) $stop; + $write("*-* All Finished *-*\n"); + $finish; end end @@ -93,7 +93,7 @@ module Test (/*AUTOARG*/ // verilator lint_off MULTIDRIVEN output reg [15:0] out2; - reg [7:0] mem [4]; + reg [7:0] mem [4]; // verilator lint_on MULTIDRIVEN task clear(); @@ -102,14 +102,14 @@ module Test (/*AUTOARG*/ always @(posedge clk) begin if (en[0]) begin - mem[a0] <= d0; - out2[7:0] <= d0; + mem[a0] <= d0; + out2[7:0] <= d0; end end always @(negedge clk) begin if (en[1]) begin - mem[a1] <= d1; - out2[15:8] <= d0; + mem[a1] <= d1; + out2[15:8] <= d0; end end diff --git a/test_regress/t/t_mod_interface_array0.v b/test_regress/t/t_mod_interface_array0.v index 00c600b91..ea9a4914e 100644 --- a/test_regress/t/t_mod_interface_array0.v +++ b/test_regress/t/t_mod_interface_array0.v @@ -19,7 +19,7 @@ module intf_source ); generate for (genvar i=0; i < N;i++) begin - assign i_intf_source[i].long_name = intf_input[i]; + assign i_intf_source[i].long_name = intf_input[i]; end endgenerate endmodule @@ -31,7 +31,7 @@ module intf_sink ); generate for (genvar i=0; i < N;i++) begin - assign a_out[i] = i_intf_sink[i].long_name; + assign a_out[i] = i_intf_sink[i].long_name; end endgenerate endmodule diff --git a/test_regress/t/t_mod_interface_array1.v b/test_regress/t/t_mod_interface_array1.v index f524a79a6..bd497af90 100644 --- a/test_regress/t/t_mod_interface_array1.v +++ b/test_regress/t/t_mod_interface_array1.v @@ -19,7 +19,7 @@ module intf_source ); generate for (genvar i=0; i < N;i++) begin - assign i_intf_source[i].long_name = intf_input[i]; + assign i_intf_source[i].long_name = intf_input[i]; end endgenerate endmodule @@ -31,7 +31,7 @@ module intf_sink ); generate for (genvar i=0; i < N;i++) begin - assign a_out[i] = i_intf_sink[i].long_name; + assign a_out[i] = i_intf_sink[i].long_name; end endgenerate endmodule diff --git a/test_regress/t/t_mod_interface_array2.v b/test_regress/t/t_mod_interface_array2.v index 0c8101c6b..b7f7647f8 100644 --- a/test_regress/t/t_mod_interface_array2.v +++ b/test_regress/t/t_mod_interface_array2.v @@ -20,7 +20,7 @@ module intf_source ); generate for (genvar i=0; i < N;i++) begin - assign i_intf_source[i].long_name = intf_input[i]; + assign i_intf_source[i].long_name = intf_input[i]; end endgenerate endmodule @@ -32,7 +32,7 @@ module intf_sink ); generate for (genvar i=0; i < N;i++) begin - assign a_out[i] = i_intf_sink[i].long_name; + assign a_out[i] = i_intf_sink[i].long_name; end endgenerate endmodule diff --git a/test_regress/t/t_mod_recurse.v b/test_regress/t/t_mod_recurse.v index 370900e77..7236d83b3 100644 --- a/test_regress/t/t_mod_recurse.v +++ b/test_regress/t/t_mod_recurse.v @@ -10,9 +10,9 @@ module t (/*AUTOARG*/ ); input clk; - integer cyc = 0; - reg [63:0] crc; - reg [63:0] sum; + integer cyc = 0; + reg [63:0] crc; + reg [63:0] sum; // Take CRC data and apply to testblock inputs wire [7:0] tripline = crc[7:0]; @@ -37,23 +37,23 @@ module t (/*AUTOARG*/ crc <= {crc[62:0], crc[63] ^ crc[2] ^ crc[0]}; sum <= result ^ {sum[62:0], sum[63] ^ sum[2] ^ sum[0]}; if (cyc==0) begin - // Setup - crc <= 64'h5aef0c8d_d70a4497; - sum <= 64'h0; + // Setup + crc <= 64'h5aef0c8d_d70a4497; + sum <= 64'h0; end else if (cyc<10) begin - sum <= 64'h0; + sum <= 64'h0; end else if (cyc<90) begin end else if (cyc==99) begin - $write("[%0t] cyc==%0d crc=%x sum=%x\n", $time, cyc, crc, sum); - if (crc !== 64'hc77bb9b3784ea091) $stop; - // What checksum will we end up with (above print should match) + $write("[%0t] cyc==%0d crc=%x sum=%x\n", $time, cyc, crc, sum); + if (crc !== 64'hc77bb9b3784ea091) $stop; + // What checksum will we end up with (above print should match) `define EXPECTED_SUM 64'hc5fc632f816568fb - if (sum !== `EXPECTED_SUM) $stop; - $write("*-* All Finished *-*\n"); - $finish; + if (sum !== `EXPECTED_SUM) $stop; + $write("*-* All Finished *-*\n"); + $finish; end end @@ -67,45 +67,45 @@ module PriorityChoice (out, outN, tripline); output reg out; output reg [OCODEWIDTH-1:0] outN; input wire [(1< 0) begin - runner = runnerm1; - runnerq = runnerq - 60'd1; - runnerw = runnerw - 90'd1; - $write ("[%0t] runner=%d\n", $time, runner); + runner = runnerm1; + runnerq = runnerq - 60'd1; + runnerw = runnerw - 90'd1; + $write ("[%0t] runner=%d\n", $time, runner); end end diff --git a/test_regress/t/t_order_doubleloop.v b/test_regress/t/t_order_doubleloop.v index 8607ccc96..d5ffae5f8 100644 --- a/test_regress/t/t_order_doubleloop.v +++ b/test_regress/t/t_order_doubleloop.v @@ -29,26 +29,26 @@ module t (/*AUTOARG*/ $write("[%0t] cyc %d\n", $time,cyc); cyc <= cyc + 1; if (cyc==2) begin - // Test # of iters - lastdlycnt = 0; - comcnt = 0; - dlycnt <= 0; + // Test # of iters + lastdlycnt = 0; + comcnt = 0; + dlycnt <= 0; end if (cyc==3) begin - dlyrun <= 5; - dlycnt <= 0; + dlyrun <= 5; + dlycnt <= 0; end if (cyc==4) begin - comrun = 4; + comrun = 4; end end always @ (negedge clk) begin if (cyc==5) begin - $display("%d %d\n", dlycnt, comcnt); - if (dlycnt != 32'd5) $stop; - if (comcnt != 32'd19) $stop; - $write("*-* All Finished *-*\n"); - $finish; + $display("%d %d\n", dlycnt, comcnt); + if (dlycnt != 32'd5) $stop; + if (comcnt != 32'd19) $stop; + $write("*-* All Finished *-*\n"); + $finish; end end @@ -56,25 +56,25 @@ module t (/*AUTOARG*/ reg runclk; initial runclk = 1'b0; always @ (/*AS*/comrunm1 or dlycnt) begin if (lastdlycnt != dlycnt) begin - comrun = 3; - $write ("[%0t] comrun=%0d start\n", $time, comrun); + comrun = 3; + $write ("[%0t] comrun=%0d start\n", $time, comrun); end else if (comrun > 0) begin - comrun = comrunm1; - if (comrunm1==1) begin - runclk = 1; - $write ("[%0t] comrun=%0d [trigger clk]\n", $time, comrun); - end - else $write ("[%0t] comrun=%0d\n", $time, comrun); + comrun = comrunm1; + if (comrunm1==1) begin + runclk = 1; + $write ("[%0t] comrun=%0d [trigger clk]\n", $time, comrun); + end + else $write ("[%0t] comrun=%0d\n", $time, comrun); end lastdlycnt = dlycnt; end always @ (/*AS*/comrun) begin if (comrun!=0) begin - comrunm1 = comrun - 32'd1; - comcnt = comcnt + 32'd1; - $write("[%0t] comcnt=%0d\n", $time,comcnt); + comrunm1 = comrun - 32'd1; + comcnt = comcnt + 32'd1; + $write("[%0t] comcnt=%0d\n", $time,comcnt); end end @@ -84,17 +84,17 @@ module t (/*AUTOARG*/ runclkrst <= 1; $write ("[%0t] runclk\n", $time); if (dlyrun > 0) begin - dlyrun <= dlyrun - 32'd1; - dlycnt <= dlycnt + 32'd1; - $write ("[%0t] dlyrun<=%0d\n", $time, dlyrun-32'd1); + dlyrun <= dlyrun - 32'd1; + dlycnt <= dlycnt + 32'd1; + $write ("[%0t] dlyrun<=%0d\n", $time, dlyrun-32'd1); end end always @* begin if (runclkrst) begin - $write ("[%0t] runclk reset\n", $time); - runclkrst = 0; - runclk = 0; + $write ("[%0t] runclk reset\n", $time); + runclkrst = 0; + runclk = 0; end end diff --git a/test_regress/t/t_order_first.v b/test_regress/t/t_order_first.v index 5fe4d1c54..79c3516e8 100644 --- a/test_regress/t/t_order_first.v +++ b/test_regress/t/t_order_first.v @@ -11,10 +11,10 @@ module t (/*AUTOARG*/ input fastclk; t_netlist tnetlist - (.also_fastclk (fastclk), + (.also_fastclk (fastclk), /*AUTOINST*/ // Inputs - .fastclk (fastclk)); + .fastclk (fastclk)); endmodule @@ -52,10 +52,10 @@ module t_netlist (/*AUTOARG*/ always @ (posedge also_fastclk) begin if (_mode==5) begin - if (a2 != 5'd2) $stop; - if (e != 5'd5) $stop; - $write("*-* All Finished *-*\n"); - $finish; + if (a2 != 5'd2) $stop; + if (e != 5'd5) $stop; + $write("*-* All Finished *-*\n"); + $finish; end _mode <= _mode + 1; end diff --git a/test_regress/t/t_order_multialways.v b/test_regress/t/t_order_multialways.v index 65d500455..f38590db8 100644 --- a/test_regress/t/t_order_multialways.v +++ b/test_regress/t/t_order_multialways.v @@ -38,25 +38,25 @@ module t (/*AUTOARG*/ integer cyc; initial cyc=1; always @ (posedge clk) begin if (cyc!=0) begin - cyc <= cyc + 1; - //$write("%d %x %x\n", cyc, h, h2); - if (h != h2) $stop; - if (cyc==1) begin - in_a <= 32'h89a14fab; - in_b <= 32'h7ab512fa; - end - if (cyc==2) begin - in_a <= 32'hf4c11a42; - in_b <= 32'h359967c6; - if (h != 32'h4fab89a1) $stop; - end - if (cyc==3) begin - if (h != 32'h1a42f4c1) $stop; - end - if (cyc==9) begin - $write("*-* All Finished *-*\n"); - $finish; - end + cyc <= cyc + 1; + //$write("%d %x %x\n", cyc, h, h2); + if (h != h2) $stop; + if (cyc==1) begin + in_a <= 32'h89a14fab; + in_b <= 32'h7ab512fa; + end + if (cyc==2) begin + in_a <= 32'hf4c11a42; + in_b <= 32'h359967c6; + if (h != 32'h4fab89a1) $stop; + end + if (cyc==3) begin + if (h != 32'h1a42f4c1) $stop; + end + if (cyc==9) begin + $write("*-* All Finished *-*\n"); + $finish; + end end end endmodule diff --git a/test_regress/t/t_order_multidriven.v b/test_regress/t/t_order_multidriven.v index b91f81797..04ba843e4 100644 --- a/test_regress/t/t_order_multidriven.v +++ b/test_regress/t/t_order_multidriven.v @@ -125,8 +125,8 @@ module FooRd( `ifdef TEST_VERBOSE $display( "MEM[%x] == %x", addr_r, i_rdata ); `endif - if (addr_r != i_rdata) $stop; - end + if (addr_r != i_rdata) $stop; + end endmodule diff --git a/test_regress/t/t_package_abs.v b/test_regress/t/t_package_abs.v index b91b45a97..fa63ba7a1 100644 --- a/test_regress/t/t_package_abs.v +++ b/test_regress/t/t_package_abs.v @@ -20,14 +20,14 @@ module t (); localparam P = 1; generate if (P == 1) begin - initial begin - if (abs(-2.1) != 2.1) $stop; - if (abs(2.2) != 2.2) $stop; - if (neg(-2.1) != -2.1) $stop; - if (neg(2.2) != -2.2) $stop; - $write("*-* All Finished *-*\n"); - $finish; - end + initial begin + if (abs(-2.1) != 2.1) $stop; + if (abs(2.2) != 2.2) $stop; + if (neg(-2.1) != -2.1) $stop; + if (neg(2.2) != -2.2) $stop; + $write("*-* All Finished *-*\n"); + $finish; + end end endgenerate endmodule diff --git a/test_regress/t/t_package_dimport.v b/test_regress/t/t_package_dimport.v index 8d8baddb0..7676ab881 100644 --- a/test_regress/t/t_package_dimport.v +++ b/test_regress/t/t_package_dimport.v @@ -55,15 +55,15 @@ module t(/*AUTOARG*/ generate if (WHICH == 1) - begin : which_true + begin : which_true sub sub_true(); defparam sub_true.RAND_NUM_MAX = MAX_EXPONENT; - end + end else - begin : which_false + begin : which_false sub sub_false(); defparam sub_false.RAND_NUM_MAX = MAX_COUNT; - end + end endgenerate endmodule diff --git a/test_regress/t/t_package_param.v b/test_regress/t/t_package_param.v index 5fa2e81fc..c13eef367 100644 --- a/test_regress/t/t_package_param.v +++ b/test_regress/t/t_package_param.v @@ -28,11 +28,11 @@ module t(/*AUTOARG*/ // Check we have the right definition always @(posedge clk) begin if (NUM == 32) begin - $write("*-* All Finished *-*\n"); - $finish; + $write("*-* All Finished *-*\n"); + $finish; end else begin - $stop; + $stop; end end diff --git a/test_regress/t/t_param.v b/test_regress/t/t_param.v index 9f84db5cf..884b8f23c 100644 --- a/test_regress/t/t_param.v +++ b/test_regress/t/t_param.v @@ -21,16 +21,16 @@ module t (/*AUTOARG*/ always @ (posedge clk) begin cyc <= cyc + 1; if (cyc==0) begin - bitsel = 0; - if (PAR[bitsel]!==1'b1) $stop; - bitsel = 1; - if (PAR[bitsel]!==1'b1) $stop; - bitsel = 2; - if (PAR[bitsel]!==1'b0) $stop; + bitsel = 0; + if (PAR[bitsel]!==1'b1) $stop; + bitsel = 1; + if (PAR[bitsel]!==1'b1) $stop; + bitsel = 2; + if (PAR[bitsel]!==1'b0) $stop; end if (cyc==1) begin - $write("*-* All Finished *-*\n"); - $finish; + $write("*-* All Finished *-*\n"); + $finish; end end diff --git a/test_regress/t/t_param_array.v b/test_regress/t/t_param_array.v index 2a58a1318..7b9805c88 100644 --- a/test_regress/t/t_param_array.v +++ b/test_regress/t/t_param_array.v @@ -7,61 +7,61 @@ module t (/*AUTOARG*/); typedef enum int { - PADTYPE_DEFAULT = 32'd0, - PADTYPE_GPIO, - PADTYPE_VDD, - PADTYPE_GND - } t_padtype; + PADTYPE_DEFAULT = 32'd0, + PADTYPE_GPIO, + PADTYPE_VDD, + PADTYPE_GND + } t_padtype; localparam int STR_PINID [0:15] - = '{ - "DEF", "ERR", "ERR", "ERR", "ERR", "ERR", "ERR", "ERR", - "PA0", "PA1", "PA2", "PA3", "PA4", "PA5", "PA6", "PA7" - }; + = '{ + "DEF", "ERR", "ERR", "ERR", "ERR", "ERR", "ERR", "ERR", + "PA0", "PA1", "PA2", "PA3", "PA4", "PA5", "PA6", "PA7" + }; typedef struct packed { t_padtype padtype; - int aux; + int aux; } t_pin_descriptor; localparam t_pin_descriptor PINOUT[ 1: 6] = '{ - '{default:0, padtype:PADTYPE_GPIO, aux:1}, - '{default:0, padtype:PADTYPE_GPIO}, - '{default:0, padtype:PADTYPE_GPIO}, - '{default:0, padtype:PADTYPE_GPIO}, - '{default:0, padtype:PADTYPE_VDD}, - '{default:0, padtype:PADTYPE_GND} - }; + '{default:0, padtype:PADTYPE_GPIO, aux:1}, + '{default:0, padtype:PADTYPE_GPIO}, + '{default:0, padtype:PADTYPE_GPIO}, + '{default:0, padtype:PADTYPE_GPIO}, + '{default:0, padtype:PADTYPE_VDD}, + '{default:0, padtype:PADTYPE_GND} + }; localparam int PINOUT_SIZE = 6; localparam int PINOUT_WA[1:PINOUT_SIZE][3] - = '{ - '{0, PADTYPE_GPIO, 0}, - '{1, PADTYPE_GPIO, 0}, - '{2, PADTYPE_GPIO, 0}, - '{5, PADTYPE_GPIO, 0}, - '{6, PADTYPE_VDD, 0}, - '{8, PADTYPE_GND , 0} - }; + = '{ + '{0, PADTYPE_GPIO, 0}, + '{1, PADTYPE_GPIO, 0}, + '{2, PADTYPE_GPIO, 0}, + '{5, PADTYPE_GPIO, 0}, + '{6, PADTYPE_VDD, 0}, + '{8, PADTYPE_GND , 0} + }; const int pinout_static_const[1:PINOUT_SIZE][3] - = '{ - '{0, PADTYPE_GPIO, 0}, - '{1, PADTYPE_GPIO, 0}, - '{2, PADTYPE_GPIO, 0}, - '{5, PADTYPE_GPIO, 0}, - '{6, PADTYPE_VDD, 0}, - '{8, PADTYPE_GND , 0} - }; + = '{ + '{0, PADTYPE_GPIO, 0}, + '{1, PADTYPE_GPIO, 0}, + '{2, PADTYPE_GPIO, 0}, + '{5, PADTYPE_GPIO, 0}, + '{6, PADTYPE_VDD, 0}, + '{8, PADTYPE_GND , 0} + }; // Make sure consants propagate checkstr #(.PINID(STR_PINID[1]), - .EXP("ERR")) + .EXP("ERR")) substr1 (); checkstr #(.PINID(STR_PINID[8]), - .EXP("PA0")) + .EXP("PA0")) substr8 (); initial begin diff --git a/test_regress/t/t_param_bit_sel.v b/test_regress/t/t_param_bit_sel.v index 9159485f4..03a381a11 100644 --- a/test_regress/t/t_param_bit_sel.v +++ b/test_regress/t/t_param_bit_sel.v @@ -22,11 +22,11 @@ module t (/*AUTOARG*/ always @(posedge clk) begin if (b == 1'b0) begin - $write("*-* All Finished *-*\n"); - $finish; + $write("*-* All Finished *-*\n"); + $finish; end else begin - $stop; + $stop; end end diff --git a/test_regress/t/t_param_ceil.v b/test_regress/t/t_param_ceil.v index e66c57db0..645c5104b 100644 --- a/test_regress/t/t_param_ceil.v +++ b/test_regress/t/t_param_ceil.v @@ -8,12 +8,12 @@ module t (/*AUTOARG*/); /*AUTOWIRE*/ // Beginning of automatic wires (for undeclared instantiated-module outputs) - wire [31:0] O_out; // From test of Test.v + wire [31:0] O_out; // From test of Test.v // End of automatics Test test (/*AUTOINST*/ - // Outputs - .O_out (O_out[31:0])); + // Outputs + .O_out (O_out[31:0])); initial begin if (O_out != 32'h4) $stop; @@ -34,8 +34,8 @@ module Test .pBAR(2) ) U_test ( - .O_out(O_out) - ); + .O_out(O_out) + ); endmodule module test diff --git a/test_regress/t/t_param_chain.v b/test_regress/t/t_param_chain.v index 80ee98fda..a74a93ef3 100644 --- a/test_regress/t/t_param_chain.v +++ b/test_regress/t/t_param_chain.v @@ -10,10 +10,10 @@ module t (/*AUTOARG*/); input integer x; input integer y; begin - begin : blk - automatic int temp; - temp = x; - end + begin : blk + automatic int temp; + temp = x; + end end max2 = ( x > y ) ? x : y; endfunction diff --git a/test_regress/t/t_param_first.v b/test_regress/t/t_param_first.v index 8e812bd3c..2ef817ccb 100644 --- a/test_regress/t/t_param_first.v +++ b/test_regress/t/t_param_first.v @@ -10,22 +10,22 @@ module t(/*AUTOARG*/ ); input clk; - reg _ranit; + reg _ranit; /*AUTOWIRE*/ // Beginning of automatic wires (for undeclared instantiated-module outputs) - wire [4:0] par1; // From a1 of t_param_first_a.v - wire [4:0] par2; // From a2 of t_param_first_a.v - wire [4:0] par3; // From a3 of t_param_first_a.v - wire [4:0] par4; // From a4 of t_param_first_a.v - wire [1:0] varwidth1; // From a1 of t_param_first_a.v - wire [2:0] varwidth2; // From a2 of t_param_first_a.v - wire [3:0] varwidth3; // From a3 of t_param_first_a.v - wire [3:0] varwidth4; // From a4 of t_param_first_a.v + wire [4:0] par1; // From a1 of t_param_first_a.v + wire [4:0] par2; // From a2 of t_param_first_a.v + wire [4:0] par3; // From a3 of t_param_first_a.v + wire [4:0] par4; // From a4 of t_param_first_a.v + wire [1:0] varwidth1; // From a1 of t_param_first_a.v + wire [2:0] varwidth2; // From a2 of t_param_first_a.v + wire [3:0] varwidth3; // From a3 of t_param_first_a.v + wire [3:0] varwidth4; // From a4 of t_param_first_a.v // End of automatics /*t_param_first_a AUTO_TEMPLATE ( - .par (par@[])); - .varwidth (varwidth@[])); + .par (par@[])); + .varwidth (varwidth@[])); */ parameter XX = 2'bXX; @@ -35,31 +35,31 @@ module t(/*AUTOARG*/ t_param_first_a #(1,5) a1 ( // Outputs - .varwidth (varwidth1[1:0]), + .varwidth (varwidth1[1:0]), /*AUTOINST*/ // Outputs - .par (par1[4:0])); // Templated + .par (par1[4:0])); // Templated t_param_first_a #(2,5) a2 ( // Outputs - .varwidth (varwidth2[2:0]), + .varwidth (varwidth2[2:0]), /*AUTOINST*/ // Outputs - .par (par2[4:0])); // Templated + .par (par2[4:0])); // Templated t_param_first_a #(THREE,5) a3 ( // Outputs - .varwidth (varwidth3[3:0]), + .varwidth (varwidth3[3:0]), /*AUTOINST*/ // Outputs - .par (par3[4:0])); // Templated + .par (par3[4:0])); // Templated t_param_first_a #(THREE,5) a4 ( // Outputs - .varwidth (varwidth4[3:0]), + .varwidth (varwidth4[3:0]), /*AUTOINST*/ // Outputs - .par (par4[4:0])); // Templated + .par (par4[4:0])); // Templated parameter THREE_BITS_WIDE = 3'b011; parameter THREE_2WIDE = 2'b11; @@ -71,12 +71,12 @@ module t(/*AUTOARG*/ // But the width of a RHS/LHS on a upper node does affect lower nodes; // Thus must double-descend in width analysis. // VCS 7.0.1 is broken on this test! - parameter T10 = (3'h7+3'h7)+4'h0; //initial if (T10!==4'd14) $stop; - parameter T11 = 4'h0+(3'h7+3'h7); //initial if (T11!==4'd14) $stop; + parameter T10 = (3'h7+3'h7)+4'h0; //initial if (T10!==4'd14) $stop; + parameter T11 = 4'h0+(3'h7+3'h7); //initial if (T11!==4'd14) $stop; // Parameters assign LHS is affectively width zero. - parameter T12 = THREE_2WIDE + THREE_2WIDE; initial if (T12!==2'd2) $stop; - parameter T13 = THREE_2WIDE + 3; initial if (T13!==32'd6) $stop; + parameter T12 = THREE_2WIDE + THREE_2WIDE; initial if (T12!==2'd2) $stop; + parameter T13 = THREE_2WIDE + 3; initial if (T13!==32'd6) $stop; // Must be careful about LSB's with extracts parameter [39:8] T14 = 32'h00_1234_56; initial if (T14[24:16]!==9'h34) $stop; @@ -84,7 +84,7 @@ module t(/*AUTOARG*/ // parameter THREEPP_32P_WIDE = 3'd4*3'd4*2+3'd3; parameter THREE_32_WIDE = 3%32; - parameter THIRTYTWO = 2; // Param is 32 bits + parameter THIRTYTWO = 2; // Param is 32 bits parameter [40:0] WIDEPARAM = 41'h12_3456789a; parameter [40:0] WIDEPARAM2 = WIDEPARAM; @@ -100,47 +100,47 @@ module t(/*AUTOARG*/ always @ (posedge clk) begin if (!_ranit) begin - _ranit <= 1; - $write("[%0t] t_param: Running\n", $time); - // - $write(" %d %d %d\n", par1,par2,par3); - if (par1!==5'd1) $stop; - if (par2!==5'd2) $stop; - if (par3!==5'd3) $stop; - if (par4!==5'd3) $stop; - if (varwidth1!==2'd2) $stop; - if (varwidth2!==3'd2) $stop; - if (varwidth3!==4'd2) $stop; - if (varwidth4!==4'd2) $stop; - if (threebits !== 3'b011) $stop; - if (eight !== 8'b00010000) $stop; - if (eight2two !== 2'b10) $stop; - $write(" Params = %b %b\n %b %b\n", - THREEPP_32_WIDE,THREEPP_3_WIDE, - THIRTYTWO, THREEPP_32P_WIDE); - if (THREEPP_32_WIDE !== 32'h23) $stop; - if (THREEPP_3_WIDE !== 3'h3) $stop; - if (THREEPP_32P_WIDE !== 32'h23) $stop; - if (THIRTYTWO[1:0] !== 2'h2) $stop; - if (THIRTYTWO !== 32'h2) $stop; - if (THIRTYTWO !== 2) $stop; - if ((THIRTYTWO[1:0]+2'b00) !== 2'b10) $stop; - if ({1'b1,{THIRTYTWO[1:0]+2'b00}} !== 3'b110) $stop; - if (XX===0 || XX===1 || XX===2 || XX===3) $stop; // Paradoxical but right, since 1'bx!=0 && !=1 - // - // Example of assignment LHS affecting expression widths. - // verilator lint_off WIDTH - // surefire lint_off ASWCMB - // surefire lint_off ASWCBB - eightb = (4'd8+4'd8)/4'd4; if (eightb!==8'd4) $stop; - fourb = (4'd8+4'd8)/4'd4; if (fourb!==4'd0) $stop; - fourb = (4'd8+8)/4'd4; if (fourb!==4'd4) $stop; - // verilator lint_on WIDTH - // surefire lint_on ASWCMB - // surefire lint_on ASWCBB - // - $write("*-* All Finished *-*\n"); - $finish; + _ranit <= 1; + $write("[%0t] t_param: Running\n", $time); + // + $write(" %d %d %d\n", par1,par2,par3); + if (par1!==5'd1) $stop; + if (par2!==5'd2) $stop; + if (par3!==5'd3) $stop; + if (par4!==5'd3) $stop; + if (varwidth1!==2'd2) $stop; + if (varwidth2!==3'd2) $stop; + if (varwidth3!==4'd2) $stop; + if (varwidth4!==4'd2) $stop; + if (threebits !== 3'b011) $stop; + if (eight !== 8'b00010000) $stop; + if (eight2two !== 2'b10) $stop; + $write(" Params = %b %b\n %b %b\n", + THREEPP_32_WIDE,THREEPP_3_WIDE, + THIRTYTWO, THREEPP_32P_WIDE); + if (THREEPP_32_WIDE !== 32'h23) $stop; + if (THREEPP_3_WIDE !== 3'h3) $stop; + if (THREEPP_32P_WIDE !== 32'h23) $stop; + if (THIRTYTWO[1:0] !== 2'h2) $stop; + if (THIRTYTWO !== 32'h2) $stop; + if (THIRTYTWO !== 2) $stop; + if ((THIRTYTWO[1:0]+2'b00) !== 2'b10) $stop; + if ({1'b1,{THIRTYTWO[1:0]+2'b00}} !== 3'b110) $stop; + if (XX===0 || XX===1 || XX===2 || XX===3) $stop; // Paradoxical but right, since 1'bx!=0 && !=1 + // + // Example of assignment LHS affecting expression widths. + // verilator lint_off WIDTH + // surefire lint_off ASWCMB + // surefire lint_off ASWCBB + eightb = (4'd8+4'd8)/4'd4; if (eightb!==8'd4) $stop; + fourb = (4'd8+4'd8)/4'd4; if (fourb!==4'd0) $stop; + fourb = (4'd8+8)/4'd4; if (fourb!==4'd4) $stop; + // verilator lint_on WIDTH + // surefire lint_on ASWCMB + // surefire lint_on ASWCBB + // + $write("*-* All Finished *-*\n"); + $finish; end end diff --git a/test_regress/t/t_param_first_a.v b/test_regress/t/t_param_first_a.v index 66c180b2d..accad60bb 100644 --- a/test_regress/t/t_param_first_a.v +++ b/test_regress/t/t_param_first_a.v @@ -15,14 +15,14 @@ module t_param_first_a (/*AUTOARG*/ /*AUTOOUTPUT*/ // Beginning of automatic outputs (from unused autoinst outputs) - output [4:0] par; // From b of t_param_first_b.v - output [X:0] varwidth; // From b of t_param_first_b.v + output [4:0] par; // From b of t_param_first_b.v + output [X:0] varwidth; // From b of t_param_first_b.v // End of automatics t_param_first_b #(X,FIVE,TWO) b (/*AUTOINST*/ // Outputs - .par (par[4:0]), - .varwidth (varwidth[X:0])); + .par (par[4:0]), + .varwidth (varwidth[X:0])); endmodule diff --git a/test_regress/t/t_param_first_b.v b/test_regress/t/t_param_first_b.v index 99e8971c1..ab49f7be1 100644 --- a/test_regress/t/t_param_first_b.v +++ b/test_regress/t/t_param_first_b.v @@ -13,10 +13,10 @@ module t_param_first_b (/*AUTOARG*/ parameter FIVE = 0; // Overridden parameter TWO = 2; - output [4:0] par; - output [X:0] varwidth; + output [4:0] par; + output [X:0] varwidth; - wire [4:0] par = X; - wire [X:0] varwidth = (FIVE==5)?TWO:0; + wire [4:0] par = X; + wire [X:0] varwidth = (FIVE==5)?TWO:0; endmodule diff --git a/test_regress/t/t_param_if_blk.v b/test_regress/t/t_param_if_blk.v index b3a24bfdf..ad660b739 100644 --- a/test_regress/t/t_param_if_blk.v +++ b/test_regress/t/t_param_if_blk.v @@ -12,9 +12,9 @@ module t (/*AUTOARG*/ ); input clk; - integer cyc = 0; - reg [63:0] crc; - reg [63:0] sum; + integer cyc = 0; + reg [63:0] crc; + reg [63:0] sum; // Take CRC data and apply to testblock inputs wire [7:0] datai = crc[7:0]; @@ -22,16 +22,16 @@ module t (/*AUTOARG*/ /*AUTOWIRE*/ // Beginning of automatic wires (for undeclared instantiated-module outputs) - logic [7:0] datao; // From test of Test.v + logic [7:0] datao; // From test of Test.v // End of automatics Test test (/*AUTOINST*/ - // Outputs - .datao (datao[7:0]), - // Inputs - .clk (clk), - .datai (datai[7:0]), - .enable (enable)); + // Outputs + .datao (datao[7:0]), + // Inputs + .clk (clk), + .datai (datai[7:0]), + .enable (enable)); // Aggregate outputs into a single result vector wire [63:0] result = {56'h0, datao}; @@ -45,23 +45,23 @@ module t (/*AUTOARG*/ crc <= {crc[62:0], crc[63] ^ crc[2] ^ crc[0]}; sum <= result ^ {sum[62:0], sum[63] ^ sum[2] ^ sum[0]}; if (cyc==0) begin - // Setup - crc <= 64'h5aef0c8d_d70a4497; - sum <= 64'h0; + // Setup + crc <= 64'h5aef0c8d_d70a4497; + sum <= 64'h0; end else if (cyc<10) begin - sum <= 64'h0; + sum <= 64'h0; end else if (cyc<90) begin end else if (cyc==99) begin - $write("[%0t] cyc==%0d crc=%x sum=%x\n", $time, cyc, crc, sum); - if (crc !== 64'hc77bb9b3784ea091) $stop; - // What checksum will we end up with (above print should match) + $write("[%0t] cyc==%0d crc=%x sum=%x\n", $time, cyc, crc, sum); + if (crc !== 64'hc77bb9b3784ea091) $stop; + // What checksum will we end up with (above print should match) `define EXPECTED_SUM 64'h9d550d82d38926fa - if (sum !== `EXPECTED_SUM) $stop; - $write("*-* All Finished *-*\n"); - $finish; + if (sum !== `EXPECTED_SUM) $stop; + $write("*-* All Finished *-*\n"); + $finish; end end @@ -71,11 +71,11 @@ endmodule module Nested ( - input logic clk, - input logic x, + input logic clk, + input logic x, output logic y ); - logic t; + logic t; always_comb t = x ^ 1'b1; always_ff @(posedge clk) begin @@ -86,14 +86,14 @@ endmodule module Test ( - input logic clk, + input logic clk, input logic [7:0] datai, - input logic enable, + input logic enable, output logic [7:0] datao ); // verilator lint_off BLKANDNBLK - logic [7:0] datat; + logic [7:0] datat; // verilator lint_on BLKANDNBLK for (genvar i = 0; i < 8; i++) begin @@ -101,41 +101,41 @@ module Test `ifndef FAIL logic t; always_comb begin - t = datai[i] ^ 1'b1; - end + t = datai[i] ^ 1'b1; + end always_ff @(posedge clk) begin - if (clk) + if (clk) datat[i] <= t; - end + end `else Nested nested_i - ( - .clk(clk), - .x(datai[i]), - .y(datat[i]) //<== via Vcellout wire - ); + ( + .clk(clk), + .x(datai[i]), + .y(datat[i]) //<== via Vcellout wire + ); `endif always_comb begin - casez (enable) - 1'b1: datao[i] = datat[i]; - 1'b0: datao[i] = '0; - default: datao[i] = 'x; - endcase - end + casez (enable) + 1'b1: datao[i] = datat[i]; + 1'b0: datao[i] = '0; + default: datao[i] = 'x; + endcase + end end else begin always_ff @(posedge clk) begin - if (clk) + if (clk) datat[i] <= 0; //<== assign delayed end always_comb begin - casez (enable) - 1'b1: datao[i] = datat[i] ^ 1'b1; - 1'b0: datao[i] = '1; - default: datao[i] = 'x; - endcase - end + casez (enable) + 1'b1: datao[i] = datat[i] ^ 1'b1; + 1'b0: datao[i] = '1; + default: datao[i] = 'x; + endcase + end end end endmodule diff --git a/test_regress/t/t_param_long.v b/test_regress/t/t_param_long.v index 34c3cf6fc..fc1fecc10 100644 --- a/test_regress/t/t_param_long.v +++ b/test_regress/t/t_param_long.v @@ -85,8 +85,8 @@ module t (/*AUTOARG*/ always @ (posedge clk) begin cyc <= cyc + 1; if (cyc==1) begin - $write("*-* All Finished *-*\n"); - $finish; + $write("*-* All Finished *-*\n"); + $finish; end end diff --git a/test_regress/t/t_param_module.v b/test_regress/t/t_param_module.v index 69c7f1b77..89d8e77bc 100644 --- a/test_regress/t/t_param_module.v +++ b/test_regress/t/t_param_module.v @@ -23,11 +23,11 @@ module t (/*AUTOARG*/ input clk; localparam logic[4:0] WID = 16; - //localparam WID = 16; // No problem if defined like this + //localparam WID = 16; // No problem if defined like this wire [15:0] b33; test #(WID) i_test_33(.clk (clk), - .b (b33)); + .b (b33)); endmodule diff --git a/test_regress/t/t_param_named.v b/test_regress/t/t_param_named.v index 54de8242c..633b6a220 100644 --- a/test_regress/t/t_param_named.v +++ b/test_regress/t/t_param_named.v @@ -17,15 +17,15 @@ module t (/*AUTOARG*/ `endif m3 #(.P3(PAR), - .P2(2)) + .P2(2)) m3(.clk(clk)); integer cyc=1; always @ (posedge clk) begin cyc <= cyc + 1; if (cyc==1) begin - $write("*-* All Finished *-*\n"); - $finish; + $write("*-* All Finished *-*\n"); + $finish; end end diff --git a/test_regress/t/t_param_no_parentheses.v b/test_regress/t/t_param_no_parentheses.v index a5f427104..2b644d4f6 100644 --- a/test_regress/t/t_param_no_parentheses.v +++ b/test_regress/t/t_param_no_parentheses.v @@ -24,16 +24,16 @@ module t (/*AUTOARG*/ always @ (posedge clk) begin cyc <= cyc + 1; if (cyc==0) begin - bitsel = 0; - if (PAR[bitsel]!==1'b1) $stop; - bitsel = 1; - if (PAR[bitsel]!==1'b1) $stop; - bitsel = 2; - if (PAR[bitsel]!==1'b0) $stop; + bitsel = 0; + if (PAR[bitsel]!==1'b1) $stop; + bitsel = 1; + if (PAR[bitsel]!==1'b1) $stop; + bitsel = 2; + if (PAR[bitsel]!==1'b0) $stop; end if (cyc==1) begin - $write("*-* All Finished *-*\n"); - $finish; + $write("*-* All Finished *-*\n"); + $finish; end end diff --git a/test_regress/t/t_param_public.v b/test_regress/t/t_param_public.v index 6c7bcdf14..3d44c62e8 100644 --- a/test_regress/t/t_param_public.v +++ b/test_regress/t/t_param_public.v @@ -32,8 +32,8 @@ module a; endmodule module b #( - parameter TWO /*verilator public*/ = 22 - ); + parameter TWO /*verilator public*/ = 22 + ); initial if (TWO != 2) $stop; `ifdef VERILATOR initial if ($c32("this->TWO") != 2) $stop; diff --git a/test_regress/t/t_param_repl.v b/test_regress/t/t_param_repl.v index 39f22a119..0cc2c107a 100644 --- a/test_regress/t/t_param_repl.v +++ b/test_regress/t/t_param_repl.v @@ -10,41 +10,41 @@ module t (/*AUTOARG*/ ); input clk; - parameter [31:0] TWENTY4 = 24; - parameter [31:0] PA = TWENTY4/8; - parameter [1:0] VALUE = 2'b10; - parameter [5:0] REPL = {PA{VALUE}}; - parameter [7:0] CONC = {REPL,VALUE}; + parameter [31:0] TWENTY4 = 24; + parameter [31:0] PA = TWENTY4/8; + parameter [1:0] VALUE = 2'b10; + parameter [5:0] REPL = {PA{VALUE}}; + parameter [7:0] CONC = {REPL,VALUE}; - parameter DBITS = 32; - parameter INIT_BYTE = 8'h1F; - parameter DWORDS_LOG2 = 7; - parameter DWORDS = (1<Jo_![Cl) #nj1]p,3^1~,="E@QZB\T)eU\pC#C|7=\$J$##A[@-@{Qk] -`line 160 "t/t_preproc.v" 0 +`line 162 "t/t_preproc.v" 0 `endprotected endmodule -`line 164 "t/t_preproc.v" 0 +`line 166 "t/t_preproc.v" 0 module t_lint_pragma_protected; -`line 168 "t/t_preproc.v" 0 +`line 170 "t/t_preproc.v" 0 `pragma protect begin_protected `pragma protect version=1 `pragma protect encrypt_agent="XXXXX" @@ -290,7 +293,7 @@ module t_lint_pragma_protected; ICAgICAgICAgICAgICAgICAgIEdOVSBMRVNTRVIgR0VORVJBTCBQVUJMSUMgTElDRU5TRQogICAg KSAyMDA3IE== -`line 181 "t/t_preproc.v" 0 +`line 183 "t/t_preproc.v" 0 `pragma protect key_keyowner="BIG3#2" `pragma protect key_keyname="BBBBBB" `pragma protect key_method="RSA" @@ -300,7 +303,7 @@ IEV2ZXJ5b25lIGlzIHBlcm1pdHRlZCB0byBjb3B5IGFuZCBkaXN0cmlidXRlIHZlcmJhdGltIGNv cGllcwogb2YgdGhpcyBsaWNlbnNlIGRvY3VtZW50LCBidXQgY2hhbmdpbmcgaXQgaXMgbm90IGFs bG93ZWQuCgoKICBUaGl= -`line 190 "t/t_preproc.v" 0 +`line 192 "t/t_preproc.v" 0 `pragma protect key_keyowner="BIG3#3" `pragma protect key_keyname="CCCCCCCC" `pragma protect key_method="RSA" @@ -310,7 +313,7 @@ TGljZW5zZSBpbmNvcnBvcmF0ZXMKdGhlIHRlcm1zIGFuZCBjb25kaXRpb25zIG9mIHZlcnNpb24g MyBvZiB0aGUgR05VIEdlbmVyYWwgUHVibGljCkxpY2Vuc2UsIHN1cHBsZW1lbnRlZCBieSB0aGUg YWRkaXRpb25hbCBwZXJ= -`line 199 "t/t_preproc.v" 0 +`line 201 "t/t_preproc.v" 0 `pragma protect encoding = (enctype = "BASE64", line_length = 76, bytes = 295) `pragma protect data_block aW5pdGlvbnMuCgogIEFzIHVzZWQgaGVyZWluLCAidGhpcyBMaWNlbnNlIiByZWZlcnMgdG8gdmVy @@ -321,18 +324,18 @@ ZCBieSB0aGlzIExpY2Vuc2UsCm90aGVyIHRoYW4gYW4gQXBwbGljYXRpb24gb3IgYSBDb21iaW5l ZCBXb3JrIGFzIG== -`line 209 "t/t_preproc.v" 0 +`line 211 "t/t_preproc.v" 0 `pragma protect end_protected -`line 211 "t/t_preproc.v" 0 +`line 213 "t/t_preproc.v" 0 `pragma protect `pragma protect end -`line 215 "t/t_preproc.v" 0 +`line 217 "t/t_preproc.v" 0 endmodule -`line 217 "t/t_preproc.v" 0 +`line 219 "t/t_preproc.v" 0 @@ -343,17 +346,17 @@ endmodule -`line 227 "t/t_preproc.v" 0 +`line 229 "t/t_preproc.v" 0 begin addr <= (({regs[6], regs[7]} + 1)); rd <= 1; end and begin addr <= (({regs[6], regs[7]})); wdata <= (rdata); wr <= 1; end begin addr <= ({regs[6], regs[7]} + 1); rd <= 1; end begin addr <= ({regs[6], regs[7]}); wdata <= (rdata); wr <= 1; end more -`line 231 "t/t_preproc.v" 0 +`line 233 "t/t_preproc.v" 0 -`line 234 "t/t_preproc.v" 0 +`line 236 "t/t_preproc.v" 0 `line 1 "t/t_preproc_inc4.vh" 1 `line 2 "t/t_preproc_inc4.vh" 0 @@ -365,57 +368,57 @@ begin addr <= ({regs[6], regs[7]}); wdata <= (rdata); wr <= 1; end more `line 8 "t/t_preproc_inc4.vh" 2 -`line 234 "t/t_preproc.v" 0 +`line 236 "t/t_preproc.v" 0 -`line 235 "t/t_preproc.v" 0 +`line 237 "t/t_preproc.v" 0 -`line 238 "t/t_preproc.v" 0 - - `line 240 "t/t_preproc.v" 0 + +`line 242 "t/t_preproc.v" 0 + -`line 244 "t/t_preproc.v" 0 +`line 246 "t/t_preproc.v" 0 -`line 247 "t/t_preproc.v" 0 +`line 249 "t/t_preproc.v" 0 $blah("ab,cd","e,f"); $blah(this.logfile,vec); $blah(this.logfile,vec[1,2,3]); $blah(this.logfile,{blah.name(), " is not foo"}); -`line 253 "t/t_preproc.v" 0 +`line 255 "t/t_preproc.v" 0 -`line 256 "t/t_preproc.v" 0 +`line 258 "t/t_preproc.v" 0 `pragma foo = 1 `default_nettype none `default_nettype uwire -`line 260 "t/t_preproc.v" 0 +`line 262 "t/t_preproc.v" 0 -`line 263 "t/t_preproc.v" 0 +`line 265 "t/t_preproc.v" 0 -`line 267 "t/t_preproc.v" 0 -Line_Preproc_Check 267 - `line 269 "t/t_preproc.v" 0 +Line_Preproc_Check 269 + +`line 271 "t/t_preproc.v" 0 -`line 272 "t/t_preproc.v" 0 +`line 274 "t/t_preproc.v" 0 @@ -423,15 +426,15 @@ Line_Preproc_Check 267 -`line 279 "t/t_preproc.v" 0 +`line 281 "t/t_preproc.v" 0 (x,y) -Line_Preproc_Check 280 +Line_Preproc_Check 282 -`line 282 "t/t_preproc.v" 0 +`line 284 "t/t_preproc.v" 0 -`line 285 "t/t_preproc.v" 0 +`line 287 "t/t_preproc.v" 0 @@ -440,17 +443,17 @@ beginend beginend "beginend" -`line 293 "t/t_preproc.v" 0 +`line 295 "t/t_preproc.v" 0 `\esc`def -`line 299 "t/t_preproc.v" 0 +`line 301 "t/t_preproc.v" 0 Not a \`define -`line 301 "t/t_preproc.v" 0 +`line 303 "t/t_preproc.v" 0 @@ -459,23 +462,23 @@ Not a \`define x,y)--bee submacro has comma paren -`line 309 "t/t_preproc.v" 0 +`line 311 "t/t_preproc.v" 0 $display("10 %d %d", $bits(foo), 10); -`line 314 "t/t_preproc.v" 0 +`line 316 "t/t_preproc.v" 0 -`line 319 "t/t_preproc.v" 0 +`line 321 "t/t_preproc.v" 0 -`line 322 "t/t_preproc.v" 0 +`line 324 "t/t_preproc.v" 0 @@ -490,30 +493,30 @@ $display("10 %d %d", $bits(foo), 10); -`line 336 "t/t_preproc.v" 0 - -`line 336 "t/t_preproc.v" 0 - -`line 336 "t/t_preproc.v" 0 - -`line 336 "t/t_preproc.v" 0 - -`line 336 "t/t_preproc.v" 0 - -`line 336 "t/t_preproc.v" 0 - -`line 336 "t/t_preproc.v" 0 - -`line 336 "t/t_preproc.v" 0 - -`line 336 "t/t_preproc.v" 0 - -`line 336 "t/t_preproc.v" 0 - assign a3 = ~b3 ; -`line 336 "t/t_preproc.v" 0 - - `line 338 "t/t_preproc.v" 0 + +`line 338 "t/t_preproc.v" 0 + +`line 338 "t/t_preproc.v" 0 + +`line 338 "t/t_preproc.v" 0 + +`line 338 "t/t_preproc.v" 0 + +`line 338 "t/t_preproc.v" 0 + +`line 338 "t/t_preproc.v" 0 + +`line 338 "t/t_preproc.v" 0 + +`line 338 "t/t_preproc.v" 0 + +`line 338 "t/t_preproc.v" 0 + assign a3 = ~b3 ; +`line 338 "t/t_preproc.v" 0 + + +`line 340 "t/t_preproc.v" 0 \ @@ -524,58 +527,57 @@ $display("10 %d %d", $bits(foo), 10); -`line 347 "t/t_preproc.v" 0 +`line 349 "t/t_preproc.v" 0 -`line 347 "t/t_preproc.v" 0 +`line 349 "t/t_preproc.v" 0 -`line 347 "t/t_preproc.v" 0 +`line 349 "t/t_preproc.v" 0 def i -`line 349 "t/t_preproc.v" 0 - - `line 351 "t/t_preproc.v" 0 + +`line 353 "t/t_preproc.v" 0 + -`line 355 "t/t_preproc.v" 0 +`line 357 "t/t_preproc.v" 0 -`line 361 "t/t_preproc.v" 0 +`line 363 "t/t_preproc.v" 0 1 /*verilator NOT IN DEFINE*/ (nodef) 2 /*verilator PART OF DEFINE*/ (hasdef) 3 -`line 363 "t/t_preproc.v" 0 +`line 365 "t/t_preproc.v" 0 /*verilator NOT PART OF DEFINE*/ (nodef) -`line 364 "t/t_preproc.v" 0 +`line 366 "t/t_preproc.v" 0 4 -`line 364 "t/t_preproc.v" 0 +`line 366 "t/t_preproc.v" 0 /*verilator PART OF DEFINE*/ (nodef) -`line 365 "t/t_preproc.v" 0 +`line 367 "t/t_preproc.v" 0 5 also in -`line 365 "t/t_preproc.v" 0 +`line 367 "t/t_preproc.v" 0 also3 (nodef) HAS a NEW -`line 368 "t/t_preproc.v" 0 -LINE - `line 370 "t/t_preproc.v" 0 - +LINE `line 372 "t/t_preproc.v" 0 +`line 374 "t/t_preproc.v" 0 + @@ -587,11 +589,12 @@ LINE -`line 385 "t/t_preproc.v" 0 + +`line 387 "t/t_preproc.v" 0 -`line 388 "t/t_preproc.v" 0 +`line 390 "t/t_preproc.v" 0 EXP: clxx_scen clxx_scen EXP: clxx_scen @@ -599,44 +602,44 @@ EXP: clxx_scen EXP: do if (start("verilog/inc1.v", 25)) begin message({"Blah-", "clx_scen", " end"}); end while(0); -`line 394 "t/t_preproc.v" 0 +`line 396 "t/t_preproc.v" 0 do -`line 394 "t/t_preproc.v" 0 +`line 396 "t/t_preproc.v" 0 -`line 394 "t/t_preproc.v" 0 +`line 396 "t/t_preproc.v" 0 -`line 394 "t/t_preproc.v" 0 +`line 396 "t/t_preproc.v" 0 -`line 394 "t/t_preproc.v" 0 - -`line 394 "t/t_preproc.v" 0 - if (start("t/t_preproc.v", 394)) begin -`line 394 "t/t_preproc.v" 0 - -`line 394 "t/t_preproc.v" 0 - message({"Blah-", "clx_scen", " end"}); -`line 394 "t/t_preproc.v" 0 - end -`line 394 "t/t_preproc.v" 0 - -`line 394 "t/t_preproc.v" 0 - while(0); - `line 396 "t/t_preproc.v" 0 +`line 396 "t/t_preproc.v" 0 + if (start("t/t_preproc.v", 396)) begin +`line 396 "t/t_preproc.v" 0 + +`line 396 "t/t_preproc.v" 0 + message({"Blah-", "clx_scen", " end"}); +`line 396 "t/t_preproc.v" 0 + end +`line 396 "t/t_preproc.v" 0 + +`line 396 "t/t_preproc.v" 0 + while(0); `line 398 "t/t_preproc.v" 0 +`line 400 "t/t_preproc.v" 0 + -`line 402 "t/t_preproc.v" 0 + +`line 404 "t/t_preproc.v" 0 -`line 402 "t/t_preproc.v" 0 +`line 404 "t/t_preproc.v" 0 -`line 403 "t/t_preproc.v" 0 +`line 405 "t/t_preproc.v" 0 EXP: This is fooed @@ -644,7 +647,7 @@ This is fooed EXP: This is fooed_2 This is fooed_2 -`line 410 "t/t_preproc.v" 0 +`line 412 "t/t_preproc.v" 0 np @@ -656,11 +659,11 @@ np -`line 421 "t/t_preproc.v" 0 +`line 423 "t/t_preproc.v" 0 -`line 424 "t/t_preproc.v" 0 +`line 426 "t/t_preproc.v" 0 @@ -669,12 +672,12 @@ np -`line 432 "t/t_preproc.v" 0 +`line 434 "t/t_preproc.v" 0 -`line 436 "t/t_preproc.v" 0 +`line 438 "t/t_preproc.v" 0 hello3hello3hello3 hello4hello4hello4hello4 @@ -682,7 +685,7 @@ hello4hello4hello4hello4 -`line 442 "t/t_preproc.v" 0 +`line 444 "t/t_preproc.v" 0 `line 1 "t/t_preproc_inc4.vh" 1 `line 2 "t/t_preproc_inc4.vh" 0 @@ -694,9 +697,9 @@ hello4hello4hello4hello4 `line 8 "t/t_preproc_inc4.vh" 2 -`line 442 "t/t_preproc.v" 0 +`line 444 "t/t_preproc.v" 0 -`line 443 "t/t_preproc.v" 0 +`line 445 "t/t_preproc.v" 0 @@ -706,28 +709,28 @@ hello4hello4hello4hello4 -`line 451 "t/t_preproc.v" 0 +`line 453 "t/t_preproc.v" 0 -Line_Preproc_Check 455 +Line_Preproc_Check 457 -Line_Preproc_Check 461 +Line_Preproc_Check 463 "FOO \ BAR " "arg_line1 \ arg_line2" "FOO \ BAR " -`line 464 "t/t_preproc.v" 0 -Line_Preproc_Check 464 +`line 466 "t/t_preproc.v" 0 +Line_Preproc_Check 466 -`line 468 "t/t_preproc.v" 0 +`line 470 "t/t_preproc.v" 0 @@ -738,14 +741,14 @@ abc -`line 478 "t/t_preproc.v" 0 +`line 480 "t/t_preproc.v" 0 EXP: sonet_frame sonet_frame -`line 484 "t/t_preproc.v" 0 +`line 486 "t/t_preproc.v" 0 EXP: sonet_frame @@ -756,7 +759,7 @@ sonet_frame EXP: sonet_frame sonet_frame -`line 494 "t/t_preproc.v" 0 +`line 496 "t/t_preproc.v" 0 @@ -764,13 +767,13 @@ EXP: module zzz ; endmodule module zzz ; endmodule module zzz ; endmodule -`line 501 "t/t_preproc.v" 0 +`line 503 "t/t_preproc.v" 0 EXP: module a_b ; endmodule module a_b ; endmodule module a_b ; endmodule -`line 506 "t/t_preproc.v" 0 +`line 508 "t/t_preproc.v" 0 integer foo; @@ -784,7 +787,7 @@ module t; initial begin : \`LEX_CAT(a[0],_assignment) -`line 518 "t/t_preproc.v" 0 +`line 520 "t/t_preproc.v" 0 $write("GOT%%m='%m' EXP='%s'\n", "t.\\`LEX_CAT(a[0],_assignment) "); end @@ -793,7 +796,7 @@ module t; initial begin : \a[0]_assignment_a[1] -`line 525 "t/t_preproc.v" 0 +`line 527 "t/t_preproc.v" 0 $write("GOT%%m='%m' EXP='%s'\n", "t.\\a[0]_assignment_a[1] "); end @@ -809,7 +812,7 @@ module t; initial begin : \`CAT(ff,bb) -`line 539 "t/t_preproc.v" 0 +`line 541 "t/t_preproc.v" 0 $write("GOT%%m='%m' EXP='%s'\n", "t.\\`CAT(ff,bb) "); end @@ -817,7 +820,7 @@ module t; initial begin : \`zzz -`line 545 "t/t_preproc.v" 0 +`line 547 "t/t_preproc.v" 0 $write("GOT%%m='%m' EXP='%s'\n", "t.\\`zzz "); end @@ -826,11 +829,11 @@ module t; initial begin : \`FOO -`line 552 "t/t_preproc.v" 0 +`line 554 "t/t_preproc.v" 0 $write("GOT%%m='%m' OTHER_EXP='%s'\n OUR_EXP='%s'", "t.bar ","t.\\`FOO "); end initial begin : \xx`FOO -`line 554 "t/t_preproc.v" 0 +`line 556 "t/t_preproc.v" 0 $write("GOT%%m='%m' EXP='%s'\n", "t.\\xx`FOO "); end @@ -863,27 +866,27 @@ module t; initial -`line 585 "t/t_preproc.v" 0 +`line 587 "t/t_preproc.v" 0 $display("%s%s","a1","b2c3\n"); endmodule -`line 588 "t/t_preproc.v" 0 +`line 590 "t/t_preproc.v" 0 -`line 591 "t/t_preproc.v" 0 +`line 593 "t/t_preproc.v" 0 $display("RAM0"); $display("CPU"); -`line 596 "t/t_preproc.v" 0 +`line 598 "t/t_preproc.v" 0 -`line 601 "t/t_preproc.v" 0 +`line 603 "t/t_preproc.v" 0 XXE_FAMILY = XXE_ @@ -891,7 +894,7 @@ XXE_FAMILY = XXE_ $display("XXE_ is defined"); -`line 608 "t/t_preproc.v" 0 +`line 610 "t/t_preproc.v" 0 XYE_FAMILY = XYE_ @@ -899,7 +902,7 @@ XYE_FAMILY = XYE_ $display("XYE_ is defined"); -`line 615 "t/t_preproc.v" 0 +`line 617 "t/t_preproc.v" 0 XXS_FAMILY = XXS_some @@ -907,7 +910,7 @@ XXS_FAMILY = XXS_some $display("XXS_some is defined"); -`line 622 "t/t_preproc.v" 0 +`line 624 "t/t_preproc.v" 0 XYS_FAMILY = XYS_foo @@ -915,11 +918,11 @@ XYS_FAMILY = XYS_foo $display("XYS_foo is defined"); -`line 629 "t/t_preproc.v" 0 - - `line 631 "t/t_preproc.v" 0 + +`line 633 "t/t_preproc.v" 0 + @@ -927,7 +930,7 @@ XYS_FAMILY = XYS_foo -`line 639 "t/t_preproc.v" 0 +`line 641 "t/t_preproc.v" 0 @@ -935,7 +938,7 @@ XYS_FAMILY = XYS_foo -`line 646 "t/t_preproc.v" 0 +`line 648 "t/t_preproc.v" 0 @@ -943,7 +946,7 @@ XYS_FAMILY = XYS_foo -`line 653 "t/t_preproc.v" 0 +`line 655 "t/t_preproc.v" 0 @@ -951,26 +954,26 @@ XYS_FAMILY = XYS_foo -`line 660 "t/t_preproc.v" 0 - - `line 662 "t/t_preproc.v" 0 `line 664 "t/t_preproc.v" 0 + + +`line 666 "t/t_preproc.v" 0 (.mySig (myInterface.pa5), -`line 668 "t/t_preproc.v" 0 +`line 670 "t/t_preproc.v" 0 -`line 671 "t/t_preproc.v" 0 +`line 673 "t/t_preproc.v" 0 `dbg_hdl(UVM_LOW, ("Functional coverage enabled: paramgrp")); -`line 674 "t/t_preproc.v" 0 +`line 676 "t/t_preproc.v" 0 @@ -979,28 +982,28 @@ XYS_FAMILY = XYS_foo -`line 682 "t/t_preproc.v" 0 +`line 684 "t/t_preproc.v" 0 module pcc2_cfg; generate -`line 684 "t/t_preproc.v" 0 +`line 686 "t/t_preproc.v" 0 covergroup a @(posedge b); -`line 684 "t/t_preproc.v" 0 +`line 686 "t/t_preproc.v" 0 c: coverpoint d iff ((c) === 1'b1); endgroup -`line 684 "t/t_preproc.v" 0 +`line 686 "t/t_preproc.v" 0 a u_a; -`line 684 "t/t_preproc.v" 0 +`line 686 "t/t_preproc.v" 0 initial do begin $display ("DEBUG : %s [%m]", $sformatf ("Functional coverage enabled: u_a")); end while(0); endgenerate endmodule -`line 688 "t/t_preproc.v" 0 +`line 690 "t/t_preproc.v" 0 "`NOT_DEFINED_STR" -`line 693 "t/t_preproc.v" 0 +`line 695 "t/t_preproc.v" 0 @@ -1023,4 +1026,4 @@ predef 2 2 -`line 715 "t/t_preproc.v" 2 +`line 717 "t/t_preproc.v" 2 diff --git a/test_regress/t/t_preproc.v b/test_regress/t/t_preproc.v index 50f18e53d..c804ad797 100644 --- a/test_regress/t/t_preproc.v +++ b/test_regress/t/t_preproc.v @@ -3,6 +3,8 @@ // any use, without warranty, 2000-2011 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 +// This file intentionally includes some tabs + //=========================================================================== // Includes `include "t_preproc_inc2.vh" diff --git a/test_regress/t/t_preproc_comments.out b/test_regress/t/t_preproc_comments.out index 881de7e8d..7777d4332 100644 --- a/test_regress/t/t_preproc_comments.out +++ b/test_regress/t/t_preproc_comments.out @@ -5,10 +5,13 @@ // SPDX-License-Identifier: CC0-1.0 `line 6 "t/t_preproc.v" 0 +// This file intentionally includes some tabs + +`line 8 "t/t_preproc.v" 0 //=========================================================================== // Includes -`line 8 "t/t_preproc.v" 0 +`line 10 "t/t_preproc.v" 0 `line 1 "t/t_preproc_inc2.vh" 1 // DESCRIPTION: Verilog::Preproc: Example source code `line 2 "t/t_preproc_inc2.vh" 0 @@ -47,24 +50,24 @@ At file "t/t_preproc_inc2.vh" line 5 `line 9 "t/t_preproc_inc2.vh" 2 -`line 8 "t/t_preproc.v" 0 - - `line 10 "t/t_preproc.v" 0 + + +`line 12 "t/t_preproc.v" 0 //=========================================================================== // Comments -`line 13 "t/t_preproc.v" 0 +`line 15 "t/t_preproc.v" 0 /* verilator pass_thru comment */ -`line 15 "t/t_preproc.v" 0 +`line 17 "t/t_preproc.v" 0 // verilator pass_thru_comment2 -`line 17 "t/t_preproc.v" 0 +`line 19 "t/t_preproc.v" 0 //=========================================================================== // Defines -`line 20 "t/t_preproc.v" 0 +`line 22 "t/t_preproc.v" 0 // DEF_A0 set by command line @@ -75,104 +78,104 @@ At file "t/t_preproc_inc2.vh" line 5 1'b1 }; -`line 30 "t/t_preproc.v" 0 +`line 32 "t/t_preproc.v" 0 text. -`line 32 "t/t_preproc.v" 0 +`line 34 "t/t_preproc.v" 0 foo /*this */ bar /* this too */ foobar2 // but not -`line 37 "t/t_preproc.v" 0 +`line 39 "t/t_preproc.v" 0 -`line 41 "t/t_preproc.v" 0 +`line 43 "t/t_preproc.v" 0 -`line 46 "t/t_preproc.v" 0 +`line 48 "t/t_preproc.v" 0 /*******COMMENT*****/ first part -`line 47 "t/t_preproc.v" 0 +`line 49 "t/t_preproc.v" 0 second part -`line 47 "t/t_preproc.v" 0 +`line 49 "t/t_preproc.v" 0 third part { -`line 48 "t/t_preproc.v" 0 +`line 50 "t/t_preproc.v" 0 a, -`line 48 "t/t_preproc.v" 0 +`line 50 "t/t_preproc.v" 0 b, -`line 48 "t/t_preproc.v" 0 +`line 50 "t/t_preproc.v" 0 c} -Line_Preproc_Check 49 - -`line 51 "t/t_preproc.v" 0 -//=========================================================================== +Line_Preproc_Check 51 `line 53 "t/t_preproc.v" 0 - +//=========================================================================== `line 55 "t/t_preproc.v" 0 + +`line 57 "t/t_preproc.v" 0 + deep deep -`line 59 "t/t_preproc.v" 0 +`line 61 "t/t_preproc.v" 0 "Inside: `nosubst" "`nosubst" -`line 64 "t/t_preproc.v" 0 +`line 66 "t/t_preproc.v" 0 x y LLZZ x y p q LLZZ p q r s LLZZ r s LLZZ p q LLZZ p q r s LLZZ r s -`line 70 "t/t_preproc.v" 0 +`line 72 "t/t_preproc.v" 0 firstline comma","line LLZZ firstline comma","line -`line 72 "t/t_preproc.v" 0 +`line 74 "t/t_preproc.v" 0 x y LLZZ "x" y // Simulators disagree here; some substitute "a" others do not -`line 75 "t/t_preproc.v" 0 +`line 77 "t/t_preproc.v" 0 (a,b)(a,b) -`line 78 "t/t_preproc.v" 0 +`line 80 "t/t_preproc.v" 0 $display("left side: \"right side\"") -`line 81 "t/t_preproc.v" 0 +`line 83 "t/t_preproc.v" 0 bar_suffix more -`line 84 "t/t_preproc.v" 0 +`line 86 "t/t_preproc.v" 0 -`line 86 "t/t_preproc.v" 0 +`line 88 "t/t_preproc.v" 0 $c("Zap(\"",bug1,"\");");; -`line 87 "t/t_preproc.v" 0 +`line 89 "t/t_preproc.v" 0 $c("Zap(\"","bug2","\");");; -`line 89 "t/t_preproc.v" 0 +`line 91 "t/t_preproc.v" 0 /* Define inside comment: `DEEPER and `WITHTICK */ // More commentary: `zap(bug1); `zap("bug2"); -`line 92 "t/t_preproc.v" 0 +`line 94 "t/t_preproc.v" 0 //====================================================================== // display passthru -`line 95 "t/t_preproc.v" 0 +`line 97 "t/t_preproc.v" 0 @@ -194,7 +197,7 @@ bar_suffix more $display("left side: \"right side\""); $display("standalone"); -`line 116 "t/t_preproc.v" 0 +`line 118 "t/t_preproc.v" 0 // Unspecified when the stringification has multiple lines @@ -205,78 +208,78 @@ bar_suffix more end endmodule -`line 126 "t/t_preproc.v" 0 +`line 128 "t/t_preproc.v" 0 //====================================================================== // rt.cpan.org bug34429 -`line 129 "t/t_preproc.v" 0 +`line 131 "t/t_preproc.v" 0 -`line 134 "t/t_preproc.v" 0 +`line 136 "t/t_preproc.v" 0 module add1 ( input wire d1, output wire o1); -`line 135 "t/t_preproc.v" 0 +`line 137 "t/t_preproc.v" 0 wire tmp_d1 = d1; -`line 135 "t/t_preproc.v" 0 +`line 137 "t/t_preproc.v" 0 wire tmp_o1 = tmp_d1 + 1; -`line 135 "t/t_preproc.v" 0 +`line 137 "t/t_preproc.v" 0 assign o1 = tmp_o1 ; // expansion is OK endmodule module add2 ( input wire d2, output wire o2); -`line 138 "t/t_preproc.v" 0 +`line 140 "t/t_preproc.v" 0 wire tmp_d2 = d2; -`line 138 "t/t_preproc.v" 0 +`line 140 "t/t_preproc.v" 0 wire tmp_o2 = tmp_d2 + 1; -`line 138 "t/t_preproc.v" 0 +`line 140 "t/t_preproc.v" 0 assign o2 = tmp_o2 ; // expansion is bad endmodule -`line 141 "t/t_preproc.v" 0 +`line 143 "t/t_preproc.v" 0 -`line 147 "t/t_preproc.v" 0 +`line 149 "t/t_preproc.v" 0 // parameterized macro with arguments that are macros -`line 152 "t/t_preproc.v" 0 +`line 154 "t/t_preproc.v" 0 -`line 152 "t/t_preproc.v" 0 +`line 154 "t/t_preproc.v" 0 generate for (i=0; i<(3); i=i+1) begin -`line 152 "t/t_preproc.v" 0 +`line 154 "t/t_preproc.v" 0 psl cover { m5k.f .ctl._ctl_mvldx_m1.d[i] & ~m5k.f .ctl._ctl_mvldx_m1.q[i] & !m5k.f .ctl._ctl_mvldx_m1.cond & ((m5k.f .ctl.alive & m5k.f .ctl.alive_m1))} report "fondNoRise: m5kc_fcl._ctl_mvldx_m1"; -`line 152 "t/t_preproc.v" 0 +`line 154 "t/t_preproc.v" 0 psl cover { ~m5k.f .ctl._ctl_mvldx_m1.d[i] & m5k.f .ctl._ctl_mvldx_m1.q[i] & !m5k.f .ctl._ctl_mvldx_m1.cond & ((m5k.f .ctl.alive & m5k.f .ctl.alive_m1))} report "fondNoFall: m5kc_fcl._ctl_mvldx_m1"; -`line 152 "t/t_preproc.v" 0 +`line 154 "t/t_preproc.v" 0 end endgenerate // ignorecmt -`line 154 "t/t_preproc.v" 0 +`line 156 "t/t_preproc.v" 0 //====================================================================== // Quotes are legal in protected blocks. Grr. module prot(); `protected I!#r#e6<_Q{{E2+]I3<[3s)1@D|'E''i!O?]jD>Jo_![Cl) #nj1]p,3^1~,="E@QZB\T)eU\pC#C|7=\$J$##A[@-@{Qk] -`line 160 "t/t_preproc.v" 0 +`line 162 "t/t_preproc.v" 0 `endprotected endmodule //" -`line 164 "t/t_preproc.v" 0 +`line 166 "t/t_preproc.v" 0 //====================================================================== // Check IEEE1800-2017 `pragma protect encrypted modules module t_lint_pragma_protected; -`line 168 "t/t_preproc.v" 0 +`line 170 "t/t_preproc.v" 0 `pragma protect begin_protected `pragma protect version=1 `pragma protect encrypt_agent="XXXXX" @@ -290,7 +293,7 @@ module t_lint_pragma_protected; ICAgICAgICAgICAgICAgICAgIEdOVSBMRVNTRVIgR0VORVJBTCBQVUJMSUMgTElDRU5TRQogICAg KSAyMDA3IE== -`line 181 "t/t_preproc.v" 0 +`line 183 "t/t_preproc.v" 0 `pragma protect key_keyowner="BIG3#2" `pragma protect key_keyname="BBBBBB" `pragma protect key_method="RSA" @@ -300,7 +303,7 @@ IEV2ZXJ5b25lIGlzIHBlcm1pdHRlZCB0byBjb3B5IGFuZCBkaXN0cmlidXRlIHZlcmJhdGltIGNv cGllcwogb2YgdGhpcyBsaWNlbnNlIGRvY3VtZW50LCBidXQgY2hhbmdpbmcgaXQgaXMgbm90IGFs bG93ZWQuCgoKICBUaGl= -`line 190 "t/t_preproc.v" 0 +`line 192 "t/t_preproc.v" 0 `pragma protect key_keyowner="BIG3#3" `pragma protect key_keyname="CCCCCCCC" `pragma protect key_method="RSA" @@ -310,7 +313,7 @@ TGljZW5zZSBpbmNvcnBvcmF0ZXMKdGhlIHRlcm1zIGFuZCBjb25kaXRpb25zIG9mIHZlcnNpb24g MyBvZiB0aGUgR05VIEdlbmVyYWwgUHVibGljCkxpY2Vuc2UsIHN1cHBsZW1lbnRlZCBieSB0aGUg YWRkaXRpb25hbCBwZXJ= -`line 199 "t/t_preproc.v" 0 +`line 201 "t/t_preproc.v" 0 `pragma protect encoding = (enctype = "BASE64", line_length = 76, bytes = 295) `pragma protect data_block aW5pdGlvbnMuCgogIEFzIHVzZWQgaGVyZWluLCAidGhpcyBMaWNlbnNlIiByZWZlcnMgdG8gdmVy @@ -321,18 +324,18 @@ ZCBieSB0aGlzIExpY2Vuc2UsCm90aGVyIHRoYW4gYW4gQXBwbGljYXRpb24gb3IgYSBDb21iaW5l ZCBXb3JrIGFzIG== -`line 209 "t/t_preproc.v" 0 +`line 211 "t/t_preproc.v" 0 `pragma protect end_protected -`line 211 "t/t_preproc.v" 0 +`line 213 "t/t_preproc.v" 0 // encoding envelope `pragma protect `pragma protect end -`line 215 "t/t_preproc.v" 0 +`line 217 "t/t_preproc.v" 0 endmodule -`line 217 "t/t_preproc.v" 0 +`line 219 "t/t_preproc.v" 0 //====================================================================== // macro call with define that has comma @@ -343,17 +346,17 @@ endmodule -`line 227 "t/t_preproc.v" 0 +`line 229 "t/t_preproc.v" 0 begin addr <= (({regs[6], regs[7]} + 1)); rd <= 1; end and begin addr <= (({regs[6], regs[7]})); wdata <= (rdata); wr <= 1; end begin addr <= ({regs[6], regs[7]} + 1); rd <= 1; end begin addr <= ({regs[6], regs[7]}); wdata <= (rdata); wr <= 1; end more -`line 231 "t/t_preproc.v" 0 +`line 233 "t/t_preproc.v" 0 //====================================================================== // include of parameterized file -`line 234 "t/t_preproc.v" 0 +`line 236 "t/t_preproc.v" 0 `line 1 "t/t_preproc_inc4.vh" 1 // DESCRIPTION: Verilog::Preproc: Example source code `line 2 "t/t_preproc_inc4.vh" 0 @@ -365,57 +368,57 @@ begin addr <= ({regs[6], regs[7]}); wdata <= (rdata); wr <= 1; end more `line 8 "t/t_preproc_inc4.vh" 2 -`line 234 "t/t_preproc.v" 0 +`line 236 "t/t_preproc.v" 0 -`line 235 "t/t_preproc.v" 0 +`line 237 "t/t_preproc.v" 0 -`line 238 "t/t_preproc.v" 0 - - `line 240 "t/t_preproc.v" 0 + +`line 242 "t/t_preproc.v" 0 + -`line 244 "t/t_preproc.v" 0 +`line 246 "t/t_preproc.v" 0 //====================================================================== // macro call with , in {} -`line 247 "t/t_preproc.v" 0 +`line 249 "t/t_preproc.v" 0 $blah("ab,cd","e,f"); $blah(this.logfile,vec); $blah(this.logfile,vec[1,2,3]); $blah(this.logfile,{blah.name(), " is not foo"}); -`line 253 "t/t_preproc.v" 0 +`line 255 "t/t_preproc.v" 0 //====================================================================== // pragma/default net type -`line 256 "t/t_preproc.v" 0 +`line 258 "t/t_preproc.v" 0 `pragma foo = 1 `default_nettype none `default_nettype uwire -`line 260 "t/t_preproc.v" 0 +`line 262 "t/t_preproc.v" 0 //====================================================================== // Ifdef -`line 263 "t/t_preproc.v" 0 +`line 265 "t/t_preproc.v" 0 -`line 267 "t/t_preproc.v" 0 -Line_Preproc_Check 267 - `line 269 "t/t_preproc.v" 0 +Line_Preproc_Check 269 + +`line 271 "t/t_preproc.v" 0 //====================================================================== // bug84 -`line 272 "t/t_preproc.v" 0 +`line 274 "t/t_preproc.v" 0 // Hello, comments MIGHT not be legal /*more,,)cmts*/ // But newlines ARE legal... who speced THAT? @@ -423,15 +426,15 @@ Line_Preproc_Check 267 -`line 279 "t/t_preproc.v" 0 +`line 281 "t/t_preproc.v" 0 (//Here x,y //Too) -Line_Preproc_Check 280 +Line_Preproc_Check 282 -`line 282 "t/t_preproc.v" 0 +`line 284 "t/t_preproc.v" 0 //====================================================================== // defines split arguments -`line 285 "t/t_preproc.v" 0 +`line 287 "t/t_preproc.v" 0 @@ -440,17 +443,17 @@ beginend // 2001 spec doesn't require two tokens, so "beginend" ok beginend // 2001 spec doesn't require two tokens, so "beginend" ok "beginend" // No space "beginend" -`line 293 "t/t_preproc.v" 0 +`line 295 "t/t_preproc.v" 0 //====================================================================== // bug106 `\esc`def -`line 299 "t/t_preproc.v" 0 +`line 301 "t/t_preproc.v" 0 Not a \`define -`line 301 "t/t_preproc.v" 0 +`line 303 "t/t_preproc.v" 0 //====================================================================== // misparsed comma in submacro @@ -459,23 +462,23 @@ Not a \`define x,y)--bee submacro has comma paren -`line 309 "t/t_preproc.v" 0 +`line 311 "t/t_preproc.v" 0 //====================================================================== // bug191 $display("10 %d %d", $bits(foo), 10); -`line 314 "t/t_preproc.v" 0 +`line 316 "t/t_preproc.v" 0 //====================================================================== // 1800-2009 -`line 319 "t/t_preproc.v" 0 +`line 321 "t/t_preproc.v" 0 -`line 322 "t/t_preproc.v" 0 +`line 324 "t/t_preproc.v" 0 //====================================================================== // bug202 @@ -490,34 +493,34 @@ $display("10 %d %d", $bits(foo), 10); -`line 336 "t/t_preproc.v" 0 - -`line 336 "t/t_preproc.v" 0 - -`line 336 "t/t_preproc.v" 0 - -`line 336 "t/t_preproc.v" 0 - -`line 336 "t/t_preproc.v" 0 - -`line 336 "t/t_preproc.v" 0 - -`line 336 "t/t_preproc.v" 0 - -`line 336 "t/t_preproc.v" 0 - -`line 336 "t/t_preproc.v" 0 - -`line 336 "t/t_preproc.v" 0 - assign a3 = ~b3 ; -`line 336 "t/t_preproc.v" 0 - +`line 338 "t/t_preproc.v" 0 `line 338 "t/t_preproc.v" 0 + +`line 338 "t/t_preproc.v" 0 + +`line 338 "t/t_preproc.v" 0 + +`line 338 "t/t_preproc.v" 0 + +`line 338 "t/t_preproc.v" 0 + +`line 338 "t/t_preproc.v" 0 + +`line 338 "t/t_preproc.v" 0 + +`line 338 "t/t_preproc.v" 0 + +`line 338 "t/t_preproc.v" 0 + assign a3 = ~b3 ; +`line 338 "t/t_preproc.v" 0 + + +`line 340 "t/t_preproc.v" 0 /* multi \ line1*/ \ -`line 340 "t/t_preproc.v" 0 +`line 342 "t/t_preproc.v" 0 /*multi \ line2*/ @@ -526,59 +529,59 @@ $display("10 %d %d", $bits(foo), 10); -`line 347 "t/t_preproc.v" 0 +`line 349 "t/t_preproc.v" 0 -`line 347 "t/t_preproc.v" 0 +`line 349 "t/t_preproc.v" 0 -`line 347 "t/t_preproc.v" 0 +`line 349 "t/t_preproc.v" 0 /* multi line 3*/ -`line 347 "t/t_preproc.v" 0 +`line 349 "t/t_preproc.v" 0 def i -`line 349 "t/t_preproc.v" 0 +`line 351 "t/t_preproc.v" 0 //====================================================================== -`line 351 "t/t_preproc.v" 0 +`line 353 "t/t_preproc.v" 0 -`line 355 "t/t_preproc.v" 0 +`line 357 "t/t_preproc.v" 0 -`line 361 "t/t_preproc.v" 0 +`line 363 "t/t_preproc.v" 0 1 // verilator NOT IN DEFINE (nodef) 2 /* verilator PART OF DEFINE */ (hasdef) 3 -`line 363 "t/t_preproc.v" 0 +`line 365 "t/t_preproc.v" 0 /* verilator NOT PART OF DEFINE */ (nodef) -`line 364 "t/t_preproc.v" 0 +`line 366 "t/t_preproc.v" 0 4 -`line 364 "t/t_preproc.v" 0 +`line 366 "t/t_preproc.v" 0 /* verilator PART OF DEFINE */ (nodef) -`line 365 "t/t_preproc.v" 0 +`line 367 "t/t_preproc.v" 0 5 also in -`line 365 "t/t_preproc.v" 0 +`line 367 "t/t_preproc.v" 0 also3 // CMT NOT (nodef) HAS a NEW -`line 368 "t/t_preproc.v" 0 +`line 370 "t/t_preproc.v" 0 LINE -`line 370 "t/t_preproc.v" 0 +`line 372 "t/t_preproc.v" 0 //====================================================================== -`line 372 "t/t_preproc.v" 0 +`line 374 "t/t_preproc.v" 0 @@ -592,11 +595,11 @@ LINE -`line 385 "t/t_preproc.v" 0 +`line 387 "t/t_preproc.v" 0 -`line 388 "t/t_preproc.v" 0 +`line 390 "t/t_preproc.v" 0 EXP: clxx_scen clxx_scen EXP: clxx_scen @@ -604,44 +607,44 @@ EXP: clxx_scen EXP: do if (start("verilog/inc1.v", 25)) begin message({"Blah-", "clx_scen", " end"}); end while(0); -`line 394 "t/t_preproc.v" 0 +`line 396 "t/t_preproc.v" 0 do -`line 394 "t/t_preproc.v" 0 +`line 396 "t/t_preproc.v" 0 /* synopsys translate_off */ -`line 394 "t/t_preproc.v" 0 +`line 396 "t/t_preproc.v" 0 -`line 394 "t/t_preproc.v" 0 +`line 396 "t/t_preproc.v" 0 -`line 394 "t/t_preproc.v" 0 +`line 396 "t/t_preproc.v" 0 -`line 394 "t/t_preproc.v" 0 - if (start("t/t_preproc.v", 394)) begin -`line 394 "t/t_preproc.v" 0 +`line 396 "t/t_preproc.v" 0 + if (start("t/t_preproc.v", 396)) begin +`line 396 "t/t_preproc.v" 0 -`line 394 "t/t_preproc.v" 0 +`line 396 "t/t_preproc.v" 0 message({"Blah-", "clx_scen", " end"}); -`line 394 "t/t_preproc.v" 0 +`line 396 "t/t_preproc.v" 0 end -`line 394 "t/t_preproc.v" 0 +`line 396 "t/t_preproc.v" 0 /* synopsys translate_on */ -`line 394 "t/t_preproc.v" 0 +`line 396 "t/t_preproc.v" 0 while(0); -`line 396 "t/t_preproc.v" 0 +`line 398 "t/t_preproc.v" 0 //====================================================================== -`line 398 "t/t_preproc.v" 0 +`line 400 "t/t_preproc.v" 0 -`line 402 "t/t_preproc.v" 0 +`line 404 "t/t_preproc.v" 0 -`line 402 "t/t_preproc.v" 0 +`line 404 "t/t_preproc.v" 0 -`line 403 "t/t_preproc.v" 0 +`line 405 "t/t_preproc.v" 0 //`ifndef def_fooed_2 `error "No def_fooed_2" `endif EXP: This is fooed @@ -649,7 +652,7 @@ This is fooed EXP: This is fooed_2 This is fooed_2 -`line 410 "t/t_preproc.v" 0 +`line 412 "t/t_preproc.v" 0 //====================================================================== np @@ -661,11 +664,11 @@ np -`line 421 "t/t_preproc.v" 0 +`line 423 "t/t_preproc.v" 0 -`line 424 "t/t_preproc.v" 0 +`line 426 "t/t_preproc.v" 0 //====================================================================== // Metaprogramming @@ -674,12 +677,12 @@ np -`line 432 "t/t_preproc.v" 0 +`line 434 "t/t_preproc.v" 0 -`line 436 "t/t_preproc.v" 0 +`line 438 "t/t_preproc.v" 0 hello3hello3hello3 hello4hello4hello4hello4 //====================================================================== @@ -687,7 +690,7 @@ hello4hello4hello4hello4 -`line 442 "t/t_preproc.v" 0 +`line 444 "t/t_preproc.v" 0 `line 1 "t/t_preproc_inc4.vh" 1 // DESCRIPTION: Verilog::Preproc: Example source code `line 2 "t/t_preproc_inc4.vh" 0 @@ -699,9 +702,9 @@ hello4hello4hello4hello4 `line 8 "t/t_preproc_inc4.vh" 2 -`line 442 "t/t_preproc.v" 0 +`line 444 "t/t_preproc.v" 0 -`line 443 "t/t_preproc.v" 0 +`line 445 "t/t_preproc.v" 0 //====================================================================== // Defines doing defines @@ -711,28 +714,28 @@ hello4hello4hello4hello4 -`line 451 "t/t_preproc.v" 0 +`line 453 "t/t_preproc.v" 0 -Line_Preproc_Check 455 +Line_Preproc_Check 457 //====================================================================== // Quoted multiline - track line numbers, and ensure \\n gets propagated -Line_Preproc_Check 461 +Line_Preproc_Check 463 "FOO \ BAR " "arg_line1 \ arg_line2" "FOO \ BAR " -`line 464 "t/t_preproc.v" 0 -Line_Preproc_Check 464 +`line 466 "t/t_preproc.v" 0 +Line_Preproc_Check 466 //====================================================================== // bug283 -`line 468 "t/t_preproc.v" 0 +`line 470 "t/t_preproc.v" 0 @@ -743,14 +746,14 @@ abc -`line 478 "t/t_preproc.v" 0 +`line 480 "t/t_preproc.v" 0 EXP: sonet_frame sonet_frame -`line 484 "t/t_preproc.v" 0 +`line 486 "t/t_preproc.v" 0 EXP: sonet_frame @@ -761,7 +764,7 @@ sonet_frame EXP: sonet_frame sonet_frame -`line 494 "t/t_preproc.v" 0 +`line 496 "t/t_preproc.v" 0 // The existance of non-existance of a base define can make a difference @@ -769,13 +772,13 @@ EXP: module zzz ; endmodule module zzz ; endmodule module zzz ; endmodule -`line 501 "t/t_preproc.v" 0 +`line 503 "t/t_preproc.v" 0 EXP: module a_b ; endmodule module a_b ; endmodule module a_b ; endmodule -`line 506 "t/t_preproc.v" 0 +`line 508 "t/t_preproc.v" 0 //====================================================================== // bug311 integer/*NEED_SPACE*/ foo; @@ -789,7 +792,7 @@ module t; initial begin : \`LEX_CAT(a[0],_assignment) -`line 518 "t/t_preproc.v" 0 +`line 520 "t/t_preproc.v" 0 $write("GOT%%m='%m' EXP='%s'\n", "t.\\`LEX_CAT(a[0],_assignment) "); end //----- // SHOULD(simulator-dependant): Backslash doesn't prevent arguments from @@ -798,7 +801,7 @@ module t; initial begin : \a[0]_assignment_a[1] -`line 525 "t/t_preproc.v" 0 +`line 527 "t/t_preproc.v" 0 $write("GOT%%m='%m' EXP='%s'\n", "t.\\a[0]_assignment_a[1] "); end //----- @@ -814,7 +817,7 @@ module t; // Similar to above; \ does not allow expansion after substitution initial begin : \`CAT(ff,bb) -`line 539 "t/t_preproc.v" 0 +`line 541 "t/t_preproc.v" 0 $write("GOT%%m='%m' EXP='%s'\n", "t.\\`CAT(ff,bb) "); end //----- @@ -822,7 +825,7 @@ module t; // MUST: Unknown macro with backslash escape stays as escaped symbol name initial begin : \`zzz -`line 545 "t/t_preproc.v" 0 +`line 547 "t/t_preproc.v" 0 $write("GOT%%m='%m' EXP='%s'\n", "t.\\`zzz "); end //----- @@ -831,11 +834,11 @@ module t; // SHOULD(simulator-dependant): Known macro with backslash escape expands initial begin : \`FOO -`line 552 "t/t_preproc.v" 0 +`line 554 "t/t_preproc.v" 0 $write("GOT%%m='%m' OTHER_EXP='%s'\n OUR_EXP='%s'", "t.bar ","t.\\`FOO "); end // SHOULD(simulator-dependant): Prefix breaks the above initial begin : \xx`FOO -`line 554 "t/t_preproc.v" 0 +`line 556 "t/t_preproc.v" 0 $write("GOT%%m='%m' EXP='%s'\n", "t.\\xx`FOO "); end //----- @@ -868,27 +871,27 @@ module t; initial -`line 585 "t/t_preproc.v" 0 +`line 587 "t/t_preproc.v" 0 $display("%s%s","a1","b2c3\n"); endmodule -`line 588 "t/t_preproc.v" 0 +`line 590 "t/t_preproc.v" 0 //====================================================================== //bug1225 -`line 591 "t/t_preproc.v" 0 +`line 593 "t/t_preproc.v" 0 $display("RAM0"); $display("CPU"); -`line 596 "t/t_preproc.v" 0 +`line 598 "t/t_preproc.v" 0 -`line 601 "t/t_preproc.v" 0 +`line 603 "t/t_preproc.v" 0 XXE_FAMILY = XXE_ @@ -896,7 +899,7 @@ XXE_FAMILY = XXE_ $display("XXE_ is defined"); -`line 608 "t/t_preproc.v" 0 +`line 610 "t/t_preproc.v" 0 XYE_FAMILY = XYE_ @@ -904,7 +907,7 @@ XYE_FAMILY = XYE_ $display("XYE_ is defined"); -`line 615 "t/t_preproc.v" 0 +`line 617 "t/t_preproc.v" 0 XXS_FAMILY = XXS_some @@ -912,7 +915,7 @@ XXS_FAMILY = XXS_some $display("XXS_some is defined"); -`line 622 "t/t_preproc.v" 0 +`line 624 "t/t_preproc.v" 0 XYS_FAMILY = XYS_foo @@ -920,10 +923,10 @@ XYS_FAMILY = XYS_foo $display("XYS_foo is defined"); -`line 629 "t/t_preproc.v" 0 +`line 631 "t/t_preproc.v" 0 //==== -`line 631 "t/t_preproc.v" 0 +`line 633 "t/t_preproc.v" 0 @@ -932,7 +935,7 @@ XYS_FAMILY = XYS_foo -`line 639 "t/t_preproc.v" 0 +`line 641 "t/t_preproc.v" 0 @@ -940,7 +943,7 @@ XYS_FAMILY = XYS_foo -`line 646 "t/t_preproc.v" 0 +`line 648 "t/t_preproc.v" 0 @@ -948,7 +951,7 @@ XYS_FAMILY = XYS_foo -`line 653 "t/t_preproc.v" 0 +`line 655 "t/t_preproc.v" 0 @@ -956,26 +959,26 @@ XYS_FAMILY = XYS_foo -`line 660 "t/t_preproc.v" 0 - - `line 662 "t/t_preproc.v" 0 - // NEVER + `line 664 "t/t_preproc.v" 0 + // NEVER + +`line 666 "t/t_preproc.v" 0 //bug1227 (.mySig (myInterface.pa5), -`line 668 "t/t_preproc.v" 0 +`line 670 "t/t_preproc.v" 0 //====================================================================== // Stringify bug -`line 671 "t/t_preproc.v" 0 +`line 673 "t/t_preproc.v" 0 `dbg_hdl(UVM_LOW, ("Functional coverage enabled: paramgrp")); -`line 674 "t/t_preproc.v" 0 +`line 676 "t/t_preproc.v" 0 @@ -984,28 +987,28 @@ XYS_FAMILY = XYS_foo -`line 682 "t/t_preproc.v" 0 +`line 684 "t/t_preproc.v" 0 module pcc2_cfg; generate -`line 684 "t/t_preproc.v" 0 +`line 686 "t/t_preproc.v" 0 covergroup a @(posedge b); -`line 684 "t/t_preproc.v" 0 +`line 686 "t/t_preproc.v" 0 c: coverpoint d iff ((c) === 1'b1); endgroup -`line 684 "t/t_preproc.v" 0 +`line 686 "t/t_preproc.v" 0 a u_a; -`line 684 "t/t_preproc.v" 0 +`line 686 "t/t_preproc.v" 0 initial do begin $display ("DEBUG : %s [%m]", $sformatf ("Functional coverage enabled: u_a")); end while(0); endgenerate endmodule -`line 688 "t/t_preproc.v" 0 +`line 690 "t/t_preproc.v" 0 //====================================================================== // Verilog-Perl bug1668 "`NOT_DEFINED_STR" -`line 693 "t/t_preproc.v" 0 +`line 695 "t/t_preproc.v" 0 //====================================================================== // IEEE mandated predefines // undefineall should have no effect on these @@ -1028,4 +1031,4 @@ predef 2 2 // After `undefineall above, for testing --dump-defines -`line 715 "t/t_preproc.v" 2 +`line 717 "t/t_preproc.v" 2 diff --git a/test_regress/t/t_preproc_def09.v b/test_regress/t/t_preproc_def09.v index 05c68e7a6..2106080c2 100644 --- a/test_regress/t/t_preproc_def09.v +++ b/test_regress/t/t_preproc_def09.v @@ -59,16 +59,16 @@ // Also check our line counting doesn't go bad `define MACROPAREN(a=(6), - b=(eq=al), - c) 'a b c' + b=(eq=al), + c) 'a b c' `MACROPAREN( - ,, + ,, - ZOT) + ZOT) HERE-`__LINE__ - Line71 //====================================================================== diff --git a/test_regress/t/t_preproc_ifdef.v b/test_regress/t/t_preproc_ifdef.v index 19bf9c25e..4708eadef 100644 --- a/test_regress/t/t_preproc_ifdef.v +++ b/test_regress/t/t_preproc_ifdef.v @@ -15,30 +15,30 @@ module t (/*AUTOARG*/); `endif `define A -`ifdef A $display("1A"); num = num + 1; - `ifdef C $stop; - `elsif A $display("2A"); num = num + 1; - `ifdef C $stop; - `elsif B $stop; - `else $display("3A"); num = num + 1; +`ifdef A $display("1A"); num = num + 1; + `ifdef C $stop; + `elsif A $display("2A"); num = num + 1; + `ifdef C $stop; + `elsif B $stop; + `else $display("3A"); num = num + 1; `endif - `else $stop; + `else $stop; `endif - `elsif B $stop; - `ifdef A $stop; - `elsif A $stop; + `elsif B $stop; + `ifdef A $stop; + `elsif A $stop; `else `endif -`elsif C $stop; -`else $stop; +`elsif C $stop; +`else $stop; `endif if (num == 3) begin - $write("*-* All Finished *-*\n"); - $finish; + $write("*-* All Finished *-*\n"); + $finish; end else begin - $write("%%Error: Bad count: %d\n", num); - $stop; + $write("%%Error: Bad count: %d\n", num); + $stop; end end endmodule diff --git a/test_regress/t/t_repeat.v b/test_regress/t/t_repeat.v index 49fcca977..b80287bad 100644 --- a/test_regress/t/t_repeat.v +++ b/test_regress/t/t_repeat.v @@ -11,26 +11,26 @@ module t (/*AUTOARG*/); initial begin times = 0; repeat (1) begin - repeat (0) $stop; - repeat (-1) $stop; - negcnt = 'sb111; - // Not all commercial simulators agree on the below stopping or not - // verilator lint_off WIDTH - repeat (negcnt) $stop; - // verilator lint_on WIDTH - repeat (5) begin - repeat (2) begin - times = times + 1; - end - end + repeat (0) $stop; + repeat (-1) $stop; + negcnt = 'sb111; + // Not all commercial simulators agree on the below stopping or not + // verilator lint_off WIDTH + repeat (negcnt) $stop; + // verilator lint_on WIDTH + repeat (5) begin + repeat (2) begin + times = times + 1; + end + end end if (times != 10) $stop; // // verilator lint_off INFINITELOOP forever begin // verilator lint_on INFINITELOOP - $write("*-* All Finished *-*\n"); - $finish; + $write("*-* All Finished *-*\n"); + $finish; end end diff --git a/test_regress/t/t_rnd.v b/test_regress/t/t_rnd.v index 0cc259988..3f097c571 100644 --- a/test_regress/t/t_rnd.v +++ b/test_regress/t/t_rnd.v @@ -10,19 +10,19 @@ module t (/*AUTOARG*/ ); input clk; - reg _ranit; + reg _ranit; reg [2:0] a; reg [33:0] wide; - reg unused_r; + reg unused_r; initial _ranit = 0; always @ (posedge clk) begin : blockName - begin // Verify begin/begin is legal - unused_r <= 1'b1; + begin // Verify begin/begin is legal + unused_r <= 1'b1; end - begin end // Verify empty is legal + begin end // Verify empty is legal end wire one = 1'b1; @@ -30,15 +30,15 @@ module t (/*AUTOARG*/ always @ (posedge clk) begin if (!_ranit) begin - _ranit <= 1; - // - a = 3'b1xx; - wide <= 34'bx1_00000000_xxxxxxxx_00000000_xxxx0000; - if (one !== 1'b1) $stop; - if ((rand_bits & 8'b1100_0011) !== 8'b0100_0010) $stop; - // - $write("*-* All Finished *-*\n"); - $finish; + _ranit <= 1; + // + a = 3'b1xx; + wide <= 34'bx1_00000000_xxxxxxxx_00000000_xxxx0000; + if (one !== 1'b1) $stop; + if ((rand_bits & 8'b1100_0011) !== 8'b0100_0010) $stop; + // + $write("*-* All Finished *-*\n"); + $finish; end end diff --git a/test_regress/t/t_savable.v b/test_regress/t/t_savable.v index 3edc34885..8b07a7814 100644 --- a/test_regress/t/t_savable.v +++ b/test_regress/t/t_savable.v @@ -18,8 +18,8 @@ module t (/*AUTOARG*/ initial $write("Model width = %0d\n", MODEL_WIDTH); sub sub (/*AUTOINST*/ - // Inputs - .clk (clk)); + // Inputs + .clk (clk)); endmodule module sub (/*AUTOARG*/ @@ -30,20 +30,20 @@ module sub (/*AUTOARG*/ input clk; /*verilator no_inline_module*/ // So we'll get hiearachy we can test - integer cyc = 0; + integer cyc = 0; - reg [127:0] save128; - reg [47:0] save48; - reg [1:0] save2; - reg [255:0] cycdone; // Make sure each cycle executes exactly once - reg [31:0] vec[2:1][2:1]; + reg [127:0] save128; + reg [47:0] save48; + reg [1:0] save2; + reg [255:0] cycdone; // Make sure each cycle executes exactly once + reg [31:0] vec[2:1][2:1]; reg [2:1][2:1][31:0] pvec; real r; string s,s2; string sarr[2:1]; string assoc[string]; - string si; + string si; // Test loop always @ (posedge clk) begin @@ -55,14 +55,14 @@ module sub (/*AUTOARG*/ if (cycdone[cyc[7:0]]) $stop; cycdone[cyc[7:0]] <= '1; if (cyc==0) begin - // Setup - save128 <= 128'hc77bb9b3784ea0914afe43fb79d7b71e; - save48 <= 48'h4afe43fb79d7; - save2 <= 2'b10; - vec[1][1] <= 32'h0101; - vec[1][2] <= 32'h0102; - vec[2][1] <= 32'h0201; - vec[2][2] <= 32'h0202; + // Setup + save128 <= 128'hc77bb9b3784ea0914afe43fb79d7b71e; + save48 <= 48'h4afe43fb79d7; + save2 <= 2'b10; + vec[1][1] <= 32'h0101; + vec[1][2] <= 32'h0102; + vec[2][1] <= 32'h0201; + vec[2][2] <= 32'h0202; pvec[1][1] <= 32'h10101; pvec[1][2] <= 32'h10102; pvec[2][1] <= 32'h10201; @@ -74,21 +74,21 @@ module sub (/*AUTOARG*/ assoc["mapped"] <= "Is mapped"; end if (cyc==1) begin - if ($test$plusargs("save_restore")!=0) begin - // Don't allow the restored model to run from time 0, it must run from a restore - $write("%%Error: didn't really restore\n"); - $stop; - end + if ($test$plusargs("save_restore")!=0) begin + // Don't allow the restored model to run from time 0, it must run from a restore + $write("%%Error: didn't really restore\n"); + $stop; + end end else if (cyc==99) begin - if (save128 !== 128'hc77bb9b3784ea0914afe43fb79d7b71e) $stop; - if (save48 !== 48'h4afe43fb79d7) $stop; - if (save2 !== 2'b10) $stop; - if (cycdone !== {{(256-99){1'b0}}, {99{1'b1}}}) $stop; - if (vec[1][1] !== 32'h0101) $stop; - if (vec[1][2] !== 32'h0102) $stop; - if (vec[2][1] !== 32'h0201) $stop; - if (vec[2][2] !== 32'h0202) $stop; + if (save128 !== 128'hc77bb9b3784ea0914afe43fb79d7b71e) $stop; + if (save48 !== 48'h4afe43fb79d7) $stop; + if (save2 !== 2'b10) $stop; + if (cycdone !== {{(256-99){1'b0}}, {99{1'b1}}}) $stop; + if (vec[1][1] !== 32'h0101) $stop; + if (vec[1][2] !== 32'h0102) $stop; + if (vec[2][1] !== 32'h0201) $stop; + if (vec[2][2] !== 32'h0202) $stop; if (pvec[1][1] !== 32'h10101) $stop; if (pvec[1][2] !== 32'h10102) $stop; if (pvec[2][1] !== 32'h10201) $stop; diff --git a/test_regress/t/t_select_bound1.v b/test_regress/t/t_select_bound1.v index 07f38acbf..adecef33b 100644 --- a/test_regress/t/t_select_bound1.v +++ b/test_regress/t/t_select_bound1.v @@ -11,26 +11,26 @@ module t (/*AUTOARG*/ ); input clk; - integer cyc = 0; - reg [63:0] crc; - reg [63:0] sum; + integer cyc = 0; + reg [63:0] crc; + reg [63:0] sum; // Take CRC data and apply to testblock inputs wire [2:0] in = crc[2:0]; /*AUTOWIRE*/ // Beginning of automatic wires (for undeclared instantiated-module outputs) - wire [3:0] mask; // From test of Test.v - wire [3:0] out; // From test of Test.v + wire [3:0] mask; // From test of Test.v + wire [3:0] out; // From test of Test.v // End of automatics Test test (/*AUTOINST*/ - // Outputs - .out (out[3:0]), - .mask (mask[3:0]), - // Inputs - .clk (clk), - .in (in[2:0])); + // Outputs + .out (out[3:0]), + .mask (mask[3:0]), + // Inputs + .clk (clk), + .in (in[2:0])); // Aggregate outputs into a single result vector wire [63:0] result = {60'h0, out & mask}; @@ -44,23 +44,23 @@ module t (/*AUTOARG*/ crc <= {crc[62:0], crc[63] ^ crc[2] ^ crc[0]}; sum <= result ^ {sum[62:0], sum[63] ^ sum[2] ^ sum[0]}; if (cyc==0) begin - // Setup - crc <= 64'h5aef0c8d_d70a4497; - sum <= '0; + // Setup + crc <= 64'h5aef0c8d_d70a4497; + sum <= '0; end else if (cyc<10) begin - sum <= '0; + sum <= '0; end else if (cyc<90) begin end else if (cyc==99) begin - $write("[%0t] cyc==%0d crc=%x sum=%x\n", $time, cyc, crc, sum); - if (crc !== 64'hc77bb9b3784ea091) $stop; - // What checksum will we end up with (above print should match) + $write("[%0t] cyc==%0d crc=%x sum=%x\n", $time, cyc, crc, sum); + if (crc !== 64'hc77bb9b3784ea091) $stop; + // What checksum will we end up with (above print should match) `define EXPECTED_SUM 64'ha9d3a7a69d2bea75 - if (sum !== `EXPECTED_SUM) $stop; - $write("*-* All Finished *-*\n"); - $finish; + if (sum !== `EXPECTED_SUM) $stop; + $write("*-* All Finished *-*\n"); + $finish; end end diff --git a/test_regress/t/t_select_bound2.v b/test_regress/t/t_select_bound2.v index c414fbfc0..f1a522381 100644 --- a/test_regress/t/t_select_bound2.v +++ b/test_regress/t/t_select_bound2.v @@ -11,26 +11,26 @@ module t (/*AUTOARG*/ ); input clk; - integer cyc = 0; - reg [63:0] crc; - reg [63:0] sum; + integer cyc = 0; + reg [63:0] crc; + reg [63:0] sum; // Take CRC data and apply to testblock inputs wire [6:0] in = crc[6:0]; /*AUTOWIRE*/ // Beginning of automatic wires (for undeclared instantiated-module outputs) - wire [3:0] mask; // From test of Test.v - wire [3:0] out; // From test of Test.v + wire [3:0] mask; // From test of Test.v + wire [3:0] out; // From test of Test.v // End of automatics Test test (/*AUTOINST*/ - // Outputs - .out (out[3:0]), - .mask (mask[3:0]), - // Inputs - .clk (clk), - .in (in[6:0])); + // Outputs + .out (out[3:0]), + .mask (mask[3:0]), + // Inputs + .clk (clk), + .in (in[6:0])); // Aggregate outputs into a single result vector wire [63:0] result = {60'h0, out & mask}; @@ -44,23 +44,23 @@ module t (/*AUTOARG*/ crc <= {crc[62:0], crc[63] ^ crc[2] ^ crc[0]}; sum <= result ^ {sum[62:0], sum[63] ^ sum[2] ^ sum[0]}; if (cyc==0) begin - // Setup - crc <= 64'h5aef0c8d_d70a4497; - sum <= '0; + // Setup + crc <= 64'h5aef0c8d_d70a4497; + sum <= '0; end else if (cyc<10) begin - sum <= '0; + sum <= '0; end else if (cyc<90) begin end else if (cyc==99) begin - $write("[%0t] cyc==%0d crc=%x sum=%x\n", $time, cyc, crc, sum); - if (crc !== 64'hc77bb9b3784ea091) $stop; - // What checksum will we end up with (above print should match) + $write("[%0t] cyc==%0d crc=%x sum=%x\n", $time, cyc, crc, sum); + if (crc !== 64'hc77bb9b3784ea091) $stop; + // What checksum will we end up with (above print should match) `define EXPECTED_SUM 64'h4e9d3a74e9d3f656 - if (sum !== `EXPECTED_SUM) $stop; - $write("*-* All Finished *-*\n"); - $finish; + if (sum !== `EXPECTED_SUM) $stop; + $write("*-* All Finished *-*\n"); + $finish; end end @@ -74,7 +74,7 @@ module Test (/*AUTOARG*/ ); input clk; - input [6:0] in; // Note much wider than any index + input [6:0] in; // Note much wider than any index output reg [3:0] out; output reg [3:0] mask; localparam [15:5] p = 11'h1ac; diff --git a/test_regress/t/t_select_index.v b/test_regress/t/t_select_index.v index 65ad39660..8e58bc6f9 100644 --- a/test_regress/t/t_select_index.v +++ b/test_regress/t/t_select_index.v @@ -23,26 +23,26 @@ module t(/*AUTOARG*/ always @ (posedge clk) begin a <= a + 3'd1; - vvector[a] <= 1'b1; // This should use "old" value for a - vvector_flip[~a] <= 1'b1; // This should use "old" value for a + vvector[a] <= 1'b1; // This should use "old" value for a + vvector_flip[~a] <= 1'b1; // This should use "old" value for a // //======== if (_ranit==8'd0) begin - _ranit <= 8'd1; - $write("[%0t] t_select_index: Running\n", $time); - vvector <= 0; - vvector_flip <= 0; - a <= 3'b1; + _ranit <= 8'd1; + $write("[%0t] t_select_index: Running\n", $time); + vvector <= 0; + vvector_flip <= 0; + a <= 3'b1; end else _ranit <= _ranit + 8'd1; // if (_ranit==8'd3) begin - $write("%x %x\n",vvector,vvector_flip); - if (vvector !== 8'b0000110) $stop; - if (vvector_flip !== 8'b0110_0000) $stop; - // - $write("*-* All Finished *-*\n"); - $finish; + $write("%x %x\n",vvector,vvector_flip); + if (vvector !== 8'b0000110) $stop; + if (vvector_flip !== 8'b0110_0000) $stop; + // + $write("*-* All Finished *-*\n"); + $finish; end end diff --git a/test_regress/t/t_select_index2.v b/test_regress/t/t_select_index2.v index 87cca6568..c62b69965 100644 --- a/test_regress/t/t_select_index2.v +++ b/test_regress/t/t_select_index2.v @@ -20,16 +20,16 @@ module t (/*AUTOARG*/ genvar g_k; for ( g_k = 0; g_k < 8; g_k = g_k + 1 ) begin: g_index - always @* begin - // Note this isn't a genif, but normal if - // verilator lint_off SELRANGE - if(g_k<4) begin + always @* begin + // Note this isn't a genif, but normal if + // verilator lint_off SELRANGE + if(g_k<4) begin x[g_k] = (sel == 1'b1) ? 1'b1 : (en[g_k] == 1'b0) ? 1'b1 : a; end - else begin + else begin x[g_k] = (sel == 1'b0) ? 1'b1 : (en[g_k-4] == 1'b0) ? 1'b1 : a; end - // verilator lint_on SELRANGE + // verilator lint_on SELRANGE end end endgenerate diff --git a/test_regress/t/t_select_lhs_oob.v b/test_regress/t/t_select_lhs_oob.v index 826d794a9..948969667 100644 --- a/test_regress/t/t_select_lhs_oob.v +++ b/test_regress/t/t_select_lhs_oob.v @@ -9,7 +9,7 @@ module t (/*AUTOARG*/ clk ); input clk; - integer cyc = 0; + integer cyc = 0; reg [6:0] mem1d; reg [6:0] mem2d [5:0]; @@ -18,10 +18,10 @@ module t (/*AUTOARG*/ integer i,j,k; // Four different test cases for out of bounds - // = - // <= + // = + // <= // Continuous assigns - // Output pin interconnect (also covers cont assigns) + // Output pin interconnect (also covers cont assigns) // Each with both bit selects and array selects initial begin @@ -31,22 +31,22 @@ module t (/*AUTOARG*/ if (mem1d[0] !== 1'b0) $stop; // for (i=0; i<8; i=i+1) begin - for (j=0; j<8; j=j+1) begin - for (k=0; k<8; k=k+1) begin - mem1d[k] = k[0]; - mem2d[j][k] = j[0]+k[0]; - mem3d[i][j][k] = i[0]+j[0]+k[0]; - end - end + for (j=0; j<8; j=j+1) begin + for (k=0; k<8; k=k+1) begin + mem1d[k] = k[0]; + mem2d[j][k] = j[0]+k[0]; + mem3d[i][j][k] = i[0]+j[0]+k[0]; + end + end end for (i=0; i<5; i=i+1) begin - for (j=0; j<6; j=j+1) begin - for (k=0; k<7; k=k+1) begin - if (mem1d[k] !== k[0]) $stop; - if (mem2d[j][k] !== j[0]+k[0]) $stop; - if (mem3d[i][j][k] !== i[0]+j[0]+k[0]) $stop; - end - end + for (j=0; j<6; j=j+1) begin + for (k=0; k<7; k=k+1) begin + if (mem1d[k] !== k[0]) $stop; + if (mem2d[j][k] !== j[0]+k[0]) $stop; + if (mem3d[i][j][k] !== i[0]+j[0]+k[0]) $stop; + end + end end end @@ -61,33 +61,33 @@ module t (/*AUTOARG*/ `endif cyc <= cyc + 1; if (cyc<10) begin - wi <= 0; + wi <= 0; end else if (cyc==10) begin - wi <= 1; + wi <= 1; end else if (cyc==11) begin - if (reg2d[0] !== 10) $stop; - wi <= 6; + if (reg2d[0] !== 10) $stop; + wi <= 6; end else if (cyc==12) begin - if (reg2d[0] !== 10) $stop; - if (reg2d[1] !== 11) $stop; - wi <= 7; // Will be ignored + if (reg2d[0] !== 10) $stop; + if (reg2d[1] !== 11) $stop; + wi <= 7; // Will be ignored end else if (cyc==13) begin - if (reg2d[0] !== 10) $stop; - if (reg2d[1] !== 11) $stop; - if (reg2d[6] !== 12) $stop; + if (reg2d[0] !== 10) $stop; + if (reg2d[1] !== 11) $stop; + if (reg2d[6] !== 12) $stop; end else if (cyc==14) begin - if (reg2d[0] !== 10) $stop; - if (reg2d[1] !== 11) $stop; - if (reg2d[6] !== 12) $stop; + if (reg2d[0] !== 10) $stop; + if (reg2d[1] !== 11) $stop; + if (reg2d[6] !== 12) $stop; end else if (cyc==99) begin - $write("*-* All Finished *-*\n"); - $finish; + $write("*-* All Finished *-*\n"); + $finish; end end endmodule diff --git a/test_regress/t/t_select_lhs_oob2.v b/test_regress/t/t_select_lhs_oob2.v index 81d634caf..597e629a4 100644 --- a/test_regress/t/t_select_lhs_oob2.v +++ b/test_regress/t/t_select_lhs_oob2.v @@ -10,32 +10,32 @@ module t (/*AUTOARG*/ ); input clk; - integer cyc = 0; - reg [63:0] crc; - reg [63:0] sum; + integer cyc = 0; + reg [63:0] crc; + reg [63:0] sum; // Take CRC data and apply to testblock inputs wire [31:0] in = crc[31:0]; /*AUTOWIRE*/ // Beginning of automatic wires (for undeclared instantiated-module outputs) - wire [63:0] out; // From test of Test.v + wire [63:0] out; // From test of Test.v // End of automatics - wire reset_l = ~(cyc<15); - wire [63:0] d = crc[63:0]; - wire [8:0] t_wa = crc[8:0]; - wire [8:0] t_addr = {crc[18:17],3'b0,crc[13:10]}; + wire reset_l = ~(cyc<15); + wire [63:0] d = crc[63:0]; + wire [8:0] t_wa = crc[8:0]; + wire [8:0] t_addr = {crc[18:17],3'b0,crc[13:10]}; Test test (/*AUTOINST*/ - // Outputs - .out (out[63:0]), - // Inputs - .clk (clk), - .reset_l (reset_l), - .t_wa (t_wa[8:0]), - .d (d[63:0]), - .t_addr (t_addr[8:0])); + // Outputs + .out (out[63:0]), + // Inputs + .clk (clk), + .reset_l (reset_l), + .t_wa (t_wa[8:0]), + .d (d[63:0]), + .t_addr (t_addr[8:0])); // Aggregate outputs into a single result vector wire [63:0] result = {out}; @@ -49,23 +49,23 @@ module t (/*AUTOARG*/ crc <= {crc[62:0], crc[63] ^ crc[2] ^ crc[0]}; sum <= result ^ {sum[62:0], sum[63] ^ sum[2] ^ sum[0]}; if (cyc==0) begin - // Setup - crc <= 64'h5aef0c8d_d70a4497; - sum <= 64'h0; + // Setup + crc <= 64'h5aef0c8d_d70a4497; + sum <= 64'h0; end else if (cyc<10) begin - sum <= 64'h0; + sum <= 64'h0; end else if (cyc<90) begin end else if (cyc==99) begin - $write("[%0t] cyc==%0d crc=%x sum=%x\n", $time, cyc, crc, sum); - if (crc !== 64'hc77bb9b3784ea091) $stop; - // What checksum will we end up with (above print should match) + $write("[%0t] cyc==%0d crc=%x sum=%x\n", $time, cyc, crc, sum); + if (crc !== 64'hc77bb9b3784ea091) $stop; + // What checksum will we end up with (above print should match) `define EXPECTED_SUM 64'h421a41d1541ea652 - if (sum !== `EXPECTED_SUM) $stop; - $write("*-* All Finished *-*\n"); - $finish; + if (sum !== `EXPECTED_SUM) $stop; + $write("*-* All Finished *-*\n"); + $finish; end end @@ -77,65 +77,65 @@ module Test (/*AUTOARG*/ // Inputs clk, reset_l, t_wa, d, t_addr ); - input clk; - input reset_l; + input clk; + input reset_l; - reg [63:0] m_w0 [47:0]; - reg [63:0] m_w1 [23:0]; - reg [63:0] m_w2 [23:0]; - reg [63:0] m_w3 [23:0]; - reg [63:0] m_w4 [23:0]; - reg [63:0] m_w5 [23:0]; + reg [63:0] m_w0 [47:0]; + reg [63:0] m_w1 [23:0]; + reg [63:0] m_w2 [23:0]; + reg [63:0] m_w3 [23:0]; + reg [63:0] m_w4 [23:0]; + reg [63:0] m_w5 [23:0]; - input [8:0] t_wa; - input [63:0] d; + input [8:0] t_wa; + input [63:0] d; always @ (posedge clk) begin if (~reset_l) begin : blk - integer i; + integer i; - for (i=0; i<48; i=i+1) begin - m_w0[i] <= 64'h0; - end + for (i=0; i<48; i=i+1) begin + m_w0[i] <= 64'h0; + end - for (i=0; i<24; i=i+1) begin - m_w1[i] <= 64'h0; - m_w2[i] <= 64'h0; - m_w3[i] <= 64'h0; - m_w4[i] <= 64'h0; - m_w5[i] <= 64'h0; - end + for (i=0; i<24; i=i+1) begin + m_w1[i] <= 64'h0; + m_w2[i] <= 64'h0; + m_w3[i] <= 64'h0; + m_w4[i] <= 64'h0; + m_w5[i] <= 64'h0; + end end else begin - casez (t_wa[8:6]) - 3'd0: m_w0[t_wa[5:0]] <= d; - 3'd1: m_w1[t_wa[4:0]] <= d; - 3'd2: m_w2[t_wa[4:0]] <= d; - 3'd3: m_w3[t_wa[4:0]] <= d; - 3'd4: m_w4[t_wa[4:0]] <= d; - default: m_w5[t_wa[4:0]] <= d; - endcase + casez (t_wa[8:6]) + 3'd0: m_w0[t_wa[5:0]] <= d; + 3'd1: m_w1[t_wa[4:0]] <= d; + 3'd2: m_w2[t_wa[4:0]] <= d; + 3'd3: m_w3[t_wa[4:0]] <= d; + 3'd4: m_w4[t_wa[4:0]] <= d; + default: m_w5[t_wa[4:0]] <= d; + endcase end end input [8:0] t_addr; - wire [63:0] t_w0 = m_w0[t_addr[5:0]]; - wire [63:0] t_w1 = m_w1[t_addr[4:0]]; - wire [63:0] t_w2 = m_w2[t_addr[4:0]]; - wire [63:0] t_w3 = m_w3[t_addr[4:0]]; - wire [63:0] t_w4 = m_w4[t_addr[4:0]]; - wire [63:0] t_w5 = m_w5[t_addr[4:0]]; + wire [63:0] t_w0 = m_w0[t_addr[5:0]]; + wire [63:0] t_w1 = m_w1[t_addr[4:0]]; + wire [63:0] t_w2 = m_w2[t_addr[4:0]]; + wire [63:0] t_w3 = m_w3[t_addr[4:0]]; + wire [63:0] t_w4 = m_w4[t_addr[4:0]]; + wire [63:0] t_w5 = m_w5[t_addr[4:0]]; - output reg [63:0] out; + output reg [63:0] out; always @* begin casez (t_addr[8:6]) - 3'd0: out = t_w0; - 3'd1: out = t_w1; - 3'd2: out = t_w2; - 3'd3: out = t_w3; - 3'd4: out = t_w4; - default: out = t_w5; + 3'd0: out = t_w0; + 3'd1: out = t_w1; + 3'd2: out = t_w2; + 3'd3: out = t_w3; + 3'd4: out = t_w4; + default: out = t_w5; endcase end diff --git a/test_regress/t/t_select_little.v b/test_regress/t/t_select_little.v index b33d7a137..e8c1c191b 100644 --- a/test_regress/t/t_select_little.v +++ b/test_regress/t/t_select_little.v @@ -10,26 +10,26 @@ module t (/*AUTOARG*/ ); input clk; - integer cyc = 0; - reg [63:0] crc; - reg [63:0] sum; + integer cyc = 0; + reg [63:0] crc; + reg [63:0] sum; // verilator lint_off LITENDIAN wire [10:41] sel2 = crc[31:0]; wire [10:100] sel3 = {crc[26:0],crc}; - wire out20 = sel2[{1'b0,crc[3:0]} + 11]; - wire [3:0] out21 = sel2[13 : 16]; - wire [3:0] out22 = sel2[{1'b0,crc[3:0]} + 20 +: 4]; - wire [3:0] out23 = sel2[{1'b0,crc[3:0]} + 20 -: 4]; + wire out20 = sel2[{1'b0,crc[3:0]} + 11]; + wire [3:0] out21 = sel2[13 : 16]; + wire [3:0] out22 = sel2[{1'b0,crc[3:0]} + 20 +: 4]; + wire [3:0] out23 = sel2[{1'b0,crc[3:0]} + 20 -: 4]; - wire out30 = sel3[{2'b0,crc[3:0]} + 11]; - wire [3:0] out31 = sel3[13 : 16]; - wire [3:0] out32 = sel3[crc[5:0] + 20 +: 4]; - wire [3:0] out33 = sel3[crc[5:0] + 20 -: 4]; + wire out30 = sel3[{2'b0,crc[3:0]} + 11]; + wire [3:0] out31 = sel3[13 : 16]; + wire [3:0] out32 = sel3[crc[5:0] + 20 +: 4]; + wire [3:0] out33 = sel3[crc[5:0] + 20 -: 4]; // Aggregate outputs into a single result vector - wire [63:0] result = {38'h0, out20, out21, out22, out23, out30, out31, out32, out33}; + wire [63:0] result = {38'h0, out20, out21, out22, out23, out30, out31, out32, out33}; reg [19:50] sel1; initial begin @@ -54,21 +54,21 @@ module t (/*AUTOARG*/ crc <= {crc[62:0], crc[63] ^ crc[2] ^ crc[0]}; sum <= result ^ {sum[62:0], sum[63] ^ sum[2] ^ sum[0]}; if (cyc==0) begin - // Setup - crc <= 64'h5aef0c8d_d70a4497; + // Setup + crc <= 64'h5aef0c8d_d70a4497; end else if (cyc<10) begin - sum <= 64'h0; + sum <= 64'h0; end else if (cyc<90) begin end else if (cyc==99) begin - $write("[%0t] cyc==%0d crc=%x sum=%x\n", $time, cyc, crc, sum); - if (crc !== 64'hc77bb9b3784ea091) $stop; + $write("[%0t] cyc==%0d crc=%x sum=%x\n", $time, cyc, crc, sum); + if (crc !== 64'hc77bb9b3784ea091) $stop; `define EXPECTED_SUM 64'h28bf65439eb12c00 - if (sum !== `EXPECTED_SUM) $stop; - $write("*-* All Finished *-*\n"); - $finish; + if (sum !== `EXPECTED_SUM) $stop; + $write("*-* All Finished *-*\n"); + $finish; end end diff --git a/test_regress/t/t_select_loop.v b/test_regress/t/t_select_loop.v index c057d4b91..ce8084e33 100644 --- a/test_regress/t/t_select_loop.v +++ b/test_regress/t/t_select_loop.v @@ -12,44 +12,44 @@ module t (/*AUTOARG*/ input clk; integer cyc; initial cyc=1; - reg [255:0] a; - reg [255:0] q; - reg [63:0] qq; + reg [255:0] a; + reg [255:0] q; + reg [63:0] qq; - integer i; + integer i; always @* begin for (i=0; i<256; i=i+1) begin - q[255-i] = a[i]; + q[255-i] = a[i]; end q[27:16] = 12'hfed; for (i=0; i<64; i=i+1) begin - qq[63-i] = a[i]; + qq[63-i] = a[i]; end qq[27:16] = 12'hfed; end always @ (posedge clk) begin if (cyc!=0) begin - cyc <= cyc + 1; + cyc <= cyc + 1; `ifdef TEST_VERBOSE - $write("%x/%x %x\n", q, qq, a); + $write("%x/%x %x\n", q, qq, a); `endif - if (cyc==1) begin - a = 256'hed388e646c843d35de489bab2413d77045e0eb7642b148537491f3da147e7f26; - end - if (cyc==2) begin - a = 256'h0e17c88f3d5fe51a982646c8e2bd68c3e236ddfddddbdad20a48e039c9f395b8; - if (q != 256'h64fe7e285bcf892eca128d426ed707a20eebc824d5d9127bacbc21362fed1cb7) $stop; - if (qq != 64'h64fe7e285fed892e) $stop; - end - if (cyc==3) begin - if (q != 256'h1da9cf939c0712504b5bdbbbbfbb6c47c316bd471362641958a7fabcffede870) $stop; - if (qq != 64'h1da9cf939fed1250) $stop; - end - if (cyc==4) begin - $write("*-* All Finished *-*\n"); - $finish; - end + if (cyc==1) begin + a = 256'hed388e646c843d35de489bab2413d77045e0eb7642b148537491f3da147e7f26; + end + if (cyc==2) begin + a = 256'h0e17c88f3d5fe51a982646c8e2bd68c3e236ddfddddbdad20a48e039c9f395b8; + if (q != 256'h64fe7e285bcf892eca128d426ed707a20eebc824d5d9127bacbc21362fed1cb7) $stop; + if (qq != 64'h64fe7e285fed892e) $stop; + end + if (cyc==3) begin + if (q != 256'h1da9cf939c0712504b5bdbbbbfbb6c47c316bd471362641958a7fabcffede870) $stop; + if (qq != 64'h1da9cf939fed1250) $stop; + end + if (cyc==4) begin + $write("*-* All Finished *-*\n"); + $finish; + end end end endmodule diff --git a/test_regress/t/t_select_negative.v b/test_regress/t/t_select_negative.v index e62df8185..6bfad9f9e 100644 --- a/test_regress/t/t_select_negative.v +++ b/test_regress/t/t_select_negative.v @@ -10,20 +10,20 @@ module t (/*AUTOARG*/ ); input clk; - integer cyc = 0; - reg [63:0] crc; - reg [63:0] sum; + integer cyc = 0; + reg [63:0] crc; + reg [63:0] sum; wire [15:-16] sel2 = crc[31:0]; wire [80:-10] sel3 = {crc[26:0],crc}; - wire [3:0] out21 = sel2[-3 : -6]; - wire [3:0] out22 = sel2[{1'b0,crc[3:0]} - 16 +: 4]; - wire [3:0] out23 = sel2[{1'b0,crc[3:0]} - 10 -: 4]; + wire [3:0] out21 = sel2[-3 : -6]; + wire [3:0] out22 = sel2[{1'b0,crc[3:0]} - 16 +: 4]; + wire [3:0] out23 = sel2[{1'b0,crc[3:0]} - 10 -: 4]; - wire [3:0] out31 = sel3[-3 : -6]; - wire [3:0] out32 = sel3[crc[5:0] - 6 +: 4]; - wire [3:0] out33 = sel3[crc[5:0] - 6 -: 4]; + wire [3:0] out31 = sel3[-3 : -6]; + wire [3:0] out32 = sel3[crc[5:0] - 6 +: 4]; + wire [3:0] out33 = sel3[crc[5:0] - 6 -: 4]; // Aggregate outputs into a single result vector wire [63:0] result = {40'h0, out21, out22, out23, out31, out32, out33}; @@ -49,21 +49,21 @@ module t (/*AUTOARG*/ crc <= {crc[62:0], crc[63] ^ crc[2] ^ crc[0]}; sum <= result ^ {sum[62:0], sum[63] ^ sum[2] ^ sum[0]}; if (cyc==0) begin - // Setup - crc <= 64'h5aef0c8d_d70a4497; + // Setup + crc <= 64'h5aef0c8d_d70a4497; end else if (cyc<10) begin - sum <= 64'h0; + sum <= 64'h0; end else if (cyc<90) begin end else if (cyc==99) begin - $write("[%0t] cyc==%0d crc=%x sum=%x\n", $time, cyc, crc, sum); - if (crc !== 64'hc77bb9b3784ea091) $stop; + $write("[%0t] cyc==%0d crc=%x sum=%x\n", $time, cyc, crc, sum); + if (crc !== 64'hc77bb9b3784ea091) $stop; `define EXPECTED_SUM 64'hba7fe1e7ac128362 - if (sum !== `EXPECTED_SUM) $stop; - $write("*-* All Finished *-*\n"); - $finish; + if (sum !== `EXPECTED_SUM) $stop; + $write("*-* All Finished *-*\n"); + $finish; end end diff --git a/test_regress/t/t_select_plus.v b/test_regress/t/t_select_plus.v index 11ed4a9bc..9604c93cd 100644 --- a/test_regress/t/t_select_plus.v +++ b/test_regress/t/t_select_plus.v @@ -11,11 +11,11 @@ module t (/*AUTOARG*/ input clk; - reg [83:4] from; - reg [83:4] to; - reg [6:0] bitn; - reg [3:0] nibblep; - reg [3:0] nibblem; + reg [83:4] from; + reg [83:4] to; + reg [6:0] bitn; + reg [3:0] nibblep; + reg [3:0] nibblem; reg [7:0] cyc; initial cyc = 0; @@ -31,46 +31,46 @@ module t (/*AUTOARG*/ //$write("[%0t] cyc==%d nibblep==%b nibblem==%b to^from==%x\n", $time, cyc, nibblep, nibblem, from^to); cyc <= cyc + 8'd1; case (cyc) - 8'd00: begin from<=80'h7bea9d779b67e48f67da; bitn<=7'd7; end - 8'd01: begin from<=80'hefddce326b11ca5dc448; bitn<=7'd8; end - 8'd02: begin from<=80'h3f99c5f34168401e210d; bitn<=7'd4; end // truncate -: - 8'd03: begin from<=80'hc90635f0a7757614ce3f; bitn<=7'd79; end - 8'd04: begin from<=80'hc761feca3820331370ec; bitn<=7'd83; end // truncate +: - 8'd05: begin from<=80'hd6e36077bf28244f84b5; bitn<=7'd6; end // half trunc - 8'd06: begin from<=80'h90118c5d3d285a1f3252; bitn<=7'd81; end // half trunc - 8'd07: begin from<=80'h38305da3d46b5859fe16; bitn<=7'd67; end - 8'd08: begin from<=80'h4b9ade23a8f5cc5b3111; bitn<=7'd127; end // truncate - 8'd09: begin - $write("*-* All Finished *-*\n"); - $finish; - end - default: ; + 8'd00: begin from<=80'h7bea9d779b67e48f67da; bitn<=7'd7; end + 8'd01: begin from<=80'hefddce326b11ca5dc448; bitn<=7'd8; end + 8'd02: begin from<=80'h3f99c5f34168401e210d; bitn<=7'd4; end // truncate -: + 8'd03: begin from<=80'hc90635f0a7757614ce3f; bitn<=7'd79; end + 8'd04: begin from<=80'hc761feca3820331370ec; bitn<=7'd83; end // truncate +: + 8'd05: begin from<=80'hd6e36077bf28244f84b5; bitn<=7'd6; end // half trunc + 8'd06: begin from<=80'h90118c5d3d285a1f3252; bitn<=7'd81; end // half trunc + 8'd07: begin from<=80'h38305da3d46b5859fe16; bitn<=7'd67; end + 8'd08: begin from<=80'h4b9ade23a8f5cc5b3111; bitn<=7'd127; end // truncate + 8'd09: begin + $write("*-* All Finished *-*\n"); + $finish; + end + default: ; endcase case (cyc) - 8'd00: ; - 8'd01: begin if ((nibblep & 4'b1111)!==4'b1011) $stop; if ((nibblem & 4'b1111)!==4'b1010) $stop; end - 8'd02: begin if ((nibblep & 4'b1111)!==4'b0100) $stop; if ((nibblem & 4'b1111)!==4'b0100) $stop; end - 8'd03: begin if ((nibblep & 4'b1111)!==4'b1101) $stop; if ((nibblem & 4'b0000)!==4'b0000) $stop; end - 8'd04: begin if ((nibblep & 4'b1111)!==4'b1001) $stop; if ((nibblem & 4'b1111)!==4'b1001) $stop; end - 8'd05: begin if ((nibblep & 4'b0000)!==4'b0000) $stop; if ((nibblem & 4'b1111)!==4'b1100) $stop; end - 8'd06: begin if ((nibblep & 4'b1111)!==4'b1101) $stop; if ((nibblem & 4'b0000)!==4'b0000) $stop; end - 8'd07: begin if ((nibblep & 4'b0000)!==4'b0000) $stop; if ((nibblem & 4'b1111)!==4'b0100) $stop; end - 8'd08: begin if ((nibblep & 4'b1111)!==4'b0000) $stop; if ((nibblem & 4'b1111)!==4'b0101) $stop; end - 8'd09: begin if ((nibblep & 4'b0000)!==4'b0000) $stop; if ((nibblem & 4'b0000)!==4'b0000) $stop; end - default: $stop; + 8'd00: ; + 8'd01: begin if ((nibblep & 4'b1111)!==4'b1011) $stop; if ((nibblem & 4'b1111)!==4'b1010) $stop; end + 8'd02: begin if ((nibblep & 4'b1111)!==4'b0100) $stop; if ((nibblem & 4'b1111)!==4'b0100) $stop; end + 8'd03: begin if ((nibblep & 4'b1111)!==4'b1101) $stop; if ((nibblem & 4'b0000)!==4'b0000) $stop; end + 8'd04: begin if ((nibblep & 4'b1111)!==4'b1001) $stop; if ((nibblem & 4'b1111)!==4'b1001) $stop; end + 8'd05: begin if ((nibblep & 4'b0000)!==4'b0000) $stop; if ((nibblem & 4'b1111)!==4'b1100) $stop; end + 8'd06: begin if ((nibblep & 4'b1111)!==4'b1101) $stop; if ((nibblem & 4'b0000)!==4'b0000) $stop; end + 8'd07: begin if ((nibblep & 4'b0000)!==4'b0000) $stop; if ((nibblem & 4'b1111)!==4'b0100) $stop; end + 8'd08: begin if ((nibblep & 4'b1111)!==4'b0000) $stop; if ((nibblem & 4'b1111)!==4'b0101) $stop; end + 8'd09: begin if ((nibblep & 4'b0000)!==4'b0000) $stop; if ((nibblem & 4'b0000)!==4'b0000) $stop; end + default: $stop; endcase case (cyc) - 8'd00: ; - 8'd01: begin if ((to^from)!==80'h0000000000000000005b) $stop; end - 8'd02: begin if ((to^from)!==80'h0000000000000000006c) $stop; end - 8'd03: begin if ((to^from)!==80'h0000000000000000000e) $stop; end - 8'd04: begin if ((to^from)!==80'h6d000000000000000000) $stop; end - 8'd05: begin if (((to^from)&~80'hf)!==80'h90000000000000000000) $stop; end // Exceed bounds, verilator may write index 0 - 8'd06: begin if (((to^from)&~80'hf)!==80'h00000000000000000020) $stop; end // Exceed bounds, verilator may write index 0 - 8'd07: begin if (((to^from)&~80'hf)!==80'h4c000000000000000000) $stop; end - 8'd08: begin if ((to^from)!==80'h0004d000000000000000) $stop; end - 8'd09: begin if (((to^from)&~80'hf)!==80'h00000000000000000000) $stop; end - default: $stop; + 8'd00: ; + 8'd01: begin if ((to^from)!==80'h0000000000000000005b) $stop; end + 8'd02: begin if ((to^from)!==80'h0000000000000000006c) $stop; end + 8'd03: begin if ((to^from)!==80'h0000000000000000000e) $stop; end + 8'd04: begin if ((to^from)!==80'h6d000000000000000000) $stop; end + 8'd05: begin if (((to^from)&~80'hf)!==80'h90000000000000000000) $stop; end // Exceed bounds, verilator may write index 0 + 8'd06: begin if (((to^from)&~80'hf)!==80'h00000000000000000020) $stop; end // Exceed bounds, verilator may write index 0 + 8'd07: begin if (((to^from)&~80'hf)!==80'h4c000000000000000000) $stop; end + 8'd08: begin if ((to^from)!==80'h0004d000000000000000) $stop; end + 8'd09: begin if (((to^from)&~80'hf)!==80'h00000000000000000000) $stop; end + default: $stop; endcase end diff --git a/test_regress/t/t_select_plus_mul_pow2.v b/test_regress/t/t_select_plus_mul_pow2.v index 6126383a5..f010ec7af 100644 --- a/test_regress/t/t_select_plus_mul_pow2.v +++ b/test_regress/t/t_select_plus_mul_pow2.v @@ -11,9 +11,9 @@ module t (/*AUTOARG*/ input clk; - reg [63:0] from = 64'h0706050403020100; - reg [7:0] to; - reg [2:0] bitn; + reg [63:0] from = 64'h0706050403020100; + reg [7:0] to; + reg [2:0] bitn; reg [7:0] cyc; initial cyc = 0; always @* begin @@ -23,31 +23,31 @@ module t (/*AUTOARG*/ always @ (posedge clk) begin cyc <= cyc + 8'd1; case (cyc) - 8'd00: begin bitn<=3'd0; end - 8'd01: begin bitn<=3'd1; end - 8'd02: begin bitn<=3'd2; end - 8'd03: begin bitn<=3'd3; end - 8'd04: begin bitn<=3'd4; end - 8'd05: begin bitn<=3'd5; end - 8'd06: begin bitn<=3'd6; end - 8'd07: begin bitn<=3'd7; end - 8'd08: begin - $write("*-* All Finished *-*\n"); - $finish; - end - default: ; + 8'd00: begin bitn<=3'd0; end + 8'd01: begin bitn<=3'd1; end + 8'd02: begin bitn<=3'd2; end + 8'd03: begin bitn<=3'd3; end + 8'd04: begin bitn<=3'd4; end + 8'd05: begin bitn<=3'd5; end + 8'd06: begin bitn<=3'd6; end + 8'd07: begin bitn<=3'd7; end + 8'd08: begin + $write("*-* All Finished *-*\n"); + $finish; + end + default: ; endcase case (cyc) - 8'd00: ; - 8'd01: begin if (to !== 8'h00) $stop; end - 8'd02: begin if (to !== 8'h01) $stop; end - 8'd03: begin if (to !== 8'h02) $stop; end - 8'd04: begin if (to !== 8'h03) $stop; end - 8'd05: begin if (to !== 8'h04) $stop; end - 8'd06: begin if (to !== 8'h05) $stop; end - 8'd07: begin if (to !== 8'h06) $stop; end - 8'd08: begin if (to !== 8'h07) $stop; end - default: $stop; + 8'd00: ; + 8'd01: begin if (to !== 8'h00) $stop; end + 8'd02: begin if (to !== 8'h01) $stop; end + 8'd03: begin if (to !== 8'h02) $stop; end + 8'd04: begin if (to !== 8'h03) $stop; end + 8'd05: begin if (to !== 8'h04) $stop; end + 8'd06: begin if (to !== 8'h05) $stop; end + 8'd07: begin if (to !== 8'h06) $stop; end + 8'd08: begin if (to !== 8'h07) $stop; end + default: $stop; endcase end diff --git a/test_regress/t/t_select_plusloop.v b/test_regress/t/t_select_plusloop.v index 7a5ee64f0..a5cbbe063 100644 --- a/test_regress/t/t_select_plusloop.v +++ b/test_regress/t/t_select_plusloop.v @@ -23,44 +23,44 @@ module t (/*AUTOARG*/ //$write("[%0t] cyc==%0d crc=%b n=%x\n", $time, cyc, crc, narrow); cyc <= cyc + 1; if (cyc==0) begin - // Setup - narrow <= 32'h0; - quad <= 64'h0; - wide <= 128'h0; - crc <= 8'hed; - index <= 7'h0; + // Setup + narrow <= 32'h0; + quad <= 64'h0; + wide <= 128'h0; + crc <= 8'hed; + index <= 7'h0; end else if (cyc<90) begin - index <= index + 7'h2; - crc <= {crc[6:0], ~^ {crc[7],crc[5],crc[4],crc[3]}}; - // verilator lint_off WIDTH - if (index < 9'd20) narrow[index +: 3] <= crc[2:0]; - if (index < 9'd60) quad [index +: 3] <= crc[2:0]; - if (index < 9'd120) wide [index +: 3] <= crc[2:0]; - // - narrow[index[3:0]] <= ~narrow[index[3:0]]; - quad [~index[3:0]]<= ~quad [~index[3:0]]; - wide [~index[3:0]] <= ~wide [~index[3:0]]; - // verilator lint_on WIDTH + index <= index + 7'h2; + crc <= {crc[6:0], ~^ {crc[7],crc[5],crc[4],crc[3]}}; + // verilator lint_off WIDTH + if (index < 9'd20) narrow[index +: 3] <= crc[2:0]; + if (index < 9'd60) quad [index +: 3] <= crc[2:0]; + if (index < 9'd120) wide [index +: 3] <= crc[2:0]; + // + narrow[index[3:0]] <= ~narrow[index[3:0]]; + quad [~index[3:0]]<= ~quad [~index[3:0]]; + wide [~index[3:0]] <= ~wide [~index[3:0]]; + // verilator lint_on WIDTH end else if (cyc==90) begin - wide[12 +: 4] <=4'h6; quad[12 +: 4] <=4'h6; narrow[12 +: 4] <=4'h6; - wide[42 +: 4] <=4'h6; quad[42 +: 4] <=4'h6; - wide[82 +: 4] <=4'h6; + wide[12 +: 4] <=4'h6; quad[12 +: 4] <=4'h6; narrow[12 +: 4] <=4'h6; + wide[42 +: 4] <=4'h6; quad[42 +: 4] <=4'h6; + wide[82 +: 4] <=4'h6; end else if (cyc==91) begin - wide[0] <=1'b1; quad[0] <=1'b1; narrow[0] <=1'b1; - wide[41] <=1'b1; quad[41] <=1'b1; - wide[81] <=1'b1; + wide[0] <=1'b1; quad[0] <=1'b1; narrow[0] <=1'b1; + wide[41] <=1'b1; quad[41] <=1'b1; + wide[81] <=1'b1; end else if (cyc==99) begin - $write("[%0t] cyc==%0d crc=%b n=%x q=%x w=%x\n", $time, cyc, crc, narrow, quad, wide); - if (crc != 8'b01111001) $stop; - if (narrow != 32'h001661c7) $stop; - if (quad != 64'h16d49b6f64266039) $stop; - if (wide != 128'h012fd26d265b266ff6d49b6f64266039) $stop; - $write("*-* All Finished *-*\n"); - $finish; + $write("[%0t] cyc==%0d crc=%b n=%x q=%x w=%x\n", $time, cyc, crc, narrow, quad, wide); + if (crc != 8'b01111001) $stop; + if (narrow != 32'h001661c7) $stop; + if (quad != 64'h16d49b6f64266039) $stop; + if (wide != 128'h012fd26d265b266ff6d49b6f64266039) $stop; + $write("*-* All Finished *-*\n"); + $finish; end end diff --git a/test_regress/t/t_select_runtime_range.v b/test_regress/t/t_select_runtime_range.v index 40a57b989..71d06a8f7 100644 --- a/test_regress/t/t_select_runtime_range.v +++ b/test_regress/t/t_select_runtime_range.v @@ -10,7 +10,7 @@ module t (clk); reg [43:0] mi; reg [5:0] index; integer indexi; - reg read; + reg read; initial begin // Static @@ -33,44 +33,44 @@ module t (clk); integer cyc; initial cyc=1; always @ (posedge clk) begin if (cyc!=0) begin - cyc <= cyc + 1; - if (cyc==1) begin - mi = 44'h123; - end - if (cyc==2) begin - index = 6'd43; - indexi = 43; - end - if (cyc==3) begin - read = mi[index]; - if (read!==1'b0) $stop; - read = mi[indexi]; - if (read!==1'b0) $stop; - end - if (cyc==4) begin - index = 6'd44; - indexi = 44; - end - if (cyc==5) begin - read = mi[index]; - $display("-Illegal read value: %x", read); - //if (read!==1'b1 && read!==1'bx) $stop; - read = mi[indexi]; - $display("-Illegal read value: %x", read); - //if (read!==1'b1 && read!==1'bx) $stop; - end - if (cyc==6) begin - indexi = -1; - end - if (cyc==7) begin - read = mi[indexi]; - $display("-Illegal read value: %x", read); - //if (read!==1'b1 && read!==1'bx) $stop; - end - if (cyc==10) begin - $write("*-* All Finished *-*\n"); - $finish; - end + cyc <= cyc + 1; + if (cyc==1) begin + mi = 44'h123; + end + if (cyc==2) begin + index = 6'd43; + indexi = 43; + end + if (cyc==3) begin + read = mi[index]; + if (read!==1'b0) $stop; + read = mi[indexi]; + if (read!==1'b0) $stop; + end + if (cyc==4) begin + index = 6'd44; + indexi = 44; + end + if (cyc==5) begin + read = mi[index]; + $display("-Illegal read value: %x", read); + //if (read!==1'b1 && read!==1'bx) $stop; + read = mi[indexi]; + $display("-Illegal read value: %x", read); + //if (read!==1'b1 && read!==1'bx) $stop; + end + if (cyc==6) begin + indexi = -1; + end + if (cyc==7) begin + read = mi[indexi]; + $display("-Illegal read value: %x", read); + //if (read!==1'b1 && read!==1'bx) $stop; + end + if (cyc==10) begin + $write("*-* All Finished *-*\n"); + $finish; + end end end endmodule diff --git a/test_regress/t/t_select_set.v b/test_regress/t/t_select_set.v index 30054a00e..ed37bc638 100644 --- a/test_regress/t/t_select_set.v +++ b/test_regress/t/t_select_set.v @@ -16,35 +16,35 @@ module t (clk); $write ("%x %x\n", cyc, addr); `endif if (cyc!=0) begin - cyc <= cyc + 1; - if (cyc==1) begin - addr <= 40'h12_3456_7890; - end - if (cyc==2) begin - if (addr !== 40'h1234567890) $stop; - addr[31:0] <= 32'habcd_efaa; - end - if (cyc==3) begin - if (addr !== 40'h12abcdefaa) $stop; - addr[39:32] <= 8'h44; - inwide <= 64'hffeeddcc_11334466; - end - if (cyc==4) begin - if (addr !== 40'h44abcdefaa) $stop; - addr[31:0] <= inwide[31:0]; - end - if (cyc==5) begin - if (addr !== 40'h4411334466) $stop; - $display ("Flip [%x]\n", inwide[3:0]); - addr[{2'b0,inwide[3:0]}] <= ! addr[{2'b0,inwide[3:0]}]; - end - if (cyc==6) begin - if (addr !== 40'h4411334426) $stop; - end - if (cyc==10) begin - $write("*-* All Finished *-*\n"); - $finish; - end + cyc <= cyc + 1; + if (cyc==1) begin + addr <= 40'h12_3456_7890; + end + if (cyc==2) begin + if (addr !== 40'h1234567890) $stop; + addr[31:0] <= 32'habcd_efaa; + end + if (cyc==3) begin + if (addr !== 40'h12abcdefaa) $stop; + addr[39:32] <= 8'h44; + inwide <= 64'hffeeddcc_11334466; + end + if (cyc==4) begin + if (addr !== 40'h44abcdefaa) $stop; + addr[31:0] <= inwide[31:0]; + end + if (cyc==5) begin + if (addr !== 40'h4411334466) $stop; + $display ("Flip [%x]\n", inwide[3:0]); + addr[{2'b0,inwide[3:0]}] <= ! addr[{2'b0,inwide[3:0]}]; + end + if (cyc==6) begin + if (addr !== 40'h4411334426) $stop; + end + if (cyc==10) begin + $write("*-* All Finished *-*\n"); + $finish; + end end end endmodule diff --git a/test_regress/t/t_slice_init.v b/test_regress/t/t_slice_init.v index b1901f7a6..a947919cc 100644 --- a/test_regress/t/t_slice_init.v +++ b/test_regress/t/t_slice_init.v @@ -13,9 +13,9 @@ module t (/*AUTOARG*/ input [7:0] d0, d1; logic [7:0] inia [1:0][3:0] = '{ '{ '0, '1, 8'hfe, 8'hed }, - '{ '1, '1, 8'h11, 8'h22 }}; + '{ '1, '1, 8'h11, 8'h22 }}; logic [7:0] inil [0:1][0:3] = '{ '{ '0, '1, 8'hfe, 8'hed }, - '{ '1, '1, 8'h11, 8'h22 }}; + '{ '1, '1, 8'h11, 8'h22 }}; logic [7:0] data [1:0][3:0]; logic [7:0] datl [0:1][0:3]; diff --git a/test_regress/t/t_stream.v b/test_regress/t/t_stream.v index 22b16f59c..b09985eeb 100644 --- a/test_regress/t/t_stream.v +++ b/test_regress/t/t_stream.v @@ -232,76 +232,76 @@ module t (/*AUTOARG*/ din_lhs <= 4'b_01_11; - if (dout_rhs_ls_i != 32'h_80_00_00_00) $stop; - if (dout_rhs_ls_q != 64'h_80_00_00_00_00_00_00_00) $stop; - if (dout_rhs_ls_w != 96'h_80_00_00_00_00_00_00_00_00_00_00_00) $stop; + if (dout_rhs_ls_i != 32'h_80_00_00_00) $stop; + if (dout_rhs_ls_q != 64'h_80_00_00_00_00_00_00_00) $stop; + if (dout_rhs_ls_w != 96'h_80_00_00_00_00_00_00_00_00_00_00_00) $stop; if (dout_rhs_rs_i != 32'h_00_00_00_01) $stop; if (dout_rhs_rs_q != 64'h_00_00_00_00_00_00_00_01) $stop; if (dout_rhs_rs_w != 96'h_00_00_00_00_00_00_00_00_00_00_00_01) $stop; - if (dout_lhs_ls_a != 2'b_01) $stop; - if (dout_lhs_ls_b != 2'b_00) $stop; + if (dout_lhs_ls_a != 2'b_01) $stop; + if (dout_lhs_ls_b != 2'b_00) $stop; - if (dout_lhs_rs_a != 2'b_00) $stop; - if (dout_lhs_rs_b != 2'b_01) $stop; + if (dout_lhs_rs_a != 2'b_00) $stop; + if (dout_lhs_rs_b != 2'b_01) $stop; - if (dout_bhs_rs_i != 32'h_00_00_00_01) $stop; - if (dout_bhs_rs_q != 64'h_00_00_00_00_00_00_00_01) $stop; - if (dout_bhs_rs_w != 96'h_00_00_00_00_00_00_00_00_00_00_00_01) $stop; + if (dout_bhs_rs_i != 32'h_00_00_00_01) $stop; + if (dout_bhs_rs_q != 64'h_00_00_00_00_00_00_00_01) $stop; + if (dout_bhs_rs_w != 96'h_00_00_00_00_00_00_00_00_00_00_00_01) $stop; - if (dout_bhs_ls_i != 32'h_00_00_00_10) $stop; - if (dout_bhs_ls_q != 64'h_00_00_00_00_00_00_01_00) $stop; - if (dout_bhs_ls_w != 96'h_00_00_00_00_00_00_00_00_00_00_00_04) $stop; + if (dout_bhs_ls_i != 32'h_00_00_00_10) $stop; + if (dout_bhs_ls_q != 64'h_00_00_00_00_00_00_01_00) $stop; + if (dout_bhs_ls_w != 96'h_00_00_00_00_00_00_00_00_00_00_00_04) $stop; - if (dout_rhs_ls_i_23_3 != 23'h_10_00_00) $stop; - if (dout_rhs_ls_i_23_4 != 23'h_08_00_00) $stop; + if (dout_rhs_ls_i_23_3 != 23'h_10_00_00) $stop; + if (dout_rhs_ls_i_23_4 != 23'h_08_00_00) $stop; - if (dout_rhs_ls_q_37_3 != 37'h_04_00_00_00_00) $stop; - if (dout_rhs_ls_q_37_4 != 37'h_02_00_00_00_00) $stop; + if (dout_rhs_ls_q_37_3 != 37'h_04_00_00_00_00) $stop; + if (dout_rhs_ls_q_37_4 != 37'h_02_00_00_00_00) $stop; end if (cyc == 3) begin - // The values below test the strange shift-merge done at the end of - // the fast stream operators. - // All-1s in the bits being streamed should end up as all-1s. - din_i <= 32'h_00_7f_ff_ff; - din_q <= 64'h_00_00_00_1f_ff_ff_ff_ff; + // The values below test the strange shift-merge done at the end of + // the fast stream operators. + // All-1s in the bits being streamed should end up as all-1s. + din_i <= 32'h_00_7f_ff_ff; + din_q <= 64'h_00_00_00_1f_ff_ff_ff_ff; - if (dout_rhs_ls_i != 32'h_80_40_c0_20) $stop; - if (dout_rhs_ls_q != 64'h_80_40_c0_20_a0_60_e0_10) $stop; - if (dout_rhs_ls_w != 96'h_80_40_c0_20_a0_60_e0_10_90_50_d0_30) $stop; + if (dout_rhs_ls_i != 32'h_80_40_c0_20) $stop; + if (dout_rhs_ls_q != 64'h_80_40_c0_20_a0_60_e0_10) $stop; + if (dout_rhs_ls_w != 96'h_80_40_c0_20_a0_60_e0_10_90_50_d0_30) $stop; if (dout_rhs_rs_i != 32'h_04_03_02_01) $stop; if (dout_rhs_rs_q != 64'h_08_07_06_05_04_03_02_01) $stop; if (dout_rhs_rs_w != 96'h_0c_0b_0a_09_08_07_06_05_04_03_02_01) $stop; - if (dout_bhs_ls_i != 32'h_40_30_00_18) $stop; - if (dout_bhs_ls_q != 64'h_06_00_c1_81_41_00_c1_80) $stop; - if (dout_bhs_ls_w != 96'h_30_2c_28_20_01_1c_1a_04_14_0c_00_06) $stop; + if (dout_bhs_ls_i != 32'h_40_30_00_18) $stop; + if (dout_bhs_ls_q != 64'h_06_00_c1_81_41_00_c1_80) $stop; + if (dout_bhs_ls_w != 96'h_30_2c_28_20_01_1c_1a_04_14_0c_00_06) $stop; - if (dout_bhs_rs_i != 32'h_04_03_02_01) $stop; - if (dout_bhs_rs_q != 64'h_08_07_06_05_04_03_02_01) $stop; - if (dout_bhs_rs_w != 96'h_0c_0b_0a_09_08_07_06_05_04_03_02_01) $stop; + if (dout_bhs_rs_i != 32'h_04_03_02_01) $stop; + if (dout_bhs_rs_q != 64'h_08_07_06_05_04_03_02_01) $stop; + if (dout_bhs_rs_w != 96'h_0c_0b_0a_09_08_07_06_05_04_03_02_01) $stop; - if (dout_lhs_ls_a != 2'b_11) $stop; - if (dout_lhs_ls_b != 2'b_01) $stop; + if (dout_lhs_ls_a != 2'b_11) $stop; + if (dout_lhs_ls_b != 2'b_01) $stop; - if (dout_lhs_rs_a != 2'b_01) $stop; - if (dout_lhs_rs_b != 2'b_11) $stop; + if (dout_lhs_rs_a != 2'b_01) $stop; + if (dout_lhs_rs_b != 2'b_11) $stop; - if (dout_rhs_ls_i_23_3 != 23'h_10_08_c0) $stop; - if (dout_rhs_ls_i_23_4 != 23'h_08_10_18) $stop; + if (dout_rhs_ls_i_23_3 != 23'h_10_08_c0) $stop; + if (dout_rhs_ls_i_23_4 != 23'h_08_10_18) $stop; - if (dout_rhs_ls_q_37_3 != 37'h_04_02_30_10_44) $stop; - if (dout_rhs_ls_q_37_4 != 37'h_02_04_06_08_0a) $stop; + if (dout_rhs_ls_q_37_3 != 37'h_04_02_30_10_44) $stop; + if (dout_rhs_ls_q_37_4 != 37'h_02_04_06_08_0a) $stop; end - if (cyc == 4) begin - if (dout_rhs_ls_i_23_3 != 23'h_7f_ff_ff) $stop; - if (dout_rhs_ls_i_23_4 != 23'h_7f_ff_ff) $stop; + if (cyc == 4) begin + if (dout_rhs_ls_i_23_3 != 23'h_7f_ff_ff) $stop; + if (dout_rhs_ls_i_23_4 != 23'h_7f_ff_ff) $stop; - if (dout_rhs_ls_q_37_3 != 37'h_1f_ff_ff_ff_ff) $stop; - if (dout_rhs_ls_q_37_4 != 37'h_1f_ff_ff_ff_ff) $stop; - end + if (dout_rhs_ls_q_37_3 != 37'h_1f_ff_ff_ff_ff) $stop; + if (dout_rhs_ls_q_37_4 != 37'h_1f_ff_ff_ff_ff) $stop; + end if (cyc == 9) begin $write("*-* All Finished *-*\n"); $finish; diff --git a/test_regress/t/t_stream2.v b/test_regress/t/t_stream2.v index 0fadf93ae..d272958d8 100644 --- a/test_regress/t/t_stream2.v +++ b/test_regress/t/t_stream2.v @@ -10,56 +10,56 @@ module t (/*AUTOARG*/ ); input clk; - integer cyc = 0; - reg [63:0] crc; - reg [63:0] sum; + integer cyc = 0; + reg [63:0] crc; + reg [63:0] sum; /*AUTOWIRE*/ // Beginning of automatic wires (for undeclared instantiated-module outputs) - wire [67:0] left; // From test of Test.v - wire [67:0] right; // From test of Test.v + wire [67:0] left; // From test of Test.v + wire [67:0] right; // From test of Test.v // End of automatics - wire [6:0] amt = crc[6:0]; - wire [67:0] in = {crc[3:0], crc[63:0]}; + wire [6:0] amt = crc[6:0]; + wire [67:0] in = {crc[3:0], crc[63:0]}; Test test (/*AUTOINST*/ - // Outputs - .left (left[67:0]), - .right (right[67:0]), - // Inputs - .amt (amt[6:0]), - .in (in[67:0])); + // Outputs + .left (left[67:0]), + .right (right[67:0]), + // Inputs + .amt (amt[6:0]), + .in (in[67:0])); wire [63:0] result = (left[63:0] ^ {60'h0, left[67:64]} - ^ right[63:0] ^ {60'h0, right[67:64]}); + ^ right[63:0] ^ {60'h0, right[67:64]}); // Test loop always @ (posedge clk) begin `ifdef TEST_VERBOSE $write("[%0t] cyc==%0d crc=%x result=%x amt=%x left=%x right=%x\n", - $time, cyc, crc, result, amt, left, right); + $time, cyc, crc, result, amt, left, right); `endif cyc <= cyc + 1; crc <= {crc[62:0], crc[63] ^ crc[2] ^ crc[0]}; sum <= result ^ {sum[62:0], sum[63] ^ sum[2] ^ sum[0]}; if (cyc==0) begin - // Setup - crc <= 64'h5aef0c8d_d70a4497; - sum <= 64'h0; + // Setup + crc <= 64'h5aef0c8d_d70a4497; + sum <= 64'h0; end else if (cyc<10) begin - sum <= 64'h0; + sum <= 64'h0; end else if (cyc<90) begin end else if (cyc==99) begin - $write("[%0t] cyc==%0d crc=%x sum=%x\n", $time, cyc, crc, sum); - if (crc !== 64'hc77bb9b3784ea091) $stop; - // What checksum will we end up with (above print should match) + $write("[%0t] cyc==%0d crc=%x sum=%x\n", $time, cyc, crc, sum); + if (crc !== 64'hc77bb9b3784ea091) $stop; + // What checksum will we end up with (above print should match) `define EXPECTED_SUM 64'h0da01049b480c38a - if (sum !== `EXPECTED_SUM) $stop; - $write("*-* All Finished *-*\n"); - $finish; + if (sum !== `EXPECTED_SUM) $stop; + $write("*-* All Finished *-*\n"); + $finish; end end @@ -72,7 +72,7 @@ module Test (/*AUTOARG*/ amt, in ); - input [6:0] amt; + input [6:0] amt; input [67:0] in; // amt must be constant diff --git a/test_regress/t/t_stream3.v b/test_regress/t/t_stream3.v index 24b740bf3..92c4c9dcf 100644 --- a/test_regress/t/t_stream3.v +++ b/test_regress/t/t_stream3.v @@ -12,18 +12,18 @@ module t (/*AUTOARG*/ ); input clk; - integer cyc = 0; - reg [63:0] crc; - reg [63:0] sum; + integer cyc = 0; + reg [63:0] crc; + reg [63:0] sum; /*AUTOWIRE*/ generate for (genvar width=1; width<=16; width++) begin - for (genvar amt=1; amt<=width; amt++) begin - Test #(.WIDTH(width), - .AMT(amt)) - test (.ins(crc[width-1:0])); - end + for (genvar amt=1; amt<=width; amt++) begin + Test #(.WIDTH(width), + .AMT(amt)) + test (.ins(crc[width-1:0])); + end end endgenerate @@ -31,28 +31,28 @@ module t (/*AUTOARG*/ always @ (posedge clk) begin `ifdef TEST_VERBOSE $write("[%0t] cyc==%0d crc=%x\n", - $time, cyc, crc); + $time, cyc, crc); `endif cyc <= cyc + 1; crc <= {crc[62:0], crc[63] ^ crc[2] ^ crc[0]}; if (cyc==0) begin - // Setup - crc <= 64'h5aef0c8d_d70a4497; - sum <= 64'h0; + // Setup + crc <= 64'h5aef0c8d_d70a4497; + sum <= 64'h0; end else if (cyc<10) begin - sum <= 64'h0; + sum <= 64'h0; end else if (cyc<90) begin end else if (cyc==99) begin - $write("[%0t] cyc==%0d crc=%x sum=%x\n", $time, cyc, crc, sum); - if (crc !== 64'hc77bb9b3784ea091) $stop; - // What checksum will we end up with (above print should match) + $write("[%0t] cyc==%0d crc=%x sum=%x\n", $time, cyc, crc, sum); + if (crc !== 64'hc77bb9b3784ea091) $stop; + // What checksum will we end up with (above print should match) `define EXPECTED_SUM 64'h0 - if (sum !== `EXPECTED_SUM) $stop; - $write("*-* All Finished *-*\n"); - $finish; + if (sum !== `EXPECTED_SUM) $stop; + $write("*-* All Finished *-*\n"); + $finish; end end @@ -69,9 +69,9 @@ module Test (/*AUTOARG*/ input [WIDTH-1:0] ins; reg [WIDTH-1:0] got; reg [WIDTH-1:0] expec; - int istart; - int bitn; - int ostart; + int istart; + int bitn; + int ostart; always @* begin got = { << AMT {ins}}; @@ -79,16 +79,16 @@ module Test (/*AUTOARG*/ // Note always starts with right-most bit expec = 0; for (istart=0; istart= 0 - && (ostart+bitn) < WIDTH - && (ostart+bitn) >= 0) begin - expec[ostart+bitn] = ins[istart+bitn]; - end - end + ostart = WIDTH - AMT - istart; + if (ostart<0) ostart = 0; + for (bitn=0; bitn= 0 + && (ostart+bitn) < WIDTH + && (ostart+bitn) >= 0) begin + expec[ostart+bitn] = ins[istart+bitn]; + end + end end `ifdef TEST_VERBOSE diff --git a/test_regress/t/t_string.v b/test_regress/t/t_string.v index 9e5327f37..34986b836 100644 --- a/test_regress/t/t_string.v +++ b/test_regress/t/t_string.v @@ -13,19 +13,19 @@ module t (/*AUTOARG*/ ); input clk; - integer cyc = 0; + integer cyc = 0; - reg [1*8:1] vstr1; - reg [2*8:1] vstr2; - reg [6*8:1] vstr6; + reg [1*8:1] vstr1; + reg [2*8:1] vstr2; + reg [6*8:1] vstr6; - reg [4*8:1] vstr; + reg [4*8:1] vstr; const string s = "a"; // Check static assignment - string s2; - string s3; - reg eq; + string s2; + string s3; + reg eq; - byte unpack1[0:4]; + byte unpack1[0:4]; // Operators == != < <= > >= {a,b} {a{b}} a[b] // a.len, a.putc, a.getc, a.toupper, a.tolower, a.compare, a.icompare, a.substr @@ -81,54 +81,54 @@ module t (/*AUTOARG*/ always @ (posedge clk) begin cyc <= cyc + 1; if (cyc==0) begin - // Setup - s2 = "c0"; + // Setup + s2 = "c0"; end else if (cyc==1) begin - $sformat(vstr, "s2%s", s2); - `checks(vstr, "s2c0"); + $sformat(vstr, "s2%s", s2); + `checks(vstr, "s2c0"); end else if (cyc==2) begin - s3 = s2; - $sformat(vstr, "s2%s", s3); - `checks(vstr, "s2c0"); + s3 = s2; + $sformat(vstr, "s2%s", s3); + `checks(vstr, "s2c0"); end else if (cyc==3) begin - s2 = "a"; - s3 = "b"; + s2 = "a"; + s3 = "b"; end else if (cyc==4) begin - `checks({s2,s3}, "ab"); - `checks({3{s3}}, "bbb"); - `checkh(s == "a", 1'b1); - `checkh(s == "b", 1'b0); - `checkh(s != "a", 1'b0); - `checkh(s != "b", 1'b1); - `checkh(s > " ", 1'b1); - `checkh(s > "a", 1'b0); - `checkh(s >= "a", 1'b1); - `checkh(s >= "b", 1'b0); - `checkh(s < "a", 1'b0); - `checkh(s < "b", 1'b1); - `checkh(s <= " ", 1'b0); - `checkh(s <= "a", 1'b1); + `checks({s2,s3}, "ab"); + `checks({3{s3}}, "bbb"); + `checkh(s == "a", 1'b1); + `checkh(s == "b", 1'b0); + `checkh(s != "a", 1'b0); + `checkh(s != "b", 1'b1); + `checkh(s > " ", 1'b1); + `checkh(s > "a", 1'b0); + `checkh(s >= "a", 1'b1); + `checkh(s >= "b", 1'b0); + `checkh(s < "a", 1'b0); + `checkh(s < "b", 1'b1); + `checkh(s <= " ", 1'b0); + `checkh(s <= "a", 1'b1); end // String character references else if (cyc==10) begin - s2 = "astring"; + s2 = "astring"; end else if (cyc==11) begin - `checks(s2, "astring"); - `checkh(s2.len(), 7); - `checkh(s2[1], "s"); - s2[0] = "0"; - s2[3] = "3"; - `checks(s2, "0st3ing"); + `checks(s2, "astring"); + `checkh(s2.len(), 7); + `checkh(s2[1], "s"); + s2[0] = "0"; + s2[3] = "3"; + `checks(s2, "0st3ing"); end // else if (cyc==99) begin - $write("*-* All Finished *-*\n"); - $finish; + $write("*-* All Finished *-*\n"); + $finish; end end diff --git a/test_regress/t/t_struct_array.v b/test_regress/t/t_struct_array.v index 80320e831..ae6c6c18c 100644 --- a/test_regress/t/t_struct_array.v +++ b/test_regress/t/t_struct_array.v @@ -7,7 +7,7 @@ package TEST_TYPES; typedef struct a_struct_t; // Forward typedef struct packed { - logic stuff; + logic stuff; } a_struct_t; endpackage // TEST_TYPES @@ -30,7 +30,7 @@ module sub(a_out); output TEST_TYPES::a_struct_t [n-1:0] a_out; always_comb begin for (int i=0;i 1) begin - $write("%%Error: Too many similar numbers: %d\n", same); - $stop; + $write("%%Error: Too many similar numbers: %d\n", same); + $stop; end $write("*-* All Finished *-*\n"); $finish; diff --git a/test_regress/t/t_sys_time.v b/test_regress/t/t_sys_time.v index 81f0b1422..58d37931c 100644 --- a/test_regress/t/t_sys_time.v +++ b/test_regress/t/t_sys_time.v @@ -10,9 +10,9 @@ module t (/*AUTOARG*/ ); input clk; - integer cyc = 0; + integer cyc = 0; - reg [63:0] time64; + reg [63:0] time64; // Test loop @@ -23,12 +23,12 @@ module t (/*AUTOARG*/ else if (cyc<10) begin end else if (cyc<90) begin - time64 = $time; - if ($stime != time64[31:0]) $stop; + time64 = $time; + if ($stime != time64[31:0]) $stop; end else if (cyc==99) begin - $write("*-* All Finished *-*\n"); - $finish; + $write("*-* All Finished *-*\n"); + $finish; end end diff --git a/test_regress/t/t_table_fsm.v b/test_regress/t/t_table_fsm.v index 4eab60786..79a8a524f 100644 --- a/test_regress/t/t_table_fsm.v +++ b/test_regress/t/t_table_fsm.v @@ -9,26 +9,26 @@ module t (/*AUTOARG*/ ); input clk; - integer cyc = 0; - reg [63:0] crc; - reg [63:0] sum; - reg reset; + integer cyc = 0; + reg [63:0] crc; + reg [63:0] sum; + reg reset; /*AUTOWIRE*/ // Beginning of automatic wires (for undeclared instantiated-module outputs) - wire myevent; // From test of Test.v - wire myevent_pending; // From test of Test.v - wire [1:0] state; // From test of Test.v + wire myevent; // From test of Test.v + wire myevent_pending; // From test of Test.v + wire [1:0] state; // From test of Test.v // End of automatics Test test (/*AUTOINST*/ - // Outputs - .state (state[1:0]), - .myevent (myevent), - .myevent_pending (myevent_pending), - // Inputs - .clk (clk), - .reset (reset)); + // Outputs + .state (state[1:0]), + .myevent (myevent), + .myevent_pending (myevent_pending), + // Inputs + .clk (clk), + .reset (reset)); // Aggregate outputs into a single result vector wire [63:0] result = {60'h0, myevent_pending,myevent,state}; @@ -43,20 +43,20 @@ module t (/*AUTOARG*/ sum <= result ^ {sum[62:0], sum[63] ^ sum[2] ^ sum[0]}; reset <= (cyc<2); if (cyc==0) begin - // Setup - crc <= 64'h5aef0c8d_d70a4497; - sum <= 64'h0; + // Setup + crc <= 64'h5aef0c8d_d70a4497; + sum <= 64'h0; end else if (cyc<90) begin end else if (cyc==99) begin - $write("[%0t] cyc==%0d crc=%x sum=%x\n", $time, cyc, crc, sum); - if (crc !== 64'hc77bb9b3784ea091) $stop; - // What checksum will we end up with (above print should match) + $write("[%0t] cyc==%0d crc=%x sum=%x\n", $time, cyc, crc, sum); + if (crc !== 64'hc77bb9b3784ea091) $stop; + // What checksum will we end up with (above print should match) `define EXPECTED_SUM 64'h4e93a74bd97b25ef - if (sum !== `EXPECTED_SUM) $stop; - $write("*-* All Finished *-*\n"); - $finish; + if (sum !== `EXPECTED_SUM) $stop; + $write("*-* All Finished *-*\n"); + $finish; end end @@ -71,56 +71,56 @@ module Test (/*AUTOARG*/ input clk; input reset; output [1:0] state; - output myevent; - output myevent_pending; + output myevent; + output myevent_pending; - reg [5:0] count = 0; + reg [5:0] count = 0; always @ (posedge clk) if (reset) count <= 0; else count <= count + 1; - reg myevent = 1'b0; + reg myevent = 1'b0; always @ (posedge clk) myevent <= (count == 6'd27); - reg myevent_done; - reg hickup_ready; - reg hickup_done; + reg myevent_done; + reg hickup_ready; + reg hickup_done; localparam STATE_ZERO = 0; localparam STATE_ONE = 1; localparam STATE_TWO = 2; - reg [1:0] state = STATE_ZERO; - reg state_start_myevent = 1'b0; - reg state_start_hickup = 1'b0; - reg myevent_pending = 1'b0; + reg [1:0] state = STATE_ZERO; + reg state_start_myevent = 1'b0; + reg state_start_hickup = 1'b0; + reg myevent_pending = 1'b0; always @ (posedge clk) begin state <= state; myevent_pending <= myevent_pending || myevent; state_start_myevent <= 1'b0; state_start_hickup <= 1'b0; case (state) - STATE_ZERO: - if (myevent_pending) begin + STATE_ZERO: + if (myevent_pending) begin state <= STATE_ONE; myevent_pending <= 1'b0; state_start_myevent <= 1'b1; - end else if (hickup_ready) begin + end else if (hickup_ready) begin state <= STATE_TWO; state_start_hickup <= 1'b1; - end + end - STATE_ONE: - if (myevent_done) + STATE_ONE: + if (myevent_done) state <= STATE_ZERO; - STATE_TWO: - if (hickup_done) + STATE_TWO: + if (hickup_done) state <= STATE_ZERO; - default: - ; /* do nothing */ + default: + ; /* do nothing */ endcase end diff --git a/test_regress/t/t_trace_array.v b/test_regress/t/t_trace_array.v index e98e1de1a..b0cafe6eb 100644 --- a/test_regress/t/t_trace_array.v +++ b/test_regress/t/t_trace_array.v @@ -6,7 +6,7 @@ module t (clk); input clk; - integer cyc = 0; + integer cyc = 0; // Trace would overflow at 256KB which is 256 kb dump, 16 kb in a chunk @@ -20,8 +20,8 @@ module t (clk); cyc <= cyc + 1; biggie [ cyc +: 32 ] <= 32'hfeedface; if (cyc == 5) begin - $write("*-* All Finished *-*\n"); - $finish; + $write("*-* All Finished *-*\n"); + $finish; end end endmodule diff --git a/test_regress/t/t_trace_decoration.v b/test_regress/t/t_trace_decoration.v index 06ac8bfdb..4407c8390 100644 --- a/test_regress/t/t_trace_decoration.v +++ b/test_regress/t/t_trace_decoration.v @@ -6,12 +6,12 @@ module t (clk); input clk; - integer a_very_long_name_which_we_will_hash_eventually=0; + integer a_very_long_name_which_we_will_hash_eventually=0; always @ (posedge clk) begin a_very_long_name_which_we_will_hash_eventually <= a_very_long_name_which_we_will_hash_eventually + 1; if (a_very_long_name_which_we_will_hash_eventually == 5) begin - fin(); + fin(); end end diff --git a/test_regress/t/t_trace_param.v b/test_regress/t/t_trace_param.v index c112e0251..e1366ec32 100644 --- a/test_regress/t/t_trace_param.v +++ b/test_regress/t/t_trace_param.v @@ -7,7 +7,7 @@ package my_funcs; function automatic int simple_func (input int value); begin - simple_func = value; + simple_func = value; end endfunction endpackage @@ -22,8 +22,8 @@ endpackage module t import my_module_types::*; ( - input i_clk, - input [MY_PARAM-1:0] i_d, + input i_clk, + input [MY_PARAM-1:0] i_d, output logic [MY_PARAM-1:0] o_q ); diff --git a/test_regress/t/t_tri_array.v b/test_regress/t/t_tri_array.v index e79ba3d6d..fbda60f76 100644 --- a/test_regress/t/t_tri_array.v +++ b/test_regress/t/t_tri_array.v @@ -10,24 +10,24 @@ module t (/*AUTOARG*/ ); input clk; - integer cyc = 0; - reg [63:0] crc; - reg [63:0] sum; + integer cyc = 0; + reg [63:0] crc; + reg [63:0] sum; parameter NPAD = 4; - tri pad [NPAD-1:0]; // Array - wire [NPAD-1:0] data0 = crc[0 +: 4]; - wire [NPAD-1:0] data1 = crc[8 +: 4]; - wire [NPAD-1:0] en = crc[16 +: 4]; + tri pad [NPAD-1:0]; // Array + wire [NPAD-1:0] data0 = crc[0 +: 4]; + wire [NPAD-1:0] data1 = crc[8 +: 4]; + wire [NPAD-1:0] en = crc[16 +: 4]; for (genvar g=0; g 5) - a <= 17; + a <= 17; // single if with else unique0 if (cyc < 3) - b <= 17; + b <= 17; else - b <= 19; + b <= 19; // multi if, some cases may not be true unique0 if (cyc < 3) - c <= 17; + c <= 17; else if (cyc > 3) - c <= 19; + c <= 19; // multi if with else, else clause hit in some cases unique0 if (cyc < 3) - d <= 17; + d <= 17; else if (cyc > 3) - d <= 19; + d <= 19; else - d <= 21; + d <= 21; // single if with else unique if (cyc < 3) - f <= 17; + f <= 17; else - f <= 19; + f <= 19; // multi if unique if (cyc < 3) - g <= 17; + g <= 17; else if (cyc >= 3) - g <= 19; + g <= 19; // multi if with else, else clause hit in some cases unique if (cyc < 3) - h <= 17; + h <= 17; else if (cyc > 3) - h <= 19; + h <= 19; else - h <= 21; + h <= 21; //==================== // Negative test cases @@ -72,25 +72,25 @@ module t (/*AUTOARG*/ $display("testing fail 1: %d", cyc); // multi if, multiple cases true unique0 if (cyc < 3) - i <= 17; + i <= 17; else if (cyc < 5) - i <= 19; + i <= 19; `endif `ifdef FAILING_ASSERTION2 // multi if, multiple cases true unique if (cyc < 3) - j <= 17; + j <= 17; else if (cyc < 5) - j <= 19; + j <= 19; `endif `ifdef FAILING_ASSERTION3 // multi if, no cases true unique if (cyc > 1000) - k <= 17; + k <= 17; else if (cyc > 2000) - k <= 19; + k <= 19; `endif `ifdef FAILING_ASSERTION4 @@ -100,13 +100,13 @@ module t (/*AUTOARG*/ // corresponding else." In this case, the final if is the only if, but I think the clause // still applies. unique if (cyc > 5) - l <= 17; + l <= 17; `endif if (cyc==10) begin - $write("*-* All Finished *-*\n"); - $finish; + $write("*-* All Finished *-*\n"); + $finish; end end endmodule diff --git a/test_regress/t/t_unopt_array.v b/test_regress/t/t_unopt_array.v index 1ca4db785..9f3bc9718 100644 --- a/test_regress/t/t_unopt_array.v +++ b/test_regress/t/t_unopt_array.v @@ -10,24 +10,24 @@ module t (/*AUTOARG*/ ); input clk; - integer cyc = 0; - reg [63:0] crc; - reg [63:0] sum; + integer cyc = 0; + reg [63:0] crc; + reg [63:0] sum; // Take CRC data and apply to testblock inputs wire [31:0] in = crc[31:0]; /*AUTOWIRE*/ // Beginning of automatic wires (for undeclared instantiated-module outputs) - wire [31:0] out; // From test of Test.v + wire [31:0] out; // From test of Test.v // End of automatics Test test (/*AUTOINST*/ - // Outputs - .out (out[31:0]), - // Inputs - .clk (clk), - .in (in[31:0])); + // Outputs + .out (out[31:0]), + // Inputs + .clk (clk), + .in (in[31:0])); // Aggregate outputs into a single result vector wire [63:0] result = {32'h0, out}; @@ -41,23 +41,23 @@ module t (/*AUTOARG*/ crc <= {crc[62:0], crc[63] ^ crc[2] ^ crc[0]}; sum <= result ^ {sum[62:0], sum[63] ^ sum[2] ^ sum[0]}; if (cyc==0) begin - // Setup - crc <= 64'h5aef0c8d_d70a4497; - sum <= 64'h0; + // Setup + crc <= 64'h5aef0c8d_d70a4497; + sum <= 64'h0; end else if (cyc<10) begin - sum <= 64'h0; + sum <= 64'h0; end else if (cyc<90) begin end else if (cyc==99) begin - $write("[%0t] cyc==%0d crc=%x sum=%x\n", $time, cyc, crc, sum); - if (crc !== 64'hc77bb9b3784ea091) $stop; - // What checksum will we end up with (above print should match) + $write("[%0t] cyc==%0d crc=%x sum=%x\n", $time, cyc, crc, sum); + if (crc !== 64'hc77bb9b3784ea091) $stop; + // What checksum will we end up with (above print should match) `define EXPECTED_SUM 64'h458c2de282e30f8b - if (sum !== `EXPECTED_SUM) $stop; - $write("*-* All Finished *-*\n"); - $finish; + if (sum !== `EXPECTED_SUM) $stop; + $write("*-* All Finished *-*\n"); + $finish; end end @@ -74,16 +74,16 @@ module Test (/*AUTOARG*/ input [31:0] in; output wire [31:0] out; - reg [31:0] stage [3:0]; + reg [31:0] stage [3:0]; - genvar g; + genvar g; generate for (g=0; g<4; g++) begin - always_comb begin - if (g==0) stage[g] = in; - else stage[g] = {stage[g-1][30:0],1'b1}; - end + always_comb begin + if (g==0) stage[g] = in; + else stage[g] = {stage[g-1][30:0],1'b1}; + end end endgenerate diff --git a/test_regress/t/t_unopt_bound.v b/test_regress/t/t_unopt_bound.v index f02be70b5..7c708c035 100644 --- a/test_regress/t/t_unopt_bound.v +++ b/test_regress/t/t_unopt_bound.v @@ -10,12 +10,12 @@ module t ( clk, out ); input clk; output out; - reg a; - reg b; + reg a; + reg b; typedef struct packed { - logic config_a; - logic config_b; + logic config_a; + logic config_b; } param_t; // verilator lint_off UNOPTFLAT param_t conf [1:2] ; diff --git a/test_regress/t/t_unoptflat_simple.v b/test_regress/t/t_unoptflat_simple.v index 7c9f63f82..76ca19e95 100644 --- a/test_regress/t/t_unoptflat_simple.v +++ b/test_regress/t/t_unoptflat_simple.v @@ -25,8 +25,8 @@ module t (/*AUTOARG*/ `endif if (x[1] != 0) begin - $write("*-* All Finished *-*\n"); - $finish; + $write("*-* All Finished *-*\n"); + $finish; end end diff --git a/test_regress/t/t_unoptflat_simple_3.v b/test_regress/t/t_unoptflat_simple_3.v index 09c33e22a..8e1ed888e 100644 --- a/test_regress/t/t_unoptflat_simple_3.v +++ b/test_regress/t/t_unoptflat_simple_3.v @@ -20,12 +20,12 @@ module t (/*AUTOARG*/ end test1 test1i ( .clk (clk), - .xvecin (x[1:0]), - .xvecout (x[2:1])); + .xvecin (x[1:0]), + .xvecout (x[2:1])); test2 test2i ( .clk (clk), - .xvecin (x[2:1]), - .xvecout (x[1:0])); + .xvecin (x[2:1]), + .xvecout (x[1:0])); always @(posedge clk or negedge clk) begin @@ -34,8 +34,8 @@ module t (/*AUTOARG*/ `endif if (x[1] != 0) begin - $write("*-* All Finished *-*\n"); - $finish; + $write("*-* All Finished *-*\n"); + $finish; end end diff --git a/test_regress/t/t_unroll_forfor.v b/test_regress/t/t_unroll_forfor.v index a37ad75eb..972620b1a 100644 --- a/test_regress/t/t_unroll_forfor.v +++ b/test_regress/t/t_unroll_forfor.v @@ -21,15 +21,15 @@ module t (/*AUTOARG*/ // Test loop always @* begin: testmap - byte i, j; - // bug1044 - for ( i = 0; i < 9; i = i + 1 ) - // verilator lint_off WIDTH + byte i, j; + // bug1044 + for ( i = 0; i < 9; i = i + 1 ) + // verilator lint_off WIDTH for ( j=0; j<(TEST_PARAM[i*8+:8]); j=j+1) begin in_tmp[TEST_PARAM[i*8+:8]+j] = in[TEST_PARAM[i*8+:8]+j]; end - // verilator lint_on WIDTH - $write("*-* All Finished *-*\n"); - $finish; + // verilator lint_on WIDTH + $write("*-* All Finished *-*\n"); + $finish; end endmodule diff --git a/test_regress/t/t_unroll_signed.v b/test_regress/t/t_unroll_signed.v index e565137b7..72e910314 100644 --- a/test_regress/t/t_unroll_signed.v +++ b/test_regress/t/t_unroll_signed.v @@ -23,130 +23,130 @@ module t (/*AUTOARG*/ endtask // Check look unroller - reg signed signed_tests_only = 1'sb1; - integer total; + reg signed signed_tests_only = 1'sb1; + integer total; - integer i; - reg [31:0] iu; - reg [31:0] dly_to_ensure_was_unrolled [1:0]; - reg [2:0] i3; + integer i; + reg [31:0] iu; + reg [31:0] dly_to_ensure_was_unrolled [1:0]; + reg [2:0] i3; integer cyc; initial cyc = 0; always @ (posedge clk) begin cyc <= cyc + 1; case (cyc) - 1: begin - // >= signed - total = 0; - for (i=5; i>=0; i=i-1) begin - total = total - i -1; - dly_to_ensure_was_unrolled[i] <= i; - end - if (total != -21) $stop; - end - 2: begin - // > signed - total = 0; - for (i=5; i>0; i=i-1) begin - total = total - i -1; - dly_to_ensure_was_unrolled[i] <= i; - end - if (total != -20) $stop; - end - 3: begin - // < signed - total = 0; - for (i=1; i<5; i=i+1) begin - total = total - i -1; - dly_to_ensure_was_unrolled[i] <= i; - end - if (total != -14) $stop; - end - 4: begin - // <= signed - total = 0; - for (i=1; i<=5; i=i+1) begin - total = total - i -1; - dly_to_ensure_was_unrolled[i] <= i; - end - if (total != -20) $stop; - end - // UNSIGNED - 5: begin - // >= unsigned - total = 0; - for (iu=5; iu>=1; iu=iu-1) begin - total = total - iu -1; - dly_to_ensure_was_unrolled[iu] <= iu; - end - if (total != -20) $stop; - end - 6: begin - // > unsigned - total = 0; - for (iu=5; iu>1; iu=iu-1) begin - total = total - iu -1; - dly_to_ensure_was_unrolled[iu] <= iu; - end - if (total != -18) $stop; - end - 7: begin - // < unsigned - total = 0; - for (iu=1; iu<5; iu=iu+1) begin - total = total - iu -1; - dly_to_ensure_was_unrolled[iu] <= iu; - end - if (total != -14) $stop; - end - 8: begin - // <= unsigned - total = 0; - for (iu=1; iu<=5; iu=iu+1) begin - total = total - iu -1; - dly_to_ensure_was_unrolled[iu] <= iu; - end - if (total != -20) $stop; - end - //=== - 9: begin - // mostly cover a small index - total = 0; - for (i3=3'd0; i3<3'd7; i3=i3+3'd1) begin - total = total - {29'd0,i3} -1; - dly_to_ensure_was_unrolled[i3[0]] <= 0; - end - if (total != -28) $stop; - end - //=== - 10: begin - // mostly cover a small index - total = 0; - for (i3=0; i3<3'd7; i3=i3+3'd1) begin - total = total - {29'd0,i3} -1; - dly_to_ensure_was_unrolled[i3[0]] <= 0; - end - if (total != -28) $stop; - end - //=== - 11: begin - // width violation on <, causes extend - total = 0; - for (i3=3'd0; i3<7; i3=i3+1) begin - total = total - {29'd0,i3} -1; - dly_to_ensure_was_unrolled[i3[0]] <= 0; - end - if (total != -28) $stop; - end - //=== - // width violation on <, causes extend signed - // Unsupported as yet - //=== - 19: begin - $write("*-* All Finished *-*\n"); - $finish; - end - default: ; + 1: begin + // >= signed + total = 0; + for (i=5; i>=0; i=i-1) begin + total = total - i -1; + dly_to_ensure_was_unrolled[i] <= i; + end + if (total != -21) $stop; + end + 2: begin + // > signed + total = 0; + for (i=5; i>0; i=i-1) begin + total = total - i -1; + dly_to_ensure_was_unrolled[i] <= i; + end + if (total != -20) $stop; + end + 3: begin + // < signed + total = 0; + for (i=1; i<5; i=i+1) begin + total = total - i -1; + dly_to_ensure_was_unrolled[i] <= i; + end + if (total != -14) $stop; + end + 4: begin + // <= signed + total = 0; + for (i=1; i<=5; i=i+1) begin + total = total - i -1; + dly_to_ensure_was_unrolled[i] <= i; + end + if (total != -20) $stop; + end + // UNSIGNED + 5: begin + // >= unsigned + total = 0; + for (iu=5; iu>=1; iu=iu-1) begin + total = total - iu -1; + dly_to_ensure_was_unrolled[iu] <= iu; + end + if (total != -20) $stop; + end + 6: begin + // > unsigned + total = 0; + for (iu=5; iu>1; iu=iu-1) begin + total = total - iu -1; + dly_to_ensure_was_unrolled[iu] <= iu; + end + if (total != -18) $stop; + end + 7: begin + // < unsigned + total = 0; + for (iu=1; iu<5; iu=iu+1) begin + total = total - iu -1; + dly_to_ensure_was_unrolled[iu] <= iu; + end + if (total != -14) $stop; + end + 8: begin + // <= unsigned + total = 0; + for (iu=1; iu<=5; iu=iu+1) begin + total = total - iu -1; + dly_to_ensure_was_unrolled[iu] <= iu; + end + if (total != -20) $stop; + end + //=== + 9: begin + // mostly cover a small index + total = 0; + for (i3=3'd0; i3<3'd7; i3=i3+3'd1) begin + total = total - {29'd0,i3} -1; + dly_to_ensure_was_unrolled[i3[0]] <= 0; + end + if (total != -28) $stop; + end + //=== + 10: begin + // mostly cover a small index + total = 0; + for (i3=0; i3<3'd7; i3=i3+3'd1) begin + total = total - {29'd0,i3} -1; + dly_to_ensure_was_unrolled[i3[0]] <= 0; + end + if (total != -28) $stop; + end + //=== + 11: begin + // width violation on <, causes extend + total = 0; + for (i3=3'd0; i3<7; i3=i3+1) begin + total = total - {29'd0,i3} -1; + dly_to_ensure_was_unrolled[i3[0]] <= 0; + end + if (total != -28) $stop; + end + //=== + // width violation on <, causes extend signed + // Unsupported as yet + //=== + 19: begin + $write("*-* All Finished *-*\n"); + $finish; + end + default: ; endcase end endmodule diff --git a/test_regress/t/t_vams_wreal.v b/test_regress/t/t_vams_wreal.v index 6fe807df3..01d5fcc15 100644 --- a/test_regress/t/t_vams_wreal.v +++ b/test_regress/t/t_vams_wreal.v @@ -16,20 +16,20 @@ module t (/*autoarg*/ input [15:0] in; wreal aout; - integer cyc = 0; + integer cyc = 0; - real vin; - wreal vpass; + real vin; + wreal vpass; through through (.vin, .vpass); - real gnd; - wire out; + real gnd; + wire out; within_range within_range (/*AUTOINST*/ - // Interfaces - .vpass (vpass), - .gnd (gnd), - // Outputs - .out (out)); + // Interfaces + .vpass (vpass), + .gnd (gnd), + // Outputs + .out (out)); // wreal bus declaration wreal vin_upper_bus[1:0]; @@ -62,30 +62,30 @@ module t (/*autoarg*/ $write("[%0t] cyc==%0d aout=%d (%f-%f=%f)\n", $time, cyc, out, vin, gnd, within_range.in_int); `endif if (cyc==0) begin - // Setup - gnd = 0.0; - vin = 0.2; + // Setup + gnd = 0.0; + vin = 0.2; end else if (cyc==2) begin - if (out != 0) $stop; + if (out != 0) $stop; end else if (cyc==3) begin - gnd = 0.0; - vin = 0.6; + gnd = 0.0; + vin = 0.6; end else if (cyc==4) begin - if (out != 1) $stop; + if (out != 1) $stop; end else if (cyc==5) begin - gnd = 0.6; - vin = 0.8; + gnd = 0.6; + vin = 0.8; end else if (cyc==6) begin - if (out != 0) $stop; + if (out != 0) $stop; end else if (cyc==99) begin - $write("*-* All Finished *-*\n"); - $finish; + $write("*-* All Finished *-*\n"); + $finish; end end diff --git a/test_regress/t/t_var_assign_landr.v b/test_regress/t/t_var_assign_landr.v index dabaa0cef..5c6d4faa9 100644 --- a/test_regress/t/t_var_assign_landr.v +++ b/test_regress/t/t_var_assign_landr.v @@ -10,25 +10,25 @@ module t (/*AUTOARG*/ ); input clk; - integer cyc = 0; - reg [63:0] crc; - reg [255:0] sum; + integer cyc = 0; + reg [63:0] crc; + reg [255:0] sum; // Take CRC data and apply to testblock inputs wire [127:0] in = {~crc[63:0], crc[63:0]}; /*AUTOWIRE*/ // Beginning of automatic wires (for undeclared instantiated-module outputs) - wire [127:0] o1; // From test of Test.v - wire [127:0] o2; // From test of Test.v + wire [127:0] o1; // From test of Test.v + wire [127:0] o2; // From test of Test.v // End of automatics Test test (/*AUTOINST*/ - // Outputs - .o1 (o1[127:0]), - .o2 (o2[127:0]), - // Inputs - .in (in[127:0])); + // Outputs + .o1 (o1[127:0]), + .o2 (o2[127:0]), + // Inputs + .in (in[127:0])); // Test loop always @ (posedge clk) begin @@ -39,23 +39,23 @@ module t (/*AUTOARG*/ crc <= {crc[62:0], crc[63] ^ crc[2] ^ crc[0]}; sum <= {o1,o2} ^ {sum[254:0],sum[255]^sum[2]^sum[0]}; if (cyc==0) begin - // Setup - crc <= 64'h5aef0c8d_d70a4497; - sum <= '0; + // Setup + crc <= 64'h5aef0c8d_d70a4497; + sum <= '0; end else if (cyc<10) begin - sum <= '0; + sum <= '0; end else if (cyc<90) begin end else if (cyc==99) begin - $write("[%0t] cyc==%0d crc=%x sum=%x\n", $time, cyc, crc, sum); - if (crc !== 64'hc77bb9b3784ea091) $stop; - // What checksum will we end up with (above print should match) + $write("[%0t] cyc==%0d crc=%x sum=%x\n", $time, cyc, crc, sum); + if (crc !== 64'hc77bb9b3784ea091) $stop; + // What checksum will we end up with (above print should match) `define EXPECTED_SUM 256'h008a080aaa000000140550404115dc7b008a080aaae7c8cd897bc1ca49c9350a - if (sum !== `EXPECTED_SUM) $stop; - $write("*-* All Finished *-*\n"); - $finish; + if (sum !== `EXPECTED_SUM) $stop; + $write("*-* All Finished *-*\n"); + $finish; end end diff --git a/test_regress/t/t_var_escape.v b/test_regress/t/t_var_escape.v index 4cd91d58d..bc2b38ea5 100644 --- a/test_regress/t/t_var_escape.v +++ b/test_regress/t/t_var_escape.v @@ -55,14 +55,14 @@ module t (/*AUTOARG*/ if (\a0.cyc != ~cyc) $stop; if (\other.cyc != ~cyc) $stop; if (cyc==10) begin - $write("*-* All Finished *-*\n"); - $finish; + $write("*-* All Finished *-*\n"); + $finish; end end endmodule module sub ( - input [31:0] cyc - ); + input [31:0] cyc + ); endmodule diff --git a/test_regress/t/t_var_in_assign.v b/test_regress/t/t_var_in_assign.v index aa41a3d03..cf6c488ac 100644 --- a/test_regress/t/t_var_in_assign.v +++ b/test_regress/t/t_var_in_assign.v @@ -9,14 +9,14 @@ module t (/*AUTOARG*/ ); input clk; - integer cyc = 0; - integer v; + integer cyc = 0; + integer v; - reg i; + reg i; /*AUTOWIRE*/ // Beginning of automatic wires (for undeclared instantiated-module outputs) - wire oa; // From a of a.v - wire oz; // From z of z.v + wire oa; // From a of a.v + wire oz; // From z of z.v // End of automatics a a (.*); @@ -29,21 +29,21 @@ module t (/*AUTOARG*/ cyc <= cyc + 1; i <= cyc[0]; if (cyc==0) begin - v = 3; - if (v !== 3) $stop; - if (assignin(v) !== 2) $stop; - if (v !== 3) $stop; // Make sure V didn't get changed + v = 3; + if (v !== 3) $stop; + if (assignin(v) !== 2) $stop; + if (v !== 3) $stop; // Make sure V didn't get changed end else if (cyc<10) begin - if (cyc==11 && oz!==1'b0) $stop; - if (cyc==12 && oz!==1'b1) $stop; - if (cyc==12 && oa!==1'b1) $stop; + if (cyc==11 && oz!==1'b0) $stop; + if (cyc==12 && oz!==1'b1) $stop; + if (cyc==12 && oa!==1'b1) $stop; end else if (cyc<90) begin end else if (cyc==99) begin - $write("*-* All Finished *-*\n"); - $finish; + $write("*-* All Finished *-*\n"); + $finish; end end diff --git a/test_regress/t/t_var_init.v b/test_regress/t/t_var_init.v index 87f4dfab0..4d61632d6 100644 --- a/test_regress/t/t_var_init.v +++ b/test_regress/t/t_var_init.v @@ -12,9 +12,9 @@ module t (/*AUTOARG*/ input clk; parameter [31:0] p2=2, p3=3; - integer i2=2, i3=3; - reg [31:0] r2=2, r3=3; - wire [31:0] w2=2, w3=3; + integer i2=2, i3=3; + reg [31:0] r2=2, r3=3; + wire [31:0] w2=2, w3=3; always @ (posedge clk) begin if (p2 !== 2) $stop; diff --git a/test_regress/t/t_var_life.v b/test_regress/t/t_var_life.v index f8a876eb0..2ec1c4d7d 100644 --- a/test_regress/t/t_var_life.v +++ b/test_regress/t/t_var_life.v @@ -21,85 +21,85 @@ module t (/*AUTOARG*/ always @* begin fixin = {din[7:0],din[7:0]}; case (din[1:0]) - 2'b00: begin - fixin = {fixin[14:0], 1'b1}; - if (cyc==101) $display("Prevent ?: optimization a"); - end - 2'b01: begin - fixin = {fixin[13:0], 2'b11}; - if (cyc==101) $display("Prevent ?: optimization b"); - end - 2'b10: begin - fixin = {fixin[12:0], 3'b111}; - if (cyc==101) $display("Prevent ?: optimization c"); - end - 2'b11: begin - fixin = {fixin[11:0], 4'b1111}; - if (cyc==101) $display("Prevent ?: optimization d"); - end + 2'b00: begin + fixin = {fixin[14:0], 1'b1}; + if (cyc==101) $display("Prevent ?: optimization a"); + end + 2'b01: begin + fixin = {fixin[13:0], 2'b11}; + if (cyc==101) $display("Prevent ?: optimization b"); + end + 2'b10: begin + fixin = {fixin[12:0], 3'b111}; + if (cyc==101) $display("Prevent ?: optimization c"); + end + 2'b11: begin + fixin = {fixin[11:0], 4'b1111}; + if (cyc==101) $display("Prevent ?: optimization d"); + end endcase end always @ (posedge clk) begin if (cyc!=0) begin - cyc<=cyc+1; - if (cyc==1) begin - life = 16'h8000; // Dropped - life = 16'h0010; // Used below - if (life != 16'h0010) $stop; - // - life = 16'h0020; // Used below - if ($time < 10000) - if (life != 16'h0020) $stop; - // - life = 16'h8000; // Dropped - if ($time > 100000) begin - if ($time != 0) $stop; // Prevent conversion to ?: - life = 16'h1030; - end - else - life = 16'h0030; - if (life != 16'h0030) $stop; - // - life = 16'h0040; // Not dropped, no else below - if ($time > 100000) - life = 16'h1040; - if (life != 16'h0040) $stop; - // - life = 16'h8000; // Dropped - if ($time > 100000) begin - life = 16'h1050; - if (life != 0) $stop; // Ignored, as set is first - end - else begin - if ($time > 100010) - life = 16'h1050; - else life = 16'h0050; - end - if (life != 16'h0050) $stop; - end - if (cyc==2) begin - din <= 8'haa; - end - if (cyc==3) begin - din <= 8'hfb; - if (fixin != 16'h5557) $stop; - end - if (cyc==4) begin - din <= 8'h5c; - if (fixin != 16'hbfbf) $stop; - end - if (cyc==5) begin - din <= 8'hed; - if (fixin != 16'hb8b9) $stop; - end - if (cyc==6) begin - if (fixin != 16'hb7b7) $stop; - end - if (cyc==9) begin - $write("*-* All Finished *-*\n"); - $finish; - end + cyc<=cyc+1; + if (cyc==1) begin + life = 16'h8000; // Dropped + life = 16'h0010; // Used below + if (life != 16'h0010) $stop; + // + life = 16'h0020; // Used below + if ($time < 10000) + if (life != 16'h0020) $stop; + // + life = 16'h8000; // Dropped + if ($time > 100000) begin + if ($time != 0) $stop; // Prevent conversion to ?: + life = 16'h1030; + end + else + life = 16'h0030; + if (life != 16'h0030) $stop; + // + life = 16'h0040; // Not dropped, no else below + if ($time > 100000) + life = 16'h1040; + if (life != 16'h0040) $stop; + // + life = 16'h8000; // Dropped + if ($time > 100000) begin + life = 16'h1050; + if (life != 0) $stop; // Ignored, as set is first + end + else begin + if ($time > 100010) + life = 16'h1050; + else life = 16'h0050; + end + if (life != 16'h0050) $stop; + end + if (cyc==2) begin + din <= 8'haa; + end + if (cyc==3) begin + din <= 8'hfb; + if (fixin != 16'h5557) $stop; + end + if (cyc==4) begin + din <= 8'h5c; + if (fixin != 16'hbfbf) $stop; + end + if (cyc==5) begin + din <= 8'hed; + if (fixin != 16'hb8b9) $stop; + end + if (cyc==6) begin + if (fixin != 16'hb7b7) $stop; + end + if (cyc==9) begin + $write("*-* All Finished *-*\n"); + $finish; + end end end endmodule diff --git a/test_regress/t/t_var_local.v b/test_regress/t/t_var_local.v index 25a112a01..c6871625d 100644 --- a/test_regress/t/t_var_local.v +++ b/test_regress/t/t_var_local.v @@ -18,30 +18,30 @@ module t; initial begin begin : a - integer lower; - integer lower_assign=1; - lower = 1; - top = 1; - if (lower != 1) $stop; - if (lower_assign != 1) $stop; - begin : aa - integer lev2; - lev2 = 1; - lower = 2; - lower_assign = 2; - top = 2; - end - if (lower != 2) $stop; - if (lower_assign != 2) $stop; + integer lower; + integer lower_assign=1; + lower = 1; + top = 1; + if (lower != 1) $stop; + if (lower_assign != 1) $stop; + begin : aa + integer lev2; + lev2 = 1; + lower = 2; + lower_assign = 2; + top = 2; + end + if (lower != 2) $stop; + if (lower_assign != 2) $stop; end begin : b - integer lower; - lower = 1; - top = 2; - begin : empty - begin : empty - end - end + integer lower; + lower = 1; + top = 2; + begin : empty + begin : empty + end + end end tsk; tsk; // Second time to ensure we reinit the initial value diff --git a/test_regress/t/t_var_outoforder.v b/test_regress/t/t_var_outoforder.v index 9c01c7358..90b386e39 100644 --- a/test_regress/t/t_var_outoforder.v +++ b/test_regress/t/t_var_outoforder.v @@ -16,40 +16,40 @@ module t (/*AUTOARG*/ wire q; sub sub ( - .q (q), - .a (a), - .clk (clk)); + .q (q), + .a (a), + .clk (clk)); always @ (posedge clk) begin if (cyc!=0) begin - cyc <= cyc + 1; - if (cyc==1) begin - a <= 126'b1000; - end - if (cyc==2) begin - a <= 126'h1001; - end - if (cyc==3) begin - a <= 126'h1010; - end - if (cyc==4) begin - a <= 126'h1111; - if (q !== 1'b0) $stop; - end - if (cyc==5) begin - if (q !== 1'b1) $stop; - end - if (cyc==6) begin - if (q !== 1'b0) $stop; - end - if (cyc==7) begin - if (q !== 1'b0) $stop; - end - if (cyc==8) begin - if (q !== 1'b0) $stop; - $write("*-* All Finished *-*\n"); - $finish; - end + cyc <= cyc + 1; + if (cyc==1) begin + a <= 126'b1000; + end + if (cyc==2) begin + a <= 126'h1001; + end + if (cyc==3) begin + a <= 126'h1010; + end + if (cyc==4) begin + a <= 126'h1111; + if (q !== 1'b0) $stop; + end + if (cyc==5) begin + if (q !== 1'b1) $stop; + end + if (cyc==6) begin + if (q !== 1'b0) $stop; + end + if (cyc==7) begin + if (q !== 1'b0) $stop; + end + if (cyc==8) begin + if (q !== 1'b0) $stop; + $write("*-* All Finished *-*\n"); + $finish; + end end end diff --git a/test_regress/t/t_var_overcmp.v b/test_regress/t/t_var_overcmp.v index c647e4df1..c03da0f48 100644 --- a/test_regress/t/t_var_overcmp.v +++ b/test_regress/t/t_var_overcmp.v @@ -18,12 +18,12 @@ module t (/*AUTOARG*/ input [7:0] dbgsel_w; output [7:0] dout; - wire [7:0] dout = dout0 | dout1; + wire [7:0] dout = dout0 | dout1; /*AUTOWIRE*/ // Beginning of automatic wires (for undeclared instantiated-module outputs) - wire [7:0] dout0; // From sub0 of sub0.v - wire [7:0] dout1; // From sub1 of sub1.v + wire [7:0] dout0; // From sub0 of sub0.v + wire [7:0] dout1; // From sub1 of sub1.v // End of automatics initial begin @@ -31,14 +31,14 @@ module t (/*AUTOARG*/ $finish; end - reg [7:0] dbgsel_msk; + reg [7:0] dbgsel_msk; always_comb begin reg [7:0] mask; mask = 8'hff; dbgsel_msk = (dbgsel_w & mask); end - reg [7:0] dbgsel; + reg [7:0] dbgsel; always @(posedge clk) begin if ((rstn == 0)) begin dbgsel <= 0; @@ -49,21 +49,21 @@ module t (/*AUTOARG*/ end sub0 sub0 (/*AUTOINST*/ - // Outputs - .dout0 (dout0[7:0]), - // Inputs - .rstn (rstn), - .clk (clk), - .dval1 (dval1[7:0]), - .dbgsel (dbgsel[7:0])); + // Outputs + .dout0 (dout0[7:0]), + // Inputs + .rstn (rstn), + .clk (clk), + .dval1 (dval1[7:0]), + .dbgsel (dbgsel[7:0])); sub1 sub1 (/*AUTOINST*/ - // Outputs - .dout1 (dout1[7:0]), - // Inputs - .rstn (rstn), - .clk (clk), - .dval1 (dval1[7:0]), - .dbgsel (dbgsel[7:0])); + // Outputs + .dout1 (dout1[7:0]), + // Inputs + .rstn (rstn), + .clk (clk), + .dval1 (dval1[7:0]), + .dbgsel (dbgsel[7:0])); endmodule @@ -82,16 +82,16 @@ module sub0 input [7:0] dbgsel; output reg [7:0] dout0; - reg [7:0] dbgsel_d1r; + reg [7:0] dbgsel_d1r; always_comb begin // verilator lint_off WIDTH if (((dbgsel_d1r >= 34) && (dbgsel_d1r < 65))) begin - // verilator lint_on WIDTH - dout0 = dval1; + // verilator lint_on WIDTH + dout0 = dval1; end else begin - dout0 = 0; + dout0 = 0; end end @@ -118,19 +118,19 @@ module sub1 input rstn; input clk; input [7:0] dval1; - input [7:0] dbgsel; + input [7:0] dbgsel; output reg [7:0] dout1; - reg [7:0] dbgsel_d1r; + reg [7:0] dbgsel_d1r; always_comb begin // verilator lint_off WIDTH if (((dbgsel_d1r >= 334) && (dbgsel_d1r < 365))) begin - // verilator lint_on WIDTH - dout1 = dval1; + // verilator lint_on WIDTH + dout1 = dval1; end else begin - dout1 = 0; + dout1 = 0; end end diff --git a/test_regress/t/t_var_overzero.v b/test_regress/t/t_var_overzero.v index f2e6ed040..dbff3598c 100644 --- a/test_regress/t/t_var_overzero.v +++ b/test_regress/t/t_var_overzero.v @@ -20,14 +20,14 @@ module t (/*AUTOARG*/ wire [7:0] dbgsel_w = '0; tsub tsub (/*AUTOINST*/ - // Outputs - .dout (dout[7:0]), - // Inputs - .clk (clk), - .rstn (rstn), - .dval0 (dval0[7:0]), - .dval1 (dval1[7:0]), - .dbgsel_w (dbgsel_w[7:0])); + // Outputs + .dout (dout[7:0]), + // Inputs + .clk (clk), + .rstn (rstn), + .dval0 (dval0[7:0]), + .dval1 (dval1[7:0]), + .dbgsel_w (dbgsel_w[7:0])); endmodule @@ -45,12 +45,12 @@ module tsub (/*AUTOARG*/ input [7:0] dbgsel_w; output [7:0] dout; - wire [7:0] dout = dout0 | dout1; + wire [7:0] dout = dout0 | dout1; /*AUTOWIRE*/ // Beginning of automatic wires (for undeclared instantiated-module outputs) - wire [7:0] dout0; // From sub0 of sub0.v - wire [7:0] dout1; // From sub1 of sub1.v + wire [7:0] dout0; // From sub0 of sub0.v + wire [7:0] dout1; // From sub1 of sub1.v // End of automatics initial begin @@ -58,7 +58,7 @@ module tsub (/*AUTOARG*/ $finish; end - reg [7:0] dbgsel_msk; + reg [7:0] dbgsel_msk; always_comb begin reg [7:0] mask; mask = 8'hff; @@ -67,7 +67,7 @@ module tsub (/*AUTOARG*/ // TODO this should optimize away, but presently does not because // V3Gate constifies then doesn't see all other input edges have disappeared - reg [7:0] dbgsel; + reg [7:0] dbgsel; always @(posedge clk) begin if ((rstn == 0)) begin dbgsel <= 0; @@ -78,21 +78,21 @@ module tsub (/*AUTOARG*/ end sub0 sub0 (/*AUTOINST*/ - // Outputs - .dout0 (dout0[7:0]), - // Inputs - .rstn (rstn), - .clk (clk), - .dval0 (dval0[7:0]), - .dbgsel (dbgsel[7:0])); + // Outputs + .dout0 (dout0[7:0]), + // Inputs + .rstn (rstn), + .clk (clk), + .dval0 (dval0[7:0]), + .dbgsel (dbgsel[7:0])); sub1 sub1 (/*AUTOINST*/ - // Outputs - .dout1 (dout1[7:0]), - // Inputs - .rstn (rstn), - .clk (clk), - .dval1 (dval1[7:0]), - .dbgsel (dbgsel[7:0])); + // Outputs + .dout1 (dout1[7:0]), + // Inputs + .rstn (rstn), + .clk (clk), + .dval1 (dval1[7:0]), + .dbgsel (dbgsel[7:0])); endmodule @@ -111,16 +111,16 @@ module sub0 input [7:0] dbgsel; output reg [7:0] dout0; - reg [7:0] dbgsel_d1r; + reg [7:0] dbgsel_d1r; always_comb begin // verilator lint_off WIDTH if (((dbgsel_d1r >= 34) && (dbgsel_d1r < 65))) begin - // verilator lint_on WIDTH - dout0 = dval0; + // verilator lint_on WIDTH + dout0 = dval0; end else begin - dout0 = 0; + dout0 = 0; end end @@ -147,17 +147,17 @@ module sub1 input rstn; input clk; input [7:0] dval1; - input [7:0] dbgsel; + input [7:0] dbgsel; output reg [7:0] dout1; - reg [7:0] dbgsel_d1r; + reg [7:0] dbgsel_d1r; always_comb begin if (((dbgsel_d1r >= 84) && (dbgsel_d1r < 95))) begin - dout1 = dval1; + dout1 = dval1; end else begin - dout1 = 0; + dout1 = 0; end end diff --git a/test_regress/t/t_var_pinsizes.v b/test_regress/t/t_var_pinsizes.v index 22ac179cc..d0e9e26bc 100644 --- a/test_regress/t/t_var_pinsizes.v +++ b/test_regress/t/t_var_pinsizes.v @@ -16,18 +16,18 @@ module t (/*AUTOARG*/ input clk; - input i1; - input [7:0] i8; - input [15:0] i16; - input [31:0] i32; - input [63:0] i64; - input [64:0] i65; + input i1; + input [7:0] i8; + input [15:0] i16; + input [31:0] i32; + input [63:0] i64; + input [64:0] i65; input [127:0] i128; input [512:0] i513; - input i1a2 [1:0]; + input i1a2 [1:0]; input [93:0] i94a3 [2:0]; - output logic o1; + output logic o1; output logic [7:0] o8; output logic [15:0] o16; output logic [31:0] o32; @@ -35,10 +35,10 @@ module t (/*AUTOARG*/ output logic [64:0] o65; output logic [127:0] o128; output logic [512:0] o513; - output logic o1a2 [1:0]; + output logic o1a2 [1:0]; output logic [93:0] o94a3 [2:0]; - input [0:0] ibv1 /*verilator sc_bv*/; + input [0:0] ibv1 /*verilator sc_bv*/; input [15:0] ibv16 /*verilator sc_bv*/; input [0:0] ibv1_vlt; input [15:0] ibv16_vlt; diff --git a/test_regress/t/t_var_rsvd.v b/test_regress/t/t_var_rsvd.v index e006ff85c..aa3e53a2c 100644 --- a/test_regress/t/t_var_rsvd.v +++ b/test_regress/t/t_var_rsvd.v @@ -11,13 +11,13 @@ module t (/*AUTOARG*/ bool ); - input bool; // BAD + input bool; // BAD - reg vector; // OK, as not public - reg switch /*verilator public*/; // Bad + reg vector; // OK, as not public + reg switch /*verilator public*/; // Bad typedef struct packed { - logic [31:0] vector; // OK, as not public + logic [31:0] vector; // OK, as not public } test; test t; diff --git a/test_regress/t/t_var_tieout.v b/test_regress/t/t_var_tieout.v index 17ecee2e4..96855d921 100644 --- a/test_regress/t/t_var_tieout.v +++ b/test_regress/t/t_var_tieout.v @@ -13,17 +13,17 @@ module t (/*AUTOARG*/ integer out18; /*AUTOWIRE*/ // Beginning of automatic wires (for undeclared instantiated-module outputs) - wire out1; // From test of Test.v - wire out19; // From test of Test.v - wire out1b; // From test of Test.v + wire out1; // From test of Test.v + wire out19; // From test of Test.v + wire out1b; // From test of Test.v // End of automatics Test test (/*AUTOINST*/ - // Outputs - .out1 (out1), - .out18 (out18), - .out1b (out1b), - .out19 (out19)); + // Outputs + .out1 (out1), + .out18 (out18), + .out1b (out1b), + .out19 (out19)); // Test loop always @ (posedge clk) begin @@ -38,9 +38,9 @@ module t (/*AUTOARG*/ endmodule module Test ( - output wire out1 = 1'b1, - output integer out18 = 32'h18, - output var out1b = 1'b1, - output var logic out19 = 1'b1 - ); + output wire out1 = 1'b1, + output integer out18 = 32'h18, + output var out1b = 1'b1, + output var logic out19 = 1'b1 + ); endmodule diff --git a/test_regress/t/t_var_types.v b/test_regress/t/t_var_types.v index 273ad4691..cde93080b 100644 --- a/test_regress/t/t_var_types.v +++ b/test_regress/t/t_var_types.v @@ -7,87 +7,87 @@ module t (/*AUTOARG*/); // IEEE: integer_atom_type - byte d_byte; - shortint d_shortint; - int d_int; - longint d_longint; - integer d_integer; - time d_time; - chandle d_chandle; + byte d_byte; + shortint d_shortint; + int d_int; + longint d_longint; + integer d_integer; + time d_time; + chandle d_chandle; // IEEE: integer_atom_type - bit d_bit; - logic d_logic; - reg d_reg; + bit d_bit; + logic d_logic; + reg d_reg; - bit [1:0] d_bit2; - logic [1:0] d_logic2; - reg [1:0] d_reg2; + bit [1:0] d_bit2; + logic [1:0] d_logic2; + reg [1:0] d_reg2; // IEEE: non_integer_type - //UNSUP shortreal d_shortreal; - real d_real; - realtime d_realtime; + //UNSUP shortreal d_shortreal; + real d_real; + realtime d_realtime; // Declarations using var - var byte v_b; + var byte v_b; `ifndef VCS - var [2:0] v_b3; + var [2:0] v_b3; var signed [2:0] v_bs; `endif // verilator lint_off WIDTH - localparam p_implicit = {96{1'b1}}; - localparam [89:0] p_explicit = {96{1'b1}}; - localparam byte p_byte = {96{1'b1}}; - localparam shortint p_shortint = {96{1'b1}}; - localparam int p_int = {96{1'b1}}; - localparam longint p_longint = {96{1'b1}}; - localparam integer p_integer = {96{1'b1}}; - localparam reg p_reg = {96{1'b1}}; - localparam bit p_bit = {96{1'b1}}; - localparam logic p_logic = {96{1'b1}}; - localparam reg [0:0] p_reg1 = {96{1'b1}}; - localparam bit [0:0] p_bit1 = {96{1'b1}}; + localparam p_implicit = {96{1'b1}}; + localparam [89:0] p_explicit = {96{1'b1}}; + localparam byte p_byte = {96{1'b1}}; + localparam shortint p_shortint = {96{1'b1}}; + localparam int p_int = {96{1'b1}}; + localparam longint p_longint = {96{1'b1}}; + localparam integer p_integer = {96{1'b1}}; + localparam reg p_reg = {96{1'b1}}; + localparam bit p_bit = {96{1'b1}}; + localparam logic p_logic = {96{1'b1}}; + localparam reg [0:0] p_reg1 = {96{1'b1}}; + localparam bit [0:0] p_bit1 = {96{1'b1}}; localparam logic [0:0] p_logic1= {96{1'b1}}; - localparam reg [1:0] p_reg2 = {96{1'b1}}; - localparam bit [1:0] p_bit2 = {96{1'b1}}; + localparam reg [1:0] p_reg2 = {96{1'b1}}; + localparam bit [1:0] p_bit2 = {96{1'b1}}; localparam logic [1:0] p_logic2= {96{1'b1}}; // verilator lint_on WIDTH - byte v_byte[2]; - shortint v_shortint[2]; - int v_int[2]; - longint v_longint[2]; - integer v_integer[2]; - time v_time[2]; - chandle v_chandle[2]; - bit v_bit[2]; - logic v_logic[2]; - reg v_reg[2]; - real v_real[2]; - realtime v_realtime[2]; + byte v_byte[2]; + shortint v_shortint[2]; + int v_int[2]; + longint v_longint[2]; + integer v_integer[2]; + time v_time[2]; + chandle v_chandle[2]; + bit v_bit[2]; + logic v_logic[2]; + reg v_reg[2]; + real v_real[2]; + realtime v_realtime[2]; // We do this in two steps so we can check that initialization inside functions works properly // verilator lint_off WIDTH - function f_implicit; reg lv_implicit; f_implicit = lv_implicit; endfunction - function [89:0] f_explicit; reg [89:0] lv_explicit; f_explicit = lv_explicit; endfunction - function byte f_byte; byte lv_byte; f_byte = lv_byte; endfunction - function shortint f_shortint; shortint lv_shortint; f_shortint = lv_shortint; endfunction - function int f_int; int lv_int; f_int = lv_int; endfunction - function longint f_longint; longint lv_longint; f_longint = lv_longint; endfunction - function integer f_integer; integer lv_integer; f_integer = lv_integer; endfunction - function reg f_reg; reg lv_reg; f_reg = lv_reg; endfunction - function bit f_bit; bit lv_bit; f_bit = lv_bit; endfunction - function logic f_logic; logic lv_logic; f_logic = lv_logic; endfunction - function reg [0:0] f_reg1; reg [0:0] lv_reg1; f_reg1 = lv_reg1; endfunction - function bit [0:0] f_bit1; bit [0:0] lv_bit1; f_bit1 = lv_bit1; endfunction - function logic [0:0] f_logic1; logic [0:0] lv_logic1; f_logic1 = lv_logic1; endfunction - function reg [1:0] f_reg2; reg [1:0] lv_reg2; f_reg2 = lv_reg2; endfunction - function bit [1:0] f_bit2; bit [1:0] lv_bit2; f_bit2 = lv_bit2; endfunction - function logic [1:0] f_logic2; logic [1:0] lv_logic2; f_logic2 = lv_logic2; endfunction - function time f_time; time lv_time; f_time = lv_time; endfunction - function chandle f_chandle; chandle lv_chandle; f_chandle = lv_chandle; endfunction + function f_implicit; reg lv_implicit; f_implicit = lv_implicit; endfunction + function [89:0] f_explicit; reg [89:0] lv_explicit; f_explicit = lv_explicit; endfunction + function byte f_byte; byte lv_byte; f_byte = lv_byte; endfunction + function shortint f_shortint; shortint lv_shortint; f_shortint = lv_shortint; endfunction + function int f_int; int lv_int; f_int = lv_int; endfunction + function longint f_longint; longint lv_longint; f_longint = lv_longint; endfunction + function integer f_integer; integer lv_integer; f_integer = lv_integer; endfunction + function reg f_reg; reg lv_reg; f_reg = lv_reg; endfunction + function bit f_bit; bit lv_bit; f_bit = lv_bit; endfunction + function logic f_logic; logic lv_logic; f_logic = lv_logic; endfunction + function reg [0:0] f_reg1; reg [0:0] lv_reg1; f_reg1 = lv_reg1; endfunction + function bit [0:0] f_bit1; bit [0:0] lv_bit1; f_bit1 = lv_bit1; endfunction + function logic [0:0] f_logic1; logic [0:0] lv_logic1; f_logic1 = lv_logic1; endfunction + function reg [1:0] f_reg2; reg [1:0] lv_reg2; f_reg2 = lv_reg2; endfunction + function bit [1:0] f_bit2; bit [1:0] lv_bit2; f_bit2 = lv_bit2; endfunction + function logic [1:0] f_logic2; logic [1:0] lv_logic2; f_logic2 = lv_logic2; endfunction + function time f_time; time lv_time; f_time = lv_time; endfunction + function chandle f_chandle; chandle lv_chandle; f_chandle = lv_chandle; endfunction // verilator lint_on WIDTH `ifdef verilator @@ -101,30 +101,30 @@ module t (/*AUTOARG*/); `define CHECK_ALL(name,nbits,issigned,twostate,zeroinit) \ if (zeroinit ? ((name & 1'b1)!==1'b0) : ((name & 1'b1)!==`XINIT)) \ - begin $display("%%Error: Bad zero/X init for %s: %b",`"name`",name); $stop; end \ + begin $display("%%Error: Bad zero/X init for %s: %b",`"name`",name); $stop; end \ name = {96{1'b1}}; \ if (name !== {(nbits){1'b1}}) begin $display("%%Error: Bad size for %s",`"name`"); $stop; end \ if (issigned ? (name > 0) : (name < 0)) begin $display("%%Error: Bad signed for %s",`"name`"); $stop; end \ name = {96{1'bx}}; \ if (name !== {(nbits){`ALL_TWOSTATE ? `XINIT : (twostate ? 1'b0 : `XINIT)}}) \ - begin $display("%%Error: Bad twostate for %s: %b",`"name`",name); $stop; end \ + begin $display("%%Error: Bad twostate for %s: %b",`"name`",name); $stop; end \ initial begin // verilator lint_off WIDTH // verilator lint_off UNSIGNED // name b sign twost 0init - `CHECK_ALL(d_byte ,8 ,1'b1,1'b1,1'b1); - `CHECK_ALL(d_shortint ,16,1'b1,1'b1,1'b1); - `CHECK_ALL(d_int ,32,1'b1,1'b1,1'b1); - `CHECK_ALL(d_longint ,64,1'b1,1'b1,1'b1); - `CHECK_ALL(d_integer ,32,1'b1,1'b0,1'b0); - `CHECK_ALL(d_time ,64,1'b0,1'b0,1'b0); - `CHECK_ALL(d_bit ,1 ,1'b0,1'b1,1'b1); - `CHECK_ALL(d_logic ,1 ,1'b0,1'b0,1'b0); - `CHECK_ALL(d_reg ,1 ,1'b0,1'b0,1'b0); - `CHECK_ALL(d_bit2 ,2 ,1'b0,1'b1,1'b1); - `CHECK_ALL(d_logic2 ,2 ,1'b0,1'b0,1'b0); - `CHECK_ALL(d_reg2 ,2 ,1'b0,1'b0,1'b0); + `CHECK_ALL(d_byte ,8 ,1'b1,1'b1,1'b1); + `CHECK_ALL(d_shortint ,16,1'b1,1'b1,1'b1); + `CHECK_ALL(d_int ,32,1'b1,1'b1,1'b1); + `CHECK_ALL(d_longint ,64,1'b1,1'b1,1'b1); + `CHECK_ALL(d_integer ,32,1'b1,1'b0,1'b0); + `CHECK_ALL(d_time ,64,1'b0,1'b0,1'b0); + `CHECK_ALL(d_bit ,1 ,1'b0,1'b1,1'b1); + `CHECK_ALL(d_logic ,1 ,1'b0,1'b0,1'b0); + `CHECK_ALL(d_reg ,1 ,1'b0,1'b0,1'b0); + `CHECK_ALL(d_bit2 ,2 ,1'b0,1'b1,1'b1); + `CHECK_ALL(d_logic2 ,2 ,1'b0,1'b0,1'b0); + `CHECK_ALL(d_reg2 ,2 ,1'b0,1'b0,1'b0); // verilator lint_on WIDTH // verilator lint_on UNSIGNED @@ -137,80 +137,80 @@ module t (/*AUTOARG*/); if (name !== {(nbits){1'b1}}) begin $display("%%Error: Bad size for %s",`"name`"); $stop; end \ // name b - `CHECK_P(p_implicit ,96); - `CHECK_P(p_implicit[0] ,1 ); - `CHECK_P(p_explicit ,90); - `CHECK_P(p_explicit[0] ,1 ); - `CHECK_P(p_byte ,8 ); - `CHECK_P(p_byte[0] ,1 ); - `CHECK_P(p_shortint ,16); - `CHECK_P(p_shortint[0] ,1 ); - `CHECK_P(p_int ,32); - `CHECK_P(p_int[0] ,1 ); - `CHECK_P(p_longint ,64); - `CHECK_P(p_longint[0] ,1 ); - `CHECK_P(p_integer ,32); - `CHECK_P(p_integer[0] ,1 ); - `CHECK_P(p_bit ,1 ); - `CHECK_P(p_logic ,1 ); - `CHECK_P(p_reg ,1 ); - `CHECK_P(p_bit1 ,1 ); - `CHECK_P(p_logic1 ,1 ); - `CHECK_P(p_reg1 ,1 ); - `CHECK_P(p_bit1[0] ,1 ); - `CHECK_P(p_logic1[0] ,1 ); - `CHECK_P(p_reg1[0] ,1 ); - `CHECK_P(p_bit2 ,2 ); - `CHECK_P(p_logic2 ,2 ); - `CHECK_P(p_reg2 ,2 ); + `CHECK_P(p_implicit ,96); + `CHECK_P(p_implicit[0] ,1 ); + `CHECK_P(p_explicit ,90); + `CHECK_P(p_explicit[0] ,1 ); + `CHECK_P(p_byte ,8 ); + `CHECK_P(p_byte[0] ,1 ); + `CHECK_P(p_shortint ,16); + `CHECK_P(p_shortint[0] ,1 ); + `CHECK_P(p_int ,32); + `CHECK_P(p_int[0] ,1 ); + `CHECK_P(p_longint ,64); + `CHECK_P(p_longint[0] ,1 ); + `CHECK_P(p_integer ,32); + `CHECK_P(p_integer[0] ,1 ); + `CHECK_P(p_bit ,1 ); + `CHECK_P(p_logic ,1 ); + `CHECK_P(p_reg ,1 ); + `CHECK_P(p_bit1 ,1 ); + `CHECK_P(p_logic1 ,1 ); + `CHECK_P(p_reg1 ,1 ); + `CHECK_P(p_bit1[0] ,1 ); + `CHECK_P(p_logic1[0] ,1 ); + `CHECK_P(p_reg1[0] ,1 ); + `CHECK_P(p_bit2 ,2 ); + `CHECK_P(p_logic2 ,2 ); + `CHECK_P(p_reg2 ,2 ); `define CHECK_B(varname,nbits) \ if ($bits(varname) !== nbits) begin $display("%%Error: Bad size for %s",`"varname`"); $stop; end \ - `CHECK_B(v_byte[1] ,8 ); - `CHECK_B(v_shortint[1] ,16); - `CHECK_B(v_int[1] ,32); - `CHECK_B(v_longint[1] ,64); - `CHECK_B(v_integer[1] ,32); - `CHECK_B(v_time[1] ,64); + `CHECK_B(v_byte[1] ,8 ); + `CHECK_B(v_shortint[1] ,16); + `CHECK_B(v_int[1] ,32); + `CHECK_B(v_longint[1] ,64); + `CHECK_B(v_integer[1] ,32); + `CHECK_B(v_time[1] ,64); //`CHECK_B(v_chandle[1] - `CHECK_B(v_bit[1] ,1 ); - `CHECK_B(v_logic[1] ,1 ); - `CHECK_B(v_reg[1] ,1 ); - //`CHECK_B(v_real[1] ,64); // $bits not allowed - //`CHECK_B(v_realtime[1] ,64); // $bits not allowed + `CHECK_B(v_bit[1] ,1 ); + `CHECK_B(v_logic[1] ,1 ); + `CHECK_B(v_reg[1] ,1 ); + //`CHECK_B(v_real[1] ,64); // $bits not allowed + //`CHECK_B(v_realtime[1] ,64); // $bits not allowed `define CHECK_F(fname,nbits,zeroinit) \ if ($bits(fname()) !== nbits) begin $display("%%Error: Bad size for %s",`"fname`"); $stop; end \ // name b 0init - `CHECK_F(f_implicit ,1 ,1'b0); // Note 1 bit, not 96 - `CHECK_F(f_explicit ,90,1'b0); - `CHECK_F(f_byte ,8 ,1'b1); - `CHECK_F(f_shortint ,16,1'b1); - `CHECK_F(f_int ,32,1'b1); - `CHECK_F(f_longint ,64,1'b1); - `CHECK_F(f_integer ,32,1'b0); - `CHECK_F(f_time ,64,1'b0); + `CHECK_F(f_implicit ,1 ,1'b0); // Note 1 bit, not 96 + `CHECK_F(f_explicit ,90,1'b0); + `CHECK_F(f_byte ,8 ,1'b1); + `CHECK_F(f_shortint ,16,1'b1); + `CHECK_F(f_int ,32,1'b1); + `CHECK_F(f_longint ,64,1'b1); + `CHECK_F(f_integer ,32,1'b0); + `CHECK_F(f_time ,64,1'b0); `ifdef VERILATOR // else indeterminate - `CHECK_F(f_chandle ,64,1'b0); + `CHECK_F(f_chandle ,64,1'b0); `endif - `CHECK_F(f_bit ,1 ,1'b1); - `CHECK_F(f_logic ,1 ,1'b0); - `CHECK_F(f_reg ,1 ,1'b0); - `CHECK_F(f_bit1 ,1 ,1'b1); - `CHECK_F(f_logic1 ,1 ,1'b0); - `CHECK_F(f_reg1 ,1 ,1'b0); - `CHECK_F(f_bit2 ,2 ,1'b1); - `CHECK_F(f_logic2 ,2 ,1'b0); - `CHECK_F(f_reg2 ,2 ,1'b0); + `CHECK_F(f_bit ,1 ,1'b1); + `CHECK_F(f_logic ,1 ,1'b0); + `CHECK_F(f_reg ,1 ,1'b0); + `CHECK_F(f_bit1 ,1 ,1'b1); + `CHECK_F(f_logic1 ,1 ,1'b0); + `CHECK_F(f_reg1 ,1 ,1'b0); + `CHECK_F(f_bit2 ,2 ,1'b1); + `CHECK_F(f_logic2 ,2 ,1'b0); + `CHECK_F(f_reg2 ,2 ,1'b0); // For unpacked types we don't want width warnings for unsized numbers that fit - d_byte = 2; + d_byte = 2; d_shortint= 2; - d_int = 2; - d_longint = 2; - d_integer = 2; + d_int = 2; + d_longint = 2; + d_integer = 2; // Special check d_time = $time; diff --git a/test_regress/t/t_var_xref_gen.v b/test_regress/t/t_var_xref_gen.v index cb01b3375..bff5037a9 100644 --- a/test_regress/t/t_var_xref_gen.v +++ b/test_regress/t/t_var_xref_gen.v @@ -8,9 +8,9 @@ // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ - // Inputs - clk, addr, res - ); + // Inputs + clk, addr, res + ); input clk; @@ -33,7 +33,7 @@ module memory(addr, dout); output [15:0] dout; generate - genvar g_cx; + genvar g_cx; for (g_cx = 0; g_cx < CM_NUMXROWS; g_cx++) begin: cxrow_inst reg [15:0] cmem_xrow[0:CM_XROWSIZE - 1]; diff --git a/test_regress/t/t_vpi_get.v b/test_regress/t/t_vpi_get.v index b52f87282..ec1fbc4d4 100644 --- a/test_regress/t/t_vpi_get.v +++ b/test_regress/t/t_vpi_get.v @@ -54,7 +54,7 @@ extern "C" int mon_check(); `ifdef IVERILOG // stop icarus optimizing signals away - wire redundant = onebit | onetwo[1] | twoone | fourthreetwoone[3] | twobytwo; + wire redundant = onebit | onetwo[1] | twoone | fourthreetwoone[3] | twobytwo; `endif wire subin `PUBLIC_FLAT_RD; @@ -74,8 +74,8 @@ extern "C" int mon_check(); status = mon_check(); `endif if (status!=0) begin - $write("%%Error: t_vpi_get.cpp:%0d: C Test failed\n", status); - $stop; + $write("%%Error: t_vpi_get.cpp:%0d: C Test failed\n", status); + $stop; end $write("*-* All Finished *-*\n"); $finish; diff --git a/test_regress/t/t_vpi_memory.v b/test_regress/t/t_vpi_memory.v index ee99b1319..11696d6f6 100644 --- a/test_regress/t/t_vpi_memory.v +++ b/test_regress/t/t_vpi_memory.v @@ -31,13 +31,13 @@ extern "C" int mon_check(); reg [16:1] [30:0] memp31 /*verilator public_flat_rw @(posedge clk) */; reg [15:1] [32:0] memp33 /*verilator public_flat_rw @(posedge clk) */; word_t [16:1] memw /*verilator public_flat_rw @(posedge clk) */; - integer i, status; + integer i, status; `define CHECK_MEM(mem, words) \ for (i = words; i > 0; i--) \ - if (integer'(mem[i]) !== i) begin \ + if (integer'(mem[i]) !== i) begin \ $write("%%Error: %s[%d] : GOT = %d EXP = %d\n", `"mem`", i, mem[i], i); \ - status = -1; \ + status = -1; \ end // Test loop @@ -51,8 +51,8 @@ extern "C" int mon_check(); status = mon_check(); `endif if (status!=0) begin - $write("%%Error: t_vpi_memory.cpp: C Test failed (rc=%0d)\n", status); - $stop; + $write("%%Error: t_vpi_memory.cpp: C Test failed (rc=%0d)\n", status); + $stop; end `CHECK_MEM(mem0, 16) `CHECK_MEM(memp32, 16) @@ -60,8 +60,8 @@ extern "C" int mon_check(); `CHECK_MEM(memp33, 15) `CHECK_MEM(memw, 16) if (status!=0) begin - $write("%%Error: Verilog memory checks failed\n"); - $stop; + $write("%%Error: Verilog memory checks failed\n"); + $stop; end $write("*-* All Finished *-*\n"); $finish; diff --git a/test_regress/t/t_vpi_unimpl.v b/test_regress/t/t_vpi_unimpl.v index ffad82c75..464fd9f3c 100644 --- a/test_regress/t/t_vpi_unimpl.v +++ b/test_regress/t/t_vpi_unimpl.v @@ -25,9 +25,9 @@ extern "C" int mon_check(); input clk; - reg onebit /*verilator public_flat_rw @(posedge clk) */; + reg onebit /*verilator public_flat_rw @(posedge clk) */; - integer status; + integer status; // Test loop initial begin diff --git a/test_regress/t/t_vpi_var.v b/test_regress/t/t_vpi_var.v index ea2345b87..672f987fc 100644 --- a/test_regress/t/t_vpi_var.v +++ b/test_regress/t/t_vpi_var.v @@ -25,24 +25,24 @@ extern "C" int mon_check(); input clk; - reg onebit /*verilator public_flat_rw @(posedge clk) */; - reg [2:1] twoone /*verilator public_flat_rw @(posedge clk) */; - reg [2:1] fourthreetwoone[4:3] /*verilator public_flat_rw @(posedge clk) */; + reg onebit /*verilator public_flat_rw @(posedge clk) */; + reg [2:1] twoone /*verilator public_flat_rw @(posedge clk) */; + reg [2:1] fourthreetwoone[4:3] /*verilator public_flat_rw @(posedge clk) */; // verilator lint_off LITENDIAN - reg [0:61] quads[2:3] /*verilator public_flat_rw @(posedge clk) */; + reg [0:61] quads[2:3] /*verilator public_flat_rw @(posedge clk) */; // verilator lint_on LITENDIAN - reg [31:0] count /*verilator public_flat_rd */; - reg [31:0] half_count /*verilator public_flat_rd */; + reg [31:0] count /*verilator public_flat_rd */; + reg [31:0] half_count /*verilator public_flat_rd */; - reg [7:0] text_byte /*verilator public_flat_rw @(posedge clk) */; - reg [15:0] text_half /*verilator public_flat_rw @(posedge clk) */; - reg [31:0] text_word /*verilator public_flat_rw @(posedge clk) */; - reg [63:0] text_long /*verilator public_flat_rw @(posedge clk) */; - reg [511:0] text /*verilator public_flat_rw @(posedge clk) */; + reg [7:0] text_byte /*verilator public_flat_rw @(posedge clk) */; + reg [15:0] text_half /*verilator public_flat_rw @(posedge clk) */; + reg [31:0] text_word /*verilator public_flat_rw @(posedge clk) */; + reg [63:0] text_long /*verilator public_flat_rw @(posedge clk) */; + reg [511:0] text /*verilator public_flat_rw @(posedge clk) */; - integer status; + integer status; sub sub(); @@ -66,8 +66,8 @@ extern "C" int mon_check(); status = mon_check(); `endif if (status!=0) begin - $write("%%Error: t_vpi_var.cpp:%0d: C Test failed\n", status); - $stop; + $write("%%Error: t_vpi_var.cpp:%0d: C Test failed\n", status); + $stop; end $write("%%Info: Checking results\n"); if (onebit != 1'b1) $stop; @@ -83,11 +83,11 @@ extern "C" int mon_check(); always @(posedge clk) begin count <= count + 2; if (count[1]) - half_count <= half_count + 2; + half_count <= half_count + 2; if (count == 1000) begin - $write("*-* All Finished *-*\n"); - $finish; + $write("*-* All Finished *-*\n"); + $finish; end end @@ -115,7 +115,7 @@ module arr; reg [LENGTH-1:0] sig /*verilator public_flat_rw*/; reg [LENGTH-1:0] rfr /*verilator public_flat_rw*/; - reg check /*verilator public_flat_rw*/; + reg check /*verilator public_flat_rw*/; reg verbose /*verilator public_flat_rw*/; initial begin diff --git a/test_regress/t/t_wire_types.v b/test_regress/t/t_wire_types.v index fb67e7a7b..564d096e1 100644 --- a/test_regress/t/t_wire_types.v +++ b/test_regress/t/t_wire_types.v @@ -14,22 +14,22 @@ module t (/*AUTOARG*/ `define checkr(gotv,expv) do if ((gotv) != (expv)) begin $write("%%Error: %s:%0d: got=%f exp=%f\n", `__FILE__,`__LINE__, (gotv), (expv)); $stop; end while(0); // IEEE: integer_atom_type - wire byte w_byte; + wire byte w_byte; wire shortint w_shortint; - wire int w_int; - wire longint w_longint; - wire integer w_integer; + wire int w_int; + wire longint w_longint; + wire integer w_integer; // IEEE: integer_atom_type - wire bit w_bit; - wire logic w_logic; + wire bit w_bit; + wire logic w_logic; - wire bit [1:0] w_bit2; - wire logic [1:0] w_logic2; + wire bit [1:0] w_bit2; + wire logic [1:0] w_logic2; // IEEE: non_integer_type - //UNSUP shortreal w_shortreal; - wire real w_real; + //UNSUP shortreal w_shortreal; + wire real w_real; assign w_byte = 8'h12; assign w_shortint = 16'h1234; diff --git a/test_regress/t/t_xml_debugcheck.out b/test_regress/t/t_xml_debugcheck.out index 7ef8e07b3..839942936 100644 --- a/test_regress/t/t_xml_debugcheck.out +++ b/test_regress/t/t_xml_debugcheck.out @@ -23,20 +23,20 @@ - + - + - - - - - - + + + + + + @@ -57,9 +57,9 @@ - - - + + + @@ -69,113 +69,113 @@ - - - - + + + + - - - - + + + + - - + + - - - - + + + + - + - - - + + + - + - - - - + + + + - - - - + + + + - - - + + + - - - - + + + + - + - - - - + + + + - - - - + + + + - - - + + + - - - - + + + + - + - - - - + + + + - - - + + + - - - - + + + + @@ -183,18 +183,18 @@ - - - + + + - - - + + + - - - - + + + + @@ -202,82 +202,82 @@ - + - - - - + + + + - - - - + + + + - - - + + + - - - - + + + + - + - - - - + + + + - - - - + + + + - - - + + + - - - - + + + + - + - - - - + + + + - - - + + + - - - - + + + + @@ -285,18 +285,18 @@ - - - + + + - - - + + + - - - - + + + + @@ -304,12 +304,12 @@ - + - - - + + + @@ -319,113 +319,113 @@ - - - - + + + + - - - - + + + + - - + + - - - - + + + + - + - - - + + + - + - - - - + + + + - - - - + + + + - - - + + + - - - - + + + + - + - - - - + + + + - - - - + + + + - - - + + + - - - - + + + + - + - - - - + + + + - - - + + + - - - - + + + + @@ -433,18 +433,18 @@ - - - + + + - - - + + + - - - - + + + + @@ -452,82 +452,82 @@ - + - - - - + + + + - - - - + + + + - - - + + + - - - - + + + + - + - - - - + + + + - - - - + + + + - - - + + + - - - - + + + + - + - - - - + + + + - - - + + + - - - - + + + + @@ -535,18 +535,18 @@ - - - + + + - - - + + + - - - - + + + + @@ -554,12 +554,12 @@ - + - - - + + + @@ -569,113 +569,113 @@ - - - - + + + + - - - - + + + + - - + + - - - - + + + + - + - - - + + + - + - - - - + + + + - - - - + + + + - - - + + + - - - - + + + + - + - - - - + + + + - - - - + + + + - - - + + + - - - - + + + + - + - - - - + + + + - - - + + + - - - - + + + + @@ -683,18 +683,18 @@ - - - + + + - - - + + + - - - - + + + + @@ -702,82 +702,82 @@ - + - - - - + + + + - - - - + + + + - - - + + + - - - - + + + + - + - - - - + + + + - - - - + + + + - - - + + + - - - - + + + + - + - - - - + + + + - - - + + + - - - - + + + + @@ -785,18 +785,18 @@ - - - + + + - - - + + + - - - - + + + + @@ -804,12 +804,12 @@ - + - - - + + + @@ -819,10 +819,10 @@ - - + + - + @@ -837,18 +837,18 @@ - - - + + + - + - - - + + + @@ -1328,20 +1328,20 @@ - - - - + + + + - - - - + + + + - + @@ -1411,7 +1411,7 @@ - + @@ -1432,8 +1432,8 @@ - - + + @@ -1445,26 +1445,26 @@ - + - + - + - + - + - + @@ -1509,17 +1509,17 @@ - + - - + + - - + + - - + + @@ -1544,10 +1544,10 @@ - - + + - + diff --git a/test_regress/t/t_xml_tag.out b/test_regress/t/t_xml_tag.out index 71b99ee25..e2d426fd9 100644 --- a/test_regress/t/t_xml_tag.out +++ b/test_regress/t/t_xml_tag.out @@ -62,10 +62,10 @@ - - - - + + + + diff --git a/test_regress/t/t_xml_tag.v b/test_regress/t/t_xml_tag.v index 6b5a75fe9..736942cbf 100644 --- a/test_regress/t/t_xml_tag.v +++ b/test_regress/t/t_xml_tag.v @@ -18,10 +18,10 @@ module m // This is a comment typedef struct packed { - logic clk; /* verilator tag this is clk */ - logic k; /* verilator lint_off UNUSED */ - logic enable; // verilator tag enable - logic data; // verilator tag data + logic clk; /* verilator tag this is clk */ + logic k; /* verilator lint_off UNUSED */ + logic enable; // verilator tag enable + logic data; // verilator tag data } my_struct; // verilator tag my_struct // This is a comment From 99d39cb6ff022f38c401edec6272a1313217fd13 Mon Sep 17 00:00:00 2001 From: Wilson Snyder Date: Sun, 1 May 2022 10:43:04 -0400 Subject: [PATCH 41/44] Fix autoconf warning --- configure.ac | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/configure.ac b/configure.ac index 0be207f17..a983dc6d9 100644 --- a/configure.ac +++ b/configure.ac @@ -14,7 +14,7 @@ AC_INIT([Verilator],[4.221 devel], # and commit using "devel release" or "Version bump" message # Then 'make maintainer-dist' -AC_CONFIG_HEADER(src/config_build.h) +AC_CONFIG_HEADERS(src/config_build.h) AC_CONFIG_FILES(Makefile src/Makefile src/Makefile_obj include/verilated.mk include/verilated_config.h verilator.pc verilator-config.cmake verilator-config-version.cmake) # Version From 267315e7d468a9536008a808a97a5877933768d0 Mon Sep 17 00:00:00 2001 From: Wilson Snyder Date: Sun, 1 May 2022 22:01:30 -0400 Subject: [PATCH 42/44] Commentary: Update ChangeLog --- Changes | 7 ++++++- docs/guide/contributors.rst | 4 ++-- 2 files changed, 8 insertions(+), 3 deletions(-) diff --git a/Changes b/Changes index ad4f5463c..d0062cdd9 100644 --- a/Changes +++ b/Changes @@ -17,14 +17,19 @@ Verilator 4.221 devel * Deprecate 'vluint64_t' and similar types (#3255). * Raise error on assignment to const in initial blocks. [Geza Lore, Shunyao CAD] * Issue INITIALDLY/COMBDLY/BLKSEQ warnings consistent with Verilator execution. [Geza Lore, Shunyao CAD] +* Support LoongArch ISA multithreading (#3353) (#3354). [Xi Zhang] * Fix MSVC localtime_s (#3124). * Fix Bison 3.8.2 error (#3366). [elike-ypq] * Fix rare bug in -Oz (V3Localize) (#3286). [Geza Lore, Shunyao CAD] * Fix tracing interfaces inside interfaces (#3309). [Kevin Millis] * Fix filenames with dots overwriting debug .vpp files (#3373). -* Fix including VK_USER_OBJS in make library (#3370). [Julien Margetts] +* Fix including VK_USER_OBJS in make library (#3370) (#3382). [Julien Margetts] +* Fix hang in generate symbol references (#3391) (#3398). [Yoda Lee] +* Fix missing #include (#3392). [Aliaksei Chapyzhenka] * Fix crash in recursive module inlining (#3393). [david-sawatzke] * Fix --protect-ids mangling names of library methods. [Geza Lore, Shunyao CAD] +* Fix foreach segmentation fault (#3400). [Kamil Rakoczy] + Verilator 4.220 2022-03-12 ========================== diff --git a/docs/guide/contributors.rst b/docs/guide/contributors.rst index 54e5400e2..68b17d671 100644 --- a/docs/guide/contributors.rst +++ b/docs/guide/contributors.rst @@ -23,14 +23,14 @@ Contributors Many people have provided ideas and other assistance with Verilator. Verilator is receiving major development support from the `CHIPS Alliance -`_. +`_ and `Shunyao CAD `_. Previous major corporate sponsors of Verilator, by providing significant contributions of time or funds included include: Atmel Corporation, Cavium Inc., Compaq Corporation, Digital Equipment Corporation, Embecosm Ltd., Hicamp Systems, Intel Corporation, Mindspeed Technologies Inc., MicroTune Inc., picoChip Designs Ltd., Sun Microsystems Inc., Nauticus Networks Inc., -and SiCortex Inc. +SiCortex Inc, and Shunyao CAD. The people who have contributed major functionality are: Byron Bradley, Jeremy Bennett, Lane Brooks, John Coiner, Duane Galbi, Geza Lore, Todd From a2792785fe02e28de17dd74a7541accb990602b2 Mon Sep 17 00:00:00 2001 From: Geza Lore Date: Mon, 2 May 2022 09:42:12 +0100 Subject: [PATCH 43/44] Add V3GraphVertex::dotRank to add GraphViz ranks to graph dumps This is a simple debugging aid to allow constraining the graph layout via GraphViz rank directives. Note this is not related in any way to the vertex 'rank' attribute used by some of the graph algorithms. No functional change. --- src/V3Graph.cpp | 33 ++++++++++++++++++++++++++++++++- src/V3Graph.h | 1 + 2 files changed, 33 insertions(+), 1 deletion(-) diff --git a/src/V3Graph.cpp b/src/V3Graph.cpp index d47b786a6..1b5bc1ae4 100644 --- a/src/V3Graph.cpp +++ b/src/V3Graph.cpp @@ -23,6 +23,8 @@ #include #include +#include +#include #include int V3Graph::s_debug = 0; @@ -325,11 +327,19 @@ void V3Graph::dumpDotFile(const string& filename, bool colorAsSubgraph) const { *logp << "\t\t rankdir=" << dotRankDir() << "];\n"; // List of all possible subgraphs + // Collections of explicit ranks + std::unordered_set ranks; + std::unordered_multimap rankSets; std::multimap subgraphs; for (V3GraphVertex* vertexp = verticesBeginp(); vertexp; vertexp = vertexp->verticesNextp()) { const string vertexSubgraph = (colorAsSubgraph && vertexp->color()) ? cvtToStr(vertexp->color()) : ""; subgraphs.emplace(vertexSubgraph, vertexp); + const string& dotRank = vertexp->dotRank(); + if (!dotRank.empty()) { + ranks.emplace(dotRank); + rankSets.emplace(dotRank, vertexp); + } } // We use a map here, as we don't want to corrupt anything (userp) in the graph, @@ -346,7 +356,10 @@ void V3Graph::dumpDotFile(const string& filename, bool colorAsSubgraph) const { if (subgr != vertexSubgraph) { if (subgr != "") *logp << "\t};\n"; subgr = vertexSubgraph; - if (subgr != "") *logp << "\tsubgraph cluster_" << subgr << " {\n"; + if (subgr != "") { + *logp << "\tsubgraph cluster_" << subgr << " {\n"; + *logp << "\tlabel=\"" << subgr << "\"\n"; + } } if (subgr != "") *logp << "\t"; *logp << "\tn" << vertexp->dotName() << (n++) << "\t[fontsize=8 " @@ -382,6 +395,24 @@ void V3Graph::dumpDotFile(const string& filename, bool colorAsSubgraph) const { } } } + + // Print ranks + for (auto dotRank : ranks) { + *logp << "\t{ rank="; + if (dotRank != "sink" && dotRank != "source" && dotRank != "min" && dotRank != "max") { + *logp << "same"; + } else { + *logp << dotRank; + } + *logp << "; "; + auto bounds = rankSets.equal_range(dotRank); + for (auto it{bounds.first}; it != bounds.second; ++it) { + if (it != bounds.first) *logp << ", "; + *logp << 'n' << numMap[it->second] << ""; + } + *logp << " }\n"; + } + // Vertex::m_user end, now unused // Trailer diff --git a/src/V3Graph.h b/src/V3Graph.h index c8319f5a8..ae59fe4a4 100644 --- a/src/V3Graph.h +++ b/src/V3Graph.h @@ -218,6 +218,7 @@ public: virtual string dotShape() const { return ""; } virtual string dotStyle() const { return ""; } virtual string dotName() const { return ""; } + virtual string dotRank() const { return ""; } virtual uint32_t rankAdder() const { return 1; } virtual FileLine* fileline() const { return nullptr; } // nullptr for unknown virtual int sortCmp(const V3GraphVertex* rhsp) const { From aa86c777f4787db7d10fbbbb5019ed4d20a7fcfb Mon Sep 17 00:00:00 2001 From: Wilson Snyder Date: Mon, 2 May 2022 22:17:20 -0400 Subject: [PATCH 44/44] Version bump --- Changes | 2 +- configure.ac | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/Changes b/Changes index d0062cdd9..b1760a0d8 100644 --- a/Changes +++ b/Changes @@ -8,7 +8,7 @@ The changes in each Verilator version are described below. The contributors that suggested a given feature are shown in []. Thanks! -Verilator 4.221 devel +Verilator 4.222 2022-05-02 ========================== **Minor:** diff --git a/configure.ac b/configure.ac index a983dc6d9..5ec247c2a 100644 --- a/configure.ac +++ b/configure.ac @@ -7,7 +7,7 @@ #AC_INIT([Verilator],[#.### YYYY-MM-DD]) #AC_INIT([Verilator],[#.### devel]) -AC_INIT([Verilator],[4.221 devel], +AC_INIT([Verilator],[4.222 2022-05-02], [https://verilator.org], [verilator],[https://verilator.org]) # When releasing, also update header of Changes file