diff --git a/Changes b/Changes
index 42c0aefa2..a04e55c94 100644
--- a/Changes
+++ b/Changes
@@ -14,6 +14,8 @@ The contributors that suggested a given feature are shown in []. Thanks!
 
 ****  Add vpiTimeUnit and allow to specify time as string, bug1636. [Stefan Wallentowitz]
 
+****  Add error when `resetall inside module (IEEE 2017-22.3).
+
 ****  Fix little endian cell ranges, bug1631. [Julien Margetts]
 
 
diff --git a/src/verilog.l b/src/verilog.l
index cf321fb13..a4412d938 100644
--- a/src/verilog.l
+++ b/src/verilog.l
@@ -927,8 +927,8 @@ vnum    {vnum1}|{vnum2}|{vnum3}|{vnum4}|{vnum5}
   "`protect"                            { FL_FWD; FL_BRK; }
   "`remove_gatenames"                   { FL_FWD; FL_BRK; }  // Verilog-XL compatibility
   "`remove_netnames"                    { FL_FWD; FL_BRK; }  // Verilog-XL compatibility
-  "`resetall"                           { FL_FWD; PARSEP->fileline()->warnOn(V3ErrorCode::I_DEF_NETTYPE_WIRE, true);
-                                          FL_BRK; }  // Rest handled by preproc
+  "`resetall"                           { FL; PARSEP->fileline()->warnOn(V3ErrorCode::I_DEF_NETTYPE_WIRE, true);
+                                          return yaT_RESETALL; }  // Rest handled by preproc
   "`suppress_faults"                    { FL_FWD; FL_BRK; }  // Verilog-XL compatibility
   "`timescale"{ws}+[^\n\r]*             { FL_FWD; FL_BRK; }  // Verilog spec - not supported
   "`uselib"{ws}+[^\n\r]*                { FL_FWD; FL_BRK; }  // Verilog-XL compatibility
diff --git a/src/verilog.y b/src/verilog.y
index 84441eb0f..63958535f 100644
--- a/src/verilog.y
+++ b/src/verilog.y
@@ -287,6 +287,8 @@ class AstSenTree;
 %token<strp>		yaD_IGNORE	"${ignored-bbox-sys}"
 %token<strp>		yaD_DPI		"${dpi-sys}"
 
+%token<fl>		yaT_RESETALL	"`resetall"
+
 // <fl> is the fileline, abbreviated to shorten "$<fl>1" references
 %token<fl>		'!'
 %token<fl>		'#'
@@ -742,6 +744,7 @@ description:			// ==IEEE: description
        	|	bind_directive				{ if ($1) GRAMMARP->unitPackage($1->fileline())->addStmtp($1); }
 	//	unsupported	// IEEE: config_declaration
 	//			// Verilator only
+	|	yaT_RESETALL				{ }  // Else, under design, and illegal based on IEEE 22.3
 	|	vltItem					{ }
 	|	error					{ }
 	;
diff --git a/test_regress/t/t_lint_implicit_def_bad.out b/test_regress/t/t_lint_implicit_def_bad.out
index 9d3577db9..b9b0185e0 100644
--- a/test_regress/t/t_lint_implicit_def_bad.out
+++ b/test_regress/t/t_lint_implicit_def_bad.out
@@ -1,8 +1,8 @@
-%Warning-IMPLICIT: t/t_lint_implicit_def_bad.v:10: Signal definition not found, creating implicitly: 'imp_warn'
+%Warning-IMPLICIT: t/t_lint_implicit_def_bad.v:12: Signal definition not found, creating implicitly: 'imp_warn'
    assign imp_warn = 1'b1;
           ^~~~~~~~
                    ... Use "/* verilator lint_off IMPLICIT */" and lint_on around source to disable this message.
-%Error: t/t_lint_implicit_def_bad.v:15: Signal definition not found, and implicit disabled with `default_nettype: 'imp_err'
+%Error: t/t_lint_implicit_def_bad.v:17: Signal definition not found, and implicit disabled with `default_nettype: 'imp_err'
    assign imp_err = 1'b1;
           ^~~~~~~
 %Error: Exiting due to
diff --git a/test_regress/t/t_lint_implicit_def_bad.v b/test_regress/t/t_lint_implicit_def_bad.v
index 071ccbfd0..6dc14ca06 100644
--- a/test_regress/t/t_lint_implicit_def_bad.v
+++ b/test_regress/t/t_lint_implicit_def_bad.v
@@ -7,6 +7,8 @@ module t (a,z);
    input a;
    output z;
 
+   sub sub ();
+
    assign imp_warn = 1'b1;
    // verilator lint_off IMPLICIT
    assign imp_ok = 1'b1;
@@ -16,8 +18,10 @@ module t (a,z);
 
 `default_nettype wire
    assign imp_ok2 = 1'b1;
+endmodule
 
 `default_nettype none
 `resetall
+module sub;
    assign imp_ok3 = 1'b1;
 endmodule
diff --git a/test_regress/t/t_pp_pragma_bad.out b/test_regress/t/t_pp_pragma_bad.out
index 3d4e7490b..2af125eaa 100644
--- a/test_regress/t/t_pp_pragma_bad.out
+++ b/test_regress/t/t_pp_pragma_bad.out
@@ -1,4 +1,7 @@
 %Error: t/t_pp_pragma_bad.v:6: `pragma is missing a pragma_expression.
 `pragma
 ^~~~~~~
-%Error: Exiting due to
+%Error: t/t_pp_pragma_bad.v:10: syntax error, unexpected `resetall
+`resetall   
+^~~~~~~~~
+%Error: Cannot continue
diff --git a/test_regress/t/t_pp_pragma_bad.v b/test_regress/t/t_pp_pragma_bad.v
index 2abfe64b7..1ffa7be9b 100644
--- a/test_regress/t/t_pp_pragma_bad.v
+++ b/test_regress/t/t_pp_pragma_bad.v
@@ -4,3 +4,9 @@
 // without warranty, 2019 by Wilson Snyder.
 
 `pragma
+
+`resetall  // Ok
+module t;
+`resetall  // Bad
+endmodule
+`resetall  // Ok