diff --git a/test_regress/t/t_assert_assert.v b/test_regress/t/t_assert_assert.v index 8065336c7..f211722e0 100644 --- a/test_regress/t/t_assert_assert.v +++ b/test_regress/t/t_assert_assert.v @@ -23,11 +23,11 @@ module t ( int cnt_ff; assert property (@(negedge clk) disable iff (value[1]) value[2]) begin - assert (value[0]) ++cnt_tt; + assert (value[0])++cnt_tt; else ++cnt_tf; end else begin - assert (value[0]) ++cnt_ft; + assert (value[0])++cnt_ft; else ++cnt_ff; end @@ -35,7 +35,7 @@ module t ( always @(posedge clk) begin cyc <= cyc + 1; if (cyc == 10) begin - assert(cyc == 10); // For debug to compare with other asserts + assert (cyc == 10); // For debug to compare with other asserts value <= 0; cnt_tt = 0; cnt_tf = 0; diff --git a/test_regress/t/t_assert_basic.v b/test_regress/t/t_assert_basic.v index 55360519d..6a40e8e99 100644 --- a/test_regress/t/t_assert_basic.v +++ b/test_regress/t/t_assert_basic.v @@ -13,20 +13,16 @@ module t ( integer cyc; initial cyc = 1; wire [7:0] cyc_copy = cyc[7:0]; - typedef enum logic { CAST_ONE = 1'b1 } cast_e; + typedef enum logic {CAST_ONE = 1'b1} cast_e; cast_e cast_dst; integer action_hits = 0; - assert property (@(posedge clk) 1'b1) - if (cyc >= 0) action_hits++; + assert property (@(posedge clk) 1'b1) if (cyc >= 0) action_hits++; - assert property (@(posedge clk) 1'b1) - action_hits++; - else - action_hits--; + assert property (@(posedge clk) 1'b1) action_hits++; + else action_hits--; - cover property (@(posedge clk) 1'b1) - action_hits++; + cover property (@(posedge clk) 1'b1) action_hits++; initial begin $cast(cast_dst, 1); @@ -44,12 +40,9 @@ module t ( if (cyc != 0) begin cyc <= cyc + 1; toggle <= !cyc[0]; - assert (cyc >= 0) - if (cyc >= 0) action_hits++; - assert (cyc >= 0) - action_hits++; - else - action_hits--; + assert (cyc >= 0) if (cyc >= 0) action_hits++; + assert (cyc >= 0) action_hits++; + else action_hits--; if (cyc == 7) assert (cyc[0] == cyc[1]); // bug743 if (cyc == 9) begin `ifdef FAILING_ASSERTIONS diff --git a/test_regress/t/t_assert_ctl_lock_arg.v b/test_regress/t/t_assert_ctl_lock_arg.v index b74fa3516..45d50566f 100644 --- a/test_regress/t/t_assert_ctl_lock_arg.v +++ b/test_regress/t/t_assert_ctl_lock_arg.v @@ -31,11 +31,18 @@ module t; always #5 clk = ~clk; // posedge clk at t = 5, 15, 25, 35, 45, 55, 65, 75, 85, 95 - always @(posedge clk) imm_assert : assert (fals) else imm_fails = imm_fails + 1; + always @(posedge clk) + imm_assert : + assert (fals) + else imm_fails = imm_fails + 1; - conc_assert : assert property (@(posedge clk) fals) else conc_fails = conc_fails + 1; + conc_assert : + assert property (@(posedge clk) fals) + else conc_fails = conc_fails + 1; - conc_assume : assume property (@(posedge clk) fals) else assume_fails = assume_fails + 1; + conc_assume : + assume property (@(posedge clk) fals) + else assume_fails = assume_fails + 1; initial begin #6; // t=6 diff --git a/test_regress/t/t_assert_question.v b/test_regress/t/t_assert_question.v index 518d90d43..5a15799c4 100644 --- a/test_regress/t/t_assert_question.v +++ b/test_regress/t/t_assert_question.v @@ -4,27 +4,22 @@ // SPDX-FileCopyrightText: 2016 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 -module t (/*AUTOARG*/ - // Outputs - dout, - // Inputs - clk, sel, a, c - ); - - input clk; - input bit [3:0] sel; - input bit [3:0] a; - input bit c; - output bit dout; +module t ( + input clk, + input bit [3:0] sel, + input bit [3:0] a, + input bit c, + output bit dout +); localparam logic DC = 1'b?; always_ff @(posedge clk) begin - unique casez(sel) + unique casez (sel) 4'b0000: dout <= a[0]; 4'b001?: dout <= a[1]; - {1'b0, 1'b1, 1'b?, 1'b?}: dout <= a[2]; - {1'b1, 1'b?, 1'b?, DC}: dout <= a[3]; + {1'b0, 1'b1, 1'b?, 1'b?} : dout <= a[2]; + {1'b1, 1'b?, 1'b?, DC} : dout <= a[3]; default: dout <= '0; endcase $write("*-* All Finished *-*\n"); diff --git a/test_regress/t/t_class_lparam_circular_bad.out b/test_regress/t/t_class_lparam_circular_bad.out index cf135b8fe..0a00d40f1 100644 --- a/test_regress/t/t_class_lparam_circular_bad.out +++ b/test_regress/t/t_class_lparam_circular_bad.out @@ -1,14 +1,14 @@ -%Error: t/t_class_lparam_circular_bad.v:16:18: Variable's initial value is circular: 'a' +%Error: t/t_class_lparam_circular_bad.v:18:18: Variable's initial value is circular: 'a' : ... note: In instance 't' - 16 | localparam int a = a; + 18 | localparam int a = a; | ^ ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. -%Error: t/t_class_lparam_circular_bad.v:21:18: Variable's initial value is circular: 'a' +%Error: t/t_class_lparam_circular_bad.v:25:18: Variable's initial value is circular: 'a' : ... note: In instance 't' - 21 | localparam int a = b; + 25 | localparam int a = b; | ^ -%Error: t/t_class_lparam_circular_bad.v:27:18: Variable's initial value is circular: 'p' +%Error: t/t_class_lparam_circular_bad.v:33:18: Variable's initial value is circular: 'p' : ... note: In instance 't' - 27 | localparam int p = q; + 33 | localparam int p = q; | ^ %Error: Exiting due to diff --git a/test_regress/t/t_class_lparam_circular_bad.v b/test_regress/t/t_class_lparam_circular_bad.v index 919d3db71..63aa122b4 100644 --- a/test_regress/t/t_class_lparam_circular_bad.v +++ b/test_regress/t/t_class_lparam_circular_bad.v @@ -12,24 +12,32 @@ // SPDX-FileCopyrightText: 2026 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 -class Self #(parameter int W = 1); +class Self #( + parameter int W = 1 +); localparam int a = a; endclass -class Direct #(parameter int W = 1); +class Direct #( + parameter int W = 1 +); // Two-step cycle: a -> b -> a localparam int a = b; localparam int b = a; endclass -class Indirect #(parameter int W = 1); +class Indirect #( + parameter int W = 1 +); // Three-step cycle through sibling lparams: p -> q -> r -> p localparam int p = q; localparam int q = r; localparam int r = p; endclass -module Sub #(parameter int P = 0) (); +module Sub #( + parameter int P = 0 +) (); endmodule module t; diff --git a/test_regress/t/t_class_lparam_cycle_bad.out b/test_regress/t/t_class_lparam_cycle_bad.out index 9caae73c0..8672e5921 100644 --- a/test_regress/t/t_class_lparam_cycle_bad.out +++ b/test_regress/t/t_class_lparam_cycle_bad.out @@ -1,6 +1,6 @@ -%Error: t/t_class_lparam_cycle_bad.v:25:20: Variable's initial value is circular: 'a' +%Error: t/t_class_lparam_cycle_bad.v:31:20: Variable's initial value is circular: 'a' : ... note: In instance 't' - 25 | localparam int a = inner_a::v + b; + 31 | localparam int a = inner_a::v + b; | ^ ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. %Error: Exiting due to diff --git a/test_regress/t/t_class_lparam_cycle_bad.v b/test_regress/t/t_class_lparam_cycle_bad.v index c3469b215..7942bf7a2 100644 --- a/test_regress/t/t_class_lparam_cycle_bad.v +++ b/test_regress/t/t_class_lparam_cycle_bad.v @@ -10,15 +10,21 @@ // SPDX-FileCopyrightText: 2026 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 -module Sub #(parameter int WIDTH = 0) (); +module Sub #( + parameter int WIDTH = 0 +) (); endmodule module t; - virtual class A #(parameter int x = 0); + virtual class A #( + parameter int x = 0 + ); localparam int v = x * 2; endclass - virtual class B #(parameter int y = 0); + virtual class B #( + parameter int y = 0 + ); typedef A#(y + 1) inner_a; // 'a' is deferred (holds the inner_a::v Dot) and also references 'b'; // 'b' references 'a' back -> cycle through the deferred fold. diff --git a/test_regress/t/t_class_lparam_deferred.v b/test_regress/t/t_class_lparam_deferred.v index 912c6d44a..2b09162d0 100644 --- a/test_regress/t/t_class_lparam_deferred.v +++ b/test_regress/t/t_class_lparam_deferred.v @@ -30,70 +30,87 @@ typedef struct packed { } inner_t; typedef struct packed { - inner_t jt; + inner_t jt; logic [7:0] tag; } cfg_t; -typedef struct packed { - inner_t [1:0] entries; -} table_t; +typedef struct packed {inner_t [1:0] entries;} table_t; package pkg; - virtual class C #(parameter int W = 1); + virtual class C #( + parameter int W = 1 + ); typedef logic [W-1:0] data_t; endclass endpackage // Struct localparam whose fields derive from the class parameter, plus a // wrapper class whose own lparam reads a nested struct field. -class SC #(parameter int W = 1); - localparam cfg_t cfg = '{jt: '{cam_type: W[7:0], depth: W[7:0] + 8'd1}, - tag: W[7:0] + 8'd2}; +class SC #( + parameter int W = 1 +); + localparam cfg_t cfg = '{jt: '{cam_type: W[7:0], depth: W[7:0] + 8'd1}, tag: W[7:0] + 8'd2}; localparam logic [7:0] bits = W[7:0]; - localparam inner_t [1:0] entries = '{default: '{cam_type: W[7:0], - depth: W[7:0] + 8'd1}}; - localparam table_t tbl = '{entries: '{default: '{cam_type: W[7:0], - depth: W[7:0] + 8'd1}}}; + localparam inner_t [1:0] entries = '{default: '{cam_type: W[7:0], depth: W[7:0] + 8'd1}}; + localparam table_t tbl = '{entries: '{default: '{cam_type: W[7:0], depth: W[7:0] + 8'd1}}}; endclass -class SD #(parameter int W = 1); +class SD #( + parameter int W = 1 +); typedef SC#(W) CC; localparam int q = int'(CC::cfg.tag) + 100; endclass -class P #(parameter cfg_t p = '{default: 0}); +class P #( + parameter cfg_t p = '{default: 0} +); localparam cfg_t pp = p; endclass -module Sub #(parameter int WIDTH = 0) (); +module Sub #( + parameter int WIDTH = 0 +) (); endmodule // Two-level: outer module forwards its param to an inner cell, so the // deferred lparam value must flow through the cell-deparam chain. -module SubL1 #(parameter int W = 0) (); +module SubL1 #( + parameter int W = 0 +) (); Sub #(W) inner (); endmodule -interface SubIface #(parameter int IW = 1) (); +interface SubIface #( + parameter int IW = 1 +) (); logic [IW-1:0] data; endinterface // Takes an interface port - must elaborate after the iface cell pin is // fully constified. -module Consumer (SubIface si); +module Consumer ( + SubIface si +); endmodule // Presence is observable, to confirm each generate flavour elaborated. -module Tag #(parameter int ID = 0) (); +module Tag #( + parameter int ID = 0 +) (); endmodule -module Sink #(parameter int BITS = 1) (); +module Sink #( + parameter int BITS = 1 +) (); logic [BITS-1:0] data; endmodule // Parameterized wrapper so the class specialization is deferred until // V3Param processes the cell instance. -module Mid #(parameter int W = 8) (); +module Mid #( + parameter int W = 8 +) (); typedef SC#(W) CFG; // (5) single-level struct field access, then nested (lsb accumulation) Sub #(int'(CFG::cfg.tag)) u_tag (); @@ -115,12 +132,14 @@ module Mid #(parameter int W = 8) (); typedef pkg::C#(W) PCFG; typedef struct packed { PCFG::data_t payload; - logic v; + logic v; } wrap_t; Sink #(.BITS($bits(wrap_t))) u_sink (); endmodule -module PairHolder #(parameter cfg_t cfg = '{default: 0}) (); +module PairHolder #( + parameter cfg_t cfg = '{default: 0} +) (); typedef P#(cfg) PALIAS; localparam logic [7:0] tag_val = PALIAS::pp.tag; localparam logic [7:0] cam_val = PALIAS::pp.jt.cam_type; @@ -128,16 +147,31 @@ endmodule // (7) The pin's RefDType has no typedefp() to follow - it points at the // enclosing ParamTypeDType - so the deferred walk must descend refDTypep(). -module TChild #(parameter type T = logic, parameter int EXP = 1) (input T a_i); +module TChild #( + parameter type T = logic, + parameter int EXP = 1 +) ( + input T a_i +); initial `checkh($bits(T), EXP); endmodule -module TFwd #(parameter type T = logic, parameter int EXP = 1) (); - TChild #(.T(T), .EXP(EXP)) u (.a_i('0)); +module TFwd #( + parameter type T = logic, + parameter int EXP = 1 +) (); + TChild #( + .T(T), + .EXP(EXP) + ) u ( + .a_i('0) + ); endmodule module t; - virtual class C #(parameter int a = 0); + virtual class C #( + parameter int a = 0 + ); localparam int b = a; typedef logic [a-1:0] inner_t; // localparam derived from a typedef inside the same class @@ -145,10 +179,14 @@ module t; endclass // Two-level: B2's lparam value contains a class::member Dot of its own - virtual class A2 #(parameter int x = 0); + virtual class A2 #( + parameter int x = 0 + ); localparam int v = x * 2; endclass - virtual class B2 #(parameter int y = 0); + virtual class B2 #( + parameter int y = 0 + ); typedef A2#(y + 1) inner_a; localparam int width = inner_a::v; // nested Dot inside B2's lparam // `sib` is deferred (holds the Dot); `sib_use` reads it as a sibling, so @@ -157,7 +195,9 @@ module t; localparam int sib_use = sib + 1; endclass // Three-level: C2 wraps B2 wraps A2 - virtual class C2 #(parameter int z = 0); + virtual class C2 #( + parameter int z = 0 + ); typedef B2#(z * 3) inner_b; localparam int total = inner_b::width; // double-nested Dot endclass @@ -211,13 +251,21 @@ module t; end if (b5 > b3) begin : gi_t Tag #(200) inst (); - end else begin : gi_f + end + else begin : gi_f Tag #(201) inst (); end case (b5) - 3: begin : gc Tag #(303) inst (); end - 5: begin : gc Tag #(305) inst (); end - default: begin : gc Tag #(399) inst (); end + 3: begin : gc + Tag #(303) inst (); + end + 5: begin : gc + Tag #(305) inst (); + end + default: + begin : gc + Tag #(399) inst (); + end endcase // (3) typedef range from a deferred lparam; class type-arg using a @@ -240,10 +288,28 @@ module t; localparam type t_plain = pkg::C#(12)::data_t; typedef pkg::C#(9) alias_c; localparam type t_alias = alias_c::data_t; - TChild #(.T(t_plain), .EXP(12)) u_plain (.a_i('0)); - TChild #(.T(cfg_t), .EXP(24)) u_tstruct (.a_i('0)); - TChild #(.T(t_alias), .EXP(9)) u_alias (.a_i('0)); - TFwd #(.T(t_plain), .EXP(12)) u_fwd (); + TChild #( + .T(t_plain), + .EXP(12) + ) u_plain ( + .a_i('0) + ); + TChild #( + .T(cfg_t), + .EXP(24) + ) u_tstruct ( + .a_i('0) + ); + TChild #( + .T(t_alias), + .EXP(9) + ) u_alias ( + .a_i('0) + ); + TFwd #( + .T(t_plain), + .EXP(12) + ) u_fwd (); initial begin `checkh(b3, 32'd3); diff --git a/test_regress/t/t_class_lparam_generate_inline.v b/test_regress/t/t_class_lparam_generate_inline.v index fbadd78c8..97f16708e 100644 --- a/test_regress/t/t_class_lparam_generate_inline.v +++ b/test_regress/t/t_class_lparam_generate_inline.v @@ -50,7 +50,8 @@ module t; // (1) Generate-if cond: inline specialization, single '::' if (C#(5)::b > C#(3)::b) begin : gi_t Tag #(200) inst (); - end else begin : gi_f + end + else begin : gi_f Tag #(201) inst (); end @@ -73,9 +74,16 @@ module t; // (5) Generate-case selector = inline specialization case (P::cfg#(5)::width) - 3: begin : gc Tag #(303) inst (); end - 5: begin : gc Tag #(305) inst (); end - default: begin : gc Tag #(399) inst (); end + 3: begin : gc + Tag #(303) inst (); + end + 5: begin : gc + Tag #(305) inst (); + end + default: + begin : gc + Tag #(399) inst (); + end endcase initial begin diff --git a/test_regress/t/t_class_lparam_nonparam_bad.out b/test_regress/t/t_class_lparam_nonparam_bad.out index 57dee0917..44264d2e8 100644 --- a/test_regress/t/t_class_lparam_nonparam_bad.out +++ b/test_regress/t/t_class_lparam_nonparam_bad.out @@ -1,21 +1,21 @@ -%Error-UNSUPPORTED: t/t_class_lparam_nonparam_bad.v:26:14: dotted expressions in parameters +%Error-UNSUPPORTED: t/t_class_lparam_nonparam_bad.v:30:14: dotted expressions in parameters : ... note: In instance 't' : ... Suggest use a typedef - 26 | Sub #(CFG::notaparam) u_prop (); + 30 | Sub #(CFG::notaparam) u_prop (); | ^~~~~~~~~ ... For error description see https://verilator.org/warn/UNSUPPORTED?v=latest -%Error: t/t_class_lparam_nonparam_bad.v:26:14: Can't convert defparam value to constant: Param '__paramNumber1' of 'u_prop' +%Error: t/t_class_lparam_nonparam_bad.v:30:14: Can't convert defparam value to constant: Param '__paramNumber1' of 'u_prop' : ... note: In instance 't' - 26 | Sub #(CFG::notaparam) u_prop (); + 30 | Sub #(CFG::notaparam) u_prop (); | ^~~~~~~~~ ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. -%Error-UNSUPPORTED: t/t_class_lparam_nonparam_bad.v:27:14: dotted expressions in parameters +%Error-UNSUPPORTED: t/t_class_lparam_nonparam_bad.v:31:14: dotted expressions in parameters : ... note: In instance 't' : ... Suggest use a typedef - 27 | Sub #(CFG::alsonotaparam) u_static (); + 31 | Sub #(CFG::alsonotaparam) u_static (); | ^~~~~~~~~~~~~ -%Error: t/t_class_lparam_nonparam_bad.v:27:14: Can't convert defparam value to constant: Param '__paramNumber1' of 'u_static' +%Error: t/t_class_lparam_nonparam_bad.v:31:14: Can't convert defparam value to constant: Param '__paramNumber1' of 'u_static' : ... note: In instance 't' - 27 | Sub #(CFG::alsonotaparam) u_static (); + 31 | Sub #(CFG::alsonotaparam) u_static (); | ^~~~~~~~~~~~~ %Error: Exiting due to diff --git a/test_regress/t/t_class_lparam_nonparam_bad.v b/test_regress/t/t_class_lparam_nonparam_bad.v index a4de1b0b6..ee870bd52 100644 --- a/test_regress/t/t_class_lparam_nonparam_bad.v +++ b/test_regress/t/t_class_lparam_nonparam_bad.v @@ -11,13 +11,17 @@ // SPDX-FileCopyrightText: 2026 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 -class C #(parameter int W = 1); +class C #( + parameter int W = 1 +); int notaparam; static int alsonotaparam; localparam int good = W; endclass -module Sub #(parameter int P = 0) (); +module Sub #( + parameter int P = 0 +) (); endmodule module t; diff --git a/test_regress/t/t_class_lparam_repeat_ref.v b/test_regress/t/t_class_lparam_repeat_ref.v index c4cb137f2..4d1952606 100644 --- a/test_regress/t/t_class_lparam_repeat_ref.v +++ b/test_regress/t/t_class_lparam_repeat_ref.v @@ -16,7 +16,9 @@ `define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0) // verilog_format: on -class Inner #(parameter int V = 1); +class Inner #( + parameter int V = 1 +); localparam int v = V; endclass diff --git a/test_regress/t/t_class_lparam_sibling_chain.v b/test_regress/t/t_class_lparam_sibling_chain.v index c528a5621..776d3e7cd 100644 --- a/test_regress/t/t_class_lparam_sibling_chain.v +++ b/test_regress/t/t_class_lparam_sibling_chain.v @@ -17,11 +17,15 @@ `define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0) // verilog_format: on -class Inner #(parameter int V = 1); +class Inner #( + parameter int V = 1 +); localparam int v = V; endclass -class C #(parameter int W = 1); +class C #( + parameter int W = 1 +); // Only `base` holds the class::member Dot directly. localparam int base = Inner#(W)::v; // `one` is a bare VarRef to a sibling that is not yet Const. diff --git a/test_regress/t/t_class_lparam_struct_field_chain_bad.out b/test_regress/t/t_class_lparam_struct_field_chain_bad.out index abe85d45f..c82042794 100644 --- a/test_regress/t/t_class_lparam_struct_field_chain_bad.out +++ b/test_regress/t/t_class_lparam_struct_field_chain_bad.out @@ -1,19 +1,19 @@ -%Error-UNSUPPORTED: t/t_class_lparam_struct_field_chain_bad.v:36:27: Unsupported: Member call on object 'SEL' which is a 'BASICDTYPE 'logic'' +%Error-UNSUPPORTED: t/t_class_lparam_struct_field_chain_bad.v:41:27: Unsupported: Member call on object 'SEL' which is a 'BASICDTYPE 'logic'' : ... note: In instance 't.u' - 36 | Sub #(int'(CFG::cfg.tag.bogus)) u_nonstruct (); + 41 | Sub #(int'(CFG::cfg.tag.bogus)) u_nonstruct (); | ^~~~~ ... For error description see https://verilator.org/warn/UNSUPPORTED?v=latest -%Error-UNSUPPORTED: t/t_class_lparam_struct_field_chain_bad.v:36:12: Unsupported: static cast to 'int' from 'VOIDDTYPE' +%Error-UNSUPPORTED: t/t_class_lparam_struct_field_chain_bad.v:41:12: Unsupported: static cast to 'int' from 'VOIDDTYPE' : ... note: In instance 't.u' - 36 | Sub #(int'(CFG::cfg.tag.bogus)) u_nonstruct (); + 41 | Sub #(int'(CFG::cfg.tag.bogus)) u_nonstruct (); | ^ -%Error: t/t_class_lparam_struct_field_chain_bad.v:36:12: Can't convert defparam value to constant: Param '__paramNumber1' of 'u_nonstruct' +%Error: t/t_class_lparam_struct_field_chain_bad.v:41:12: Can't convert defparam value to constant: Param '__paramNumber1' of 'u_nonstruct' : ... note: In instance 't.u' - 36 | Sub #(int'(CFG::cfg.tag.bogus)) u_nonstruct (); + 41 | Sub #(int'(CFG::cfg.tag.bogus)) u_nonstruct (); | ^ ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. -%Error: t/t_class_lparam_struct_field_chain_bad.v:38:26: Member 'nosuchfield' not found in structure +%Error: t/t_class_lparam_struct_field_chain_bad.v:43:26: Member 'nosuchfield' not found in structure : ... note: In instance 't.u' - 38 | Sub #(int'(CFG::cfg.jt.nosuchfield)) u_nomember (); + 43 | Sub #(int'(CFG::cfg.jt.nosuchfield)) u_nomember (); | ^~~~~~~~~~~ %Error: Exiting due to diff --git a/test_regress/t/t_class_lparam_struct_field_chain_bad.v b/test_regress/t/t_class_lparam_struct_field_chain_bad.v index 2c16a5493..45cd2811d 100644 --- a/test_regress/t/t_class_lparam_struct_field_chain_bad.v +++ b/test_regress/t/t_class_lparam_struct_field_chain_bad.v @@ -18,19 +18,24 @@ typedef struct packed { } inner_t; typedef struct packed { - inner_t jt; + inner_t jt; logic [7:0] tag; } cfg_t; -class C #(parameter int W = 1); - localparam cfg_t cfg = '{jt: '{cam_type: W[7:0], depth: W[7:0] + 8'd1}, - tag: W[7:0] + 8'd2}; +class C #( + parameter int W = 1 +); + localparam cfg_t cfg = '{jt: '{cam_type: W[7:0], depth: W[7:0] + 8'd1}, tag: W[7:0] + 8'd2}; endclass -module Sub #(parameter int WIDTH = 0) (); +module Sub #( + parameter int WIDTH = 0 +) (); endmodule -module Mid #(parameter int W = 8) (); +module Mid #( + parameter int W = 8 +) (); typedef C#(W) CFG; // (1) `.bogus` on the scalar field `tag`: dotting into a non-struct Sub #(int'(CFG::cfg.tag.bogus)) u_nonstruct (); diff --git a/test_regress/t/t_class_param_rewrite.v b/test_regress/t/t_class_param_rewrite.v index 1303af3db..32f04b96d 100644 --- a/test_regress/t/t_class_param_rewrite.v +++ b/test_regress/t/t_class_param_rewrite.v @@ -5,20 +5,20 @@ // SPDX-License-Identifier: CC0-1.0 module test; - typedef enum { FOO_0 } foo_e; - typedef enum { BAR_0 } bar_e; + typedef enum {FOO_0} foo_e; + typedef enum {BAR_0} bar_e; - class baz #(parameter type E = foo_e); + class baz #( + parameter type E = foo_e + ); static function void print(); E enum_item; - if (enum_item.first().name() != "BAR_0") - $stop; + if (enum_item.first().name() != "BAR_0") $stop; endfunction class Inner1; static function void print(); E enum_item; - if (enum_item.first().name() != "BAR_0") - $stop; + if (enum_item.first().name() != "BAR_0") $stop; endfunction endclass endclass diff --git a/test_regress/t/t_class_param_self_ref_typedef.v b/test_regress/t/t_class_param_self_ref_typedef.v index 06310e1ef..a30175bd5 100644 --- a/test_regress/t/t_class_param_self_ref_typedef.v +++ b/test_regress/t/t_class_param_self_ref_typedef.v @@ -16,11 +16,15 @@ // verilog_format: on package pkg; - class item_base #(type DATA = int); + class item_base #( + type DATA = int + ); DATA value; endclass - class holder #(type FIN = int); + class holder #( + type FIN = int + ); typedef item_base#(FIN) my_item_t; virtual function holder::my_item_t get_bare(); @@ -30,11 +34,15 @@ package pkg; endclass // Same, but the typedef is inherited from a base class instead. - class base_holder #(type FIN = int); + class base_holder #( + type FIN = int + ); typedef item_base#(FIN) my_item_t; endclass - class derived #(type FIN = int) extends base_holder#(FIN); + class derived #( + type FIN = int + ) extends base_holder #(FIN); virtual function derived::my_item_t get_bare(); my_item_t item; return item; @@ -47,12 +55,12 @@ module t; // Non-default parameters, so the specialization differs from the template // default and the bug is observable. - holder#(byte) h; - derived#(shortint) d; + holder #(byte) h; + derived #(shortint) d; initial begin - automatic holder#(byte)::my_item_t got; - automatic derived#(shortint)::my_item_t got_inherited; + automatic holder #(byte)::my_item_t got; + automatic derived #(shortint)::my_item_t got_inherited; h = new; got = h.get_bare(); `checkd($bits(got.value), 8); diff --git a/test_regress/t/t_class_param_struct.v b/test_regress/t/t_class_param_struct.v index ec41c732f..329b5a024 100644 --- a/test_regress/t/t_class_param_struct.v +++ b/test_regress/t/t_class_param_struct.v @@ -10,9 +10,7 @@ // verilog_format: on package P; - typedef struct { - int depth; - } memory_config_t; + typedef struct {int depth;} memory_config_t; typedef struct { memory_config_t memory; diff --git a/test_regress/t/t_class_scope_chain_alias_bad.out b/test_regress/t/t_class_scope_chain_alias_bad.out index 0e97075f7..9be8f35d2 100644 --- a/test_regress/t/t_class_scope_chain_alias_bad.out +++ b/test_regress/t/t_class_scope_chain_alias_bad.out @@ -1,5 +1,5 @@ -%Error-UNSUPPORTED: t/t_class_scope_chain_alias_bad.v:38:6: Unsupported: Multiple '::' package/class reference - 38 | Q::AliasPC::inner::u e; +%Error-UNSUPPORTED: t/t_class_scope_chain_alias_bad.v:36:6: Unsupported: Multiple '::' package/class reference + 36 | Q::AliasPC::inner::u e; | ^~~~~~~ ... For error description see https://verilator.org/warn/UNSUPPORTED?v=latest %Error: Exiting due to diff --git a/test_regress/t/t_class_scope_chain_alias_bad.v b/test_regress/t/t_class_scope_chain_alias_bad.v index f92f7250c..8c9e4302b 100644 --- a/test_regress/t/t_class_scope_chain_alias_bad.v +++ b/test_regress/t/t_class_scope_chain_alias_bad.v @@ -13,9 +13,7 @@ // SPDX-License-Identifier: CC0-1.0 package P; - typedef struct packed { - int depth; - } config_t; + typedef struct packed {int depth;} config_t; virtual class PC #( parameter config_t c diff --git a/test_regress/t/t_class_scope_pkg_alias.v b/test_regress/t/t_class_scope_pkg_alias.v index 47ae83d72..f94edf353 100644 --- a/test_regress/t/t_class_scope_pkg_alias.v +++ b/test_regress/t/t_class_scope_pkg_alias.v @@ -33,7 +33,7 @@ package base_pkg; typedef logic [width-1:0] data_t; typedef struct packed { logic [c.meta-1:0] m; - data_t d; + data_t d; } meta_t; endclass endpackage @@ -41,18 +41,18 @@ endpackage package top_pkg; localparam base_pkg::config_t cfgv = '{depth: 512, meta: 4}; // Typedef alias of a parameterized class, in a different package - typedef base_pkg::cfg #(cfgv) AliasCFG; + typedef base_pkg::cfg#(cfgv) AliasCFG; endpackage // Alias-scoped type as a port, and in the body, of an instantiated submodule module Leaf ( - input top_pkg::AliasCFG::meta_t in_meta, - output top_pkg::AliasCFG::data_t out_data + input top_pkg::AliasCFG::meta_t in_meta, + output top_pkg::AliasCFG::data_t out_data ); top_pkg::AliasCFG::meta_t body_meta; always_comb begin body_meta = in_meta; - out_data = body_meta.d; + out_data = body_meta.d; end initial begin `checkh($bits(in_meta), 13); @@ -64,8 +64,8 @@ module Mid (); top_pkg::AliasCFG::meta_t m; top_pkg::AliasCFG::data_t d; Leaf leaf ( - .in_meta (m), - .out_data (d) + .in_meta(m), + .out_data(d) ); initial m = '0; endmodule diff --git a/test_regress/t/t_class_type_dep_param.v b/test_regress/t/t_class_type_dep_param.v index a2d9f1418..6039294cb 100644 --- a/test_regress/t/t_class_type_dep_param.v +++ b/test_regress/t/t_class_type_dep_param.v @@ -26,9 +26,7 @@ // verilog_format: on package pkg; - typedef struct packed { - int depth; - } config_t; + typedef struct packed {int depth;} config_t; virtual class cfg #( parameter config_t c @@ -41,10 +39,10 @@ endpackage // Child with a type parameter defaulted from another parameter, as in a // sample-and-hold style utility module module Holder #( - parameter int width = 0, + parameter int width = 0, parameter type data_t = logic [width-1:0] ) ( - input data_t dat_i, + input data_t dat_i, output data_t dat_o ); always_comb dat_o = dat_i; @@ -53,7 +51,7 @@ endmodule module Sub #( parameter pkg::config_t cfg ) (); - typedef pkg::cfg #(cfg) CFG; + typedef pkg::cfg#(cfg) CFG; CFG::data_t src, dst; typedef CFG::data_t unpacked_t[3:1]; typedef CFG::data_t dynamic_t[]; @@ -69,17 +67,21 @@ module Sub #( localparam int UnpackedBits = $bits(unpacked_data); // (2) $bits() of a class-scoped-typed signal, as a cell parameter pin - Holder #(.width($bits(src))) holder ( - .dat_i (src), - .dat_o (dst) + Holder #( + .width($bits(src)) + ) holder ( + .dat_i(src), + .dat_o(dst) ); // (3) Same, inside a generate arm if (CFG::width > 0) begin : gen_arm CFG::data_t arm_src, arm_dst; - Holder #(.width($bits(arm_src))) armHolder ( - .dat_i (arm_src), - .dat_o (arm_dst) + Holder #( + .width($bits(arm_src)) + ) armHolder ( + .dat_i(arm_src), + .dat_o(arm_dst) ); initial arm_src = '0; end diff --git a/test_regress/t/t_class_type_param_upcast_chain.v b/test_regress/t/t_class_type_param_upcast_chain.v index 91e767027..182e0b770 100644 --- a/test_regress/t/t_class_type_param_upcast_chain.v +++ b/test_regress/t/t_class_type_param_upcast_chain.v @@ -7,7 +7,9 @@ // Output class type-parameter upcast through a 3-level extends chain. package x_pkg; - virtual class x_t_fifo_base #(type T = int); + virtual class x_t_fifo_base #( + type T = int + ); T m_val; virtual task put(input T t); m_val = t; @@ -16,9 +18,13 @@ package x_pkg; t = m_val; endtask endclass - class x_t_fifo #(type T = int) extends x_t_fifo_base #(T); + class x_t_fifo #( + type T = int + ) extends x_t_fifo_base #(T); endclass - class x_t_analysis_fifo #(type T = int) extends x_t_fifo #(T); + class x_t_analysis_fifo #( + type T = int + ) extends x_t_fifo #(T); endclass endpackage diff --git a/test_regress/t/t_cover_expr.out b/test_regress/t/t_cover_expr.out index d6d6f454b..e3f195f0d 100644 --- a/test_regress/t/t_cover_expr.out +++ b/test_regress/t/t_cover_expr.out @@ -211,7 +211,7 @@ end end for (int loop_var_2 = 0; loop_var_2 < 32; loop_var_2 += 2) begin -~000131 if (cyc[loop_var_2] | cyc[loop_var_2 + 1]) $write(""); +~000131 if (cyc[loop_var_2] | cyc[loop_var_2+1]) $write(""); -000006 point: type=expr comment=(cyc[(loop_var_2 + 32'sh1)[4:0]+:1]==1) => 1 hier=top.t +000131 point: type=expr comment=(cyc[loop_var_2[4:0]+:1]==0 && cyc[(loop_var_2 + 32'sh1)[4:0]+:1]==0) => 0 hier=top.t -000009 point: type=expr comment=(cyc[loop_var_2[4:0]+:1]==1) => 1 hier=top.t diff --git a/test_regress/t/t_cover_expr.v b/test_regress/t/t_cover_expr.v index dbd5417c3..b6bdeff2c 100644 --- a/test_regress/t/t_cover_expr.v +++ b/test_regress/t/t_cover_expr.v @@ -88,7 +88,7 @@ module t ( end end for (int loop_var_2 = 0; loop_var_2 < 32; loop_var_2 += 2) begin - if (cyc[loop_var_2] | cyc[loop_var_2 + 1]) $write(""); + if (cyc[loop_var_2] | cyc[loop_var_2+1]) $write(""); end // stop at the first layer even if there's more to find if ((cyc[3+32'(t1&&t2)+:2] == cyc[5+32'(t3||t4)+:2]) || cyc[31]) $write(""); diff --git a/test_regress/t/t_cover_expr_max.out b/test_regress/t/t_cover_expr_max.out index 7996113b3..d31e5682a 100644 --- a/test_regress/t/t_cover_expr_max.out +++ b/test_regress/t/t_cover_expr_max.out @@ -211,7 +211,7 @@ end end for (int loop_var_2 = 0; loop_var_2 < 32; loop_var_2 += 2) begin -~000131 if (cyc[loop_var_2] | cyc[loop_var_2 + 1]) $write(""); +~000131 if (cyc[loop_var_2] | cyc[loop_var_2+1]) $write(""); -000006 point: type=expr comment=(cyc[(loop_var_2 + 32'sh1)[4:0]+:1]==1) => 1 hier=top.t +000131 point: type=expr comment=(cyc[loop_var_2[4:0]+:1]==0 && cyc[(loop_var_2 + 32'sh1)[4:0]+:1]==0) => 0 hier=top.t -000009 point: type=expr comment=(cyc[loop_var_2[4:0]+:1]==1) => 1 hier=top.t diff --git a/test_regress/t/t_cover_expr_trace.out b/test_regress/t/t_cover_expr_trace.out index d6d6f454b..e3f195f0d 100644 --- a/test_regress/t/t_cover_expr_trace.out +++ b/test_regress/t/t_cover_expr_trace.out @@ -211,7 +211,7 @@ end end for (int loop_var_2 = 0; loop_var_2 < 32; loop_var_2 += 2) begin -~000131 if (cyc[loop_var_2] | cyc[loop_var_2 + 1]) $write(""); +~000131 if (cyc[loop_var_2] | cyc[loop_var_2+1]) $write(""); -000006 point: type=expr comment=(cyc[(loop_var_2 + 32'sh1)[4:0]+:1]==1) => 1 hier=top.t +000131 point: type=expr comment=(cyc[loop_var_2[4:0]+:1]==0 && cyc[(loop_var_2 + 32'sh1)[4:0]+:1]==0) => 0 hier=top.t -000009 point: type=expr comment=(cyc[loop_var_2[4:0]+:1]==1) => 1 hier=top.t diff --git a/test_regress/t/t_cover_fsm_beginif.out b/test_regress/t/t_cover_fsm_beginif.out index e7192d335..bf186fc49 100644 --- a/test_regress/t/t_cover_fsm_beginif.out +++ b/test_regress/t/t_cover_fsm_beginif.out @@ -337,7 +337,8 @@ %000000 // [fsm_state t.nested_bitand_guard_u.state_q::S2] *** UNCOVERED *** if (choose) state_d = S1; else state_d = S0; - end else if (state_q == S1) state_d = S2; + end + else if (state_q == S1) state_d = S2; else if (state_q == S2) state_d = S0; end @@ -549,7 +550,8 @@ if (rst) begin state_q <= S0; other_q <= S0; - end else begin + end + else begin state_q <= state_d; other_q <= other_d; end @@ -573,24 +575,84 @@ int cyc; state_t state /*verilator fsm_reset_arc*/; - fsm_if_enum_oneblock enum_oneblock_u (.clk(clk), .rst(rst), .start(start)); - fsm_if_enum_twoproc enum_twoproc_u (.clk(clk), .rst(rst), .start(start)); - fsm_if_localparam localparam_u (.clk(clk), .rst(rst), .start(start)); - fsm_if_parameter parameter_u (.clk(clk), .rst(rst), .start(start)); - fsm_if_literal_forced literal_forced_u (.clk(clk), .rst(rst)); - fsm_if_guard_state_first guard_state_first_u (.clk(clk), .rst(rst), .start(start)); - fsm_if_guard_first guard_first_u (.clk(clk), .rst(rst), .start(start)); - fsm_if_local_alias local_alias_u (.clk(clk), .rst(rst), .start(start)); - fsm_if_continuous_alias continuous_alias_u (.clk(clk), .rst(rst), .start(start)); + fsm_if_enum_oneblock enum_oneblock_u ( + .clk(clk), + .rst(rst), + .start(start) + ); + fsm_if_enum_twoproc enum_twoproc_u ( + .clk(clk), + .rst(rst), + .start(start) + ); + fsm_if_localparam localparam_u ( + .clk(clk), + .rst(rst), + .start(start) + ); + fsm_if_parameter parameter_u ( + .clk(clk), + .rst(rst), + .start(start) + ); + fsm_if_literal_forced literal_forced_u ( + .clk(clk), + .rst(rst) + ); + fsm_if_guard_state_first guard_state_first_u ( + .clk(clk), + .rst(rst), + .start(start) + ); + fsm_if_guard_first guard_first_u ( + .clk(clk), + .rst(rst), + .start(start) + ); + fsm_if_local_alias local_alias_u ( + .clk(clk), + .rst(rst), + .start(start) + ); + fsm_if_continuous_alias continuous_alias_u ( + .clk(clk), + .rst(rst), + .start(start) + ); fsm_if_nested_bitand_guard nested_bitand_guard_u ( - .clk(clk), .rst(rst), .start(start), .choose(choose)); - fsm_if_default_incl default_incl_u (.clk(clk), .rst(rst), .start(start)); + .clk(clk), + .rst(rst), + .start(start), + .choose(choose) + ); + fsm_if_default_incl default_incl_u ( + .clk(clk), + .rst(rst), + .start(start) + ); fsm_if_oneblock_late_continuous_alias oneblock_late_continuous_alias_u ( - .clk(clk), .rst(rst), .start(start)); - fsm_if_nextstate_compare nextstate_compare_u (.clk(clk), .rst(rst), .start(start)); - fsm_if_reversed_compare reversed_compare_u (.clk(clk), .rst(rst)); - fsm_if_duplicate_alias duplicate_alias_u (.clk(clk), .rst(rst), .start(start)); - fsm_if_case_priority case_priority_u (.clk(clk), .rst(rst)); + .clk(clk), + .rst(rst), + .start(start) + ); + fsm_if_nextstate_compare nextstate_compare_u ( + .clk(clk), + .rst(rst), + .start(start) + ); + fsm_if_reversed_compare reversed_compare_u ( + .clk(clk), + .rst(rst) + ); + fsm_if_duplicate_alias duplicate_alias_u ( + .clk(clk), + .rst(rst), + .start(start) + ); + fsm_if_case_priority case_priority_u ( + .clk(clk), + .rst(rst) + ); initial begin rst = 1'b1; diff --git a/test_regress/t/t_cover_fsm_beginif.v b/test_regress/t/t_cover_fsm_beginif.v index 98895846f..12b5ec5c7 100644 --- a/test_regress/t/t_cover_fsm_beginif.v +++ b/test_regress/t/t_cover_fsm_beginif.v @@ -251,7 +251,8 @@ module fsm_if_nested_bitand_guard ( if ((state_q == S0) & start) begin if (choose) state_d = S1; else state_d = S0; - end else if (state_q == S1) state_d = S2; + end + else if (state_q == S1) state_d = S2; else if (state_q == S2) state_d = S0; end @@ -422,7 +423,8 @@ module fsm_if_case_priority ( if (rst) begin state_q <= S0; other_q <= S0; - end else begin + end + else begin state_q <= state_d; other_q <= other_d; end @@ -446,24 +448,84 @@ module t ( int cyc; state_t state /*verilator fsm_reset_arc*/; - fsm_if_enum_oneblock enum_oneblock_u (.clk(clk), .rst(rst), .start(start)); - fsm_if_enum_twoproc enum_twoproc_u (.clk(clk), .rst(rst), .start(start)); - fsm_if_localparam localparam_u (.clk(clk), .rst(rst), .start(start)); - fsm_if_parameter parameter_u (.clk(clk), .rst(rst), .start(start)); - fsm_if_literal_forced literal_forced_u (.clk(clk), .rst(rst)); - fsm_if_guard_state_first guard_state_first_u (.clk(clk), .rst(rst), .start(start)); - fsm_if_guard_first guard_first_u (.clk(clk), .rst(rst), .start(start)); - fsm_if_local_alias local_alias_u (.clk(clk), .rst(rst), .start(start)); - fsm_if_continuous_alias continuous_alias_u (.clk(clk), .rst(rst), .start(start)); + fsm_if_enum_oneblock enum_oneblock_u ( + .clk(clk), + .rst(rst), + .start(start) + ); + fsm_if_enum_twoproc enum_twoproc_u ( + .clk(clk), + .rst(rst), + .start(start) + ); + fsm_if_localparam localparam_u ( + .clk(clk), + .rst(rst), + .start(start) + ); + fsm_if_parameter parameter_u ( + .clk(clk), + .rst(rst), + .start(start) + ); + fsm_if_literal_forced literal_forced_u ( + .clk(clk), + .rst(rst) + ); + fsm_if_guard_state_first guard_state_first_u ( + .clk(clk), + .rst(rst), + .start(start) + ); + fsm_if_guard_first guard_first_u ( + .clk(clk), + .rst(rst), + .start(start) + ); + fsm_if_local_alias local_alias_u ( + .clk(clk), + .rst(rst), + .start(start) + ); + fsm_if_continuous_alias continuous_alias_u ( + .clk(clk), + .rst(rst), + .start(start) + ); fsm_if_nested_bitand_guard nested_bitand_guard_u ( - .clk(clk), .rst(rst), .start(start), .choose(choose)); - fsm_if_default_incl default_incl_u (.clk(clk), .rst(rst), .start(start)); + .clk(clk), + .rst(rst), + .start(start), + .choose(choose) + ); + fsm_if_default_incl default_incl_u ( + .clk(clk), + .rst(rst), + .start(start) + ); fsm_if_oneblock_late_continuous_alias oneblock_late_continuous_alias_u ( - .clk(clk), .rst(rst), .start(start)); - fsm_if_nextstate_compare nextstate_compare_u (.clk(clk), .rst(rst), .start(start)); - fsm_if_reversed_compare reversed_compare_u (.clk(clk), .rst(rst)); - fsm_if_duplicate_alias duplicate_alias_u (.clk(clk), .rst(rst), .start(start)); - fsm_if_case_priority case_priority_u (.clk(clk), .rst(rst)); + .clk(clk), + .rst(rst), + .start(start) + ); + fsm_if_nextstate_compare nextstate_compare_u ( + .clk(clk), + .rst(rst), + .start(start) + ); + fsm_if_reversed_compare reversed_compare_u ( + .clk(clk), + .rst(rst) + ); + fsm_if_duplicate_alias duplicate_alias_u ( + .clk(clk), + .rst(rst), + .start(start) + ); + fsm_if_case_priority case_priority_u ( + .clk(clk), + .rst(rst) + ); initial begin rst = 1'b1; diff --git a/test_regress/t/t_cover_fsm_negative_extract.out b/test_regress/t/t_cover_fsm_negative_extract.out index 9794c51ea..a9e82a72d 100644 --- a/test_regress/t/t_cover_fsm_negative_extract.out +++ b/test_regress/t/t_cover_fsm_negative_extract.out @@ -378,20 +378,35 @@ fsm_if_mixed_vars_bad mixed_vars_u (.clk(clk)); fsm_if_one_branch_bad one_branch_u (.clk(clk)); fsm_if_duplicate_bad duplicate_u (.clk(clk)); - fsm_if_two_comparisons_bad two_comparisons_u (.clk(clk), .start(start)); + fsm_if_two_comparisons_bad two_comparisons_u ( + .clk(clk), + .start(start) + ); fsm_if_or_bad or_u (.clk(clk)); - fsm_if_alias_guard_bad alias_guard_u (.clk(clk), .start(start)); + fsm_if_alias_guard_bad alias_guard_u ( + .clk(clk), + .start(start) + ); fsm_if_ambiguous_alias_bad ambiguous_alias_u (.clk(clk)); fsm_if_missing_default_bad missing_default_u (.clk(clk)); fsm_if_no_assign_bad no_assign_u (.clk(clk)); fsm_if_nonvar_compare_bad nonvar_compare_u (.clk(clk)); fsm_if_var_rhs_compare_bad var_rhs_compare_u (.clk(clk)); - fsm_if_var_target_bad var_target_u (.clk(clk), .dyn(dyn_case[1:0])); + fsm_if_var_target_bad var_target_u ( + .clk(clk), + .dyn(dyn_case[1:0]) + ); fsm_if_alias_other_state_bad alias_other_state_u (.clk(clk)); - fsm_if_bit_or_bad bit_or_u (.clk(clk), .start(start)); + fsm_if_bit_or_bad bit_or_u ( + .clk(clk), + .start(start) + ); fsm_if_reduction_bad reduction_u (.clk(clk)); fsm_direct_active_low_dynamic_reset_bad active_low_dynamic_reset_u ( - .clk(clk), .rst_n(cyc != 0), .dyn_reset(dyn_case[1:0])); + .clk(clk), + .rst_n(cyc != 0), + .dyn_reset(dyn_case[1:0]) + ); always @(posedge clk) begin cyc <= cyc + 1; diff --git a/test_regress/t/t_cover_fsm_negative_extract.v b/test_regress/t/t_cover_fsm_negative_extract.v index 2e467b898..595c92fab 100644 --- a/test_regress/t/t_cover_fsm_negative_extract.v +++ b/test_regress/t/t_cover_fsm_negative_extract.v @@ -372,20 +372,35 @@ module t ( fsm_if_mixed_vars_bad mixed_vars_u (.clk(clk)); fsm_if_one_branch_bad one_branch_u (.clk(clk)); fsm_if_duplicate_bad duplicate_u (.clk(clk)); - fsm_if_two_comparisons_bad two_comparisons_u (.clk(clk), .start(start)); + fsm_if_two_comparisons_bad two_comparisons_u ( + .clk(clk), + .start(start) + ); fsm_if_or_bad or_u (.clk(clk)); - fsm_if_alias_guard_bad alias_guard_u (.clk(clk), .start(start)); + fsm_if_alias_guard_bad alias_guard_u ( + .clk(clk), + .start(start) + ); fsm_if_ambiguous_alias_bad ambiguous_alias_u (.clk(clk)); fsm_if_missing_default_bad missing_default_u (.clk(clk)); fsm_if_no_assign_bad no_assign_u (.clk(clk)); fsm_if_nonvar_compare_bad nonvar_compare_u (.clk(clk)); fsm_if_var_rhs_compare_bad var_rhs_compare_u (.clk(clk)); - fsm_if_var_target_bad var_target_u (.clk(clk), .dyn(dyn_case[1:0])); + fsm_if_var_target_bad var_target_u ( + .clk(clk), + .dyn(dyn_case[1:0]) + ); fsm_if_alias_other_state_bad alias_other_state_u (.clk(clk)); - fsm_if_bit_or_bad bit_or_u (.clk(clk), .start(start)); + fsm_if_bit_or_bad bit_or_u ( + .clk(clk), + .start(start) + ); fsm_if_reduction_bad reduction_u (.clk(clk)); fsm_direct_active_low_dynamic_reset_bad active_low_dynamic_reset_u ( - .clk(clk), .rst_n(cyc != 0), .dyn_reset(dyn_case[1:0])); + .clk(clk), + .rst_n(cyc != 0), + .dyn_reset(dyn_case[1:0]) + ); always @(posedge clk) begin cyc <= cyc + 1; diff --git a/test_regress/t/t_cover_line_expr.out b/test_regress/t/t_cover_line_expr.out index 705075836..5f7e2ca28 100644 --- a/test_regress/t/t_cover_line_expr.out +++ b/test_regress/t/t_cover_line_expr.out @@ -289,7 +289,7 @@ ~000144 for (int loop_var_2 = 0; loop_var_2 < 32; loop_var_2 += 2) begin -000009 point: type=line comment=block hier=top.t +000144 point: type=line comment=block hier=top.t -~000131 if (cyc[loop_var_2] | cyc[loop_var_2 + 1]) $write(""); +~000131 if (cyc[loop_var_2] | cyc[loop_var_2+1]) $write(""); -000006 point: type=expr comment=(cyc[(loop_var_2 + 32'sh1)[4:0]+:1]==1) => 1 hier=top.t +000131 point: type=expr comment=(cyc[loop_var_2[4:0]+:1]==0 && cyc[(loop_var_2 + 32'sh1)[4:0]+:1]==0) => 0 hier=top.t -000009 point: type=expr comment=(cyc[loop_var_2[4:0]+:1]==1) => 1 hier=top.t diff --git a/test_regress/t/t_cover_property.v b/test_regress/t/t_cover_property.v index 97174b434..f86824405 100644 --- a/test_regress/t/t_cover_property.v +++ b/test_regress/t/t_cover_property.v @@ -44,7 +44,7 @@ module t ( cp_seq0 : cover property (a ##0 b) n_seq0++; cp_strong : - cover property (strong(a ##1 b)) n_strong++; + cover property (strong (a ##1 b)) n_strong++; cp_bool : cover property (a) n_bool++; cp_named : diff --git a/test_regress/t/t_covergroup_bin_const_expr.v b/test_regress/t/t_covergroup_bin_const_expr.v index 5d25ed3d5..8f15cad33 100644 --- a/test_regress/t/t_covergroup_bin_const_expr.v +++ b/test_regress/t/t_covergroup_bin_const_expr.v @@ -43,13 +43,13 @@ module t #( bins bins3[] = {[3 ** 3 : 58 - 7], [LOCAL_PARAM : PARAM]}; } endgroup - c_trans ctrans; + c_trans ctrans; c_values cvalues; c_ranges cranges; initial begin - ctrans = new(); + ctrans = new(); cvalues = new(); cranges = new(); // Transition diff --git a/test_regress/t/t_dfg_break_cycles.v b/test_regress/t/t_dfg_break_cycles.v index 0698d17a9..74e501dbc 100644 --- a/test_regress/t/t_dfg_break_cycles.v +++ b/test_regress/t/t_dfg_break_cycles.v @@ -7,18 +7,21 @@ `define signal(name, width) wire [width-1:0] name module t ( -`include "portlist.vh" // Boilerplate generated by t_dfg_break_cycles.py - rand_a, rand_b, srand_a, srand_b + `include "portlist.vh" // Boilerplate generated by t_dfg_break_cycles.py + rand_a, + rand_b, + srand_a, + srand_b ); -`include "portdecl.vh" // Boilerplate generated by t_dfg_break_cycles.py + `include "portdecl.vh" // Boilerplate generated by t_dfg_break_cycles.py input rand_a; input rand_b; input srand_a; input srand_b; - wire logic [63:0] rand_a; - wire logic [63:0] rand_b; + wire logic [63:0] rand_a; + wire logic [63:0] rand_b; wire logic signed [63:0] srand_a; wire logic signed [63:0] srand_b; @@ -26,117 +29,117 @@ module t ( // Interesting user code to cover ////////////////////////////////////////////////////////////////////////// - `signal(GRAY_SEL, 3); // UNOPTFLAT + `signal(GRAY_SEL, 3); // UNOPTFLAT assign GRAY_SEL = rand_a[2:0] ^ 3'(GRAY_SEL[2:1]); - `signal(GRAY_SHIFT, 3); // UNOPTFLAT + `signal(GRAY_SHIFT, 3); // UNOPTFLAT assign GRAY_SHIFT = rand_a[2:0] ^ (GRAY_SHIFT >> 1); - `signal(GRAY_REV_SEL, 3); // UNOPTFLAT + `signal(GRAY_REV_SEL, 3); // UNOPTFLAT assign GRAY_REV_SEL = rand_a[2:0] ^ {GRAY_REV_SEL[1:0], 1'b0}; - `signal(GRAY_REV_SHIFT, 3); // UNOPTFLAT + `signal(GRAY_REV_SHIFT, 3); // UNOPTFLAT assign GRAY_REV_SHIFT = rand_a[2:0] ^ (GRAY_REV_SHIFT << 1); ////////////////////////////////////////////////////////////////////////// // Fill coverage ////////////////////////////////////////////////////////////////////////// - `signal(CONCAT_RHS, 2); // UNOPTFLAT + `signal(CONCAT_RHS, 2); // UNOPTFLAT assign CONCAT_RHS[0] = rand_a[0]; assign CONCAT_RHS[1] = CONCAT_RHS[0]; - `signal(CONCAT_LHS, 2); // UNOPTFLAT + `signal(CONCAT_LHS, 2); // UNOPTFLAT assign CONCAT_LHS[0] = CONCAT_LHS[1]; assign CONCAT_LHS[1] = rand_a[1]; - `signal(CONCAT_MID, 3); // UNOPTFLAT + `signal(CONCAT_MID, 3); // UNOPTFLAT assign CONCAT_MID[0] = |CONCAT_MID[2:1]; assign CONCAT_MID[2:1] = {rand_a[2], ~rand_a[2]}; - `signal(SEL, 3); // UNOPTFLAT + `signal(SEL, 3); // UNOPTFLAT assign SEL[0] = rand_a[4]; assign SEL[1] = SEL[0]; assign SEL[2] = SEL[1]; - `signal(ZX, 8); // UNOPTFLAT + `signal(ZX, 8); // UNOPTFLAT assign ZX[0] = rand_a[3]; assign ZX[3:1] = 3'(ZX[0]); assign ZX[4] = ZX[1]; assign ZX[6:5] = ZX[2:1]; assign ZX[7] = ZX[3]; - `signal(SX_0, 5); // UNOPTFLAT + `signal(SX_0, 5); // UNOPTFLAT assign SX_0[0] = rand_a[3]; assign SX_0[3:1] = 3'(signed'(SX_0[0])); - `signal(SX_1, 5); // UNOPTFLAT + `signal(SX_1, 5); // UNOPTFLAT assign SX_1 = 5'(signed'({rand_a[0], SX_1[1]})); - `signal(SX_2, 5); // UNOPTFLAT + `signal(SX_2, 5); // UNOPTFLAT assign SX_2 = 5'(signed'({rand_a[0], SX_2[2]})); - `signal(SX_3, 5); // UNOPTFLAT + `signal(SX_3, 5); // UNOPTFLAT assign SX_3 = 5'(signed'({rand_a[0], SX_3[3:2]})); - `signal(SX_4, 5); // UNOPTFLAT + `signal(SX_4, 5); // UNOPTFLAT assign SX_4 = 5'(signed'({rand_a[0], SX_4[4:3]})); - `signal(NOT, 3); // UNOPTFLAT + `signal(NOT, 3); // UNOPTFLAT assign NOT = ~(rand_a[2:0] ^ 3'(NOT[2:1])); - `signal(AND, 3); // UNOPTFLAT + `signal(AND, 3); // UNOPTFLAT assign AND = rand_a[2:0] & 3'(AND[2:1]); - `signal(OR, 3); // UNOPTFLAT + `signal(OR, 3); // UNOPTFLAT assign OR = rand_a[2:0] | 3'(OR[2:1]); - `signal(SHIFTRS, 14); // UNOPTFLAT + `signal(SHIFTRS, 14); // UNOPTFLAT assign SHIFTRS = { - SHIFTRS[6:5], // 13:12 - SHIFTRS[7:6], // 11:10 - SHIFTRS[5:4], // 9:8 + SHIFTRS[6:5], // 13:12 + SHIFTRS[7:6], // 11:10 + SHIFTRS[5:4], // 9:8 signed'(SHIFTRS[3:0]) >>> 2, // 7:4 - rand_a[3:0] // 3:0 + rand_a[3:0] // 3:0 }; - `signal(SHIFTRS_2_A, 10); // UNOPTFLAT + `signal(SHIFTRS_2_A, 10); // UNOPTFLAT wire logic [9:0] SHIFTRS_2_B = signed'(SHIFTRS_2_A) >>> 2; assign SHIFTRS_2_A = {rand_a[1:0], SHIFTRS_2_B[9:2]}; - `signal(SHIFTRS_3_A, 10); // UNOPTFLAT + `signal(SHIFTRS_3_A, 10); // UNOPTFLAT wire logic [9:0] SHIFTRS_3_B = signed'(SHIFTRS_3_A) >>> 10; assign SHIFTRS_3_A = {rand_a[1:0], SHIFTRS_3_B[9:2]}; - `signal(SHIFTRS_4_A, 10); // UNOPTFLAT + `signal(SHIFTRS_4_A, 10); // UNOPTFLAT wire logic [9:0] SHIFTRS_4_B = signed'(SHIFTRS_4_A) >>> 2; assign SHIFTRS_4_A = {rand_a[3:0], SHIFTRS_4_B[7:2]}; - `signal(SHIFTRS_VARIABLE, 2); // UNOPTFLAT + `signal(SHIFTRS_VARIABLE, 2); // UNOPTFLAT assign SHIFTRS_VARIABLE = signed'(rand_a[1:0] ^ ({1'b0, SHIFTRS_VARIABLE[1]}) >>> rand_b[0]); - `signal(SHIFTRS_VARIABLE_2, 2); // UNOPTFLAT + `signal(SHIFTRS_VARIABLE_2, 2); // UNOPTFLAT assign SHIFTRS_VARIABLE_2 = signed'(rand_a[1:0] ^ ({1'b1, SHIFTRS_VARIABLE_2[1]}) >>> rand_b[0]); - `signal(SHIFTRS_VARIABLE_3_A, 4); // UNOPTFLAT + `signal(SHIFTRS_VARIABLE_3_A, 4); // UNOPTFLAT `signal(SHIFTRS_VARIABLE_3_B, 5); assign SHIFTRS_VARIABLE_3_B = signed'({4'b1111, SHIFTRS_VARIABLE_3_A[1]}) >>> rand_b[0]; assign SHIFTRS_VARIABLE_3_A = rand_a[3:0] ^ SHIFTRS_VARIABLE_3_B[3:0]; - `signal(SHIFTRS_VARIABLE_4_A, 4); // UNOPTFLAT + `signal(SHIFTRS_VARIABLE_4_A, 4); // UNOPTFLAT `signal(SHIFTRS_VARIABLE_4_B, 5); assign SHIFTRS_VARIABLE_4_B = signed'({4'b1111, SHIFTRS_VARIABLE_4_A[1]}) >>> rand_b[0]; assign SHIFTRS_VARIABLE_4_A = rand_a[3:0] ^ SHIFTRS_VARIABLE_4_B[4:1]; - `signal(SHIFTRS_VARIABLE_5, 2); // UNOPTFLAT + `signal(SHIFTRS_VARIABLE_5, 2); // UNOPTFLAT assign SHIFTRS_VARIABLE_5 = signed'({rand_a[0], SHIFTRS_VARIABLE_5[1]}) >>> rand_b[0]; - `signal(SHIFTR, 14); // UNOPTFLAT + `signal(SHIFTR, 14); // UNOPTFLAT assign SHIFTR = { - SHIFTR[6:5], // 13:12 - SHIFTR[7:6], // 11:10 - SHIFTR[5:4], // 9:8 - SHIFTR[3:0] >> 2, // 7:4 - rand_a[3:0] // 3:0 + SHIFTR[6:5], // 13:12 + SHIFTR[7:6], // 11:10 + SHIFTR[5:4], // 9:8 + SHIFTR[3:0] >> 2, // 7:4 + rand_a[3:0] // 3:0 }; - `signal(SHIFTR_2_A, 10); // UNOPTFLAT + `signal(SHIFTR_2_A, 10); // UNOPTFLAT wire logic [9:0] SHIFTR_2_B = SHIFTR_2_A >> 2; assign SHIFTR_2_A = {rand_a[1:0], SHIFTR_2_B[9:2]}; @@ -144,27 +147,27 @@ module t ( wire logic [9:0] SHIFTR_3_B = SHIFTR_3_A >> 10; assign SHIFTR_3_A = {rand_a[1:0], SHIFTR_3_B[9:2]}; - `signal(SHIFTR_VARIABLE, 2); // UNOPTFLAT + `signal(SHIFTR_VARIABLE, 2); // UNOPTFLAT assign SHIFTR_VARIABLE = rand_a[1:0] ^ ({1'b0, SHIFTR_VARIABLE[1]} >> rand_b[0]); - `signal(SHIFTR_VARIABLE_2, 2); // UNOPTFLAT + `signal(SHIFTR_VARIABLE_2, 2); // UNOPTFLAT assign SHIFTR_VARIABLE_2 = rand_a[1:0] ^ ({1'b1, SHIFTR_VARIABLE_2[1]} >> rand_b[0]); - `signal(SHIFTR_VARIABLE_3_A, 4); // UNOPTFLAT + `signal(SHIFTR_VARIABLE_3_A, 4); // UNOPTFLAT `signal(SHIFTR_VARIABLE_3_B, 5); assign SHIFTR_VARIABLE_3_B = {4'b1111, SHIFTR_VARIABLE_3_A[1]} >> rand_b[0]; assign SHIFTR_VARIABLE_3_A = rand_a[3:0] ^ SHIFTR_VARIABLE_3_B[3:0]; - `signal(SHIFTL, 14); // UNOPTFLAT + `signal(SHIFTL, 14); // UNOPTFLAT assign SHIFTL = { - SHIFTL[6:5], // 13:12 - SHIFTL[7:6], // 11:10 - SHIFTL[5:4], // 9:8 - SHIFTL[3:0] << 2, // 7:4 - rand_a[3:0] // 3:0 + SHIFTL[6:5], // 13:12 + SHIFTL[7:6], // 11:10 + SHIFTL[5:4], // 9:8 + SHIFTL[3:0] << 2, // 7:4 + rand_a[3:0] // 3:0 }; - `signal(SHIFTL_2_A, 10); // UNOPTFLAT + `signal(SHIFTL_2_A, 10); // UNOPTFLAT wire logic [9:0] SHIFTL_2_B = SHIFTL_2_A << 2; assign SHIFTL_2_A = {SHIFTL_2_B[9:2], rand_a[1:0]}; @@ -172,34 +175,34 @@ module t ( wire logic [9:0] SHIFTL_3_B = SHIFTL_3_A << 10; assign SHIFTL_3_A = {SHIFTL_3_B[9:2], rand_a[1:0]}; - `signal(SHIFTL_VARIABLE, 2); // UNOPTFLAT + `signal(SHIFTL_VARIABLE, 2); // UNOPTFLAT assign SHIFTL_VARIABLE = rand_a[1:0] ^ ({SHIFTL_VARIABLE[0], 1'b0} << rand_b[0]); - `signal(SHIFTL_VARIABLE_2, 2); // UNOPTFLAT + `signal(SHIFTL_VARIABLE_2, 2); // UNOPTFLAT assign SHIFTL_VARIABLE_2 = rand_a[1:0] ^ ({SHIFTL_VARIABLE_2[0], 1'b1} << rand_b[0]); - `signal(SHIFTL_VARIABLE_3_A, 4); // UNOPTFLAT + `signal(SHIFTL_VARIABLE_3_A, 4); // UNOPTFLAT `signal(SHIFTL_VARIABLE_3_B, 5); assign SHIFTL_VARIABLE_3_B = {SHIFTL_VARIABLE_3_A[0], 4'b1111} << rand_b[0]; assign SHIFTL_VARIABLE_3_A = rand_a[3:0] ^ SHIFTL_VARIABLE_3_B[4:1]; - `signal(VAR_A, 2); // UNOPTFLAT + `signal(VAR_A, 2); // UNOPTFLAT wire logic [1:0] VAR_B; assign VAR_A = {rand_a[0], VAR_B[0]}; assign VAR_B = (VAR_A >> 1) ^ 2'(VAR_B[1]); - `signal(REPLICATE_1, 4); // UNOPTFLAT + `signal(REPLICATE_1, 4); // UNOPTFLAT assign REPLICATE_1 = rand_a[3:0] ^ ({2{REPLICATE_1[3:2]}} >> 2); - `signal(REPLICATE_2_A, 10); // UNOPTFLAT + `signal(REPLICATE_2_A, 10); // UNOPTFLAT wire logic [7:0] REPLICATE_2_B; assign REPLICATE_2_B = {4{REPLICATE_2_A[1:0]}}; assign REPLICATE_2_A = {^REPLICATE_2_A[8:0], REPLICATE_2_B, rand_a[0]}; - `signal(REPLICATE_3_A, 9); // UNOPTFLAT + `signal(REPLICATE_3_A, 9); // UNOPTFLAT assign REPLICATE_3_A = {{4{REPLICATE_3_A[1:0]}}, rand_a[0]}; - `signal(REPLICATE_4_A, 4); // UNOPTFLAT + `signal(REPLICATE_4_A, 4); // UNOPTFLAT wire logic [3:0] REPLICATE_4_B; assign REPLICATE_4_B = {2{REPLICATE_4_A[1:0]}}; assign REPLICATE_4_A = {REPLICATE_4_B[2:1], rand_a[1:0]}; @@ -214,26 +217,26 @@ module t ( `signal(REPLICATE_5, 4); assign REPLICATE_5 = replicate_5_int; - `signal(PARTIAL, 4); // UNOPTFLAT + `signal(PARTIAL, 4); // UNOPTFLAT assign PARTIAL[0] = rand_a[0]; // PARTIAL[1] intentionally unconnected assign PARTIAL[3:2] = rand_a[3:2] ^ {PARTIAL[2], PARTIAL[0]}; - wire [2:0] array_0 [2]; + wire [2:0] array_0[2]; assign array_0[0] = rand_a[2:0]; assign array_0[1] = array_0[0]; - `signal(ARRAY_0, 3); // UNOPTFLAT + `signal(ARRAY_0, 3); // UNOPTFLAT assign ARRAY_0 = array_0[1]; - wire [2:0] array_1 [1]; + wire [2:0] array_1[1]; assign array_1[0][0] = rand_a[0]; assign array_1[0][1] = array_1[0][0]; assign array_1[0][2] = array_1[0][1]; - `signal(ARRAY_1, 3); // UNOPTFLAT + `signal(ARRAY_1, 3); // UNOPTFLAT assign ARRAY_1 = array_1[0]; - wire [2:0] array_2a [2]; // UNOPTFLAT - wire [2:0] array_2b [2]; // UNOPTFLAT + wire [2:0] array_2a[2]; // UNOPTFLAT + wire [2:0] array_2b[2]; // UNOPTFLAT assign array_2a[0][0] = rand_a[0]; assign array_2a[0][1] = array_2b[1][0]; assign array_2a[0][2] = array_2b[1][1]; @@ -242,88 +245,88 @@ module t ( `signal(ARRAY_2, 3); assign ARRAY_2 = array_2a[0]; - wire [2:0] array_3 [2]; + wire [2:0] array_3[2]; assign array_3[0] = rand_a[2:0] ^ array_3[1] >> 1; assign array_3[1] = array_3[0]; - `signal(ARRAY_3, 3); // UNOPTFLAT + `signal(ARRAY_3, 3); // UNOPTFLAT assign ARRAY_3 = array_3[0]; - `signal(ADD_A, 8); // UNOPTFLAT + `signal(ADD_A, 8); // UNOPTFLAT `signal(ADD_B, 8); `signal(ADD_C, 8); assign ADD_C = rand_b[7:0] + ADD_B; assign ADD_B = (ADD_A << 4) + rand_a[7:0]; assign ADD_A = {ADD_C[7], 7'd0}; - `signal(SUB_A, 8); // UNOPTFLAT + `signal(SUB_A, 8); // UNOPTFLAT `signal(SUB_B, 8); `signal(SUB_C, 8); assign SUB_C = rand_b[7:0] - SUB_B; assign SUB_B = (SUB_A << 4) - rand_a[7:0]; assign SUB_A = {SUB_C[7], 7'd0}; - `signal(REDAND_A, 1); // UNOPTFLAT + `signal(REDAND_A, 1); // UNOPTFLAT `signal(REDAND_B, 3); assign REDAND_A = &(REDAND_B >> 1); assign REDAND_B = {rand_a[1:0], REDAND_A}; - `signal(REDOR_A, 1); // UNOPTFLAT + `signal(REDOR_A, 1); // UNOPTFLAT `signal(REDOR_B, 3); assign REDOR_A = |(REDOR_B >> 1); assign REDOR_B = {rand_a[1:0], REDOR_A}; - `signal(REDXOR_A, 1); // UNOPTFLAT + `signal(REDXOR_A, 1); // UNOPTFLAT `signal(REDXOR_B, 3); assign REDXOR_A = ^(REDXOR_B >> 1); assign REDXOR_B = {rand_a[1:0], REDXOR_A}; - `signal(EQ_A, 1); // UNOPTFLAT + `signal(EQ_A, 1); // UNOPTFLAT `signal(EQ_B, 3); assign EQ_A = EQ_B >> 1 == rand_b[2:0]; assign EQ_B = {rand_a[1:0], EQ_A}; - `signal(NEQ_A, 1); // UNOPTFLAT + `signal(NEQ_A, 1); // UNOPTFLAT `signal(NEQ_B, 3); assign NEQ_A = NEQ_B >> 1 != rand_b[2:0]; assign NEQ_B = {rand_a[1:0], NEQ_A}; - `signal(LT_A, 1); // UNOPTFLAT + `signal(LT_A, 1); // UNOPTFLAT `signal(LT_B, 3); assign LT_A = LT_B >> 1 < rand_b[2:0]; assign LT_B = {rand_a[1:0], LT_A}; - `signal(LTE_A, 1); // UNOPTFLAT + `signal(LTE_A, 1); // UNOPTFLAT `signal(LTE_B, 3); assign LTE_A = LTE_B >> 1 <= rand_b[2:0]; assign LTE_B = {rand_a[1:0], LTE_A}; - `signal(GT_A, 1); // UNOPTFLAT + `signal(GT_A, 1); // UNOPTFLAT `signal(GT_B, 3); assign GT_A = GT_B >> 1 > rand_b[2:0]; assign GT_B = {rand_a[1:0], GT_A}; - `signal(GTE_A, 1); // UNOPTFLAT + `signal(GTE_A, 1); // UNOPTFLAT `signal(GTE_B, 3); assign GTE_A = GTE_B >> 1 >= rand_b[2:0]; assign GTE_B = {rand_a[1:0], GTE_A}; - `signal(COND_THEN, 3); // UNOPTFLAT + `signal(COND_THEN, 3); // UNOPTFLAT assign COND_THEN = {rand_a[0], rand_a[0] ? 2'(COND_THEN << 2) : rand_b[1:0]}; - `signal(COND_ELSE, 3); // UNOPTFLAT + `signal(COND_ELSE, 3); // UNOPTFLAT assign COND_ELSE = {rand_a[0], rand_a[0] ? rand_b[1:0] : 2'(COND_ELSE << 2)}; - `signal(COND_COND, 3); // UNOPTFLAT + `signal(COND_COND, 3); // UNOPTFLAT assign COND_COND = {rand_a[0], (COND_COND >> 2) == 3'b001 ? rand_b[3:2] : rand_b[1:0]}; // verilator lint_off WIDTHTRUNC - `signal(COND_THEN_2, 3); // UNOPTFLAT + `signal(COND_THEN_2, 3); // UNOPTFLAT assign COND_THEN_2 = {rand_a[0], rand_a[1:0] ? 2'(COND_THEN_2 << 2) : rand_b[1:0]}; - `signal(COND_ELSE_2, 3); // UNOPTFLAT + `signal(COND_ELSE_2, 3); // UNOPTFLAT assign COND_ELSE_2 = {rand_a[0], rand_a[1:0] ? rand_b[1:0] : 2'(COND_ELSE_2 << 2)}; - `signal(COND_COND_2, 3); // UNOPTFLAT + `signal(COND_COND_2, 3); // UNOPTFLAT assign COND_COND_2 = {rand_a[0], COND_COND_2 >> 2 ? rand_b[3:2] : rand_b[1:0]}; // verilator lint_on WIDTHTRUNC @@ -335,7 +338,7 @@ module t ( always_0[0] = rand_a[0]; end assign always_0[1] = ~always_0[0]; - `signal(ALWAYS_0, 4); // UNOPTFLAT + `signal(ALWAYS_0, 4); // UNOPTFLAT assign ALWAYS_0 = always_0; // verilator lint_on ALWCOMBORDER @@ -347,7 +350,7 @@ module t ( always_1[3:2] = always_1[1:0]; end assign always_1[1] = always_1[0]; - `signal(ALWAYS_1, 5); // UNOPTFLAT + `signal(ALWAYS_1, 5); // UNOPTFLAT assign ALWAYS_1 = always_1; // verilator lint_on ALWCOMBORDER @@ -357,7 +360,7 @@ module t ( always_2[2:0] = 3'((always_2 << 1) | 4'(rand_a[0])); always_2[3] = rand_a[0]; end - `signal(ALWAYS_2, 4); // UNOPTFLAT + `signal(ALWAYS_2, 4); // UNOPTFLAT assign ALWAYS_2 = always_2; // verilator lint_on ALWCOMBORDER @@ -370,36 +373,36 @@ module t ( always_3[3] = |always_3[2:1]; end assign always_3[1] = always_3[0]; - `signal(ALWAYS_3, 5); // UNOPTFLAT + `signal(ALWAYS_3, 5); // UNOPTFLAT assign ALWAYS_3 = always_3; // verilator lint_on ALWCOMBORDER - logic [31:0] array_4[3]; // UNOPTFLAT + logic [31:0] array_4[3]; // UNOPTFLAT // Input assign array_4[0] = rand_a[31:0]; // Sums 1 - assign array_4[1][ 0 +: 3] = array_4[0][ 2 +: 2] + array_4[0][ 0 +: 2]; - assign array_4[1][ 3 +: 3] = array_4[0][ 6 +: 2] + array_4[0][ 4 +: 2]; - assign array_4[1][ 6 +: 3] = array_4[0][10 +: 2] + array_4[0][ 8 +: 2]; - assign array_4[1][ 9 +: 3] = array_4[0][14 +: 2] + array_4[0][12 +: 2]; - assign array_4[1][12 +: 3] = array_4[0][18 +: 2] + array_4[0][16 +: 2]; - assign array_4[1][15 +: 3] = array_4[0][22 +: 2] + array_4[0][20 +: 2]; - assign array_4[1][18 +: 3] = array_4[0][26 +: 2] + array_4[0][24 +: 2]; - assign array_4[1][21 +: 3] = array_4[0][30 +: 2] + array_4[0][28 +: 2]; + assign array_4[1][0+:3] = array_4[0][2+:2] + array_4[0][0+:2]; + assign array_4[1][3+:3] = array_4[0][6+:2] + array_4[0][4+:2]; + assign array_4[1][6+:3] = array_4[0][10+:2] + array_4[0][8+:2]; + assign array_4[1][9+:3] = array_4[0][14+:2] + array_4[0][12+:2]; + assign array_4[1][12+:3] = array_4[0][18+:2] + array_4[0][16+:2]; + assign array_4[1][15+:3] = array_4[0][22+:2] + array_4[0][20+:2]; + assign array_4[1][18+:3] = array_4[0][26+:2] + array_4[0][24+:2]; + assign array_4[1][21+:3] = array_4[0][30+:2] + array_4[0][28+:2]; // Sums 2 - assign array_4[2][ 0 +: 4] = array_4[1][ 3 +: 3] + array_4[1][ 0 +: 3]; - assign array_4[2][ 4 +: 4] = array_4[1][ 9 +: 3] + array_4[1][ 6 +: 3]; - assign array_4[2][ 8 +: 4] = array_4[1][15 +: 3] + array_4[1][12 +: 3]; - assign array_4[2][12 +: 4] = array_4[1][21 +: 3] + array_4[1][18 +: 3]; + assign array_4[2][0+:4] = array_4[1][3+:3] + array_4[1][0+:3]; + assign array_4[2][4+:4] = array_4[1][9+:3] + array_4[1][6+:3]; + assign array_4[2][8+:4] = array_4[1][15+:3] + array_4[1][12+:3]; + assign array_4[2][12+:4] = array_4[1][21+:3] + array_4[1][18+:3]; // Outupt `signal(ARRAY_4, 32); - assign ARRAY_4 = array_4[2]; + assign ARRAY_4 = array_4[2]; - logic [1:0] packed_0; // UNOPTFLAT - logic packed_0_lsb; + logic [1:0] packed_0; // UNOPTFLAT + logic packed_0_lsb; always_comb begin - packed_0[1] = rand_b[1]; - packed_0_lsb = packed_0[0]; + packed_0[1] = rand_b[1]; + packed_0_lsb = packed_0[0]; end always_comb packed_0[0] = rand_b[0]; assign PACKED_0 = packed_0; @@ -412,7 +415,7 @@ module t ( ////////////////////////////////////////////////////////////////////////// // verilator lint_off UNOPTFLAT - logic array_5 [0:6]; + logic array_5[0:6]; // Unconnected d[0:3] assign array_5[4] = array_5[0] ? array_5[0] : array_5[1]; assign array_5[5] = array_5[2] ? array_5[2] : array_5[3]; @@ -425,40 +428,40 @@ module t ( // Volatile variables ////////////////////////////////////////////////////////////////////////// - `signal(VOLATILE_PACKED_OUT_OF_CYCLE, 64); // UNOPTFLAT - wire logic [63:0] volatile_packed_out_of_cycle /* verilator forceable */ = rand_a; + `signal(VOLATILE_PACKED_OUT_OF_CYCLE, 64); // UNOPTFLAT + wire logic [63:0] volatile_packed_out_of_cycle /* verilator forceable */ = rand_a; assign VOLATILE_PACKED_OUT_OF_CYCLE = volatile_packed_out_of_cycle ^ 64'(VOLATILE_PACKED_OUT_OF_CYCLE[63:1]); - wire logic [2:0] volatile_packed_in_cycle /* verilator forceable */; // UNOPTFLAT + wire logic [2:0] volatile_packed_in_cycle /* verilator forceable */; // UNOPTFLAT // verilator lint_off UNOPTFLAT `signal(VOLATILE_PACKED_IN_CYCLE, 3); assign volatile_packed_in_cycle = rand_a[2:0] ^ 3'(volatile_packed_in_cycle[2:1]); assign VOLATILE_PACKED_IN_CYCLE = volatile_packed_in_cycle; // verilator lint_on - wire [2:0] volatile_array_out_of_cycle_a [2] /* verilator public_flat_rw */; + wire [2:0] volatile_array_out_of_cycle_a[2] /* verilator public_flat_rw */; assign volatile_array_out_of_cycle_a[0] = rand_a[2:0]; - wire [2:0] volatile_array_out_of_cycle_b [2]; + wire [2:0] volatile_array_out_of_cycle_b[2]; assign volatile_array_out_of_cycle_b[0] = volatile_array_out_of_cycle_a[0]; assign volatile_array_out_of_cycle_b[1] = volatile_array_out_of_cycle_b[0]; - `signal(VOLATILE_ARRAY_OUT_OF_CYCLE, 3); // UNOPTFLAT + `signal(VOLATILE_ARRAY_OUT_OF_CYCLE, 3); // UNOPTFLAT assign VOLATILE_ARRAY_OUT_OF_CYCLE = volatile_array_out_of_cycle_a[1]; // verilator lint_off UNOPTFLAT - wire [2:0] volatile_array_in_cycle_0 [2] /* verilator public_flat_rw */; + wire [2:0] volatile_array_in_cycle_0[2] /* verilator public_flat_rw */; assign volatile_array_in_cycle_0[0] = rand_a[2:0]; assign volatile_array_in_cycle_0[1] = volatile_array_in_cycle_0[0]; - `signal(VOLATILE_ARRAY_IN_CYCLE_0, 3); // UNOPTFLAT + `signal(VOLATILE_ARRAY_IN_CYCLE_0, 3); // UNOPTFLAT assign VOLATILE_ARRAY_IN_CYCLE_0 = volatile_array_in_cycle_0[1]; // verilator lint_on // verilator lint_off UNOPTFLAT - wire [2:0] volatile_array_in_cycle_1a [2] /* verilator public_flat_rw */; - wire [2:0] volatile_array_in_cycle_1b [2] /* verilator public_flat_rw */; + wire [2:0] volatile_array_in_cycle_1a[2] /* verilator public_flat_rw */; + wire [2:0] volatile_array_in_cycle_1b[2] /* verilator public_flat_rw */; assign volatile_array_in_cycle_1a[0] = rand_a[2:0]; assign volatile_array_in_cycle_1a[1] = volatile_array_in_cycle_1b[0]; assign volatile_array_in_cycle_1b = volatile_array_in_cycle_1a; - `signal(VOLATILE_ARRAY_IN_CYCLE_1, 3); // UNOPTFLAT + `signal(VOLATILE_ARRAY_IN_CYCLE_1, 3); // UNOPTFLAT assign VOLATILE_ARRAY_IN_CYCLE_1 = volatile_array_in_cycle_1a[1]; // verilator lint_on @@ -466,78 +469,78 @@ module t ( // Match masked ////////////////////////////////////////////////////////////////////////// - logic [63:0] match_masked; // UNOPTFLAT + logic [63:0] match_masked; // UNOPTFLAT always_comb begin casez (rand_a[31:0]) - 32'b????????_????????_????????_???????1 : match_masked[31:0] = 32'd00; - 32'b????????_????????_????????_??????1? : match_masked[31:0] = 32'd01; - 32'b????????_????????_????????_?????1?? : match_masked[31:0] = 32'd02; - 32'b????????_????????_????????_????1??? : match_masked[31:0] = 32'd03; - 32'b????????_????????_????????_???1???? : match_masked[31:0] = 32'd04; - 32'b????????_????????_????????_??1????? : match_masked[31:0] = 32'd05; - 32'b????????_????????_????????_?1?????? : match_masked[31:0] = 32'd06; - 32'b????????_????????_????????_1??????? : match_masked[31:0] = 32'd07; - 32'b????????_????????_???????1_???????? : match_masked[31:0] = 32'd08; - 32'b????????_????????_??????1?_???????? : match_masked[31:0] = 32'd09; - 32'b????????_????????_?????1??_???????? : match_masked[31:0] = 32'd10; - 32'b????????_????????_????1???_???????? : match_masked[31:0] = 32'd11; - 32'b????????_????????_???1????_???????? : match_masked[31:0] = 32'd12; - 32'b????????_????????_??1?????_???????? : match_masked[31:0] = 32'd13; - 32'b????????_????????_?1??????_???????? : match_masked[31:0] = 32'd14; - 32'b????????_????????_1???????_???????? : match_masked[31:0] = 32'd15; - 32'b????????_???????1_????????_???????? : match_masked[31:0] = 32'd16; - 32'b????????_??????1?_????????_???????? : match_masked[31:0] = 32'd17; - 32'b????????_?????1??_????????_???????? : match_masked[31:0] = 32'd18; - 32'b????????_????1???_????????_???????? : match_masked[31:0] = 32'd19; - 32'b????????_???1????_????????_???????? : match_masked[31:0] = 32'd20; - 32'b????????_??1?????_????????_???????? : match_masked[31:0] = 32'd21; - 32'b????????_?1??????_????????_???????? : match_masked[31:0] = 32'd22; - 32'b????????_1???????_????????_???????? : match_masked[31:0] = 32'd23; - 32'b???????1_????????_????????_???????? : match_masked[31:0] = 32'd24; - 32'b??????1?_????????_????????_???????? : match_masked[31:0] = 32'd25; - 32'b?????1??_????????_????????_???????? : match_masked[31:0] = 32'd26; - 32'b????1???_????????_????????_???????? : match_masked[31:0] = 32'd27; - 32'b???1????_????????_????????_???????? : match_masked[31:0] = 32'd28; - 32'b??1?????_????????_????????_???????? : match_masked[31:0] = 32'd29; - 32'b?1??????_????????_????????_???????? : match_masked[31:0] = 32'd30; - 32'b1???????_????????_????????_???????? : match_masked[31:0] = 32'd31; - default : match_masked[31:0] = '1; + 32'b????????_????????_????????_???????1: match_masked[31:0] = 32'd00; + 32'b????????_????????_????????_??????1?: match_masked[31:0] = 32'd01; + 32'b????????_????????_????????_?????1??: match_masked[31:0] = 32'd02; + 32'b????????_????????_????????_????1???: match_masked[31:0] = 32'd03; + 32'b????????_????????_????????_???1????: match_masked[31:0] = 32'd04; + 32'b????????_????????_????????_??1?????: match_masked[31:0] = 32'd05; + 32'b????????_????????_????????_?1??????: match_masked[31:0] = 32'd06; + 32'b????????_????????_????????_1???????: match_masked[31:0] = 32'd07; + 32'b????????_????????_???????1_????????: match_masked[31:0] = 32'd08; + 32'b????????_????????_??????1?_????????: match_masked[31:0] = 32'd09; + 32'b????????_????????_?????1??_????????: match_masked[31:0] = 32'd10; + 32'b????????_????????_????1???_????????: match_masked[31:0] = 32'd11; + 32'b????????_????????_???1????_????????: match_masked[31:0] = 32'd12; + 32'b????????_????????_??1?????_????????: match_masked[31:0] = 32'd13; + 32'b????????_????????_?1??????_????????: match_masked[31:0] = 32'd14; + 32'b????????_????????_1???????_????????: match_masked[31:0] = 32'd15; + 32'b????????_???????1_????????_????????: match_masked[31:0] = 32'd16; + 32'b????????_??????1?_????????_????????: match_masked[31:0] = 32'd17; + 32'b????????_?????1??_????????_????????: match_masked[31:0] = 32'd18; + 32'b????????_????1???_????????_????????: match_masked[31:0] = 32'd19; + 32'b????????_???1????_????????_????????: match_masked[31:0] = 32'd20; + 32'b????????_??1?????_????????_????????: match_masked[31:0] = 32'd21; + 32'b????????_?1??????_????????_????????: match_masked[31:0] = 32'd22; + 32'b????????_1???????_????????_????????: match_masked[31:0] = 32'd23; + 32'b???????1_????????_????????_????????: match_masked[31:0] = 32'd24; + 32'b??????1?_????????_????????_????????: match_masked[31:0] = 32'd25; + 32'b?????1??_????????_????????_????????: match_masked[31:0] = 32'd26; + 32'b????1???_????????_????????_????????: match_masked[31:0] = 32'd27; + 32'b???1????_????????_????????_????????: match_masked[31:0] = 32'd28; + 32'b??1?????_????????_????????_????????: match_masked[31:0] = 32'd29; + 32'b?1??????_????????_????????_????????: match_masked[31:0] = 32'd30; + 32'b1???????_????????_????????_????????: match_masked[31:0] = 32'd31; + default: match_masked[31:0] = '1; endcase end always_comb begin casez (match_masked[31:0]) - 32'd00 : match_masked[63:32] = 32'b00000000_00000000_00000000_00000001; - 32'd01 : match_masked[63:32] = 32'b00000000_00000000_00000000_00000010; - 32'd02 : match_masked[63:32] = 32'b00000000_00000000_00000000_00000100; - 32'd03 : match_masked[63:32] = 32'b00000000_00000000_00000000_00001000; - 32'd04 : match_masked[63:32] = 32'b00000000_00000000_00000000_00010000; - 32'd05 : match_masked[63:32] = 32'b00000000_00000000_00000000_00100000; - 32'd06 : match_masked[63:32] = 32'b00000000_00000000_00000000_01000000; - 32'd07 : match_masked[63:32] = 32'b00000000_00000000_00000000_10000000; - 32'd08 : match_masked[63:32] = 32'b00000000_00000000_00000001_00000000; - 32'd09 : match_masked[63:32] = 32'b00000000_00000000_00000010_00000000; - 32'd10 : match_masked[63:32] = 32'b00000000_00000000_00000100_00000000; - 32'd11 : match_masked[63:32] = 32'b00000000_00000000_00001000_00000000; - 32'd12 : match_masked[63:32] = 32'b00000000_00000000_00010000_00000000; - 32'd13 : match_masked[63:32] = 32'b00000000_00000000_00100000_00000000; - 32'd14 : match_masked[63:32] = 32'b00000000_00000000_01000000_00000000; - 32'd15 : match_masked[63:32] = 32'b00000000_00000000_10000000_00000000; - 32'd16 : match_masked[63:32] = 32'b00000000_00000001_00000000_00000000; - 32'd17 : match_masked[63:32] = 32'b00000000_00000010_00000000_00000000; - 32'd18 : match_masked[63:32] = 32'b00000000_00000100_00000000_00000000; - 32'd19 : match_masked[63:32] = 32'b00000000_00001000_00000000_00000000; - 32'd20 : match_masked[63:32] = 32'b00000000_00010000_00000000_00000000; - 32'd21 : match_masked[63:32] = 32'b00000000_00100000_00000000_00000000; - 32'd22 : match_masked[63:32] = 32'b00000000_01000000_00000000_00000000; - 32'd23 : match_masked[63:32] = 32'b00000000_10000000_00000000_00000000; - 32'd24 : match_masked[63:32] = 32'b00000001_00000000_00000000_00000000; - 32'd25 : match_masked[63:32] = 32'b00000010_00000000_00000000_00000000; - 32'd26 : match_masked[63:32] = 32'b00000100_00000000_00000000_00000000; - 32'd27 : match_masked[63:32] = 32'b00001000_00000000_00000000_00000000; - 32'd28 : match_masked[63:32] = 32'b00010000_00000000_00000000_00000000; - 32'd29 : match_masked[63:32] = 32'b00100000_00000000_00000000_00000000; - 32'd30 : match_masked[63:32] = 32'b01000000_00000000_00000000_00000000; - 32'd31 : match_masked[63:32] = 32'b10000000_00000000_00000000_00000000; + 32'd00: match_masked[63:32] = 32'b00000000_00000000_00000000_00000001; + 32'd01: match_masked[63:32] = 32'b00000000_00000000_00000000_00000010; + 32'd02: match_masked[63:32] = 32'b00000000_00000000_00000000_00000100; + 32'd03: match_masked[63:32] = 32'b00000000_00000000_00000000_00001000; + 32'd04: match_masked[63:32] = 32'b00000000_00000000_00000000_00010000; + 32'd05: match_masked[63:32] = 32'b00000000_00000000_00000000_00100000; + 32'd06: match_masked[63:32] = 32'b00000000_00000000_00000000_01000000; + 32'd07: match_masked[63:32] = 32'b00000000_00000000_00000000_10000000; + 32'd08: match_masked[63:32] = 32'b00000000_00000000_00000001_00000000; + 32'd09: match_masked[63:32] = 32'b00000000_00000000_00000010_00000000; + 32'd10: match_masked[63:32] = 32'b00000000_00000000_00000100_00000000; + 32'd11: match_masked[63:32] = 32'b00000000_00000000_00001000_00000000; + 32'd12: match_masked[63:32] = 32'b00000000_00000000_00010000_00000000; + 32'd13: match_masked[63:32] = 32'b00000000_00000000_00100000_00000000; + 32'd14: match_masked[63:32] = 32'b00000000_00000000_01000000_00000000; + 32'd15: match_masked[63:32] = 32'b00000000_00000000_10000000_00000000; + 32'd16: match_masked[63:32] = 32'b00000000_00000001_00000000_00000000; + 32'd17: match_masked[63:32] = 32'b00000000_00000010_00000000_00000000; + 32'd18: match_masked[63:32] = 32'b00000000_00000100_00000000_00000000; + 32'd19: match_masked[63:32] = 32'b00000000_00001000_00000000_00000000; + 32'd20: match_masked[63:32] = 32'b00000000_00010000_00000000_00000000; + 32'd21: match_masked[63:32] = 32'b00000000_00100000_00000000_00000000; + 32'd22: match_masked[63:32] = 32'b00000000_01000000_00000000_00000000; + 32'd23: match_masked[63:32] = 32'b00000000_10000000_00000000_00000000; + 32'd24: match_masked[63:32] = 32'b00000001_00000000_00000000_00000000; + 32'd25: match_masked[63:32] = 32'b00000010_00000000_00000000_00000000; + 32'd26: match_masked[63:32] = 32'b00000100_00000000_00000000_00000000; + 32'd27: match_masked[63:32] = 32'b00001000_00000000_00000000_00000000; + 32'd28: match_masked[63:32] = 32'b00010000_00000000_00000000_00000000; + 32'd29: match_masked[63:32] = 32'b00100000_00000000_00000000_00000000; + 32'd30: match_masked[63:32] = 32'b01000000_00000000_00000000_00000000; + 32'd31: match_masked[63:32] = 32'b10000000_00000000_00000000_00000000; default: match_masked[63:32] = 32'b00000000_00000000_00000000_00000000; endcase end diff --git a/test_regress/t/t_dfg_break_cycles_deep.v b/test_regress/t/t_dfg_break_cycles_deep.v index 16b62940b..eac23d5c0 100644 --- a/test_regress/t/t_dfg_break_cycles_deep.v +++ b/test_regress/t/t_dfg_break_cycles_deep.v @@ -11,9 +11,9 @@ // (acyclic) bits through the whole Concat chain. module prim ( - input logic i, - output logic o - ); + input logic i, + output logic o +); assign o = !(!i); endmodule @@ -37,7 +37,10 @@ module t; for (genvar i = 0; i < WIDTH; ++i) begin : gen_width assign arr[i][0] = din[i]; for (genvar j = 0; j < DEPTH; ++j) begin : gen_depth - prim u_prim (.i(arr[i][j]), .o(arr[i][j+1])); + prim u_prim ( + .i(arr[i][j]), + .o(arr[i][j+1]) + ); end end endgenerate @@ -54,7 +57,7 @@ module t; always @(posedge clk) begin cyc <= cyc + 1; din <= WIDTH'(cyc); - for (int i = 0; i < WIDTH; ++i) sel[i] <= $clog2(DEPTH+1)'((cyc * 7 + i) % (DEPTH + 1)); + for (int i = 0; i < WIDTH; ++i) sel[i] <= $clog2(DEPTH + 1)'((cyc * 7 + i) % (DEPTH + 1)); // The chain is a buffer, so every element equals the driving input bit if (cyc > 1) begin if (dout !== din) begin diff --git a/test_regress/t/t_dfg_synthesis.v b/test_regress/t/t_dfg_synthesis.v index c13d4f47c..27995571e 100644 --- a/test_regress/t/t_dfg_synthesis.v +++ b/test_regress/t/t_dfg_synthesis.v @@ -14,39 +14,50 @@ package pkg; function automatic logic [7:0] branchy(input logic [7:0] a, input logic [7:0] b); if (a[0]) begin return b + 8'd1; - end else if (a[1]) begin + end + else if (a[1]) begin return b + 8'd2; - end else if (a[2]) begin + end + else if (a[2]) begin return b + 8'd3; - end else if (a[3]) begin + end + else if (a[3]) begin return b + 8'd4; - end else if (a[4]) begin + end + else if (a[4]) begin return b + 8'd5; - end else if (a[5]) begin + end + else if (a[5]) begin return b + 8'd6; - end else if (a[6]) begin + end + else if (a[6]) begin return b + 8'd7; - end else if (a[7]) begin + end + else if (a[7]) begin return b + 8'd8; - end else begin + end + else begin return b; end endfunction endpackage module t ( -`include "portlist.vh" // Boilerplate generated by t_dfg_break_cycles.py - rand_a, rand_b, srand_a, srand_b + `include "portlist.vh" // Boilerplate generated by t_dfg_break_cycles.py + rand_a, + rand_b, + srand_a, + srand_b ); -`include "portdecl.vh" // Boilerplate generated by t_dfg_break_cycles.py + `include "portdecl.vh" // Boilerplate generated by t_dfg_break_cycles.py input rand_a; input rand_b; input srand_a; input srand_b; - wire logic [63:0] rand_a; - wire logic [63:0] rand_b; + wire logic [63:0] rand_a; + wire logic [63:0] rand_b; wire logic signed [63:0] srand_a; wire logic signed [63:0] srand_b; @@ -62,9 +73,9 @@ module t ( logic [1:0] reassign; always_comb begin - reassign[0] = rand_a[0]; + reassign[0] = rand_a[0]; reassign[0] = ~rand_a[0]; - reassign[1] = rand_a[1]; + reassign[1] = rand_a[1]; reassign[1] = ~rand_a[1]; end `signal(REASSIGN, reassign); @@ -72,9 +83,9 @@ module t ( logic [1:0] use_intermediate_a; logic [1:0] use_intermediate_b; always_comb begin - use_intermediate_a[0] = rand_a[0]; + use_intermediate_a[0] = rand_a[0]; use_intermediate_b[0] = ~use_intermediate_a[0]; - use_intermediate_a[1] = rand_a[1]; + use_intermediate_a[1] = rand_a[1]; use_intermediate_a[0] = ~rand_a[0]; use_intermediate_b[1] = ~use_intermediate_a[1]; use_intermediate_a[1] = ~rand_a[1]; @@ -113,7 +124,8 @@ module t ( conditional_a = 4'd0; if (rand_a[0]) begin conditional_a = rand_b[3:0]; - end else begin + end + else begin conditional_a = ~rand_b[3:0]; end end @@ -130,7 +142,7 @@ module t ( // verilator lint_off LATCH logic [3:0] conditional_c; - always_comb begin // nosynth + always_comb begin // nosynth if (rand_a[0]) begin conditional_c = rand_b[3:0]; end @@ -145,9 +157,11 @@ module t ( always_comb begin if (rand_a[0]) begin conditional_d = rand_b[3:0]; - end else if (rand_a[1]) begin + end + else if (rand_a[1]) begin conditional_d = ~rand_b[3:0]; - end else begin + end + else begin conditional_d = rand_b[7:4]; end end @@ -158,10 +172,12 @@ module t ( conditional_e = 4'd0; if (rand_a[0]) begin conditional_e = rand_b[3:0]; - end else begin + end + else begin if (rand_a[1]) begin conditional_e = rand_b[3:0]; - end else begin + end + else begin conditional_e = rand_b[7:4]; end conditional_e = ~conditional_e; @@ -176,7 +192,8 @@ module t ( if (rand_b[1]) begin condigional_f = rand_a[0]; end - end else begin + end + else begin condigional_f = 1'b0; end end @@ -188,27 +205,34 @@ module t ( if (rand_a[1]) begin if (rand_a[2]) begin conditional_g = 3'b111; - end else begin + end + else begin conditional_g = 3'b011; end - end else begin + end + else begin if (rand_a[2]) begin conditional_g = 3'b101; - end else begin + end + else begin conditional_g = 3'b001; end end - end else begin + end + else begin if (rand_a[1]) begin if (rand_a[2]) begin conditional_g = 3'b110; - end else begin + end + else begin conditional_g = 3'b010; end - end else begin + end + else begin if (rand_a[2]) begin conditional_g = 3'b100; - end else begin + end + else begin conditional_g = 3'b000; end end @@ -224,19 +248,22 @@ module t ( if (rand_a[2]) begin conditional_h = 3'b111; end - end else begin + end + else begin conditional_h = 3'b001; if (rand_a[2]) begin conditional_h = 3'b101; end end - end else begin + end + else begin if (rand_a[1]) begin conditional_h = 3'b010; if (rand_a[2]) begin conditional_h = 3'b110; end - end else begin + end + else begin conditional_h = 3'b000; if (rand_a[2]) begin conditional_h = 3'b100; @@ -247,7 +274,7 @@ module t ( `signal(CONDITONAL_H, conditional_h); logic [2:0] conditional_i; - always_comb begin // Dumbass trailing zeroes count + always_comb begin // Dumbass trailing zeroes count do begin conditional_i = 3'd0; if (rand_a[0]) break; @@ -263,22 +290,25 @@ module t ( `signal(CONDITONAL_I, conditional_i); logic [2:0] conditional_j; - always_comb begin // Even more dumbass trailing ones count + always_comb begin // Even more dumbass trailing ones count do begin conditional_j = 3'd0; if (rand_a[0]) begin conditional_j = 3'd1; - end else begin + end + else begin break; end if (rand_a[1]) begin conditional_j = 3'd2; - end else begin + end + else begin break; end if (rand_a[2]) begin conditional_j = 3'd3; - end else begin + end + else begin break; end if (rand_a[3]) begin @@ -302,22 +332,26 @@ module t ( if (rand_a[3]) break; conditional_k = 3'd4; end while (0); - end else begin + end + else begin do begin conditional_k = 3'd0; if (rand_a[0]) begin conditional_k = 3'd1; - end else begin + end + else begin break; end if (rand_a[1]) begin conditional_k = 3'd2; - end else begin + end + else begin break; end if (rand_a[2]) begin conditional_k = 3'd3; - end else begin + end + else begin break; end if (rand_a[3]) begin @@ -357,7 +391,8 @@ module t ( partial_conditional_a[1:0] = 2'd0; if (rand_a[0]) begin partial_conditional_a[0] = rand_b[0]; - end else begin + end + else begin partial_conditional_a[1] = rand_b[1]; end partial_conditional_a[4:3] = rand_b[4:3]; @@ -389,7 +424,7 @@ module t ( // verilator lint_off LATCH logic [3:0] latch_a; logic [3:0] latch_b; - always_comb begin // nosynth + always_comb begin // nosynth if (rand_b[0]) begin latch_a[3:1] = ~rand_a[3:1]; end @@ -403,16 +438,17 @@ module t ( logic static_temporary_a; logic static_temporary_b; logic static_temporary_tmp; - always_comb begin // revert + always_comb begin // revert static_temporary_tmp = rand_a[0]; static_temporary_a = ~static_temporary_tmp; end - always_comb begin // revert + always_comb begin // revert static_temporary_tmp = static_temporary_a; static_temporary_b = ~static_temporary_tmp; end // verilator lint_on MULTIDRIVEN - `signal(STATIC_TEMPORARY, {static_temporary_tmp, static_temporary_b, static_temporary_a, rand_a[0]}); + `signal(STATIC_TEMPORARY, { + static_temporary_tmp, static_temporary_b, static_temporary_a, rand_a[0]}); logic [2:0] partial_temporary_a; logic [2:0] partial_temporary_tmp; @@ -440,41 +476,45 @@ module t ( assign circular_0_z = circular_0_x & rand_a[0]; `signal(CIRCULAR_0, {circular_0_x, circular_0_y, circular_0_z}); - logic [2:0] nsp_a; // Non series-parallel CFG + logic [2:0] nsp_a; // Non series-parallel CFG always_comb begin do begin - nsp_a = 3'd0; // BB 0 -> BB 1 / BB 2 + nsp_a = 3'd0; // BB 0 -> BB 1 / BB 2 if (rand_a[1:0] == 2'd0) begin - nsp_a = 3'd1; // BB 1 -> BB 4 - end else begin - nsp_a = 3'd2; // BB 2 -> BB 3 / BB 4 + nsp_a = 3'd1; // BB 1 -> BB 4 + end + else begin + nsp_a = 3'd2; // BB 2 -> BB 3 / BB 4 if (rand_a[1:0] == 2'd1) begin - nsp_a = 3'd3; // BB3 -> BB 5 + nsp_a = 3'd3; // BB3 -> BB 5 break; end end - nsp_a = 3'd4; // BB 4 -> BB 5 + nsp_a = 3'd4; // BB 4 -> BB 5 end while (0); //nsp_a = 3'd5; // BB 5 end `signal(NSP_A, nsp_a); - logic [2:0] nsp_b; // Non series-parallel CFG + logic [2:0] nsp_b; // Non series-parallel CFG always_comb begin do begin nsp_b = 3'd0; if (rand_a[1:0] == 2'd0) begin nsp_b = 3'd1; - end else begin + end + else begin nsp_b = 3'd2; if (rand_a[1:0] == 2'd1) begin nsp_b = 3'd3; break; - end else begin + end + else begin nsp_b = 3'd4; if (rand_a[1:0] == 2'd2) begin nsp_b = 3'd5; - end else begin + end + else begin nsp_b = 3'd6; break; end @@ -485,7 +525,7 @@ module t ( end `signal(NSP_B, nsp_b); - logic [2:0] part_sp_a; // Contains series-parallel sub-graph CFG + logic [2:0] part_sp_a; // Contains series-parallel sub-graph CFG always_comb begin do begin part_sp_a = 3'd0; @@ -494,7 +534,8 @@ module t ( if (rand_a[1]) begin part_sp_a = 3'd2; end - end else begin + end + else begin part_sp_a = 3'd3; if (rand_a[2]) begin part_sp_a = 3'd4; @@ -518,7 +559,8 @@ module t ( if (rand_a[0]) begin both_break = 2'd0; break; - end else begin + end + else begin both_break = 2'd1; break; end @@ -526,7 +568,7 @@ module t ( if (rand_a[1]) begin both_break = 2'd2; end - end while(0); + end while (0); end `signal(BOTH_BREAK, both_break); @@ -572,12 +614,12 @@ module t ( logic [1:0] via_creset; always_comb begin - automatic logic [1:0] a /* = AstCReset */; + automatic logic [1:0] a /* = AstCReset */; via_creset = a + 2'd1; end `signal(VIA_CRESET, via_creset); - logic [1:0] LUT [2] = '{0: 2'b11, 1: 2'b10}; + logic [1:0] LUT[2] = '{0: 2'b11, 1: 2'b10}; logic [1:0] array_read; always_comb begin array_read = 2'd0; diff --git a/test_regress/t/t_display.v b/test_regress/t/t_display.v index 942bc8f3f..1dc3bab3d 100644 --- a/test_regress/t/t_display.v +++ b/test_regress/t/t_display.v @@ -199,7 +199,7 @@ z\nq"; two", "one two"); // Str check -`ifndef NC // NC-Verilog 5.3 chokes on this test +`ifndef NC // NC-Verilog 5.3 chokes on this test if (str !== 32'h00_bf_11_0a) $stop; `endif @@ -266,7 +266,7 @@ module sub; task write_m; $write("[%0t] In %m (%l)\n", $time); begin : subblock - $write("[%0t] In %M (%L)\n", $time); // Uppercase %M test + $write("[%0t] In %M (%L)\n", $time); // Uppercase %M test end endtask endmodule diff --git a/test_regress/t/t_func_endian.v b/test_regress/t/t_func_endian.v index 255b9d460..f782f71c1 100644 --- a/test_regress/t/t_func_endian.v +++ b/test_regress/t/t_func_endian.v @@ -19,17 +19,18 @@ module t ( /*AUTOWIRE*/ // Beginning of automatic wires (for undeclared instantiated-module outputs) - wire [31:0] out; // From test of Test.v + wire [31:0] out; // From test of Test.v // End of automatics Test test ( /*AUTOINST*/ - // Outputs - .out (out[31:0]), - // Inputs - .clk (clk), - .noswap (noswap), - .nibble (nibble), - .in (in[31:0])); + // Outputs + .out(out[31:0]), + // Inputs + .clk(clk), + .noswap(noswap), + .nibble(nibble), + .in(in[31:0]) + ); // Aggregate outputs into a single result vector wire [63:0] result = {32'h0, out}; @@ -63,11 +64,14 @@ module t ( endmodule module Test ( /*AUTOARG*/ - // Outputs - out, - // Inputs - clk, noswap, nibble, in - ); + // Outputs + out, + // Inputs + clk, + noswap, + nibble, + in +); input clk; input noswap; diff --git a/test_regress/t/t_func_under2.v b/test_regress/t/t_func_under2.v index 044f21a88..566c993a3 100644 --- a/test_regress/t/t_func_under2.v +++ b/test_regress/t/t_func_under2.v @@ -6,16 +6,16 @@ // bug598 -module t (/*AUTOARG*/ - // Outputs - val, - // Inputs - clk - ); +module t ( /*AUTOARG*/ + // Outputs + val, + // Inputs + clk +); - input clk; - output integer val; - integer dbg_addr = 0; + input clk; + output integer val; + integer dbg_addr = 0; function func1; input en; @@ -24,19 +24,19 @@ module t (/*AUTOARG*/ endfunction function func2; - input en; + input en; input [31:0] a; func2 = en && (a == 2); endfunction always @(posedge clk) begin - case( 1'b1 ) + case (1'b1) // This line is OK: - func1(1'b1, dbg_addr) : val = 1; + func1(1'b1, dbg_addr): val = 1; // This fails: // %Error: Internal Error: test.v:23: ../V3Task.cpp:993: Function not underneath a statement - func2(1'b1, dbg_addr) : val = 2; - default : val = 0; + func2(1'b1, dbg_addr): val = 2; + default: val = 0; endcase // $write("*-* All Finished *-*\n"); diff --git a/test_regress/t/t_gate_elim_cycle.v b/test_regress/t/t_gate_elim_cycle.v index 8885eb608..ba1e04160 100644 --- a/test_regress/t/t_gate_elim_cycle.v +++ b/test_regress/t/t_gate_elim_cycle.v @@ -4,30 +4,31 @@ // SPDX-FileCopyrightText: 2025 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 -module GND(output G); +module GND ( + output G +); assign G = 0; endmodule -module CARRY2( - output [1:0] CO, - input CI, - input [1:0] DI, S +module CARRY2 ( + output [1:0] CO, + input CI, + input [1:0] DI, + S ); - assign CO[0] = S[0] ? CI : DI[0]; + assign CO[0] = S[0] ? CI : DI[0]; assign CO[1] = S[1] ? CO[0] : DI[1]; endmodule module A; wire const0; wire ci; - GND GND ( - .G(const0) - ); + GND GND (.G(const0)); CARRY2 CARRY2 ( - .CO(), + .CO(), - .CI(ci), - .DI({const0,const0}), - .S({const0,const0}) + .CI(ci), + .DI({const0, const0}), + .S({const0, const0}) ); endmodule diff --git a/test_regress/t/t_iface_typedef_capture_uaf.v b/test_regress/t/t_iface_typedef_capture_uaf.v index 97c4b4dde..d551a4ac0 100644 --- a/test_regress/t/t_iface_typedef_capture_uaf.v +++ b/test_regress/t/t_iface_typedef_capture_uaf.v @@ -49,7 +49,8 @@ module genif_body #( request_t internal_req; assign internal_req = master.req; always_comb slave.req = internal_req; - end else begin : gen_off + end + else begin : gen_off always_comb slave.req = '0; end endmodule @@ -69,8 +70,18 @@ module t; avmm_if #(.DW(64)) off_m_if (); avmm_if #(.DW(64)) off_s_if (); // ENABLE=0 deletes the generate branch holding the captured typedef - genif_body #(.ENABLE(1)) body_on (.master(on_m_if), .slave(on_s_if)); - genif_body #(.ENABLE(0)) body_off (.master(off_m_if), .slave(off_s_if)); + genif_body #( + .ENABLE(1) + ) body_on ( + .master(on_m_if), + .slave(on_s_if) + ); + genif_body #( + .ENABLE(0) + ) body_off ( + .master(off_m_if), + .slave(off_s_if) + ); initial begin #1; diff --git a/test_regress/t/t_interface_modport_expr.v b/test_regress/t/t_interface_modport_expr.v index 3e2f39689..30f6f0e65 100644 --- a/test_regress/t/t_interface_modport_expr.v +++ b/test_regress/t/t_interface_modport_expr.v @@ -60,10 +60,10 @@ module top (); initial begin #1; - `checkh(myIf.sig_b, 8'h42); // mp1: b = a - `checkh(myIf.sig_d, 8'hAB); // mp2: b = a - `checkh(myIf.sig_f, 8'hCD); // mp3: f = sig_e - `checkh(myIf.m3, 8'hFF); // mp4: out = in1 ^ in2 + `checkh(myIf.sig_b, 8'h42); // mp1: b = a + `checkh(myIf.sig_d, 8'hAB); // mp2: b = a + `checkh(myIf.sig_f, 8'hCD); // mp3: f = sig_e + `checkh(myIf.m3, 8'hFF); // mp4: out = in1 ^ in2 #1; $write("*-* All Finished *-*\n"); $finish; diff --git a/test_regress/t/t_math_concat64.v b/test_regress/t/t_math_concat64.v index 6a38e92ba..9de494722 100644 --- a/test_regress/t/t_math_concat64.v +++ b/test_regress/t/t_math_concat64.v @@ -4,20 +4,20 @@ // SPDX-FileCopyrightText: 2005 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 -module t (/*AUTOARG*/ - // Inputs - clk - ); +module t ( /*AUTOARG*/ + // Inputs + clk +); input clk; integer cyc; initial cyc = 1; - reg [127:0] i; + reg [127:0] i; wire [127:0] q1; wire [127:0] q32; wire [127:0] q64; - wire [ 63:0] q64_low; + wire [63:0] q64_low; // verilog_format: off assign q1 = { diff --git a/test_regress/t/t_math_cond_huge.v b/test_regress/t/t_math_cond_huge.v index 6f4c58340..8d978f43c 100644 --- a/test_regress/t/t_math_cond_huge.v +++ b/test_regress/t/t_math_cond_huge.v @@ -4,19 +4,17 @@ // SPDX-FileCopyrightText: 2008 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 -module t (/*AUTOARG*/ - // Inputs - clk - ); - input clk; +module t ( + input clk +); - integer cyc = 0; - reg [63:0] crc; - reg [63:0] sum; + integer cyc = 0; + reg [63:0] crc; + reg [63:0] sum; // Take CRC data and apply to testblock inputs - wire [7:0] sel = crc[7:0]; - wire [255+3:0] in = {crc[2:0],crc,crc,crc,crc}; + wire [7:0] sel = crc[7:0]; + wire [255+3:0] in = {crc[2:0],crc,crc,crc,crc}; /*AUTOWIRE*/ // Beginning of automatic wires (for undeclared instantiated-module outputs) @@ -323,12 +321,12 @@ module t (/*AUTOARG*/ endmodule -module Test - ( output wire [3:0] out, +module Test ( + output wire [3:0] out, - input [7:0] sel, + input [7:0] sel, - // verilog_format: off + // verilog_format: off input [3:0] i0, i1, i2, i3, i4, i5, i6, i7, i8, i9, i10, i11, i12, i13, i14, i15, i16, i17, i18, i19, i20, i21, i22, i23, i24, i25, i26, i27, i28, i29, i30, i31, i32, i33, i34, i35, i36, i37, i38, i39, i40, i41, i42, i43, i44, i45, i46, i47, i48, i49, i50, @@ -347,7 +345,7 @@ module Test i228, i229, i230, i231, i232, i233, i234, i235, i236, i237, i238, i239, i240, i241, i242, i243, i244, i245, i246, i247, i248, i249, i250, i251, i252, i253, i254, i255 // verilog_format: on - ); +); assign out = (sel==8'h00) ? i0 : (sel==8'h01) ? i1 : (sel==8'h02) ? i2 : (sel==8'h03) ? i3 diff --git a/test_regress/t/t_math_signed2.v b/test_regress/t/t_math_signed2.v index 560686be1..4068b2a89 100644 --- a/test_regress/t/t_math_signed2.v +++ b/test_regress/t/t_math_signed2.v @@ -4,64 +4,59 @@ // SPDX-FileCopyrightText: 2007 Peter Debacker // SPDX-License-Identifier: CC0-1.0 -module t (/*AUTOARG*/ - // Inputs - clk - ); - input clk; +module t ( + input clk +); - reg [10:0] in; - reg signed[7:0] min; - reg signed[7:0] max; - wire signed[7:0] filtered_data; - reg signed[7:0] delay_minmax[31:0]; + reg [10:0] in; + reg signed [7:0] min; + reg signed [7:0] max; + wire signed [7:0] filtered_data; + reg signed [7:0] delay_minmax[31:0]; integer k; initial begin in = 11'b10000001000; - for(k=0;k<32;k=k+1) - delay_minmax[k] = 0; + for (k = 0; k < 32; k = k + 1) delay_minmax[k] = 0; end - assign filtered_data = $signed(in[10:3]); + assign filtered_data = $signed(in[10:3]); - always @(posedge clk) begin - in = in + 8; + always @(posedge clk) begin + in = in + 8; `ifdef TEST_VERBOSE - $write("filtered_data: %d\n", filtered_data); + $write("filtered_data: %d\n", filtered_data); `endif - // delay line shift - for (k=31;k>0;k=k-1) begin - delay_minmax[k] = delay_minmax[k-1]; - end - delay_minmax[0] = filtered_data; + // delay line shift + for (k = 31; k > 0; k = k - 1) begin + delay_minmax[k] = delay_minmax[k-1]; + end + delay_minmax[0] = filtered_data; `ifdef TEST_VERBOSE - $write("delay_minmax[0] = %d\n", delay_minmax[0]); - $write("delay_minmax[31] = %d\n", delay_minmax[31]); + $write("delay_minmax[0] = %d\n", delay_minmax[0]); + $write("delay_minmax[31] = %d\n", delay_minmax[31]); `endif - // find min and max - min = 127; - max = -128; + // find min and max + min = 127; + max = -128; `ifdef TEST_VERBOSE - $write("max init: %d\n", max); - $write("min init: %d\n", min); + $write("max init: %d\n", max); + $write("min init: %d\n", min); `endif - for(k=0;k<32;k=k+1) begin - if ((delay_minmax[k]) > $signed(max)) - max = delay_minmax[k]; - if ((delay_minmax[k]) < $signed(min)) - min = delay_minmax[k]; - end + for (k = 0; k < 32; k = k + 1) begin + if ((delay_minmax[k]) > $signed(max)) max = delay_minmax[k]; + if ((delay_minmax[k]) < $signed(min)) min = delay_minmax[k]; + end `ifdef TEST_VERBOSE - $write("max: %d\n", max); - $write("min: %d\n", min); + $write("max: %d\n", max); + $write("min: %d\n", min); `endif - if (min == 127) begin - $stop; - end - else if (filtered_data >= -61) begin - $write("*-* All Finished *-*\n"); - $finish; - end - end + if (min == 127) begin + $stop; + end + else if (filtered_data >= -61) begin + $write("*-* All Finished *-*\n"); + $finish; + end + end endmodule diff --git a/test_regress/t/t_nba_mixed_update_clocked.v b/test_regress/t/t_nba_mixed_update_clocked.v index 20c4d9631..814ed8132 100644 --- a/test_regress/t/t_nba_mixed_update_clocked.v +++ b/test_regress/t/t_nba_mixed_update_clocked.v @@ -30,30 +30,31 @@ module t ( } pair = '{a: 1'b0, b: 1'b0}; always @(posedge clk) begin - $display("cyc = %d (%08x) x[1] = %0d, x[0] = %0d, y1 = %0d, y0 = %0d z[1] = %02x z[1] = %02x pair.a = %0d pair.b = %0d", - cyc, cyc, x[1], x[0], y1, y0, z[1], z[0], pair.a, pair.b); - `check(x[0], cyc[0]); - `check(x[1], cyc[0]); - `check(y0, cyc[0]); - `check(y1, cyc[0]); - `check(z[0], {8{cyc[0]}}); - `check(z[1], {8{cyc[0]}}); - `check(pair.a, cyc[0]); - `check(pair.b, cyc[0]); - x[1] <= ~x[1]; - y1 <= ~y1; - for (int i = 0; i < 8; ++i) z[1][i] <= ~z[1][i]; - pair.b <= ~pair.b; - cyc = cyc + 1; - x[0] = cyc[0]; - y0 = cyc[0]; - for (int i = 0; i < 8; ++i) z[0][i] = cyc[0]; - pair.a = cyc[0]; - if (cyc == 99) begin - $display(x); - $write("*-* All Finished *-*\n"); - $finish; - end + $display( + "cyc = %d (%08x) x[1] = %0d, x[0] = %0d, y1 = %0d, y0 = %0d z[1] = %02x z[1] = %02x pair.a = %0d pair.b = %0d", + cyc, cyc, x[1], x[0], y1, y0, z[1], z[0], pair.a, pair.b); + `check(x[0], cyc[0]); + `check(x[1], cyc[0]); + `check(y0, cyc[0]); + `check(y1, cyc[0]); + `check(z[0], {8{cyc[0]}}); + `check(z[1], {8{cyc[0]}}); + `check(pair.a, cyc[0]); + `check(pair.b, cyc[0]); + x[1] <= ~x[1]; + y1 <= ~y1; + for (int i = 0; i < 8; ++i) z[1][i] <= ~z[1][i]; + pair.b <= ~pair.b; + cyc = cyc + 1; + x[0] = cyc[0]; + y0 = cyc[0]; + for (int i = 0; i < 8; ++i) z[0][i] = cyc[0]; + pair.a = cyc[0]; + if (cyc == 99) begin + $display(x); + $write("*-* All Finished *-*\n"); + $finish; + end end endmodule diff --git a/test_regress/t/t_nba_mixed_update_comb.v b/test_regress/t/t_nba_mixed_update_comb.v index ec65b1d57..2646405af 100644 --- a/test_regress/t/t_nba_mixed_update_comb.v +++ b/test_regress/t/t_nba_mixed_update_comb.v @@ -39,33 +39,34 @@ module t ( assign x[0] = cyc[0]; assign y0 = sameAsCycButCantBeOptimized_0[0]; always_comb begin - for (int i = 0; i < 8; ++i) z[0][i] = sameAsCycButCantBeOptimized_1[0]; + for (int i = 0; i < 8; ++i) z[0][i] = sameAsCycButCantBeOptimized_1[0]; end assign pair.a = sameAsCycButCantBeOptimized_2[0]; always @(posedge clk) begin - $display("cyc = %d (%08x) x[1] = %0d, x[0] = %0d, y1 = %0d, y0 = %0d z[1] = %02x z[1] = %02x", cyc, cyc, x[1], x[0], y1, y0, z[1], z[0]); - `check(x[0], cyc[0]); - `check(x[1], cyc[0]); - `check(y0, cyc[0]); - `check(y1, cyc[0]); - `check(z[0], {8{cyc[0]}}); - `check(z[1], {8{cyc[0]}}); - `check(pair.a, cyc[0]); - `check(pair.b, cyc[0]); - x[1] <= ~x[1]; - y1 <= ~y1; - for (int i = 0; i < 8; ++i) z[1][i] <= ~z[1][i]; - pair.b <= ~pair.b; - cyc = cyc + 1; - sameAsCycButCantBeOptimized_0 = cyc; - sameAsCycButCantBeOptimized_1 = cyc; - sameAsCycButCantBeOptimized_2 = cyc; - if (cyc == 99) begin - $display(x); - $write("*-* All Finished *-*\n"); - $finish; - end + $display("cyc = %d (%08x) x[1] = %0d, x[0] = %0d, y1 = %0d, y0 = %0d z[1] = %02x z[1] = %02x", + cyc, cyc, x[1], x[0], y1, y0, z[1], z[0]); + `check(x[0], cyc[0]); + `check(x[1], cyc[0]); + `check(y0, cyc[0]); + `check(y1, cyc[0]); + `check(z[0], {8{cyc[0]}}); + `check(z[1], {8{cyc[0]}}); + `check(pair.a, cyc[0]); + `check(pair.b, cyc[0]); + x[1] <= ~x[1]; + y1 <= ~y1; + for (int i = 0; i < 8; ++i) z[1][i] <= ~z[1][i]; + pair.b <= ~pair.b; + cyc = cyc + 1; + sameAsCycButCantBeOptimized_0 = cyc; + sameAsCycButCantBeOptimized_1 = cyc; + sameAsCycButCantBeOptimized_2 = cyc; + if (cyc == 99) begin + $display(x); + $write("*-* All Finished *-*\n"); + $finish; + end end endmodule diff --git a/test_regress/t/t_opt_balance_cats.v b/test_regress/t/t_opt_balance_cats.v index d50d68a64..8297c3992 100644 --- a/test_regress/t/t_opt_balance_cats.v +++ b/test_regress/t/t_opt_balance_cats.v @@ -4,10 +4,12 @@ // SPDX-FileCopyrightText: 2024 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 -module t( - clk, - i0, o0, - i1, o1 +module t ( + clk, + i0, + o0, + i1, + o1 ); localparam N = 2000; // Deliberately not multiple of 32 @@ -23,16 +25,16 @@ module t( wire [N-1:0] o0; for (genvar n = 0; n + 31 < N; n += 32) begin - assign o0[n+ 0 +: 1] = i0[(N-1-n)- 0 -: 1]; - assign o0[n+ 1 +: 1] = i0[(N-1-n)- 1 -: 1]; - assign o0[n+ 2 +: 2] = i0[(N-1-n)- 2 -: 2]; - assign o0[n+ 4 +: 4] = i0[(N-1-n)- 4 -: 4]; - assign o0[n+ 8 +: 8] = i0[(N-1-n)- 8 -: 8]; - assign o0[n+16 +: 8] = i0[(N-1-n)-16 -: 8]; - assign o0[n+24 +: 4] = i0[(N-1-n)-24 -: 4]; - assign o0[n+28 +: 2] = i0[(N-1-n)-28 -: 2]; - assign o0[n+30 +: 1] = i0[(N-1-n)-30 -: 1]; - assign o0[n+31 +: 1] = i0[(N-1-n)-31 -: 1]; + assign o0[n+0+:1] = i0[(N-1-n)-0-:1]; + assign o0[n+1+:1] = i0[(N-1-n)-1-:1]; + assign o0[n+2+:2] = i0[(N-1-n)-2-:2]; + assign o0[n+4+:4] = i0[(N-1-n)-4-:4]; + assign o0[n+8+:8] = i0[(N-1-n)-8-:8]; + assign o0[n+16+:8] = i0[(N-1-n)-16-:8]; + assign o0[n+24+:4] = i0[(N-1-n)-24-:4]; + assign o0[n+28+:2] = i0[(N-1-n)-28-:2]; + assign o0[n+30+:1] = i0[(N-1-n)-30-:1]; + assign o0[n+31+:1] = i0[(N-1-n)-31-:1]; end for (genvar n = N / 32 * 32; n < N; ++n) begin @@ -48,7 +50,7 @@ module t( logic [N-1:0] o1; always @(posedge clk) begin - o1 = N'({i1[0 +: N/4], (N/2 - 128)'(i1[N/2 +: N/8]), 128'({i1[0 +: 10], 22'(i1[10 +: 10])})}); + o1 = N'({i1[0+:N/4], (N / 2 - 128)'(i1[N/2+:N/8]), 128'({i1[0+:10], 22'(i1[10+:10])})}); end endmodule diff --git a/test_regress/t/t_opt_expand_sel_wide_nested.v b/test_regress/t/t_opt_expand_sel_wide_nested.v index ff0de62fa..d558ca055 100644 --- a/test_regress/t/t_opt_expand_sel_wide_nested.v +++ b/test_regress/t/t_opt_expand_sel_wide_nested.v @@ -40,8 +40,8 @@ module t; // Deeply nested variable offset selects from a wide value. logic [15:0][31:0] lut = '0; - logic [31:0] arr[16] = '{default: 32'h0}; // Same as 'lut', but unpacked - logic [3:0] start = 4'h0; + logic [31:0] arr[16] = '{default: 32'h0}; // Same as 'lut', but unpacked + logic [3:0] start = 4'h0; // Explicitly nested so test doesn't depend on unrolling/dfg, or other opts wire [3:0] chainLut @@ -64,18 +64,18 @@ module t; // Check access boundaries logic [511:0] data = 512'h0; - logic [8:0] lsb = 9'h0; + logic [8:0] lsb = 9'h0; - wire [0:0] sel01 = data[lsb+:01]; - wire [3:0] sel04 = data[lsb+:04]; + wire [0:0] sel01 = data[lsb+:01]; + wire [3:0] sel04 = data[lsb+:04]; wire [30:0] sel31 = data[lsb+:31]; wire [31:0] sel32 = data[lsb+:32]; wire [32:0] sel33 = data[lsb+:33]; wire [63:0] sel64 = data[lsb+:64]; always @(posedge clk) begin - `checkh(sel01, 1'(data >> lsb)); - `checkh(sel04, 4'(data >> lsb)); + `checkh(sel01, 1'(data >> lsb)); + `checkh(sel04, 4'(data >> lsb)); `checkh(sel31, 31'(data >> lsb)); `checkh(sel32, 32'(data >> lsb)); `checkh(sel33, 33'(data >> lsb)); diff --git a/test_regress/t/t_opt_inline_funcs.v b/test_regress/t/t_opt_inline_funcs.v index e1aaa6481..0bd4c3d2c 100644 --- a/test_regress/t/t_opt_inline_funcs.v +++ b/test_regress/t/t_opt_inline_funcs.v @@ -20,7 +20,7 @@ module t; endtask logic [16:0] clearBit_i; - int clearBit_idx; + int clearBit_idx; logic [16:0] clearBit_o; function automatic logic [16:0] clearBit(logic [16:0] i, int idx); i[idx] = 1'b0; @@ -31,9 +31,9 @@ module t; `check(clearBit_o, (clearBit_i & ~(17'd1 << clearBit_idx))); end - logic [2:0] lut_idx; - logic [4:0] lut_o; - localparam logic [4:0] LUT [7:0] = '{5'd0, 5'd1, 5'd2, 5'd3, 5'd4, 5'd5, 5'd6, 5'd7}; + logic [2:0] lut_idx; + logic [4:0] lut_o; + localparam logic [4:0] LUT[7:0] = '{5'd0, 5'd1, 5'd2, 5'd3, 5'd4, 5'd5, 5'd6, 5'd7}; function automatic logic [4:0] lut(logic [2:0] idx); return LUT[idx]; endfunction diff --git a/test_regress/t/t_opt_localize_deep.v b/test_regress/t/t_opt_localize_deep.v index 19568bb26..ff5a68b01 100644 --- a/test_regress/t/t_opt_localize_deep.v +++ b/test_regress/t/t_opt_localize_deep.v @@ -5,16 +5,14 @@ // SPDX-License-Identifier: CC0-1.0 `ifdef verilator - `define dontOptimize $c1("1") +`define dontOptimize $c1("1") `else - `define dontOptimize 1'b1 +`define dontOptimize 1'b1 `endif -module t (/*AUTOARG*/ - // Inputs - clk - ); - input clk; +module t ( + input clk +); int cyc = 0; int x = 0; @@ -78,8 +76,8 @@ module t (/*AUTOARG*/ $write("[%0t] cyc=%0d x=%x\n", $time, cyc, x); if (x !== cyc) $stop; if (cyc == 99) begin - $write("*-* All Finished *-*\n"); - $finish; + $write("*-* All Finished *-*\n"); + $finish; end end endmodule diff --git a/test_regress/t/t_package_struct.v b/test_regress/t/t_package_struct.v index aafb2f24d..6487024c0 100644 --- a/test_regress/t/t_package_struct.v +++ b/test_regress/t/t_package_struct.v @@ -5,21 +5,19 @@ // SPDX-License-Identifier: CC0-1.0 package pkg; - typedef struct { - string a, b; - struct { - bit a, b; - } has; - } strings; + typedef struct { + string a, b; + struct {bit a, b;} has; + } strings; endpackage module t; initial begin - pkg::strings stct; - stct.a = "hello"; - stct.b = "world"; - $display("%s, %s (%1b, %1b)", stct.a, stct.b, stct.has.a, stct.has.b); - $write("*-* All Finished *-*\n"); - $finish; + pkg::strings stct; + stct.a = "hello"; + stct.b = "world"; + $display("%s, %s (%1b, %1b)", stct.a, stct.b, stct.has.a, stct.has.b); + $write("*-* All Finished *-*\n"); + $finish; end endmodule diff --git a/test_regress/t/t_param_slice.v b/test_regress/t/t_param_slice.v index 358c1edd6..836002ad3 100644 --- a/test_regress/t/t_param_slice.v +++ b/test_regress/t/t_param_slice.v @@ -4,21 +4,21 @@ // SPDX-FileCopyrightText: 2025 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 -`timescale 1ns/1ps +`timescale 1ns / 1ps // Test constant parameter slicing of unpacked arrays with various slice ranges. module issue_desc #( - parameter int els_p = 1, - parameter int val_p [els_p+1:2], - parameter int orig_els = 1 + parameter int els_p = 1, + parameter int val_p[els_p+1:2], + parameter int orig_els = 1 ) (); // Drop the lowest index (2) in each recursion: slice [high:3] if (els_p > 1) begin : r issue_desc #( - .els_p(els_p-1), - .val_p(val_p[els_p+1:3]), - .orig_els(orig_els) - ) x(); + .els_p(els_p - 1), + .val_p(val_p[els_p+1:3]), + .orig_els(orig_els) + ) x (); end initial begin automatic int expected = orig_els - els_p + 1; @@ -31,17 +31,17 @@ module issue_desc #( endmodule module issue_rev #( - parameter int els_p = 1, - parameter int val_p [2:els_p+1], - parameter int orig_els = 1 + parameter int els_p = 1, + parameter int val_p[2:els_p+1], + parameter int orig_els = 1 ) (); // Drop the lowest index (2) in each recursion: slice [3:high] if (els_p > 1) begin : r issue_rev #( - .els_p(els_p-1), - .val_p(val_p[3:els_p+1]), - .orig_els(orig_els) - ) x(); + .els_p(els_p - 1), + .val_p(val_p[3:els_p+1]), + .orig_els(orig_els) + ) x (); end initial begin automatic int expected = orig_els - els_p + 1; @@ -54,18 +54,18 @@ module issue_rev #( endmodule module issue_def #( - parameter int els_p = 1, - // Internal default fill is zero; the test overrides this with DEADBEEF. - parameter int val_p [els_p+1:2] = '{default:0}, - parameter int orig_els = 1 + parameter int els_p = 1, + // Internal default fill is zero; the test overrides this with DEADBEEF. + parameter int val_p[els_p+1:2] = '{default: 0}, + parameter int orig_els = 1 ) (); // Recursively slice off the lowest index (2) if (els_p > 1) begin : r issue_def #( - .els_p(els_p-1), - .val_p(val_p[els_p+1:3]), - .orig_els(orig_els) - ) x(); + .els_p(els_p - 1), + .val_p(val_p[els_p+1:3]), + .orig_els(orig_els) + ) x (); end initial begin // Expect 32'hDEADBEEF when overridden by the top-level test. @@ -80,15 +80,27 @@ endmodule module t; // For els_p=5, the range [els_p+1:2] is [6:2]. // Descending initializer: index 6=5,5=4,4=3,3=2,2=1. - parameter int val_desc [6:2] = '{5,4,3,2,1}; + parameter int val_desc[6:2] = '{5, 4, 3, 2, 1}; // Reverse slice initializer: ascending values on [2:6]. - parameter int val_rev [2:6] = '{1,2,3,4,5}; + parameter int val_rev[2:6] = '{1, 2, 3, 4, 5}; // Override for default-array test: all elements set to 32'hDEADBEEF on [6:2]. - parameter int val_def [6:2] = '{default: 32'hDEADBEEF}; + parameter int val_def[6:2] = '{default: 32'hDEADBEEF}; - issue_desc #(.els_p(5), .val_p(val_desc), .orig_els(5)) iss_desc(); - issue_rev #(.els_p(5), .val_p(val_rev), .orig_els(5)) iss_rev(); - issue_def #(.els_p(5), .val_p(val_def), .orig_els(5)) iss_def(); + issue_desc #( + .els_p(5), + .val_p(val_desc), + .orig_els(5) + ) iss_desc (); + issue_rev #( + .els_p(5), + .val_p(val_rev), + .orig_els(5) + ) iss_rev (); + issue_def #( + .els_p(5), + .val_p(val_def), + .orig_els(5) + ) iss_def (); initial begin #1; diff --git a/test_regress/t/t_param_type_dep_chain.v b/test_regress/t/t_param_type_dep_chain.v index ca8377a3a..c06406fe5 100644 --- a/test_regress/t/t_param_type_dep_chain.v +++ b/test_regress/t/t_param_type_dep_chain.v @@ -4,6 +4,11 @@ // SPDX-FileCopyrightText: 2026 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 +// verilog_format: off +`define stop $stop +`define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got=%0x exp=%0x (%s !== %s)\n", `__FILE__,`__LINE__, (gotv), (expv), `"gotv`", `"expv`"); `stop; end while(0); +// verilog_format: on + // Chained paramtypes: type B = A where A = logic[W-1:0]. The iterative // RefDType substitution in cellPinCleanup must unwind the chain over // multiple passes: B -> REFDTYPE(A) -> A's body -> VARREF(W) -> override. @@ -14,10 +19,10 @@ // against each spec's resolved B and pass cleanly. module m #( - parameter int W = 8, - parameter type A = logic [W-1:0], - parameter type B = A, - parameter B val = '0 + parameter int W = 8, + parameter type A = logic [W-1:0], + parameter type B = A, + parameter B val = '0 ) (); A a_sig; B b_sig; @@ -26,50 +31,41 @@ module m #( endmodule module t; - m #(.W(8), .val(8'hA5)) i8 (); - m #(.W(16), .val(16'hBEEF)) i16 (); - m #(.W(32), .val(32'hDEADBEEF)) i32 (); + m #( + .W(8), + .val(8'hA5) + ) i8 (); + m #( + .W(16), + .val(16'hBEEF) + ) i16 (); + m #( + .W(32), + .val(32'hDEADBEEF) + ) i32 (); initial begin #1; - if ($bits(i8.val) !== 8) begin - $write("%%Error $bits(i8.val)=%0d\n", $bits(i8.val)); $stop; - end - if ($bits(i8.a_sig) !== 8) begin - $write("%%Error $bits(i8.a_sig)=%0d\n", $bits(i8.a_sig)); $stop; - end - if ($bits(i8.b_sig) !== 8) begin - $write("%%Error $bits(i8.b_sig)=%0d\n", $bits(i8.b_sig)); $stop; - end - if (i8.val !== 8'hA5) begin $write("%%Error i8.val=%h\n", i8.val); $stop; end - if (i8.a_sig !== 8'hFF) begin $write("%%Error i8.a_sig=%h\n", i8.a_sig); $stop; end - if (i8.b_sig !== 8'hFF) begin $write("%%Error i8.b_sig=%h\n", i8.b_sig); $stop; end + `checkh($bits(i8.val), 8); + `checkh($bits(i8.a_sig), 8); + `checkh($bits(i8.b_sig), 8); + `checkh(i8.val, 8'hA5); + `checkh(i8.a_sig, 8'hFF); + `checkh(i8.b_sig, 8'hFF); - if ($bits(i16.val) !== 16) begin - $write("%%Error $bits(i16.val)=%0d\n", $bits(i16.val)); $stop; - end - if ($bits(i16.a_sig) !== 16) begin - $write("%%Error $bits(i16.a_sig)=%0d\n", $bits(i16.a_sig)); $stop; - end - if ($bits(i16.b_sig) !== 16) begin - $write("%%Error $bits(i16.b_sig)=%0d\n", $bits(i16.b_sig)); $stop; - end - if (i16.val !== 16'hBEEF) begin $write("%%Error i16.val=%h\n", i16.val); $stop; end - if (i16.a_sig !== 16'hFFFF) begin $write("%%Error i16.a_sig=%h\n", i16.a_sig); $stop; end - if (i16.b_sig !== 16'hFFFF) begin $write("%%Error i16.b_sig=%h\n", i16.b_sig); $stop; end + `checkh($bits(i16.val), 16); + `checkh($bits(i16.a_sig), 16); + `checkh($bits(i16.b_sig), 16); + `checkh(i16.val, 16'hBEEF); + `checkh(i16.a_sig, 16'hFFFF); + `checkh(i16.b_sig, 16'hFFFF); - if ($bits(i32.val) !== 32) begin - $write("%%Error $bits(i32.val)=%0d\n", $bits(i32.val)); $stop; - end - if ($bits(i32.a_sig) !== 32) begin - $write("%%Error $bits(i32.a_sig)=%0d\n", $bits(i32.a_sig)); $stop; - end - if ($bits(i32.b_sig) !== 32) begin - $write("%%Error $bits(i32.b_sig)=%0d\n", $bits(i32.b_sig)); $stop; - end - if (i32.val !== 32'hDEADBEEF) begin $write("%%Error i32.val=%h\n", i32.val); $stop; end - if (i32.a_sig !== 32'hFFFFFFFF) begin $write("%%Error i32.a_sig=%h\n", i32.a_sig); $stop; end - if (i32.b_sig !== 32'hFFFFFFFF) begin $write("%%Error i32.b_sig=%h\n", i32.b_sig); $stop; end + `checkh($bits(i32.val), 32); + `checkh($bits(i32.a_sig), 32); + `checkh($bits(i32.b_sig), 32); + `checkh(i32.val, 32'hDEADBEEF); + `checkh(i32.a_sig, 32'hFFFFFFFF); + `checkh(i32.b_sig, 32'hFFFFFFFF); $write("*-* All Finished *-*\n"); $finish; diff --git a/test_regress/t/t_param_type_dep_cross_inst.v b/test_regress/t/t_param_type_dep_cross_inst.v index 7a61d1a50..bbcdcaf5f 100644 --- a/test_regress/t/t_param_type_dep_cross_inst.v +++ b/test_regress/t/t_param_type_dep_cross_inst.v @@ -4,42 +4,65 @@ // SPDX-FileCopyrightText: 2026 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 +// verilog_format: off +`define stop $stop +`define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got=%0x exp=%0x (%s !== %s)\n", `__FILE__,`__LINE__, (gotv), (expv), `"gotv`", `"expv`"); `stop; end while(0); +// verilog_format: on + // Interleaved specs (A B A C B A). Any cross-instance leakage from // template poisoning causes a later instance of a repeated tuple to // mismatch its expected value. module m #( - parameter int W = 8, - parameter type T = logic [W-1:0], - parameter T VAL = '0 + parameter int W = 8, + parameter type T = logic [W-1:0], + parameter T VAL = '0 ) (); logic [W-1:0] observed; assign observed = VAL; endmodule module t; - m #(.W(8), .VAL(8'h11)) ia1 (); // A - m #(.W(16), .VAL(16'h2222)) ib1 (); // B - m #(.W(8), .VAL(8'h11)) ia2 (); // A - m #(.W(32), .VAL(32'h33333333)) ic1 (); // C - m #(.W(16), .VAL(16'h2222)) ib2 (); // B - m #(.W(8), .VAL(8'h11)) ia3 (); // A + m #( + .W(8), + .VAL(8'h11) + ) ia1 (); // A + m #( + .W(16), + .VAL(16'h2222) + ) ib1 (); // B + m #( + .W(8), + .VAL(8'h11) + ) ia2 (); // A + m #( + .W(32), + .VAL(32'h33333333) + ) ic1 (); // C + m #( + .W(16), + .VAL(16'h2222) + ) ib2 (); // B + m #( + .W(8), + .VAL(8'h11) + ) ia3 (); // A initial begin #1; - if ($bits(ia1.observed) !== 8) begin $write("%%Error ia1 bits\n"); $stop; end - if ($bits(ib1.observed) !== 16) begin $write("%%Error ib1 bits\n"); $stop; end - if ($bits(ia2.observed) !== 8) begin $write("%%Error ia2 bits\n"); $stop; end - if ($bits(ic1.observed) !== 32) begin $write("%%Error ic1 bits\n"); $stop; end - if ($bits(ib2.observed) !== 16) begin $write("%%Error ib2 bits\n"); $stop; end - if ($bits(ia3.observed) !== 8) begin $write("%%Error ia3 bits\n"); $stop; end + `checkh($bits(ia1.observed), 8); + `checkh($bits(ib1.observed), 16); + `checkh($bits(ia2.observed), 8); + `checkh($bits(ic1.observed), 32); + `checkh($bits(ib2.observed), 16); + `checkh($bits(ia3.observed), 8); - if (ia1.observed !== 8'h11) begin $write("%%Error ia1=%h\n", ia1.observed); $stop; end - if (ib1.observed !== 16'h2222) begin $write("%%Error ib1=%h\n", ib1.observed); $stop; end - if (ia2.observed !== 8'h11) begin $write("%%Error ia2=%h\n", ia2.observed); $stop; end - if (ic1.observed !== 32'h33333333) begin $write("%%Error ic1=%h\n", ic1.observed); $stop; end - if (ib2.observed !== 16'h2222) begin $write("%%Error ib2=%h\n", ib2.observed); $stop; end - if (ia3.observed !== 8'h11) begin $write("%%Error ia3=%h\n", ia3.observed); $stop; end + `checkh(ia1.observed, 8'h11); + `checkh(ib1.observed, 16'h2222); + `checkh(ia2.observed, 8'h11); + `checkh(ic1.observed, 32'h33333333); + `checkh(ib2.observed, 16'h2222); + `checkh(ia3.observed, 8'h11); $write("*-* All Finished *-*\n"); $finish; diff --git a/test_regress/t/t_param_type_dep_deep.v b/test_regress/t/t_param_type_dep_deep.v index 88972c69e..55394f2d8 100644 --- a/test_regress/t/t_param_type_dep_deep.v +++ b/test_regress/t/t_param_type_dep_deep.v @@ -4,6 +4,11 @@ // SPDX-FileCopyrightText: 2026 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 +// verilog_format: off +`define stop $stop +`define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got=%0x exp=%0x (%s !== %s)\n", `__FILE__,`__LINE__, (gotv), (expv), `"gotv`", `"expv`"); `stop; end while(0); +// verilog_format: on + // Deep value-param chain under a type param. Each intermediate must // recompute per spec; template poisoning at any level fails a specific // assertion pointing at the leaking level. Each instance overrides @@ -12,48 +17,46 @@ // unwind. module m #( - parameter int W1 = 4, - parameter int W2 = W1 + 4, - parameter int W3 = W2 * 2, - parameter int W4 = W3 + 1, - parameter type T = logic [W4-1:0], - parameter T val = '0 + parameter int W1 = 4, + parameter int W2 = W1 + 4, + parameter int W3 = W2 * 2, + parameter int W4 = W3 + 1, + parameter type T = logic [W4-1:0], + parameter T val = '0 ) (); endmodule module t; - m #(.W1(8), .val(25'h1234567)) iw8 (); // W4 = 25 - m iwd (); // default W4 = 17 - m #(.W1(16), .val(41'h123456789AB)) iw16 (); // W4 = 41 + m #( + .W1(8), + .val(25'h1234567) + ) iw8 (); // W4 = 25 + m iwd (); // default W4 = 17 + m #( + .W1(16), + .val(41'h123456789AB) + ) iw16 (); // W4 = 41 initial begin - if (iw8.W1 !== 8) begin $write("%%Error iw8.W1=%0d\n", iw8.W1); $stop; end - if (iw8.W2 !== 12) begin $write("%%Error iw8.W2=%0d\n", iw8.W2); $stop; end - if (iw8.W3 !== 24) begin $write("%%Error iw8.W3=%0d\n", iw8.W3); $stop; end - if (iw8.W4 !== 25) begin $write("%%Error iw8.W4=%0d\n", iw8.W4); $stop; end - if ($bits(iw8.val) !== 25) begin - $write("%%Error $bits(iw8.val)=%0d\n", $bits(iw8.val)); $stop; - end - if (iw8.val !== 25'h1234567) begin $write("%%Error iw8.val=%h\n", iw8.val); $stop; end + `checkh(iw8.W1, 8); + `checkh(iw8.W2, 12); + `checkh(iw8.W3, 24); + `checkh(iw8.W4, 25); + `checkh($bits(iw8.val), 25); + `checkh(iw8.val, 25'h1234567); - if (iwd.W1 !== 4) begin $write("%%Error iwd.W1=%0d\n", iwd.W1); $stop; end - if (iwd.W2 !== 8) begin $write("%%Error iwd.W2=%0d\n", iwd.W2); $stop; end - if (iwd.W3 !== 16) begin $write("%%Error iwd.W3=%0d\n", iwd.W3); $stop; end - if (iwd.W4 !== 17) begin $write("%%Error iwd.W4=%0d\n", iwd.W4); $stop; end - if ($bits(iwd.val) !== 17) begin - $write("%%Error $bits(iwd.val)=%0d\n", $bits(iwd.val)); $stop; - end + `checkh(iwd.W1, 4); + `checkh(iwd.W2, 8); + `checkh(iwd.W3, 16); + `checkh(iwd.W4, 17); + `checkh($bits(iwd.val), 17); - if (iw16.W1 !== 16) begin $write("%%Error iw16.W1=%0d\n", iw16.W1); $stop; end - if (iw16.W2 !== 20) begin $write("%%Error iw16.W2=%0d\n", iw16.W2); $stop; end - if (iw16.W3 !== 40) begin $write("%%Error iw16.W3=%0d\n", iw16.W3); $stop; end - if (iw16.W4 !== 41) begin $write("%%Error iw16.W4=%0d\n", iw16.W4); $stop; end - if ($bits(iw16.val) !== 41) begin - $write("%%Error $bits(iw16.val)=%0d\n", $bits(iw16.val)); $stop; - end - if (iw16.val !== 41'h123456789AB) begin - $write("%%Error iw16.val=%h\n", iw16.val); $stop; - end + `checkh(iw16.W1, 16); + `checkh(iw16.W2, 20); + `checkh(iw16.W3, 40); + `checkh(iw16.W4, 41); + `checkh($bits(iw16.val), 41); + `checkh(iw16.val, 41'h123456789AB); $write("*-* All Finished *-*\n"); $finish; diff --git a/test_regress/t/t_param_type_dep_hash_norm.v b/test_regress/t/t_param_type_dep_hash_norm.v index 6566d71e0..33ba8861a 100644 --- a/test_regress/t/t_param_type_dep_hash_norm.v +++ b/test_regress/t/t_param_type_dep_hash_norm.v @@ -4,6 +4,11 @@ // SPDX-FileCopyrightText: 2026 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 +// verilog_format: off +`define stop $stop +`define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got=%0x exp=%0x (%s !== %s)\n", `__FILE__,`__LINE__, (gotv), (expv), `"gotv`", `"expv`"); `stop; end while(0); +// verilog_format: on + // Hash-normalization: the port type must resolve per-specialization, not // from the template default. Two pin values differing only in bits above // the template-default width must still produce distinct specs when the @@ -20,45 +25,41 @@ endmodule module t; // width=24 -> width2=32 -> data_t is 32 bits - test #(.width(24), .data(32'hFFFFFFFF)) i_aa (); - test #(.width(24), .data(32'h11FFFFFF)) i_ab (); - test #(.width(24), .data(32'h11FFFFFF)) i_ac (); + test #( + .width(24), + .data(32'hFFFFFFFF) + ) i_aa (); + test #( + .width(24), + .data(32'h11FFFFFF) + ) i_ab (); + test #( + .width(24), + .data(32'h11FFFFFF) + ) i_ac (); // width=16 -> width2=24 -> data_t is 24 bits - test #(.width(16), .data(24'hFFFFFF)) i_bb (); + test #( + .width(16), + .data(24'hFFFFFF) + ) i_bb (); initial begin - if ($bits(i_aa.data) !== 32) begin - $write("%%Error $bits(i_aa.data)=%0d expected 32\n", $bits(i_aa.data)); $stop; - end - if ($bits(i_ab.data) !== 32) begin - $write("%%Error $bits(i_ab.data)=%0d expected 32\n", $bits(i_ab.data)); $stop; - end - if ($bits(i_ac.data) !== 32) begin - $write("%%Error $bits(i_ac.data)=%0d expected 32\n", $bits(i_ac.data)); $stop; - end - if ($bits(i_bb.data) !== 24) begin - $write("%%Error $bits(i_bb.data)=%0d expected 24\n", $bits(i_bb.data)); $stop; - end - if (i_aa.data !== 32'hFFFFFFFF) begin - $write("%%Error i_aa.data=%h\n", i_aa.data); $stop; - end - if (i_ab.data !== 32'h11FFFFFF) begin - $write("%%Error i_ab.data=%h\n", i_ab.data); $stop; - end - if (i_ac.data !== 32'h11FFFFFF) begin - $write("%%Error i_ac.data=%h\n", i_ac.data); $stop; - end - if (i_bb.data !== 24'hFFFFFF) begin - $write("%%Error i_bb.data=%h\n", i_bb.data); $stop; - end + `checkh($bits(i_aa.data), 32); + `checkh($bits(i_ab.data), 32); + `checkh($bits(i_ac.data), 32); + `checkh($bits(i_bb.data), 24); + `checkh(i_aa.data, 32'hFFFFFFFF); + `checkh(i_ab.data, 32'h11FFFFFF); + `checkh(i_ac.data, 32'h11FFFFFF); + `checkh(i_bb.data, 24'hFFFFFF); // Distinct full-32b values must NOT share a spec (values differ). if (i_aa.data === i_ab.data) begin - $write("%%Error i_aa.data and i_ab.data must differ\n"); $stop; + $write("%%Error i_aa.data and i_ab.data must differ\n"); + `stop; end // Equal pin values share a spec (#5479 dedup). - if (i_ab.data !== i_ac.data) begin - $write("%%Error i_ab.data and i_ac.data must match\n"); $stop; - end + `checkh(i_ab.data, i_ac.data); + $write("*-* All Finished *-*\n"); $finish; end diff --git a/test_regress/t/t_param_type_dep_hier.v b/test_regress/t/t_param_type_dep_hier.v index 22012bb70..0938a47af 100644 --- a/test_regress/t/t_param_type_dep_hier.v +++ b/test_regress/t/t_param_type_dep_hier.v @@ -4,57 +4,63 @@ // SPDX-FileCopyrightText: 2026 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 +// verilog_format: off +`define stop $stop +`define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got=%0x exp=%0x (%s !== %s)\n", `__FILE__,`__LINE__, (gotv), (expv), `"gotv`", `"expv`"); `stop; end while(0); +// verilog_format: on + // Ariane-shaped 3-level hierarchy with parameter forwarding. Each // mid instance forwards its paramtype to its leaf. Three distinct // width/value tuples catch cross-hierarchy template leakage. module leaf #( - parameter int W = 4, - parameter type T = logic [W-1:0], - parameter T VAL = '0 + parameter int W = 4, + parameter type T = logic [W-1:0], + parameter T VAL = '0 ) (); logic [W-1:0] observed; assign observed = VAL; endmodule module mid #( - parameter int W = 4, - parameter type T = logic [W-1:0], - parameter T VAL = '0 + parameter int W = 4, + parameter type T = logic [W-1:0], + parameter T VAL = '0 ) (); - leaf #(.W(W), .T(T), .VAL(VAL)) l (); + leaf #( + .W(W), + .T(T), + .VAL(VAL) + ) l (); endmodule module t; - mid #(.W(8), .VAL(8'hA5)) m_a (); - mid #(.W(16), .VAL(16'hBEEF)) m_b (); - mid #(.W(32), .VAL(32'hDEADBEEF)) m_c (); + mid #( + .W(8), + .VAL(8'hA5) + ) m_a (); + mid #( + .W(16), + .VAL(16'hBEEF) + ) m_b (); + mid #( + .W(32), + .VAL(32'hDEADBEEF) + ) m_c (); initial begin #1; - if (m_a.l.W !== 8) begin $write("%%Error m_a.l.W=%0d\n", m_a.l.W); $stop; end - if ($bits(m_a.l.observed) !== 8) begin - $write("%%Error $bits(m_a.l.observed)=%0d\n", $bits(m_a.l.observed)); $stop; - end - if (m_a.l.observed !== 8'hA5) begin - $write("%%Error m_a.l.observed=%h\n", m_a.l.observed); $stop; - end + `checkh(m_a.l.W, 8); + `checkh($bits(m_a.l.observed), 8); + `checkh(m_a.l.observed, 8'hA5); - if (m_b.l.W !== 16) begin $write("%%Error m_b.l.W=%0d\n", m_b.l.W); $stop; end - if ($bits(m_b.l.observed) !== 16) begin - $write("%%Error $bits(m_b.l.observed)=%0d\n", $bits(m_b.l.observed)); $stop; - end - if (m_b.l.observed !== 16'hBEEF) begin - $write("%%Error m_b.l.observed=%h\n", m_b.l.observed); $stop; - end + `checkh(m_b.l.W, 16); + `checkh($bits(m_b.l.observed), 16); + `checkh(m_b.l.observed, 16'hBEEF); - if (m_c.l.W !== 32) begin $write("%%Error m_c.l.W=%0d\n", m_c.l.W); $stop; end - if ($bits(m_c.l.observed) !== 32) begin - $write("%%Error $bits(m_c.l.observed)=%0d\n", $bits(m_c.l.observed)); $stop; - end - if (m_c.l.observed !== 32'hDEADBEEF) begin - $write("%%Error m_c.l.observed=%h\n", m_c.l.observed); $stop; - end + `checkh(m_c.l.W, 32); + `checkh($bits(m_c.l.observed), 32); + `checkh(m_c.l.observed, 32'hDEADBEEF); $write("*-* All Finished *-*\n"); $finish; diff --git a/test_regress/t/t_param_type_dep_recompute.v b/test_regress/t/t_param_type_dep_recompute.v index 21c9b81ed..eaba0aa4d 100644 --- a/test_regress/t/t_param_type_dep_recompute.v +++ b/test_regress/t/t_param_type_dep_recompute.v @@ -4,6 +4,11 @@ // SPDX-FileCopyrightText: 2026 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 +// verilog_format: off +`define stop $stop +`define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got=%0x exp=%0x (%s !== %s)\n", `__FILE__,`__LINE__, (gotv), (expv), `"gotv`", `"expv`"); `stop; end while(0); +// verilog_format: on + // Dependent value-param + type-param + value-param-of-type-param must be // re-evaluated per specialization, not baked from the template default. // Regression test for template poisoning in V3Param::cellPinCleanup: the @@ -27,68 +32,41 @@ module test #( endmodule module t; - test #(.width(24), .data(32'h0)) inst_a (); - test #(.width(16), .data(24'h0)) inst_b (); - test #(.width( 8), .data(16'h0)) inst_c (); + test #( + .width(24), + .data(32'h0) + ) inst_a (); + test #( + .width(16), + .data(24'h0) + ) inst_b (); + test #( + .width(8), + .data(16'h0) + ) inst_c (); initial begin #1; // inst_a: width=24 -> width2=32 -> data_t is 32 bits - if (inst_a.width2 !== 32) begin - $write("%%Error inst_a.width2=%0d expected 32\n", inst_a.width2); $stop; - end - if ($bits(inst_a.data) !== 32) begin - $write("%%Error $bits(inst_a.data)=%0d expected 32\n", $bits(inst_a.data)); $stop; - end - if (inst_a.data !== 32'h0) begin - $write("%%Error inst_a.data=%h expected 0\n", inst_a.data); $stop; - end - if ($bits(inst_a.data_t_sig) !== 32) begin - $write("%%Error $bits(inst_a.data_t_sig)=%0d expected 32\n", - $bits(inst_a.data_t_sig)); $stop; - end - if (inst_a.data_t_sig !== 32'hFFFFFFFF) begin - $write("%%Error inst_a.data_t_sig=%h expected FFFFFFFF\n", - inst_a.data_t_sig); $stop; - end + `checkh(inst_a.width2, 32); + `checkh($bits(inst_a.data), 32); + `checkh(inst_a.data, 32'h0); + `checkh($bits(inst_a.data_t_sig), 32); + `checkh(inst_a.data_t_sig, 32'hFFFFFFFF); // inst_b: width=16 -> width2=24 -> data_t is 24 bits - if (inst_b.width2 !== 24) begin - $write("%%Error inst_b.width2=%0d expected 24\n", inst_b.width2); $stop; - end - if ($bits(inst_b.data) !== 24) begin - $write("%%Error $bits(inst_b.data)=%0d expected 24\n", $bits(inst_b.data)); $stop; - end - if (inst_b.data !== 24'h0) begin - $write("%%Error inst_b.data=%h expected 0\n", inst_b.data); $stop; - end - if ($bits(inst_b.data_t_sig) !== 24) begin - $write("%%Error $bits(inst_b.data_t_sig)=%0d expected 24\n", - $bits(inst_b.data_t_sig)); $stop; - end - if (inst_b.data_t_sig !== 24'hFFFFFF) begin - $write("%%Error inst_b.data_t_sig=%h expected FFFFFF\n", - inst_b.data_t_sig); $stop; - end + `checkh(inst_b.width2, 24); + `checkh($bits(inst_b.data), 24); + `checkh(inst_b.data, 24'h0); + `checkh($bits(inst_b.data_t_sig), 24); + `checkh(inst_b.data_t_sig, 24'hFFFFFF); // inst_c: width=8 -> width2=16 -> data_t is 16 bits - if (inst_c.width2 !== 16) begin - $write("%%Error inst_c.width2=%0d expected 16\n", inst_c.width2); $stop; - end - if ($bits(inst_c.data) !== 16) begin - $write("%%Error $bits(inst_c.data)=%0d expected 16\n", $bits(inst_c.data)); $stop; - end - if (inst_c.data !== 16'h0) begin - $write("%%Error inst_c.data=%h expected 0\n", inst_c.data); $stop; - end - if ($bits(inst_c.data_t_sig) !== 16) begin - $write("%%Error $bits(inst_c.data_t_sig)=%0d expected 16\n", - $bits(inst_c.data_t_sig)); $stop; - end - if (inst_c.data_t_sig !== 16'hFFFF) begin - $write("%%Error inst_c.data_t_sig=%h expected FFFF\n", - inst_c.data_t_sig); $stop; - end + `checkh(inst_c.width2, 16); + `checkh($bits(inst_c.data), 16); + `checkh(inst_c.data, 16'h0); + `checkh($bits(inst_c.data_t_sig), 16); + `checkh(inst_c.data_t_sig, 16'hFFFF); $write("*-* All Finished *-*\n"); $finish; diff --git a/test_regress/t/t_param_type_dep_struct.v b/test_regress/t/t_param_type_dep_struct.v index e2323f36b..ff95a2003 100644 --- a/test_regress/t/t_param_type_dep_struct.v +++ b/test_regress/t/t_param_type_dep_struct.v @@ -4,13 +4,18 @@ // SPDX-FileCopyrightText: 2026 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 +// verilog_format: off +`define stop $stop +`define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got=%0x exp=%0x (%s !== %s)\n", `__FILE__,`__LINE__, (gotv), (expv), `"gotv`", `"expv`"); `stop; end while(0); +// verilog_format: on + // Packed struct type param with dependent field widths. $bits and // field access on a typed-by-paramtype variable must see the correct // per-spec field widths. Also exercises the #7445 CVA6 pattern // (struct member access on a VARREF of a parameterized type). module m #( - parameter int W = 8, + parameter int W = 8, parameter type T = struct packed { logic [W-1:0] a; logic [W-1:0] b; @@ -23,35 +28,35 @@ module m #( endmodule module t; - m #(.W(4)) i4 (); - m #(.W(8)) i8 (); + m #(.W(4)) i4 (); + m #(.W(8)) i8 (); m #(.W(16)) i16 (); initial begin #1; - if ($bits(i4.t_sig) !== 8) begin $write("%%Error i4.t_sig bits\n"); $stop; end - if ($bits(i4.t_sig.a) !== 4) begin $write("%%Error i4.t_sig.a bits\n"); $stop; end - if ($bits(i4.t_sig.b) !== 4) begin $write("%%Error i4.t_sig.b bits\n"); $stop; end - if ($bits(i4.a_sig) !== 4) begin $write("%%Error i4.a_sig bits\n"); $stop; end - if (i4.t_sig.a !== 4'hF) begin $write("%%Error i4.t_sig.a=%h\n", i4.t_sig.a); $stop; end - if (i4.t_sig.b !== 4'hF) begin $write("%%Error i4.t_sig.b=%h\n", i4.t_sig.b); $stop; end - if (i4.a_sig !== 4'hF) begin $write("%%Error i4.a_sig=%h\n", i4.a_sig); $stop; end + `checkh($bits(i4.t_sig), 8); + `checkh($bits(i4.t_sig.a), 4); + `checkh($bits(i4.t_sig.b), 4); + `checkh($bits(i4.a_sig), 4); + `checkh(i4.t_sig.a, 4'hF); + `checkh(i4.t_sig.b, 4'hF); + `checkh(i4.a_sig, 4'hF); - if ($bits(i8.t_sig) !== 16) begin $write("%%Error i8.t_sig bits\n"); $stop; end - if ($bits(i8.t_sig.a) !== 8) begin $write("%%Error i8.t_sig.a bits\n"); $stop; end - if ($bits(i8.t_sig.b) !== 8) begin $write("%%Error i8.t_sig.b bits\n"); $stop; end - if ($bits(i8.a_sig) !== 8) begin $write("%%Error i8.a_sig bits\n"); $stop; end - if (i8.t_sig.a !== 8'hFF) begin $write("%%Error i8.t_sig.a=%h\n", i8.t_sig.a); $stop; end - if (i8.t_sig.b !== 8'hFF) begin $write("%%Error i8.t_sig.b=%h\n", i8.t_sig.b); $stop; end - if (i8.a_sig !== 8'hFF) begin $write("%%Error i8.a_sig=%h\n", i8.a_sig); $stop; end + `checkh($bits(i8.t_sig), 16); + `checkh($bits(i8.t_sig.a), 8); + `checkh($bits(i8.t_sig.b), 8); + `checkh($bits(i8.a_sig), 8); + `checkh(i8.t_sig.a, 8'hFF); + `checkh(i8.t_sig.b, 8'hFF); + `checkh(i8.a_sig, 8'hFF); - if ($bits(i16.t_sig) !== 32) begin $write("%%Error i16.t_sig bits\n"); $stop; end - if ($bits(i16.t_sig.a) !== 16) begin $write("%%Error i16.t_sig.a bits\n"); $stop; end - if ($bits(i16.t_sig.b) !== 16) begin $write("%%Error i16.t_sig.b bits\n"); $stop; end - if ($bits(i16.a_sig) !== 16) begin $write("%%Error i16.a_sig bits\n"); $stop; end - if (i16.t_sig.a !== 16'hFFFF) begin $write("%%Error i16.t_sig.a=%h\n", i16.t_sig.a); $stop; end - if (i16.t_sig.b !== 16'hFFFF) begin $write("%%Error i16.t_sig.b=%h\n", i16.t_sig.b); $stop; end - if (i16.a_sig !== 16'hFFFF) begin $write("%%Error i16.a_sig=%h\n", i16.a_sig); $stop; end + `checkh($bits(i16.t_sig), 32); + `checkh($bits(i16.t_sig.a), 16); + `checkh($bits(i16.t_sig.b), 16); + `checkh($bits(i16.a_sig), 16); + `checkh(i16.t_sig.a, 16'hFFFF); + `checkh(i16.t_sig.b, 16'hFFFF); + `checkh(i16.a_sig, 16'hFFFF); $write("*-* All Finished *-*\n"); $finish; diff --git a/test_regress/t/t_prop_followed_by.v b/test_regress/t/t_prop_followed_by.v index 6cc11045a..a1267bf7c 100644 --- a/test_regress/t/t_prop_followed_by.v +++ b/test_regress/t/t_prop_followed_by.v @@ -28,8 +28,7 @@ module t ( // Smoke: trivially-true forms must compile and never fail. assert property (@(posedge clk) 1'b1 #-# 1'b1); - assert property (@(posedge clk) 1'b1 #-# 1'b1) - action_hits++; + assert property (@(posedge clk) 1'b1 #-# 1'b1) action_hits++; assert property (@(posedge clk) 0 |-> (0 #-# 0)); assert property (@(posedge clk) 0 |-> (0 #=# 0)); diff --git a/test_regress/t/t_property_until.v b/test_regress/t/t_property_until.v index d20efa1fd..519369725 100644 --- a/test_regress/t/t_property_until.v +++ b/test_regress/t/t_property_until.v @@ -24,58 +24,45 @@ module t ( localparam MAX = 15; integer cyc = 1; - assert property (@(posedge clk) 0 until 1) - results[1].passs++; + assert property (@(posedge clk) 0 until 1) results[1].passs++; else results[1].fails++; - assert property (@(posedge clk) 1 until 0) - results[2].passs++; + assert property (@(posedge clk) 1 until 0) results[2].passs++; else results[2].fails++; - assert property (@(posedge clk) cyc < 5 until cyc >= 5) - results[3].passs++; + assert property (@(posedge clk) cyc < 5 until cyc >= 5) results[3].passs++; else results[3].fails++; - assert property (@(posedge clk) cyc % 3 == 0 until cyc % 5 == 0) - results[4].passs++; + assert property (@(posedge clk) cyc % 3 == 0 until cyc % 5 == 0) results[4].passs++; else results[4].fails++; - assert property (@(posedge clk) cyc % 3 != 0 until_with cyc % 4 != 0) - results[5].passs++; + assert property (@(posedge clk) cyc % 3 != 0 until_with cyc % 4 != 0) results[5].passs++; else results[5].fails++; - assert property (@(posedge clk) 0 s_until 1) - results[6].passs++; + assert property (@(posedge clk) 0 s_until 1) results[6].passs++; else results[6].fails++; - assert property (@(posedge clk) cyc < 5 s_until cyc >= 5) - results[7].passs++; + assert property (@(posedge clk) cyc < 5 s_until cyc >= 5) results[7].passs++; else results[7].fails++; - assert property (@(posedge clk) cyc % 3 == 0 s_until cyc % 5 == 0) - results[8].passs++; + assert property (@(posedge clk) cyc % 3 == 0 s_until cyc % 5 == 0) results[8].passs++; else results[8].fails++; // Check that s_until accepts immediately when RHS is true, even if LHS is false. - assert property (@(posedge clk) cyc % 2 == 0 s_until 1) - results[9].passs++; + assert property (@(posedge clk) cyc % 2 == 0 s_until 1) results[9].passs++; else results[9].fails++; // Check that s_until_with requires LHS when RHS is true on the same tick. - assert property (@(posedge clk) 0 s_until_with 1) - results[10].passs++; + assert property (@(posedge clk) 0 s_until_with 1) results[10].passs++; else results[10].fails++; - assert property (@(posedge clk) 1 s_until_with cyc >= 5) - results[11].passs++; + assert property (@(posedge clk) 1 s_until_with cyc >= 5) results[11].passs++; else results[11].fails++; - assert property (@(posedge clk) cyc <= 5 s_until_with cyc >= 5) - results[12].passs++; + assert property (@(posedge clk) cyc <= 5 s_until_with cyc >= 5) results[12].passs++; else results[12].fails++; - assert property (@(posedge clk) cyc < 5 s_until_with cyc >= 5) - results[13].passs++; + assert property (@(posedge clk) cyc < 5 s_until_with cyc >= 5) results[13].passs++; else results[13].fails++; always @(edge clk) begin diff --git a/test_regress/t/t_rand_member_mode_deriv.v b/test_regress/t/t_rand_member_mode_deriv.v index cb1376d2c..6f0aad4eb 100644 --- a/test_regress/t/t_rand_member_mode_deriv.v +++ b/test_regress/t/t_rand_member_mode_deriv.v @@ -6,9 +6,7 @@ class RandomValue; rand int value; - constraint small_int_c { - value < 10; - } + constraint small_int_c {value < 10;} task disable_val(); value.rand_mode(0); endtask diff --git a/test_regress/t/t_randc_wide_constraint.v b/test_regress/t/t_randc_wide_constraint.v index 49346d61c..02a4bfcf4 100644 --- a/test_regress/t/t_randc_wide_constraint.v +++ b/test_regress/t/t_randc_wide_constraint.v @@ -18,13 +18,13 @@ class RandcFull; // Full 16-bit domain (65536 valid values). // Old enumerateRandcValues() would try to enumerate all -> hang. - constraint range_c { value >= 0; } + constraint range_c {value >= 0;} endclass class RandcSmall; randc bit [15:0] value; - constraint range_c { value inside {[0:7]}; } + constraint range_c {value inside {[0 : 7]};} endclass typedef enum logic [59:0] { diff --git a/test_regress/t/t_randomize_param_with.v b/test_regress/t/t_randomize_param_with.v index e47dc870c..40f93bb5c 100644 --- a/test_regress/t/t_randomize_param_with.v +++ b/test_regress/t/t_randomize_param_with.v @@ -22,16 +22,19 @@ begin \ if (ok != 1) $stop; \ end -class Cls #(int LIMIT = 3); +class Cls #( + int LIMIT = 3 +); rand int x; - int y = -100; - constraint x_limit { x <= LIMIT; }; + int y = -100; + constraint x_limit {x <= LIMIT;} + ; endclass module t; initial begin - automatic Cls#() cd = new; - automatic Cls#(5) c5 = new; + automatic Cls #() cd = new; + automatic Cls #(5) c5 = new; `check_rand(cd, cd.x, x > 0, cd.x > 0 && cd.x <= 3); `check_rand(cd, cd.x, x > y, cd.x > -100 && cd.x <= 3); diff --git a/test_regress/t/t_randomize_pow2.v b/test_regress/t/t_randomize_pow2.v index 73be88d2b..c7c3a867a 100644 --- a/test_regress/t/t_randomize_pow2.v +++ b/test_regress/t/t_randomize_pow2.v @@ -8,7 +8,10 @@ class UnsignedPow2; rand bit [3:0] n; rand bit [15:0] result; - constraint c { n inside {[0:7]}; result == 16'(2**n); } + constraint c { + n inside {[0 : 7]}; + result == 16'(2 ** n); + } function void check(); if (result !== (16'h1 << n)) begin $display("FAIL UnsignedPow2: result=%0d expected 2**%0d=%0d", result, n, 16'h1 << n); @@ -21,7 +24,10 @@ endclass class SignedExpPow2; rand int signed n; rand bit [15:0] result; - constraint c { n inside {[-2:7]}; result == 16'(2**n); } + constraint c { + n inside {[-2 : 7]}; + result == 16'(2 ** n); + } function void check(); bit [15:0] expected; expected = (n >= 0) ? (16'h1 << n) : 16'h0; diff --git a/test_regress/t/t_randomize_prepost.v b/test_regress/t/t_randomize_prepost.v index f4427fedd..e56f6e6cf 100644 --- a/test_regress/t/t_randomize_prepost.v +++ b/test_regress/t/t_randomize_prepost.v @@ -9,9 +9,7 @@ `define checkd(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got=%0d exp=%0d\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0); // verilog_format: on -typedef enum int { - RANDOMIZED = 20 -} enumed_t; +typedef enum int {RANDOMIZED = 20} enumed_t; class Base; int m_pre; @@ -37,13 +35,13 @@ class Cls extends Base; int m_cpre; int m_cpost; function void pre_randomize; - m_cpre = 111; - super.pre_randomize(); + m_cpre = 111; + super.pre_randomize(); endfunction function void post_randomize; - m_cpost = 222; - super.post_randomize(); + m_cpost = 222; + super.post_randomize(); endfunction endclass @@ -82,7 +80,7 @@ module t; `checkd(c.m_cpost, 222); c = new; - rand_result = c.randomize() with { r == RANDOMIZED; }; + rand_result = c.randomize() with {r == RANDOMIZED;}; `checkd(rand_result, 1); `checkd(c.m_pre, 10); `checkd(c.m_cpre, 111); diff --git a/test_regress/t/t_randomize_rand_mode_constr.v b/test_regress/t/t_randomize_rand_mode_constr.v index 49e6dba4d..ad7d50401 100644 --- a/test_regress/t/t_randomize_rand_mode_constr.v +++ b/test_regress/t/t_randomize_rand_mode_constr.v @@ -13,7 +13,8 @@ class Bar; rand int x; rand Foo foo; - constraint x_gt_0 {x > 0;}; + constraint x_gt_0 {x > 0;} + ; function new; foo = new; @@ -22,11 +23,13 @@ endclass class Qux extends Bar; rand int y; - constraint y_gt_x {y > x;}; - constraint y_lt_10 {y < 10;}; + constraint y_gt_x {y > x;} + ; + constraint y_lt_10 {y < 10;} + ; function bit get_rand_mode(); - return bit'(y.rand_mode()); + return bit'(y.rand_mode()); endfunction function void test; @@ -43,37 +46,37 @@ class Qux extends Bar; if (foo.b.rand_mode() != 1) $stop; // Note has rand_mode parens for (int i = 0; i < 20; ++i) begin - x = 4; - y = 8; - foo.a = 15; - foo.b = 16; - void'(randomize()); - if (x >= y) $stop; - if (x != 4) ok = 1; - if (y != 8) $stop; - if (foo.a != 15) $stop; - if (foo.b != 16) ok = 1; - end - if (!ok) $stop; - foo.b = 16; - foo.rand_mode(0); - if (foo.rand_mode == 1) $stop; - if (foo.a.rand_mode == 1) $stop; - if (foo.b.rand_mode == 0) $stop; - void'(randomize()); - if (foo.a != 15) $stop; - if (foo.b != 16) $stop; - ok = 0; - foo.rand_mode(1); - if (foo.rand_mode == 0) $stop; - for (int i = 0; i < 20; ++i) begin - foo.a = 23; - foo.b = 42; - void'(randomize()); - if (foo.a != 23) $stop; - if (foo.b != 42) ok = 1; - end - if (!ok) $stop; + x = 4; + y = 8; + foo.a = 15; + foo.b = 16; + void'(randomize()); + if (x >= y) $stop; + if (x != 4) ok = 1; + if (y != 8) $stop; + if (foo.a != 15) $stop; + if (foo.b != 16) ok = 1; + end + if (!ok) $stop; + foo.b = 16; + foo.rand_mode(0); + if (foo.rand_mode == 1) $stop; + if (foo.a.rand_mode == 1) $stop; + if (foo.b.rand_mode == 0) $stop; + void'(randomize()); + if (foo.a != 15) $stop; + if (foo.b != 16) $stop; + ok = 0; + foo.rand_mode(1); + if (foo.rand_mode == 0) $stop; + for (int i = 0; i < 20; ++i) begin + foo.a = 23; + foo.b = 42; + void'(randomize()); + if (foo.a != 23) $stop; + if (foo.b != 42) ok = 1; + end + if (!ok) $stop; endfunction endclass @@ -117,17 +120,17 @@ module t; qux.foo.b.rand_mode(0); if (qux.foo.b.rand_mode == 1) $stop; for (int i = 0; i < 20; ++i) begin - qux.x = 5; - qux.y = 8; - qux.foo.a = 13; - qux.foo.b = 21; - res = qux.randomize() with {y > 5;}; - if (qux.x >= qux.y) $stop; - if (qux.y <= 5) $stop; - if (qux.x != 5) $stop; - if (qux.y != 8) ok = 1; - if (qux.foo.a != 13) ok = 1; - if (qux.foo.b != 21) $stop; + qux.x = 5; + qux.y = 8; + qux.foo.a = 13; + qux.foo.b = 21; + res = qux.randomize() with {y > 5;}; + if (qux.x >= qux.y) $stop; + if (qux.y <= 5) $stop; + if (qux.x != 5) $stop; + if (qux.y != 8) ok = 1; + if (qux.foo.a != 13) ok = 1; + if (qux.foo.b != 21) $stop; end if (!ok) $stop; diff --git a/test_regress/t/t_sequence_intersect.v b/test_regress/t/t_sequence_intersect.v index 12c4f2208..1e59b6495 100644 --- a/test_regress/t/t_sequence_intersect.v +++ b/test_regress/t/t_sequence_intersect.v @@ -52,12 +52,10 @@ module t ( // ========================================================================= // Boolean intersect: when a & b, intersect succeeds (equivalent to AND) - assert property (@(posedge clk) disable iff (cyc < 2) - (a & b) |-> (a intersect b)); + assert property (@(posedge clk) disable iff (cyc < 2) (a & b) |-> (a intersect b)); // Boolean intersect with constant true -- reduces to just 'a' - assert property (@(posedge clk) disable iff (cyc < 2) - a |-> (a intersect 1'b1)); + assert property (@(posedge clk) disable iff (cyc < 2) a |-> (a intersect 1'b1)); // ========================================================================= // Multi-cycle sequence intersect (IEEE 1800-2023 16.9.6) @@ -65,33 +63,26 @@ module t ( // ========================================================================= // Both arms have length 1; 1'b1 guarantees completion on both sides - assert property (@(posedge clk) - (a & b) |-> (a ##1 1'b1) intersect (b ##1 1'b1)); + assert property (@(posedge clk) (a & b) |-> (a ##1 1'b1) intersect (b ##1 1'b1)); // Both arms have length 2 - assert property (@(posedge clk) - (a & b) |-> (a ##2 1'b1) intersect (b ##2 1'b1)); + assert property (@(posedge clk) (a & b) |-> (a ##2 1'b1) intersect (b ##2 1'b1)); // Different internal structure, same total length (2 cycles each) - assert property (@(posedge clk) - (a & b) |-> (a ##1 1'b1 ##1 1'b1) intersect (b ##2 1'b1)); + assert property (@(posedge clk) (a & b) |-> (a ##1 1'b1 ##1 1'b1) intersect (b ##2 1'b1)); // Standalone constant intersect (always passes) - assert property (@(posedge clk) - (1'b1 ##1 1'b1) intersect (1'b1 ##1 1'b1)); + assert property (@(posedge clk) (1'b1 ##1 1'b1) intersect (1'b1 ##1 1'b1)); // Leading-delay operands (no offset-0 check): conjoin first offset > 0. - assert property (@(posedge clk) - (##2 1'b1) intersect (##2 1'b1)); + assert property (@(posedge clk) (##2 1'b1) intersect (##2 1'b1)); // Intersect with `throughout` on one side: exercises fixedLength's // SThroughout branch (recurses into rhs to compute the length). - cover property (@(posedge clk) - (a throughout (b ##1 c)) intersect (a ##1 c)); + cover property (@(posedge clk) (a throughout (b ##1 c)) intersect (a ##1 c)); // Intersect with equal-bound range delay (##[N:N]): exercises fixedLength's // isRangeDelay() branch where minD == maxD (else returns -1). - cover property (@(posedge clk) - (a ##[2:2] b) intersect (c ##2 d)); + cover property (@(posedge clk) (a ##[2:2] b) intersect (c ##2 d)); endmodule diff --git a/test_regress/t/t_sequence_sexpr_throughout.v b/test_regress/t/t_sequence_sexpr_throughout.v index 8b9fe3cfa..70c4ba241 100644 --- a/test_regress/t/t_sequence_sexpr_throughout.v +++ b/test_regress/t/t_sequence_sexpr_throughout.v @@ -14,16 +14,16 @@ // CRC-driven random stimulus exercises throughout with varying cond/a/b signals. module t ( - input clk + input clk ); integer cyc = 0; reg [63:0] crc = '0; // Derive signals from non-adjacent CRC bits (gap > max delay to avoid LFSR correlation) wire cond = crc[0]; - wire a = crc[4]; - wire b = crc[8]; - wire c = crc[12]; + wire a = crc[4]; + wire b = crc[8]; + wire c = crc[12]; int count_fail1 = 0; int count_fail2 = 0; @@ -34,36 +34,32 @@ module t ( // Test 1: a |-> (cond throughout (1'b1 ##3 1'b1)) // If a fires, cond must hold for 4 consecutive ticks (start + 3 delay ticks). - assert property (@(posedge clk) disable iff (cyc < 10) - a |-> (cond throughout (1'b1 ##3 1'b1))) - else count_fail1 <= count_fail1 + 1; + assert property (@(posedge clk) disable iff (cyc < 10) a |-> (cond throughout (1'b1 ##3 1'b1))) + else count_fail1 <= count_fail1 + 1; // Test 2: a |-> (cond throughout (1'b1 ##1 b)) // If a fires, cond must hold for 2 ticks and b must be true at tick +1. - assert property (@(posedge clk) disable iff (cyc < 10) - a |-> (cond throughout (1'b1 ##1 b))) - else count_fail2 <= count_fail2 + 1; + assert property (@(posedge clk) disable iff (cyc < 10) a |-> (cond throughout (1'b1 ##1 b))) + else count_fail2 <= count_fail2 + 1; // Test 3: a |-> (cond throughout b) // No delay: degenerates to a |-> (cond && b). - assert property (@(posedge clk) disable iff (cyc < 10) - a |-> (cond throughout b)) - else count_fail3 <= count_fail3 + 1; + assert property (@(posedge clk) disable iff (cyc < 10) a |-> (cond throughout b)) + else count_fail3 <= count_fail3 + 1; // Test 4: throughout with range delay on RHS (IEEE 16.9.9) - assert property (@(posedge clk) disable iff (cyc < 10) - a |-> (a throughout (b ##[1:2] c))) - else count_fail4 <= count_fail4 + 1; + assert property (@(posedge clk) disable iff (cyc < 10) a |-> (a throughout (b ##[1:2] c))) + else count_fail4 <= count_fail4 + 1; // Test 5: throughout with temporal 'and' on RHS assert property (@(posedge clk) disable iff (cyc < 10) a |-> (a throughout ((b ##1 c) and (c ##1 b)))) - else count_fail5 <= count_fail5 + 1; + else count_fail5 <= count_fail5 + 1; // Test 6: nested throughout assert property (@(posedge clk) disable iff (cyc < 10) a |-> (a throughout (b throughout (b ##1 c)))) - else count_fail6 <= count_fail6 + 1; + else count_fail6 <= count_fail6 + 1; // Throughout with range-delay, pure-boolean RHS: the range-delay SExpr // generates midSource vertices that inherit the throughout guard. @@ -76,14 +72,14 @@ module t ( always @(posedge clk) begin `ifdef TEST_VERBOSE - $write("[%0t] cyc==%0d crc=%x cond=%b a=%b b=%b c=%b\n", - $time, cyc, crc, cond, a, b, c); + $write("[%0t] cyc==%0d crc=%x cond=%b a=%b b=%b c=%b\n", $time, cyc, crc, cond, a, b, c); `endif cyc <= cyc + 1; crc <= {crc[62:0], crc[63] ^ crc[2] ^ crc[0]}; if (cyc == 0) begin crc <= 64'h5aef0c8d_d70a4497; - end else if (cyc == 99) begin + end + else if (cyc == 99) begin `checkh(crc, 64'hc77bb9b3784ea091); `checkd(count_fail1, 28); `checkd(count_fail2, 33); diff --git a/test_regress/t/t_sequence_within.v b/test_regress/t/t_sequence_within.v index a7cc3c5ed..6be935358 100644 --- a/test_regress/t/t_sequence_within.v +++ b/test_regress/t/t_sequence_within.v @@ -36,23 +36,19 @@ module t ( int count_p10 = 0; // Boolean within boolean: equivalent to `a && b`. - assert property (@(posedge clk) disable iff (cyc < 10) - (a & b) |-> (a within b)) + assert property (@(posedge clk) disable iff (cyc < 10) (a & b) |-> (a within b)) count_p1 <= count_p1 + 1; // Boolean within constant true: always passes when a is high. - assert property (@(posedge clk) disable iff (cyc < 10) - a |-> (a within 1'b1)) + assert property (@(posedge clk) disable iff (cyc < 10) a |-> (a within 1'b1)) count_p2 <= count_p2 + 1; // `a` must hold at some offset within the c ##1 d window. - cover property (@(posedge clk) disable iff (cyc < 10) - a within (c ##1 d)) + cover property (@(posedge clk) disable iff (cyc < 10) a within (c ##1 d)) count_p3 <= count_p3 + 1; // `a` within a length-3 outer (four possible offsets). - cover property (@(posedge clk) disable iff (cyc < 10) - a within (c ##3 d)) + cover property (@(posedge clk) disable iff (cyc < 10) a within (c ##3 d)) count_p4 <= count_p4 + 1; // Equal-length inner/outer: single offset, reduces to intersect. @@ -61,13 +57,11 @@ module t ( count_p5 <= count_p5 + 1; // Inner length 1, outer length 3 -> three offsets (0, 1, 2). - cover property (@(posedge clk) disable iff (cyc < 10) - (a ##1 b) within (c ##3 d)) + cover property (@(posedge clk) disable iff (cyc < 10) (a ##1 b) within (c ##3 d)) count_p6 <= count_p6 + 1; // Inner length 2, outer length 3 -> two offsets (0, 1). - cover property (@(posedge clk) disable iff (cyc < 10) - (a ##2 b) within (c ##3 d)) + cover property (@(posedge clk) disable iff (cyc < 10) (a ##2 b) within (c ##3 d)) count_p7 <= count_p7 + 1; // within nested inside intersect: both must match equal length. @@ -77,8 +71,7 @@ module t ( // within combined with throughout on the outer: throughout's rhs // fixedLength still feeds into within. - cover property (@(posedge clk) disable iff (cyc < 10) - a within (a throughout (b ##1 c))) + cover property (@(posedge clk) disable iff (cyc < 10) a within (a throughout (b ##1 c))) count_p9 <= count_p9 + 1; // within on the RHS of intersect: forces the parser into the direct diff --git a/test_regress/t/t_stream_bitqueue.v b/test_regress/t/t_stream_bitqueue.v index 9b4c1ff4c..ed9996d7e 100644 --- a/test_regress/t/t_stream_bitqueue.v +++ b/test_regress/t/t_stream_bitqueue.v @@ -547,23 +547,19 @@ module t ( cdata_q = cdata_q_t'( 256'h00010203_04050607_08090a0b_0c0d0e0f_10111213_14151617_18191a1b_1c1d1e1f); p256 = {>>{cdata_q}}; - `checkh(p256, - 256'h00010203_04050607_08090a0b_0c0d0e0f_10111213_14151617_18191a1b_1c1d1e1f); + `checkh(p256, 256'h00010203_04050607_08090a0b_0c0d0e0f_10111213_14151617_18191a1b_1c1d1e1f); cdata_q = cdata_q_t'(64'h00010203_04050607); p256 = {>>{cdata_q}}; - `checkh(p256, - 256'h00010203_04050607_00000000_00000000_00000000_00000000_00000000_00000000); + `checkh(p256, 256'h00010203_04050607_00000000_00000000_00000000_00000000_00000000_00000000); // 64-bit elements qdata_q = qdata_logic_q_t'( 256'hdeadbeef_cafebabe_feedface_12345678_11112222_33334444_55556666_77778888); p256 = {>>{qdata_q}}; - `checkh(p256, - 256'hdeadbeef_cafebabe_feedface_12345678_11112222_33334444_55556666_77778888); + `checkh(p256, 256'hdeadbeef_cafebabe_feedface_12345678_11112222_33334444_55556666_77778888); qdata_q = qdata_logic_q_t'(128'hdeadbeef_cafebabe_feedface_12345678); p256 = {>>{qdata_q}}; - `checkh(p256, - 256'hdeadbeef_cafebabe_feedface_12345678_00000000_00000000_00000000_00000000); + `checkh(p256, 256'hdeadbeef_cafebabe_feedface_12345678_00000000_00000000_00000000_00000000); // 128-bit (VlWide) elements wide_q = wide_q_t'( diff --git a/test_regress/t/t_stream_crc_example.v b/test_regress/t/t_stream_crc_example.v index b78596b86..35d54577f 100644 --- a/test_regress/t/t_stream_crc_example.v +++ b/test_regress/t/t_stream_crc_example.v @@ -51,7 +51,7 @@ module t ( bits.push_front(1'b0); po = {<<8{bit_q_t'({<<{bits}})}}; - s = $sformatf("p=%p", p); + s = $sformatf("p=%p", p); `checks(s, "p='{'h84, 'haa}"); s = $sformatf("bits=%p", bits); @@ -74,9 +74,11 @@ module t ( if (cyc == 0) begin crc <= 64'h5aef0c8d_d70a4497; sum <= '0; - end else if (cyc < 10) begin + end + else if (cyc < 10) begin sum <= '0; - end else if (cyc == 99) begin + end + else if (cyc == 99) begin `checkh(crc, 64'hc77bb9b3784ea091); `checkh(sum, 64'h9721d4e989defb24); $write("*-* All Finished *-*\n"); diff --git a/test_regress/t/t_stream_queue.v b/test_regress/t/t_stream_queue.v index 54bba0cb0..c26ff6f1c 100644 --- a/test_regress/t/t_stream_queue.v +++ b/test_regress/t/t_stream_queue.v @@ -5,8 +5,9 @@ // SPDX-License-Identifier: CC0-1.0 `define stop $stop -`define checks(gotv,expv) do if ((gotv) != (expv)) begin $write("%%Error: %s:%0d: got='%h' exp='%h'\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0); -`define checks_w(width,gotv,expv) do begin \ +`define checks(gotv, + expv) do if ((gotv) != (expv)) begin $write("%%Error: %s:%0d: got='%h' exp='%h'\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0); +`define checks_w(width, gotv, expv) do begin \ logic [(width)-1:0] got_check; \ logic [(width)-1:0] exp_check; \ got_check = (gotv); \ @@ -36,14 +37,14 @@ module t; logic [15:0] sdata_pkt[$]; int int_pkt[$]; logic [63:0] qdata_pkt[$]; - logic [128:0] vlwide_pkt_129[$];//this is off by one to test edge cases + logic [128:0] vlwide_pkt_129[$]; //this is off by one to test edge cases logic [127:0] vlwide_pkt_128[$]; -/* verilator lint_off ASCRANGE */ + /* verilator lint_off ASCRANGE */ logic [0:7] byte_pkt_rev[$]; logic [0:15] sdata_pkt_rev[$]; logic [0:31] int_pkt_rev[$]; logic [0:63] qdata_pkt_rev[$]; - logic [0:128] vlwide_pkt_129_rev[$];//this is off by one to test edge cases + logic [0:128] vlwide_pkt_129_rev[$]; //this is off by one to test edge cases logic [0:127] vlwide_pkt_128_rev[$]; @@ -53,32 +54,32 @@ module t; i_crc = 42; i_char = 15; i_short = 16'hFF; - #0; // this forces no-life + #0; // this forces no-life //TODO make this work with V3Life //-------------------- STREAML ------------------------------------ //----------- CData QUEUE -------- byte_pkt = {<<8{i_char}}; o_char = {<<8{byte_pkt}}; - `checks(o_char,i_char); + `checks(o_char, i_char); byte_pkt = {<<8{i_short}}; o_short = {<<8{byte_pkt}}; - `checks(o_short,i_short); + `checks(o_short, i_short); byte_pkt = {<<8{i_header}}; o_header = {<<8{byte_pkt}}; - `checks(o_header,i_header); + `checks(o_header, i_header); - byte_pkt = {<<8{i_header,i_len}}; - {<<8{o_header,o_len}} = byte_pkt; - `checks({i_header,i_len},{o_header,o_len}); + byte_pkt = {<<8{i_header, i_len}}; + {<<8{o_header, o_len}} = byte_pkt; + `checks({i_header, i_len}, {o_header, o_len}); - byte_pkt = {<<8{i_header,i_len,i_crc,i_data}}; - {<<8{o_header,o_len,o_crc,o_data}} = byte_pkt; + byte_pkt = {<<8{i_header, i_len, i_crc, i_data}}; + {<<8{o_header, o_len, o_crc, o_data}} = byte_pkt; - `checks_w(128, {>>{byte_pkt}},{<<8{i_header,i_len,i_crc,i_data}}); - `checks_w(128, {i_header,i_len,i_crc,i_data},{<<8{byte_pkt}}); - `checks({o_header,o_len,o_crc,o_data} ,{i_header,i_len,i_crc,i_data}); + `checks_w(128, {>>{byte_pkt}}, {<<8{i_header, i_len, i_crc, i_data}}); + `checks_w(128, {i_header, i_len, i_crc, i_data}, {<<8{byte_pkt}}); + `checks({o_header, o_len, o_crc, o_data}, {i_header, i_len, i_crc, i_data}); // //----------- SData QUEUE -------- // sdata_pkt = {<<8{i_char}}; @@ -88,38 +89,38 @@ module t; sdata_pkt = {<<8{i_short}}; o_short = {<<8{sdata_pkt}}; - `checks(o_short,i_short); + `checks(o_short, i_short); sdata_pkt = {<<8{i_header}}; o_header = {<<8{sdata_pkt}}; - `checks(o_header,i_header); + `checks(o_header, i_header); //test with QData - sdata_pkt = {<<8{i_header,i_len}}; - {<<8{o_header,o_len}} = sdata_pkt; - `checks({i_header,i_len},{o_header,o_len}); + sdata_pkt = {<<8{i_header, i_len}}; + {<<8{o_header, o_len}} = sdata_pkt; + `checks({i_header, i_len}, {o_header, o_len}); - sdata_pkt = {<<8{i_header,i_len,i_crc,i_data}}; - {<<8{o_header,o_len,o_crc,o_data}} = sdata_pkt; + sdata_pkt = {<<8{i_header, i_len, i_crc, i_data}}; + {<<8{o_header, o_len, o_crc, o_data}} = sdata_pkt; - `checks_w(128, {>>{sdata_pkt}},{<<8{i_header,i_len,i_crc,i_data}}); - `checks({o_header,o_len,o_crc,o_data} ,{i_header,i_len,i_crc,i_data}); + `checks_w(128, {>>{sdata_pkt}}, {<<8{i_header, i_len, i_crc, i_data}}); + `checks({o_header, o_len, o_crc, o_data}, {i_header, i_len, i_crc, i_data}); //----------- IData QUEUE -------- int_pkt = {<<8{i_header}}; o_header = {<<8{int_pkt}}; - `checks(o_header,i_header); + `checks(o_header, i_header); //test with QData - int_pkt = {<<8{i_header,i_len}}; - {<<8{o_header,o_len}} = int_pkt; - `checks({i_header,i_len},{o_header,o_len}); + int_pkt = {<<8{i_header, i_len}}; + {<<8{o_header, o_len}} = int_pkt; + `checks({i_header, i_len}, {o_header, o_len}); - int_pkt = {<<8{i_header,i_len,i_crc,i_data}}; - {<<8{o_header,o_len,o_crc,o_data}} = int_pkt; + int_pkt = {<<8{i_header, i_len, i_crc, i_data}}; + {<<8{o_header, o_len, o_crc, o_data}} = int_pkt; - `checks_w(128, {>>{int_pkt}},{<<8{i_header,i_len,i_crc,i_data}}); - `checks({o_header,o_len,o_crc,o_data} ,{i_header,i_len,i_crc,i_data}); + `checks_w(128, {>>{int_pkt}}, {<<8{i_header, i_len, i_crc, i_data}}); + `checks({o_header, o_len, o_crc, o_data}, {i_header, i_len, i_crc, i_data}); //----------- QData QUEUE -------- qdata_pkt = {<<8{i_header}}; @@ -129,250 +130,254 @@ module t; // `checks(o_header,i_header); //test with QData - qdata_pkt = {<<8{i_header,i_len}}; - {<<8{o_header,o_len}} = qdata_pkt; - `checks({i_header,i_len},{o_header,o_len}); + qdata_pkt = {<<8{i_header, i_len}}; + {<<8{o_header, o_len}} = qdata_pkt; + `checks({i_header, i_len}, {o_header, o_len}); - qdata_pkt = {<<8{i_header,i_len,i_crc,i_data}}; - {<<8{o_header,o_len,o_crc,o_data}} = qdata_pkt; + qdata_pkt = {<<8{i_header, i_len, i_crc, i_data}}; + {<<8{o_header, o_len, o_crc, o_data}} = qdata_pkt; - `checks_w(128, {>>{qdata_pkt}},{<<8{i_header,i_len,i_crc,i_data}}); - `checks({o_header,o_len,o_crc,o_data} ,{i_header,i_len,i_crc,i_data}); + `checks_w(128, {>>{qdata_pkt}}, {<<8{i_header, i_len, i_crc, i_data}}); + `checks({o_header, o_len, o_crc, o_data}, {i_header, i_len, i_crc, i_data}); // ----------- VLWide QUEUE -------- // test with QData - vlwide_pkt_129 = {<<8{i_header,i_len}}; + vlwide_pkt_129 = {<<8{i_header, i_len}}; {<<8{o_header,o_len}} = vlwide_pkt_129; //TODO this shouldn't compile lhs should not be smaller then rhs // `checks({i_header,i_len},{o_header,o_len}); - vlwide_pkt_129 = {<<8{i_header,i_len,i_crc,i_data}}; + vlwide_pkt_129 = {<<8{i_header, i_len, i_crc, i_data}}; /* verilator lint_off WIDTHEXPAND */ - wide129 = {<<8{i_header,i_len,i_crc,i_data}}; - `checks_w(129, {>>{vlwide_pkt_129}},wide129); + wide129 = {<<8{i_header, i_len, i_crc, i_data}}; + `checks_w(129, {>>{vlwide_pkt_129}}, wide129); /* verilator lint_on WIDTHEXPAND */ //------------------------------- REVERSE ENDIAN ------------------------------ //----------- CData QUEUE -------- byte_pkt_rev = {<<8{i_char}}; o_char = {<<8{byte_pkt_rev}}; - `checks(o_char,i_char); + `checks(o_char, i_char); byte_pkt_rev = {<<8{i_short}}; o_short = {<<8{byte_pkt_rev}}; - `checks(o_short,i_short); + `checks(o_short, i_short); byte_pkt_rev = {<<8{i_header}}; o_header = {<<8{byte_pkt_rev}}; - `checks(o_header,i_header); + `checks(o_header, i_header); - byte_pkt_rev = {<<8{i_header,i_len}}; - {<<8{o_header,o_len}} = byte_pkt_rev; - `checks({i_header,i_len},{o_header,o_len}); + byte_pkt_rev = {<<8{i_header, i_len}}; + {<<8{o_header, o_len}} = byte_pkt_rev; + `checks({i_header, i_len}, {o_header, o_len}); - byte_pkt_rev = {<<8{i_header,i_len,i_crc,i_data}}; - {<<8{o_header,o_len,o_crc,o_data}} = byte_pkt_rev; + byte_pkt_rev = {<<8{i_header, i_len, i_crc, i_data}}; + {<<8{o_header, o_len, o_crc, o_data}} = byte_pkt_rev; - `checks_w(128, {>>{byte_pkt_rev}},{<<8{i_header,i_len,i_crc,i_data}}); - `checks_w(128, {i_header,i_len,i_crc,i_data},{<<8{byte_pkt_rev}}); - `checks({o_header,o_len,o_crc,o_data} ,{i_header,i_len,i_crc,i_data}); + `checks_w(128, {>>{byte_pkt_rev}}, {<<8{i_header, i_len, i_crc, i_data}}); + `checks_w(128, {i_header, i_len, i_crc, i_data}, {<<8{byte_pkt_rev}}); + `checks({o_header, o_len, o_crc, o_data}, {i_header, i_len, i_crc, i_data}); - //----------- SData QUEUE -------- + //----------- SData QUEUE -------- sdata_pkt_rev = {<<8{i_short}}; o_short = {<<8{sdata_pkt_rev}}; - `checks(o_short,i_short); + `checks(o_short, i_short); sdata_pkt_rev = {<<8{i_header}}; o_header = {<<8{sdata_pkt_rev}}; - `checks(o_header,i_header); + `checks(o_header, i_header); //test with QData - sdata_pkt_rev = {<<8{i_header,i_len}}; - {<<8{o_header,o_len}} = sdata_pkt_rev; - `checks({i_header,i_len},{o_header,o_len}); + sdata_pkt_rev = {<<8{i_header, i_len}}; + {<<8{o_header, o_len}} = sdata_pkt_rev; + `checks({i_header, i_len}, {o_header, o_len}); - sdata_pkt_rev = {<<8{i_header,i_len,i_crc,i_data}}; - {<<8{o_header,o_len,o_crc,o_data}} = sdata_pkt_rev; + sdata_pkt_rev = {<<8{i_header, i_len, i_crc, i_data}}; + {<<8{o_header, o_len, o_crc, o_data}} = sdata_pkt_rev; - `checks_w(128, {>>{sdata_pkt_rev}},{<<8{i_header,i_len,i_crc,i_data}}); - `checks({o_header,o_len,o_crc,o_data} ,{i_header,i_len,i_crc,i_data}); + `checks_w(128, {>>{sdata_pkt_rev}}, {<<8{i_header, i_len, i_crc, i_data}}); + `checks({o_header, o_len, o_crc, o_data}, {i_header, i_len, i_crc, i_data}); //----------- IData QUEUE -------- int_pkt_rev = {<<8{i_header}}; o_header = {<<8{int_pkt_rev}}; - `checks(o_header,i_header); + `checks(o_header, i_header); //test with QData - int_pkt_rev = {<<8{i_header,i_len}}; - {<<8{o_header,o_len}} = int_pkt_rev; - `checks({i_header,i_len},{o_header,o_len}); + int_pkt_rev = {<<8{i_header, i_len}}; + {<<8{o_header, o_len}} = int_pkt_rev; + `checks({i_header, i_len}, {o_header, o_len}); - int_pkt_rev = {<<8{i_header,i_len,i_crc,i_data}}; - {<<8{o_header,o_len,o_crc,o_data}} = int_pkt_rev; + int_pkt_rev = {<<8{i_header, i_len, i_crc, i_data}}; + {<<8{o_header, o_len, o_crc, o_data}} = int_pkt_rev; - `checks_w(128, {>>{int_pkt_rev}},{<<8{i_header,i_len,i_crc,i_data}}); - `checks({o_header,o_len,o_crc,o_data} ,{i_header,i_len,i_crc,i_data}); + `checks_w(128, {>>{int_pkt_rev}}, {<<8{i_header, i_len, i_crc, i_data}}); + `checks({o_header, o_len, o_crc, o_data}, {i_header, i_len, i_crc, i_data}); //----------- QData QUEUE -------- //test with QData - qdata_pkt_rev = {<<8{i_header,i_len}}; - {<<8{o_header,o_len}} = qdata_pkt_rev; - `checks({i_header,i_len},{o_header,o_len}); + qdata_pkt_rev = {<<8{i_header, i_len}}; + {<<8{o_header, o_len}} = qdata_pkt_rev; + `checks({i_header, i_len}, {o_header, o_len}); - qdata_pkt_rev = {<<8{i_header,i_len,i_crc,i_data}}; - {<<8{o_header,o_len,o_crc,o_data}} = qdata_pkt_rev; + qdata_pkt_rev = {<<8{i_header, i_len, i_crc, i_data}}; + {<<8{o_header, o_len, o_crc, o_data}} = qdata_pkt_rev; - `checks_w(128, {>>{qdata_pkt_rev}},{<<8{i_header,i_len,i_crc,i_data}}); - `checks({o_header,o_len,o_crc,o_data} ,{i_header,i_len,i_crc,i_data}); + `checks_w(128, {>>{qdata_pkt_rev}}, {<<8{i_header, i_len, i_crc, i_data}}); + `checks({o_header, o_len, o_crc, o_data}, {i_header, i_len, i_crc, i_data}); // ----------- VLWide QUEUE -------- - vlwide_pkt_129_rev = {<<8{i_header,i_len,i_crc,i_data}}; + vlwide_pkt_129_rev = {<<8{i_header, i_len, i_crc, i_data}}; /* verilator lint_off WIDTHEXPAND */ - wide129 = {<<8{i_header,i_len,i_crc,i_data}}; + wide129 = {<<8{i_header, i_len, i_crc, i_data}}; /* verilator lint_on WIDTHEXPAND */ - `checks_w(129, {>>{vlwide_pkt_129_rev}},wide129); + `checks_w(129, {>>{vlwide_pkt_129_rev}}, wide129); // // -------------------- STREAMR ------------------------------------ // //----------- CData QUEUE -------- byte_pkt = {>>{i_header}}; o_header = {>>{byte_pkt}}; - `checks(o_header,i_header); + `checks(o_header, i_header); - byte_pkt = {>>{i_header,i_len}}; - {>>{o_header,o_len}} = byte_pkt; - `checks_w(64, {>>{i_header,i_len}},{>>{o_header,o_len}}); - `checks({i_header,i_len},{o_header,o_len}); + byte_pkt = {>>{i_header, i_len}}; + {>>{o_header, o_len}} = byte_pkt; + `checks_w(64, {>>{i_header, i_len}}, {>>{o_header, o_len}}); + `checks({i_header, i_len}, {o_header, o_len}); - byte_pkt = {>>{i_header,i_len,i_crc,i_data}}; - {>>{o_header,o_len,o_crc,o_data}} = byte_pkt; + byte_pkt = {>>{i_header, i_len, i_crc, i_data}}; + {>>{o_header, o_len, o_crc, o_data}} = byte_pkt; - `checks_w(128, {>>{byte_pkt}},{>>{i_header,i_len,i_crc,i_data}}); - `checks({o_header,o_len,o_crc,o_data} ,{i_header,i_len,i_crc,i_data}); + `checks_w(128, {>>{byte_pkt}}, {>>{i_header, i_len, i_crc, i_data}}); + `checks({o_header, o_len, o_crc, o_data}, {i_header, i_len, i_crc, i_data}); //----------- IData QUEUE -------- int_pkt = {>>{i_header}}; o_header = {>>{int_pkt}}; - `checks(o_header,i_header); - `checks_w(32, o_header,{>>{int_pkt}}); - `checks_w(32, {>>{o_header}},{>>{int_pkt}}); + `checks(o_header, i_header); + `checks_w(32, o_header, {>>{int_pkt}}); + `checks_w(32, {>>{o_header}}, {>>{int_pkt}}); //test with QData - int_pkt = {>>{i_header,i_len}}; - {>>{o_header,o_len}} = int_pkt; - `checks({i_header,i_len},{o_header,o_len}); + int_pkt = {>>{i_header, i_len}}; + {>>{o_header, o_len}} = int_pkt; + `checks({i_header, i_len}, {o_header, o_len}); - int_pkt = {>>{i_header,i_len,i_crc,i_data}}; - {>>{o_header,o_len,o_crc,o_data}} = int_pkt; + int_pkt = {>>{i_header, i_len, i_crc, i_data}}; + {>>{o_header, o_len, o_crc, o_data}} = int_pkt; - `checks_w(128, {>>{int_pkt}},{>>{i_header,i_len,i_crc,i_data}}); - `checks({o_header,o_len,o_crc,o_data} ,{i_header,i_len,i_crc,i_data}); + `checks_w(128, {>>{int_pkt}}, {>>{i_header, i_len, i_crc, i_data}}); + `checks({o_header, o_len, o_crc, o_data}, {i_header, i_len, i_crc, i_data}); //----------- QData QUEUE -------- // test with QData - qdata_pkt = {>>{i_header,i_len}}; - {>>{o_header,o_len}} = qdata_pkt; - `checks({i_header,i_len},{o_header,o_len}); + qdata_pkt = {>>{i_header, i_len}}; + {>>{o_header, o_len}} = qdata_pkt; + `checks({i_header, i_len}, {o_header, o_len}); - qdata_pkt = {>>{i_header,i_len,i_crc,i_data}}; - {>>{o_header,o_len,o_crc,o_data}} = qdata_pkt; + qdata_pkt = {>>{i_header, i_len, i_crc, i_data}}; + {>>{o_header, o_len, o_crc, o_data}} = qdata_pkt; - `checks_w(128, {>>{qdata_pkt}},{>>{i_header,i_len,i_crc,i_data}}); - `checks({o_header,o_len,o_crc,o_data} ,{i_header,i_len,i_crc,i_data}); + `checks_w(128, {>>{qdata_pkt}}, {>>{i_header, i_len, i_crc, i_data}}); + `checks({o_header, o_len, o_crc, o_data}, {i_header, i_len, i_crc, i_data}); // ----------- VLWide QUEUE -------- // test with QData - vlwide_pkt_129 = {>>{i_header,i_len}}; - {>>{o_header,o_len}} = vlwide_pkt_129; - `checks({i_header,i_len},{o_header,o_len}); + vlwide_pkt_129 = {>>{i_header, i_len}}; + {>>{o_header, o_len}} = vlwide_pkt_129; + `checks({i_header, i_len}, {o_header, o_len}); - vlwide_pkt_129 = {>>{i_header,i_len,i_crc,i_data}}; - {>>{o_header,o_len,o_crc,o_data}} = vlwide_pkt_129; + vlwide_pkt_129 = {>>{i_header, i_len, i_crc, i_data}}; + {>>{o_header, o_len, o_crc, o_data}} = vlwide_pkt_129; - `checks_w(129, {>>{vlwide_pkt_129}},{>>{1'b0,i_header,i_len,i_crc,i_data}}); - `checks({o_header,o_len,o_crc,o_data} ,{i_header,i_len,i_crc,i_data}); + `checks_w(129, {>>{vlwide_pkt_129}}, {>>{1'b0, i_header, i_len, i_crc, i_data}}); + `checks({o_header, o_len, o_crc, o_data}, {i_header, i_len, i_crc, i_data}); //---------- into other queues ------ - int_pkt = {>>{i_header,i_len,i_crc,i_data}}; + int_pkt = {>>{i_header, i_len, i_crc, i_data}}; byte_pkt = {>>{int_pkt}}; - `checks_w(128, {>>{byte_pkt}},{>>{i_header,i_len,i_crc,i_data}}); + `checks_w(128, {>>{byte_pkt}}, {>>{i_header, i_len, i_crc, i_data}}); - byte_pkt = {>>{i_header,i_len,i_crc,i_data}}; + byte_pkt = {>>{i_header, i_len, i_crc, i_data}}; int_pkt = {>>{byte_pkt}}; - `checks_w(128, {>>{int_pkt}},{>>{i_header,i_len,i_crc,i_data}}); + `checks_w(128, {>>{int_pkt}}, {>>{i_header, i_len, i_crc, i_data}}); - byte_pkt = {>>{i_header,i_len,i_crc,i_data}}; + byte_pkt = {>>{i_header, i_len, i_crc, i_data}}; int_pkt = {>>{byte_pkt}}; - `checks_w(128, {>>{int_pkt}},{>>{i_header,i_len,i_crc,i_data}}); + `checks_w(128, {>>{int_pkt}}, {>>{i_header, i_len, i_crc, i_data}}); - sdata_pkt = {>>{i_header,i_len,i_crc,i_data}}; + sdata_pkt = {>>{i_header, i_len, i_crc, i_data}}; byte_pkt = {>>{sdata_pkt}}; - `checks_w(128, {>>{byte_pkt}},{>>{i_header,i_len,i_crc,i_data}}); + `checks_w(128, {>>{byte_pkt}}, {>>{i_header, i_len, i_crc, i_data}}); - byte_pkt = {>>{i_header,i_len,i_crc,i_data}}; + byte_pkt = {>>{i_header, i_len, i_crc, i_data}}; sdata_pkt = {>>{byte_pkt}}; - `checks_w(128, {>>{sdata_pkt}},{>>{i_header,i_len,i_crc,i_data}}); + `checks_w(128, {>>{sdata_pkt}}, {>>{i_header, i_len, i_crc, i_data}}); - byte_pkt = {>>{i_header,i_len,i_crc,i_data}}; + byte_pkt = {>>{i_header, i_len, i_crc, i_data}}; qdata_pkt = {>>{byte_pkt}}; - `checks_w(128, {>>{qdata_pkt}},{>>{i_header,i_len,i_crc,i_data}}); + `checks_w(128, {>>{qdata_pkt}}, {>>{i_header, i_len, i_crc, i_data}}); - qdata_pkt = {>>{i_header,i_len,i_crc,i_data}}; + qdata_pkt = {>>{i_header, i_len, i_crc, i_data}}; byte_pkt = {>>{qdata_pkt}}; - `checks_w(128, {>>{byte_pkt}},{>>{i_header,i_len,i_crc,i_data}}); + `checks_w(128, {>>{byte_pkt}}, {>>{i_header, i_len, i_crc, i_data}}); - qdata_pkt = {>>{i_header,i_len,i_crc,i_data}}; + qdata_pkt = {>>{i_header, i_len, i_crc, i_data}}; int_pkt = {>>{qdata_pkt}}; - `checks_w(128, {>>{int_pkt}},{>>{i_header,i_len,i_crc,i_data}}); + `checks_w(128, {>>{int_pkt}}, {>>{i_header, i_len, i_crc, i_data}}); - int_pkt = {>>{i_header,i_len,i_crc,i_data}}; + int_pkt = {>>{i_header, i_len, i_crc, i_data}}; qdata_pkt = {>>{int_pkt}}; - `checks_w(128, {>>{qdata_pkt}},{>>{i_header,i_len,i_crc,i_data}}); + `checks_w(128, {>>{qdata_pkt}}, {>>{i_header, i_len, i_crc, i_data}}); - byte_pkt = {>>{i_header,i_len,i_crc,i_data}}; + byte_pkt = {>>{i_header, i_len, i_crc, i_data}}; vlwide_pkt_128 = {>>{byte_pkt}}; - `checks_w(128, {>>{vlwide_pkt_128}},{>>{i_header,i_len,i_crc,i_data}}); + `checks_w(128, {>>{vlwide_pkt_128}}, {>>{i_header, i_len, i_crc, i_data}}); - vlwide_pkt_128 = {>>{i_header,i_len,i_crc,i_data}}; + vlwide_pkt_128 = {>>{i_header, i_len, i_crc, i_data}}; byte_pkt = {>>{vlwide_pkt_128}}; - `checks_w(128, {i_header,i_len,i_crc,i_data},{>>{byte_pkt}}); - `checks_w(128, {>>{byte_pkt}},{>>{i_header,i_len,i_crc,i_data}}); + `checks_w(128, {i_header, i_len, i_crc, i_data}, {>>{byte_pkt}}); + `checks_w(128, {>>{byte_pkt}}, {>>{i_header, i_len, i_crc, i_data}}); - int_pkt = {>>{i_header,i_len,i_crc,i_data}}; + int_pkt = {>>{i_header, i_len, i_crc, i_data}}; vlwide_pkt_128 = {>>{int_pkt}}; - `checks_w(128, {i_header,i_len,i_crc,i_data},{>>{vlwide_pkt_128}}); - `checks_w(128, {>>{vlwide_pkt_128}},{>>{i_header,i_len,i_crc,i_data}}); + `checks_w(128, {i_header, i_len, i_crc, i_data}, {>>{vlwide_pkt_128}}); + `checks_w(128, {>>{vlwide_pkt_128}}, {>>{i_header, i_len, i_crc, i_data}}); - vlwide_pkt_128 = {>>{i_header,i_len,i_crc,i_data}}; + vlwide_pkt_128 = {>>{i_header, i_len, i_crc, i_data}}; int_pkt = {>>{vlwide_pkt_128}}; - `checks_w(128, {i_header,i_len,i_crc,i_data},{>>{int_pkt}}); - `checks_w(128, {>>{int_pkt}},{>>{i_header,i_len,i_crc,i_data}}); + `checks_w(128, {i_header, i_len, i_crc, i_data}, {>>{int_pkt}}); + `checks_w(128, {>>{int_pkt}}, {>>{i_header, i_len, i_crc, i_data}}); - qdata_pkt = {>>{i_header,i_len,i_crc,i_data}}; + qdata_pkt = {>>{i_header, i_len, i_crc, i_data}}; vlwide_pkt_128 = {>>{qdata_pkt}}; - `checks_w(128, {i_header,i_len,i_crc,i_data},{>>{vlwide_pkt_128}}); - `checks_w(128, {>>{vlwide_pkt_128}},{>>{i_header,i_len,i_crc,i_data}}); + `checks_w(128, {i_header, i_len, i_crc, i_data}, {>>{vlwide_pkt_128}}); + `checks_w(128, {>>{vlwide_pkt_128}}, {>>{i_header, i_len, i_crc, i_data}}); - qdata_pkt = {>>{i_header,i_len,i_crc,i_data,i_header,i_len,i_crc,i_data}}; + qdata_pkt = {>>{i_header, i_len, i_crc, i_data, i_header, i_len, i_crc, i_data}}; vlwide_pkt_128 = {>>{qdata_pkt}}; - `checks_w(256, {i_header,i_len,i_crc,i_data,i_header,i_len,i_crc,i_data},{>>{vlwide_pkt_128}}); - `checks_w(256, {>>{vlwide_pkt_128}},{>>{i_header,i_len,i_crc,i_data,i_header,i_len,i_crc,i_data}}); + `checks_w(256, {i_header, i_len, i_crc, i_data, i_header, i_len, i_crc, i_data}, + {>>{vlwide_pkt_128}}); + `checks_w(256, {>>{vlwide_pkt_128}}, + {>>{i_header, i_len, i_crc, i_data, i_header, i_len, i_crc, i_data}}); - qdata_pkt = {>>{i_header,i_len,i_crc,i_data,i_header,i_len,i_crc}}; + qdata_pkt = {>>{i_header, i_len, i_crc, i_data, i_header, i_len, i_crc}}; vlwide_pkt_128 = {>>{qdata_pkt}}; - `checks_w(256, {32'h0,i_header,i_len,i_crc,i_data,i_header,i_len,i_crc},{>>{vlwide_pkt_128}}); - `checks_w(256, {>>{vlwide_pkt_128}},{>>{32'h0,i_header,i_len,i_crc,i_data,i_header,i_len,i_crc}}); + `checks_w(256, {32'h0, i_header, i_len, i_crc, i_data, i_header, i_len, i_crc}, + {>>{vlwide_pkt_128}}); + `checks_w(256, {>>{vlwide_pkt_128}}, + {>>{32'h0, i_header, i_len, i_crc, i_data, i_header, i_len, i_crc}}); - vlwide_pkt_128 = {>>{i_header,i_len,i_crc,i_data}}; + vlwide_pkt_128 = {>>{i_header, i_len, i_crc, i_data}}; qdata_pkt = {>>{vlwide_pkt_128}}; - `checks_w(128, {i_header,i_len,i_crc,i_data},{>>{vlwide_pkt_128}}); - `checks_w(128, {>>{qdata_pkt}},{>>{i_header,i_len,i_crc,i_data}}); + `checks_w(128, {i_header, i_len, i_crc, i_data}, {>>{vlwide_pkt_128}}); + `checks_w(128, {>>{qdata_pkt}}, {>>{i_header, i_len, i_crc, i_data}}); $write("*-* All Finished *-*\n"); $finish; diff --git a/test_regress/t/t_stream_unpacked_array_struct.v b/test_regress/t/t_stream_unpacked_array_struct.v index 2b8f30b53..3293695a7 100644 --- a/test_regress/t/t_stream_unpacked_array_struct.v +++ b/test_regress/t/t_stream_unpacked_array_struct.v @@ -13,7 +13,7 @@ // source but then re-wrapped the now-packed expression in AstCvtArrayToPacked, // which EmitC dereferenced as an array. -module t( +module t ( input clk ); @@ -36,8 +36,8 @@ module t( wire [W-1:0] src = crc[W-1:0]; arr_t aw_r, aw_l; - always_comb {>>{aw_r}} = src; - always_comb {<<8{aw_l}} = src; + always_comb{>>{aw_r}} = src; + always_comb{<<8{aw_l}} = src; wire [W-1:0] rd_r = {>>{aw_r}}; wire [W-1:0] rd_l = {<<8{aw_l}}; // {<<{}} read of aggregate array previously crashed diff --git a/test_regress/t/t_stream_unpacked_struct.v b/test_regress/t/t_stream_unpacked_struct.v index 6b0c6f2d6..a1977204b 100644 --- a/test_regress/t/t_stream_unpacked_struct.v +++ b/test_regress/t/t_stream_unpacked_struct.v @@ -49,17 +49,11 @@ module t; byte suffix; } struct_array_t; - typedef struct { - byte data[1:0]; - } descending_array_t; + typedef struct {byte data[1:0];} descending_array_t; - typedef struct { - byte matrix[2][3]; - } matrix_array_t; + typedef struct {byte matrix[2][3];} matrix_array_t; - typedef struct { - logic [1:0][3:0] data[2]; - } mixed_array_t; + typedef struct {logic [1:0][3:0] data[2];} mixed_array_t; typedef enum logic [2:0] { E0 = 3'd0, @@ -137,7 +131,7 @@ module t; logic [$bits(simple_t)-1:0] simple_bits_from_bits; byte byte_array_out[2]; - assign {>>{simple_cont_out}} = 20'habcde; + assign{>>{simple_cont_out}} = 20'habcde; initial begin byteswapped_bits = {<<8{32'h11223344}}; @@ -341,11 +335,12 @@ module t; real_struct.ra[0] = 4.0; real_struct.ra[1] = 5.0; real_bits = {>>{real_struct}}; - `checkh(real_bits, - {8'h42, $realtobits(1.0), $realtobits(3.0), $realtobits(4.0), $realtobits(5.0)}); + `checkh(real_bits, { + 8'h42, $realtobits(1.0), $realtobits(3.0), $realtobits(4.0), $realtobits(5.0)}); - {>>{real_struct_out}} - = {8'h99, $realtobits(2.0), $realtobits(6.0), $realtobits(7.0), $realtobits(8.0)}; + {>>{real_struct_out}} = { + 8'h99, $realtobits(2.0), $realtobits(6.0), $realtobits(7.0), $realtobits(8.0) + }; `checkh(real_struct_out.tag, 8'h99); `checkh($realtobits(real_struct_out.r), $realtobits(2.0)); `checkh($realtobits(real_struct_out.rt), $realtobits(6.0)); diff --git a/test_regress/t/t_struct_param_public.v b/test_regress/t/t_struct_param_public.v index a9f698266..4ed9ffbaa 100644 --- a/test_regress/t/t_struct_param_public.v +++ b/test_regress/t/t_struct_param_public.v @@ -7,9 +7,7 @@ // verilator lint_off UNUSEDPARAM package P; - typedef struct { - int depth; - } memory_config_t; + typedef struct {int depth;} memory_config_t; typedef struct { memory_config_t memory; diff --git a/test_regress/t/t_timing_always.v b/test_regress/t/t_timing_always.v index c002c2b3d..f77ba1a65 100644 --- a/test_regress/t/t_timing_always.v +++ b/test_regress/t/t_timing_always.v @@ -18,28 +18,22 @@ module t; bit flag_a; bit flag_b; - always @(posedge clk) - begin + always @(posedge clk) begin `WRITE_VERBOSE(("[%0t] b <= 0\n", $time)); flag_b <= 1'b0; - #2 - `WRITE_VERBOSE(("[%0t] a <= 1\n", $time)); + #2 `WRITE_VERBOSE(("[%0t] a <= 1\n", $time)); flag_a <= 1'b1; - #2 - `WRITE_VERBOSE(("[%0t] b <= 1\n", $time)); + #2 `WRITE_VERBOSE(("[%0t] b <= 1\n", $time)); flag_b <= 1'b1; end - always @(flag_a) if ($time > 0) - begin - #1 - `WRITE_VERBOSE(("[%0t] Checking if b == 0\n", $time)); - if (flag_b !== 1'b0) $stop; - #2 - `WRITE_VERBOSE(("[%0t] Checking if b == 1\n", $time)); - if (flag_b !== 1'b1) $stop; - #10 - $write("*-* All Finished *-*\n"); - $finish; - end - initial #20 $stop; // timeout + always @(flag_a) + if ($time > 0) begin + #1 `WRITE_VERBOSE(("[%0t] Checking if b == 0\n", $time)); + if (flag_b !== 1'b0) $stop; + #2 `WRITE_VERBOSE(("[%0t] Checking if b == 1\n", $time)); + if (flag_b !== 1'b1) $stop; + #10 $write("*-* All Finished *-*\n"); + $finish; + end + initial #20 $stop; // timeout endmodule diff --git a/test_regress/t/t_timing_func_fork.v b/test_regress/t/t_timing_func_fork.v index f2ac78370..5b746731a 100644 --- a/test_regress/t/t_timing_func_fork.v +++ b/test_regress/t/t_timing_func_fork.v @@ -7,55 +7,69 @@ module t; function int f1; - fork begin - #1 $stop; - end join_none + fork + begin + #1 $stop; + end + join_none f1 = 0; endfunction function int f2; - fork begin - int x; - x = #5 0; $stop; - end join_none + fork + begin + int x; + x = #5 0; + $stop; + end + join_none f2 = 0; endfunction event e; function int f3; - fork begin - int x; - @e $stop; - x = 0; - end join_none + fork + begin + int x; + @e $stop; + x = 0; + end + join_none f3 = 0; endfunction function int f4; - fork begin - int x; - x = @e 0; $stop; - end join_none + fork + begin + int x; + x = @e 0; + $stop; + end + join_none f4 = 0; endfunction int i; function int f5; - fork begin - int x; - wait(i == 0) $stop; - x = 0; - end join_none + fork + begin + int x; + wait (i == 0) $stop; + x = 0; + end + join_none f5 = 0; endfunction initial begin - fork begin - i = f1(); - $write("*-* All Finished *-*\n"); - $finish; - end join_none + fork + begin + i = f1(); + $write("*-* All Finished *-*\n"); + $finish; + end + join_none end endmodule