diff --git a/src/verilog.l b/src/verilog.l index 811c32d03..ba8c96bd5 100644 --- a/src/verilog.l +++ b/src/verilog.l @@ -570,10 +570,7 @@ escid \\[^ \t\f\r\n]+ "->" {yylval.fileline = CRELINE(); return yP_MINUSGT;} "=>" {yylval.fileline = CRELINE(); return yP_EQGT; } "*>" {yylval.fileline = CRELINE(); return yP_ASTGT; } - "+=>" {yylval.fileline = CRELINE(); return yP_PLUSEQGT; } - "+*>" {yylval.fileline = CRELINE(); return yP_PLUSASTGT; } - "-=>" {yylval.fileline = CRELINE(); return yP_MINUSEQGT; } - "-*>" {yylval.fileline = CRELINE(); return yP_MINUSASTGT; } + "&&&" {yylval.fileline = CRELINE(); return yP_ANDANDAND; } } /* Verilog 2001 Operators */ @@ -583,12 +580,33 @@ escid \\[^ \t\f\r\n]+ "**" {yylval.fileline = CRELINE(); return yP_POW;} "+:" {yylval.fileline = CRELINE(); return yP_PLUSCOLON;} "-:" {yylval.fileline = CRELINE(); return yP_MINUSCOLON;} + ".*" {yylval.fileline = CRELINE(); return yP_DOTSTAR;} } /* SystemVerilog Operators */ { "==?" {yylval.fileline = CRELINE(); return yP_WILDEQUAL;} "!=?" {yylval.fileline = CRELINE(); return yP_WILDNOTEQUAL;} + "+=" {yylval.fileline = CRELINE(); return yP_PLUSEQ; } + "-=" {yylval.fileline = CRELINE(); return yP_MINUSEQ; } + "*=" {yylval.fileline = CRELINE(); return yP_TIMESEQ; } + "/=" {yylval.fileline = CRELINE(); return yP_DIVEQ; } + "%=" {yylval.fileline = CRELINE(); return yP_MODEQ; } + "&=" {yylval.fileline = CRELINE(); return yP_ANDEQ; } + "|=" {yylval.fileline = CRELINE(); return yP_OREQ; } + "^=" {yylval.fileline = CRELINE(); return yP_XOREQ; } + "<<=" {yylval.fileline = CRELINE(); return yP_SLEFTEQ; } + ">>=" {yylval.fileline = CRELINE(); return yP_SRIGHTEQ; } + "<<<=" {yylval.fileline = CRELINE(); return yP_SLEFTEQ; } + ">>>=" {yylval.fileline = CRELINE(); return yP_SSRIGHTEQ; } + "->>" {yylval.fileline = CRELINE(); return yP_MINUSGTGT; } + "##" {yylval.fileline = CRELINE(); return yP_POUNDPOUND; } + "@@" {yylval.fileline = CRELINE(); return yP_ATAT; } + "::" {yylval.fileline = CRELINE(); return yP_COLONCOLON; } + ":=" {yylval.fileline = CRELINE(); return yP_COLONEQ; } + ":/" {yylval.fileline = CRELINE(); return yP_COLONDIV; } + "|->" {yylval.fileline = CRELINE(); return yP_ORMINUSGT; } + "|=>" {yylval.fileline = CRELINE(); return yP_OREQGT; } } /* PSL Operators */ @@ -602,8 +620,8 @@ escid \\[^ \t\f\r\n]+ "[->" {yyerrorf("Unsupported: PSL operator not implemented: %s",yytext);} // yP_BRA_MINUS_GT "[->]" {yyerrorf("Unsupported: PSL operator not implemented: %s",yytext);} // yP_BRA_MINUS_GT_KET "[=" {yyerrorf("Unsupported: PSL operator not implemented: %s",yytext);} // yP_BRA_EQ - "|->" {yyerrorf("Unsupported: PSL operator not implemented: %s",yytext);} // yP_OR_MINUS_GT - "|=>" {yyerrorf("Unsupported: PSL operator not implemented: %s",yytext);} // yP_OR_EQ_GT + "|->" {yyerrorf("Unsupported: PSL operator not implemented: %s",yytext);} // yP_ORMINUSGT + "|=>" {yyerrorf("Unsupported: PSL operator not implemented: %s",yytext);} // yP_OREQGT } /* Identifiers and numbers */ @@ -653,6 +671,10 @@ escid \\[^ \t\f\r\n]+ yylval.cdouble = 0; /* Only for delays, not used yet */ return yaFLOATNUM; } + [0-9][_0-9]*(\.[_0-9]+)?(fs|ps|ns|us|ms|s|step) { + yylval.cdouble = 0; /* Only for times, not used yet */ + return yaFLOATNUM; + } } /************************************************************************/ diff --git a/src/verilog.y b/src/verilog.y index b4b8b9ae9..15fb80698 100644 --- a/src/verilog.y +++ b/src/verilog.y @@ -248,22 +248,44 @@ class AstSenTree; %token yP_PLUSCOLON "+:" %token yP_MINUSCOLON "-:" +%token yP_MINUSGTGT "->>" %token yP_EQGT "=>" %token yP_ASTGT "*>" -%token yP_PLUSEQGT "+=>" -%token yP_PLUSASTGT "+*>" -%token yP_MINUSEQGT "-=>" -%token yP_MINUSASTGT "-*>" +%token yP_ANDANDAND "&&&" +%token yP_POUNDPOUND "##" +%token yP_DOTSTAR ".*" + +%token yP_ATAT "@@" +%token yP_COLONCOLON "::" +%token yP_COLONEQ ":=" +%token yP_COLONDIV ":/" + +%token yP_PLUSEQ "+=" +%token yP_MINUSEQ "-=" +%token yP_TIMESEQ "*=" +%token yP_DIVEQ "/=" +%token yP_MODEQ "%=" +%token yP_ANDEQ "&=" +%token yP_OREQ "|=" +%token yP_XOREQ "^=" +%token yP_SLEFTEQ "<<=" +%token yP_SRIGHTEQ ">>=" +%token yP_SSRIGHTEQ ">>>=" %token yPSL_BRA "{" %token yPSL_KET "}" %token ';' '=' ',' '(' '.' '!' '~' '[' '@' +// [* is not a operator, as "[ * ]" is legal +// [= and [-> could be repitition operators, but to match [* we don't add them. +// '( is not a operator, as "' (" is legal +// '{ could be an operator. More research needed. + //******************** // PSL op precedence %right yP_MINUSGT yP_LOGIFF /* MinusGT == -> == PSL LogIf operator */ -%right yP_OR_MINUS_GT yP_OR_EQ_GT +%right yP_ORMINUSGT yP_OREQGT %left prPSLCLK // Verilog op precedence @@ -726,7 +748,7 @@ cellpinItList: cellpinItemE { $$ = $1; } ; cellpinItemE: /* empty: ',,' is legal */ { $$ = NULL; V3Parse::s_pinNum++; } - | '.' '*' { $$ = NULL; if (V3Parse::s_pinStar) $1->v3error("Duplicate .* in a cell"); V3Parse::s_pinStar=true; } + | yP_DOTSTAR { $$ = NULL; if (V3Parse::s_pinStar) $1->v3error("Duplicate .* in a cell"); V3Parse::s_pinStar=true; } | '.' yaID { $$ = new AstPin($1,V3Parse::s_pinNum++,*$2,new AstVarRef($1,*$2,false)); $$->svImplicit(true);} | '.' yaID '(' ')' { $$ = NULL; V3Parse::s_pinNum++; } | '.' yaID '(' expr ')' { $$ = new AstPin($1,V3Parse::s_pinNum++,*$2,$4); } @@ -1136,11 +1158,24 @@ specifyJunk: dlyTerm {} /* ignored */ | yP_LOGIFF {} | yPSL_BRA {} | yPSL_KET {} - | yP_OR_MINUS_GT {} - | yP_OR_EQ_GT {} + | yP_ORMINUSGT {} + | yP_OREQGT {} | yP_EQGT {} | yP_ASTGT {} - | yP_PLUSEQGT {} | yP_PLUSASTGT {} - | yP_MINUSEQGT {} | yP_MINUSASTGT {} + | yP_ANDANDAND {} + | yP_MINUSGTGT {} + | yP_POUNDPOUND {} + | yP_DOTSTAR {} + | yP_ATAT {} + | yP_COLONCOLON {} + | yP_COLONEQ {} + | yP_COLONDIV {} + + | yP_PLUSEQ {} | yP_MINUSEQ {} + | yP_TIMESEQ {} + | yP_DIVEQ {} | yP_MODEQ {} + | yP_ANDEQ {} | yP_OREQ {} + | yP_XOREQ {} + | yP_SLEFTEQ {} | yP_SRIGHTEQ {} | yP_SSRIGHTEQ {} | error {} ;