From 44fe8741f3517959e2924b6bfd94e923a9836051 Mon Sep 17 00:00:00 2001 From: Wilson Snyder Date: Fri, 2 Mar 2007 22:24:51 +0000 Subject: [PATCH] Add /*verilator public_flat*/ git-svn-id: file://localhost/svn/verilator/trunk/verilator@891 77ca24e4-aefa-0310-84f0-b9a241c72d87 --- Changes | 2 ++ bin/verilator | 15 ++++++++++++--- src/V3AstNodes.h | 7 ++++++- src/V3LinkResolve.cpp | 5 ++++- src/verilog.l | 1 + src/verilog.y | 4 +++- 6 files changed, 28 insertions(+), 6 deletions(-) diff --git a/Changes b/Changes index 27172d161..1cc24db0e 100644 --- a/Changes +++ b/Changes @@ -5,6 +5,8 @@ indicates the contributor was also the author of the fix; Thanks! * Verilator 3.63** +*** Add /*verilator public_flat*/. [Eugene Weber] + **** Try all +libext's in the exact order given. [Michael Shinkarovsky] **** Fix elimination of public signals assigned to constants. [Eugene Weber] diff --git a/bin/verilator b/bin/verilator index 50d299a70..7c1bd6a95 100755 --- a/bin/verilator +++ b/bin/verilator @@ -423,8 +423,8 @@ enable functional coverage. =item --public -This is only for debug, and may result in mis-simulation of generated -clocks. +This is only for historical debug use. Using it may result in +mis-simulation of generated clocks. Declares all signals and modules public. This will turn off signal optimizations as if all signals had a /*verilator public*/ comments and @@ -1138,7 +1138,8 @@ be pure; they cannot reference any variables outside the task itself. Used after a input, output, register, or wire declaration to indicate the signal should be declared so that C code may read or write the value -of the signal. +of the signal. This will also declare this module public, otherwise use +/*verilator public_flat*/. =item /*verilator public*/ (task/function) @@ -1160,6 +1161,14 @@ stored state (flops) should be written, as the model will NOT notice changes made to variables in these functions. (Same as when a signal is declared public.) +=item /*verilator public_flat*/ (variable) + +Used after a input, output, register, or wire declaration to indicate the +signal should be declared so that C code may read or write the value of the +signal. This will not declare this module public, which means the name of +the signal or path to it may change based upon the module inlining which +takes place. + =item /*verilator public_module*/ Used after a module statement to indicate the module should not be inlined diff --git a/src/V3AstNodes.h b/src/V3AstNodes.h index 24f82468d..384c116ed 100644 --- a/src/V3AstNodes.h +++ b/src/V3AstNodes.h @@ -236,6 +236,7 @@ private: bool m_scClocked:1; // SystemC sc_clk<> needed bool m_scSensitive:1;// SystemC sensitive() needed bool m_sigPublic:1; // User C code accesses this signal + bool m_sigModPublic:1;// User C code accesses this signal and module bool m_usedClock:1; // Signal used as a clock bool m_usedParam:1; // Parameter is referenced (on link; later signals not setup) bool m_funcLocal:1; // Local variable for a function @@ -252,7 +253,8 @@ private: m_primaryIO=false; m_sc=false; m_scClocked=false; m_scSensitive=false; m_usedClock=false; m_usedParam=false; - m_sigPublic=false; m_funcLocal=false; m_funcReturn=false; + m_sigPublic=false; m_sigModPublic=false; + m_funcLocal=false; m_funcReturn=false; m_attrClockEn=false; m_attrIsolateAssign=false; m_fileDescr=false; m_isConst=false; m_isStatic=false; m_trace=false; @@ -307,6 +309,7 @@ public: void usedClock(bool flag) { m_usedClock = flag; } void usedParam(bool flag) { m_usedParam = flag; } void sigPublic(bool flag) { m_sigPublic = flag; } + void sigModPublic(bool flag) { m_sigModPublic = flag; } void sc(bool flag) { m_sc = flag; } void scSensitive(bool flag) { m_scSensitive = flag; } void primaryIO(bool flag) { m_primaryIO = flag; } @@ -343,6 +346,7 @@ public: bool isScWide() const; bool isScSensitive() const { return m_scSensitive; } bool isSigPublic() const; + bool isSigModPublic() const { return m_sigModPublic; } bool isTrace() const { return m_trace; } bool isConst() const { return m_isConst; } bool isStatic() const { return m_isStatic; } @@ -374,6 +378,7 @@ public: propagateAttrFrom(typevarp); combineType(typevarp->varType()); if (typevarp->isSigPublic()) sigPublic(true); + if (typevarp->isSigModPublic()) sigModPublic(true); if (typevarp->attrScClocked()) attrScClocked(true); } void inlineAttrReset(const string& name) { diff --git a/src/V3LinkResolve.cpp b/src/V3LinkResolve.cpp index bba0369ef..0da121b93 100644 --- a/src/V3LinkResolve.cpp +++ b/src/V3LinkResolve.cpp @@ -78,7 +78,10 @@ private: nodep->v3error("Arrayed variables may not be inputs nor outputs"); } if (m_ftaskp) nodep->funcLocal(true); - if (nodep->isSigPublic()) m_modp->modPublic(true); // Avoid flattening if signals are exposed + if (nodep->isSigModPublic()) { + nodep->sigModPublic(false); // We're done with this attribute + m_modp->modPublic(true); // Avoid flattening if signals are exposed + } } virtual void visit(AstNodeVarRef* nodep, AstNUser*) { diff --git a/src/verilog.l b/src/verilog.l index 2b55246a6..6ca89f702 100644 --- a/src/verilog.l +++ b/src/verilog.l @@ -448,6 +448,7 @@ escid \\[^ \t\f\r\n]+ "/*verilator no_inline_task*/" {yylval.fileline = CRELINE(); return yVL_NO_INLINE_TASK;} "/*verilator parallel_case*/" {yylval.fileline = CRELINE(); return yVL_PARALLEL_CASE;} "/*verilator public*/" {yylval.fileline = CRELINE(); return yVL_PUBLIC;} +"/*verilator public_flat*/" {yylval.fileline = CRELINE(); return yVL_PUBLIC_FLAT;} "/*verilator public_module*/" {yylval.fileline = CRELINE(); return yVL_PUBLIC_MODULE;} "/*verilator sc_clock*/" {yylval.fileline = CRELINE(); return yVL_CLOCK;} "/*verilator isolate_assignments*/" {yylval.fileline = CRELINE(); return yVL_ISOLATE_ASSIGNMENTS;} diff --git a/src/verilog.y b/src/verilog.y index be06ea8c2..aaa15184d 100644 --- a/src/verilog.y +++ b/src/verilog.y @@ -169,6 +169,7 @@ class AstSenTree; %token yVL_NO_INLINE_TASK "/*verilator no_inline_task*/" %token yVL_PARALLEL_CASE "/*verilator parallel_case*/" %token yVL_PUBLIC "/*verilator public*/" +%token yVL_PUBLIC_FLAT "/*verilator public_flat*/" %token yVL_PUBLIC_MODULE "/*verilator public_module*/" %token yVL_ISOLATE_ASSIGNMENTS "/*verilator isolate_assignments*/" %token yVL_TRACING_OFF "/*verilator tracing_off*/" @@ -522,7 +523,8 @@ sigAttrList: sigAttr {} sigAttr: yVL_CLOCK { V3Parse::s_varAttrp->attrScClocked(true); } | yVL_CLOCK_ENABLE { V3Parse::s_varAttrp->attrClockEn(true); } - | yVL_PUBLIC { V3Parse::s_varAttrp->sigPublic(true); } + | yVL_PUBLIC { V3Parse::s_varAttrp->sigPublic(true); V3Parse::s_varAttrp->sigModPublic(true); } + | yVL_PUBLIC_FLAT { V3Parse::s_varAttrp->sigPublic(true); } | yVL_ISOLATE_ASSIGNMENTS { V3Parse::s_varAttrp->attrIsolateAssign(true); } ;