From 44bd8a0c14c44c78f6b073bfc432a9f655f2d529 Mon Sep 17 00:00:00 2001 From: Wilson Snyder Date: Sat, 13 Jun 2026 22:07:14 -0400 Subject: [PATCH] Commentary: Changes update --- Changes | 29 ++++- docs/spelling.txt | 1 + test_regress/t/t_case_inside_with_x.v | 20 +++- test_regress/t/t_case_priority_overlap.v | 5 +- test_regress/t/t_constraint_redops.v | 14 +-- test_regress/t/t_cover_fsm_concat_unsup.v | 6 +- test_regress/t/t_cover_fsm_sel.out | 22 ++-- test_regress/t/t_cover_fsm_sel.v | 22 ++-- test_regress/t/t_cover_fsm_sel_assign.out | 21 ++-- test_regress/t/t_cover_fsm_sel_assign.v | 21 ++-- .../t/t_cover_fsm_sel_togglevar_unsup.out | 12 +- .../t/t_cover_fsm_sel_togglevar_unsup.v | 25 ++-- test_regress/t/t_covergroup_param_bins.v | 6 +- test_regress/t/t_disable_fork_nested.v | 113 +++++++++--------- test_regress/t/t_fsm_duplicate.v | 62 ++++------ .../t/t_property_s_eventually_iface_param.v | 10 +- test_regress/t/t_select_bound_side_effect.v | 12 +- test_regress/t/t_stream_unpacked_struct.v | 3 +- 18 files changed, 217 insertions(+), 187 deletions(-) diff --git a/Changes b/Changes index fcb769eae..ced84ea4e 100644 --- a/Changes +++ b/Changes @@ -15,7 +15,7 @@ Verilator 5.049 devel **Important:** -* Support covergroups, coverpoints, and bins (#784) (#7117). [Matthew Ballance] +* Support covergroups, coverpoints, and bins (#784) (#7117) (#7728). [Matthew Ballance] * Support new FST writer API (#6871) (#6992). [Yu-Sheng Lin] Use of FST may requiring installing liblz4 and/or liblz4-dev packages, see docs/install.rst. @@ -27,9 +27,11 @@ Verilator 5.049 devel * Add `--coverage-per-instance` (#7636). [Yogish Sekhar] * Add NOTREDOP error on reduction and negation operators (#7417) (#7623) (#7624). * Add hierarchy-aware reporting to `verilator_coverage` (#7657). [Yogish Sekhar] +* Deprecate isolate_assignments attribute (#7774) (#7144). [Geza Lore, Testorrent USA, Inc.] * Improve `--coverage-fsm` (#7490) (#7529) (#7561) (#7573) (#7619). [Yogish Sekhar] * Change `+verilator+seed` to default to 1, and 0 to randomly select (#7325) (#7516). [Miguel] * Change JSON to include parameter constant mnemonics for FSM Coverage (#7531). [Yogish Sekhar] +* Support assert property 'default disable iff` (#4848) (#7723). [Artur Bieniek, Antmicro Ltd.] * Support printing enum names for %p and %s (#5523) (#7338 repair) (#7521) (#7527). [Nick Brereton] * Support weak `until` / `until_with` property operators (#7290) (#7548) (#7685). [Yilou Wang] * Support `s_eventually` (#7291) (#7508). [Bartłomiej Chmiel, Antmicro Ltd.] @@ -59,6 +61,12 @@ Verilator 5.049 devel * Support if/if-else in properties (#7692). [Artur Bieniek, Antmicro Ltd.] * Support process::self().srand() (#7695). [Igor Zaworski, Antmicro Ltd.] * Support MacOS lldb (#7697). [Tracy Narine] +* Support assoc array methods with wide value types (#7680). [pawelktk] +* Support property case (#7721). [Artur Bieniek, Antmicro Ltd.] +* Support `s_until` and `s_until_with`(#7722). [Artur Bieniek, Antmicro Ltd.] +* Support covergroup runtime model Phase A1 (#7728). [Matthew Ballance] +* Support reduction XOR/AND operations in constraints (#7753). [Kornel Uriasz, Antmicro Ltd.] +* Support unpacked struct stream (#7767). [Nick Brereton] * Optimize emitting to_string() for compiler speedup (#7468). [Jakub Michalski, Antmicro Ltd.] * Optimize additional DFG peephole cases (#7553). [Varun Koyyalagunta, Testorrent USA, Inc.] * Optimize forced signal handling (#7554 partial) (#7572) (#7594) (#7596). [Krzysztof Bieganski, Artur Bieniek, Antmicro Ltd.] @@ -71,8 +79,16 @@ Verilator 5.049 devel * Optimize runtime assertOn() checks (#7707). [Geza Lore, Testorrent USA, Inc.] * Optimize $countones and $onehot in DFG. [Geza Lore, Testorrent USA, Inc.] * Optimize procedural loop unrolling. [Geza Lore, Testorrent USA, Inc.] +* Optimize V3Gate inlining heuristic (#7716). [Geza Lore, Testorrent USA, Inc.] +* Optimize reset in DFG (#7737). [Geza Lore, Testorrent USA, Inc.] +* Optimize DFG with relaxed live variable analysis (#7739). [Geza Lore, Testorrent USA, Inc.] +* Optimize conditional patterns sharing common MBSs/LSBs in DfgPeephole (#7760). [Geza Lore, Testorrent USA, Inc.] +* Optimize bit select removal earlier in DFG (#7762). [Geza Lore, Testorrent USA, Inc.] +* Optimize away proven redundant case statement assertions (#7771). [Geza Lore, Testorrent USA, Inc.] +* Optimize table lookups in DFG (#7772). [Geza Lore, Testorrent USA, Inc.] * Fix TSP variable ordering for mtasks (#5342) (#7610). [Muzaffer Kal] * Fix inlining static initializer in V3Gate (#5381) (#7503). [Andrew Nolte] [Geza Lore, Testorrent USA, Inc.] +* Fix timed nested fork block with disable (#6720) (#7743). [Marco Bartoli] * Fix segmentation fault when using --trace with --lib-create (#7299) (#7518). [anonkey] * Fix destructive event state before dynamic waits (#7340). [Nick Brereton] * Fix ALWCOMBORDER on variable ordering (#7350) (#7608). [Cookie] @@ -128,6 +144,7 @@ Verilator 5.049 devel * Fix loss of events due to bit shift (#7670). [Artur Bieniek, Antmicro Ltd.] * Fix parameter read through locally-declared interface instance (#7679). [Nick Brereton] * Fix skipping nulls in $sscanf (#7689). +* Fix bounds checks in expressions with read/write references (#7694). [Ryszard Rozak, Antmicro Ltd.] * Fix (const) ref default task argument handling (#7698). [Nick Brereton] * Fix `ref` argument type check for packed arrays with differing range directions (#7700). [Nick Brereton] * Fix ignoring not-found modules with encoded names (#7706). [Igor Zaworski, Antmicro Ltd.] @@ -135,6 +152,16 @@ Verilator 5.049 devel * Fix Makefile action to not write to ${srcdir} (#7715). [Larry Doolittle] * Fix splitting functions containing fork logic (#7717). [Mateusz Gancarz, Antmicro Ltd.] * Fix optimizations of assignments with timing controls (#7718). [Ryszard Rozak, Antmicro Ltd.] +* Fix s_eventually on interface (#7731) (#7733). [Marco Bartoli] +* Fix parameter values in coverage bins widths (#7732) (#7734). [Marco Bartoli] +* Fix configure fall back on dynamic malloc libraries (#7736). [Geza Lore, Testorrent USA, Inc.] +* Fix crash on overlapping priority case. [Geza Lore, Testorrent USA, Inc.] +* Fix s_eventually in parameterized interfaces (#7741). [Nick Brereton] +* Fix dpi export pointers (#7742) (#7751). [Yilin Li] +* Fix FSM detect unchecked casts and variable redeclaration (#7758). [Adam Kostrzewski, Antmicro Ltd.] +* Fix no-scope internal error on virtual interface method calls (#7759). [Yilou Wang] +* Fix 'case (_) inside' with x wildcards (#7766). [Geza Lore, Testorrent USA, Inc.] + Verilator 5.048 2026-04-26 diff --git a/docs/spelling.txt b/docs/spelling.txt index a3565cb1d..c41825793 100644 --- a/docs/spelling.txt +++ b/docs/spelling.txt @@ -924,6 +924,7 @@ localparams localtime logicals longint +lookups lossy lsb lubc diff --git a/test_regress/t/t_case_inside_with_x.v b/test_regress/t/t_case_inside_with_x.v index 51a456c7a..935d779e8 100644 --- a/test_regress/t/t_case_inside_with_x.v +++ b/test_regress/t/t_case_inside_with_x.v @@ -18,12 +18,24 @@ module top; always @(posedge clk) begin // verilator lint_off CASEWITHX case (cyc) inside - 3'b000: begin $display("case inside 000"); ++count; end - 3'b001: begin $display("case inside 001"); ++count; end + 3'b000: begin + $display("case inside 000"); + ++count; + end + 3'b001: begin + $display("case inside 001"); + ++count; + end // Should match z - 3'b01?: begin $display("case inside 01?"); ++count; end + 3'b01?: begin + $display("case inside 01?"); + ++count; + end // Should match x - 3'b1xx: begin $display("case inside 1xx"); ++count; end + 3'b1xx: begin + $display("case inside 1xx"); + ++count; + end endcase // verilator lint_on CASEWITHX cyc <= cyc + 3'd1; diff --git a/test_regress/t/t_case_priority_overlap.v b/test_regress/t/t_case_priority_overlap.v index 2de27080a..9b7e794d6 100644 --- a/test_regress/t/t_case_priority_overlap.v +++ b/test_regress/t/t_case_priority_overlap.v @@ -26,8 +26,9 @@ module t; always_comb begin priority casez (in) - 2'b1?, // fully subsumes 2'b11 below on the same case clause - 2'b11: out = 2'b10; + 2'b1?, // fully subsumes 2'b11 below on the same case clause + 2'b11: + out = 2'b10; 2'b0?: out = 2'b01; endcase end diff --git a/test_regress/t/t_constraint_redops.v b/test_regress/t/t_constraint_redops.v index e285f8e24..5eff12a63 100644 --- a/test_regress/t/t_constraint_redops.v +++ b/test_regress/t/t_constraint_redops.v @@ -83,13 +83,13 @@ class test_redops_bitfields #(RANDVAL_BITWIDTH=8); endclass module t; - test_redops_bitfields #(.RANDVAL_BITWIDTH(1)) redops_1bit; - test_redops_bitfields #(.RANDVAL_BITWIDTH(8)) redops_8bit; - test_redops_bitfields #(.RANDVAL_BITWIDTH(16)) redops_16bit; - test_redops_bitfields #(.RANDVAL_BITWIDTH(32)) redops_32bit; - test_redops_bitfields #(.RANDVAL_BITWIDTH(47)) redops_47bit; - test_redops_bitfields #(.RANDVAL_BITWIDTH(63)) redops_63bit; - test_redops_bitfields #(.RANDVAL_BITWIDTH(64)) redops_64bit; + test_redops_bitfields #(.RANDVAL_BITWIDTH(1)) redops_1bit; + test_redops_bitfields #(.RANDVAL_BITWIDTH(8)) redops_8bit; + test_redops_bitfields #(.RANDVAL_BITWIDTH(16)) redops_16bit; + test_redops_bitfields #(.RANDVAL_BITWIDTH(32)) redops_32bit; + test_redops_bitfields #(.RANDVAL_BITWIDTH(47)) redops_47bit; + test_redops_bitfields #(.RANDVAL_BITWIDTH(63)) redops_63bit; + test_redops_bitfields #(.RANDVAL_BITWIDTH(64)) redops_64bit; test_redops_bitfields #(.RANDVAL_BITWIDTH(128)) redops_128bit; initial begin diff --git a/test_regress/t/t_cover_fsm_concat_unsup.v b/test_regress/t/t_cover_fsm_concat_unsup.v index 1f9cee77a..a7d9a1f84 100644 --- a/test_regress/t/t_cover_fsm_concat_unsup.v +++ b/test_regress/t/t_cover_fsm_concat_unsup.v @@ -5,9 +5,9 @@ // SPDX-License-Identifier: CC0-1.0 module t ( - input logic[6:0] a, - input logic b, - output logic c + input logic [6:0] a, + input logic b, + output logic c ); assign c = ({a, b} == 8'h00); diff --git a/test_regress/t/t_cover_fsm_sel.out b/test_regress/t/t_cover_fsm_sel.out index 4913f5502..a87e0569d 100644 --- a/test_regress/t/t_cover_fsm_sel.out +++ b/test_regress/t/t_cover_fsm_sel.out @@ -6,19 +6,16 @@ // SPDX-License-Identifier: CC0-1.0 package P; - typedef struct packed{ - logic [7:0] vs; - } C; - typedef struct packed{ - C a; int b; + typedef struct packed {logic [7:0] vs;} C; + typedef struct packed { + C a; + int b; } B; - typedef struct packed{ - B a; - } A; + typedef struct packed {B a;} A; endpackage module t ( -%000009 input clk +%000009 input clk ); typedef enum logic [1:0] { S_IDLE = 2'd0, @@ -84,9 +81,10 @@ %000003 a.a.a.vs <= a.a.a.vs + 1; %000003 done <= (a.a.a.vs == 8'h1); %000002 if (done) begin -%000001 state <= S_DONE; -%000002 end else begin -%000002 state <= S_RUN; +%000001 state <= S_DONE; + end +%000002 else begin +%000002 state <= S_RUN; end end %000002 S_DONE: state <= S_DONE; diff --git a/test_regress/t/t_cover_fsm_sel.v b/test_regress/t/t_cover_fsm_sel.v index a06275b03..732a63553 100644 --- a/test_regress/t/t_cover_fsm_sel.v +++ b/test_regress/t/t_cover_fsm_sel.v @@ -5,19 +5,16 @@ // SPDX-License-Identifier: CC0-1.0 package P; - typedef struct packed{ - logic [7:0] vs; - } C; - typedef struct packed{ - C a; int b; + typedef struct packed {logic [7:0] vs;} C; + typedef struct packed { + C a; + int b; } B; - typedef struct packed{ - B a; - } A; + typedef struct packed {B a;} A; endpackage module t ( - input clk + input clk ); typedef enum logic [1:0] { S_IDLE = 2'd0, @@ -74,9 +71,10 @@ module t ( a.a.a.vs <= a.a.a.vs + 1; done <= (a.a.a.vs == 8'h1); if (done) begin - state <= S_DONE; - end else begin - state <= S_RUN; + state <= S_DONE; + end + else begin + state <= S_RUN; end end S_DONE: state <= S_DONE; diff --git a/test_regress/t/t_cover_fsm_sel_assign.out b/test_regress/t/t_cover_fsm_sel_assign.out index c033ed2ef..1f0c3983e 100644 --- a/test_regress/t/t_cover_fsm_sel_assign.out +++ b/test_regress/t/t_cover_fsm_sel_assign.out @@ -6,11 +6,11 @@ // SPDX-License-Identifier: CC0-1.0 module t #( - parameter int unsigned W = 16, - parameter int unsigned D = 4, - parameter int unsigned BW = 2 + parameter int unsigned W = 16, + parameter int unsigned D = 4, + parameter int unsigned BW = 2 ) ( -%000009 input clk +%000009 input clk ); typedef enum logic [1:0] { S_IDLE = 2'd0, @@ -30,8 +30,7 @@ begin %000001 logic [D-1:0][W-1:0] s; begin -%000009 always_ff @(posedge clk) -%000009 s[b] <= a; +%000009 always_ff @(posedge clk) s[b] <= a; end end @@ -71,12 +70,14 @@ %000002 S_IDLE: %000001 if (start) state <= S_RUN; %000001 else state <= S_IDLE; -%000003 S_RUN: begin; +%000003 S_RUN: begin + ; %000003 done_arr[0] <= (a[0] == 1'b1); %000002 if (done_arr[0]) begin -%000001 state <= S_DONE; -%000002 end else begin -%000002 state <= S_RUN; +%000001 state <= S_DONE; + end +%000002 else begin +%000002 state <= S_RUN; end end %000002 S_DONE: state <= S_DONE; diff --git a/test_regress/t/t_cover_fsm_sel_assign.v b/test_regress/t/t_cover_fsm_sel_assign.v index 293fa4692..9f3ecca24 100644 --- a/test_regress/t/t_cover_fsm_sel_assign.v +++ b/test_regress/t/t_cover_fsm_sel_assign.v @@ -5,11 +5,11 @@ // SPDX-License-Identifier: CC0-1.0 module t #( - parameter int unsigned W = 16, - parameter int unsigned D = 4, - parameter int unsigned BW = 2 + parameter int unsigned W = 16, + parameter int unsigned D = 4, + parameter int unsigned BW = 2 ) ( - input clk + input clk ); typedef enum logic [1:0] { S_IDLE = 2'd0, @@ -29,8 +29,7 @@ module t #( begin logic [D-1:0][W-1:0] s; begin - always_ff @(posedge clk) - s[b] <= a; + always_ff @(posedge clk) s[b] <= a; end end @@ -61,12 +60,14 @@ module t #( S_IDLE: if (start) state <= S_RUN; else state <= S_IDLE; - S_RUN: begin; + S_RUN: begin + ; done_arr[0] <= (a[0] == 1'b1); if (done_arr[0]) begin - state <= S_DONE; - end else begin - state <= S_RUN; + state <= S_DONE; + end + else begin + state <= S_RUN; end end S_DONE: state <= S_DONE; diff --git a/test_regress/t/t_cover_fsm_sel_togglevar_unsup.out b/test_regress/t/t_cover_fsm_sel_togglevar_unsup.out index 9883741c3..4b76f7298 100644 --- a/test_regress/t/t_cover_fsm_sel_togglevar_unsup.out +++ b/test_regress/t/t_cover_fsm_sel_togglevar_unsup.out @@ -1,11 +1,11 @@ -%Warning-COVERIGN: t/t_cover_fsm_sel_togglevar_unsup.v:20:14: Coverage ignored for type ASSOCARRAYDTYPE +%Warning-COVERIGN: t/t_cover_fsm_sel_togglevar_unsup.v:19:16: Coverage ignored for type ASSOCARRAYDTYPE : ... note: In instance 't' - 20 | input P::A a, - | ^ + 19 | input P::A a, + | ^ ... For warning description see https://verilator.org/warn/COVERIGN?v=latest ... Use "/* verilator lint_off COVERIGN */" and lint_on around source to disable this message. -%Warning-COVERIGN: t/t_cover_fsm_sel_togglevar_unsup.v:20:14: Coverage ignored for type WILDCARDARRAYDTYPE +%Warning-COVERIGN: t/t_cover_fsm_sel_togglevar_unsup.v:19:16: Coverage ignored for type WILDCARDARRAYDTYPE : ... note: In instance 't' - 20 | input P::A a, - | ^ + 19 | input P::A a, + | ^ %Error: Exiting due to diff --git a/test_regress/t/t_cover_fsm_sel_togglevar_unsup.v b/test_regress/t/t_cover_fsm_sel_togglevar_unsup.v index 547a14d85..9be3e9a7a 100644 --- a/test_regress/t/t_cover_fsm_sel_togglevar_unsup.v +++ b/test_regress/t/t_cover_fsm_sel_togglevar_unsup.v @@ -5,21 +5,20 @@ // SPDX-License-Identifier: CC0-1.0 package P; - typedef struct { - logic [7:0] va[int]; - logic [7:0] vw[*]; - } C; - typedef struct { - C a; int b; - } B; - typedef struct { - B a; - } A; + typedef struct { + logic [7:0] va[int]; + logic [7:0] vw[*]; + } C; + typedef struct { + C a; + int b; + } B; + typedef struct {B a;} A; endpackage module t ( - input P::A a, - output logic b, - output logic c + input P::A a, + output logic b, + output logic c ); assign b = (a.a.a.va[0] == 8'h0); assign c = (a.a.a.vw[0] == 8'h0); diff --git a/test_regress/t/t_covergroup_param_bins.v b/test_regress/t/t_covergroup_param_bins.v index ab57a4a62..ece6521cb 100644 --- a/test_regress/t/t_covergroup_param_bins.v +++ b/test_regress/t/t_covergroup_param_bins.v @@ -26,10 +26,10 @@ module t #( covergroup cg; cp: coverpoint value { bins negative = {[PMIN : -1]}; // parameter as range lower bound - bins zero = {0}; + bins zero = {0}; bins positive = {[1 : LMAX]}; // localparam as range upper bound - bins maxv = {LMAX}; // localparam as single value - bins minv = {PMIN}; // parameter as single value + bins maxv = {LMAX}; // localparam as single value + bins minv = {PMIN}; // parameter as single value } endgroup diff --git a/test_regress/t/t_disable_fork_nested.v b/test_regress/t/t_disable_fork_nested.v index ad6a4d51e..de1b2526a 100644 --- a/test_regress/t/t_disable_fork_nested.v +++ b/test_regress/t/t_disable_fork_nested.v @@ -10,45 +10,45 @@ // block keeps iterating. module disable_fork ( - input logic i_clk, + input logic i_clk, output logic [2:0] o_counter ); - time delay1 = 500ns; // min period - time delay2 = 3333ns; // max period + time delay1 = 500ns; // min period + time delay2 = 3333ns; // max period - logic clk_re = 1'b0; // rising edge of the clock - logic [2:0] counter = 3'b000; + logic clk_re = 1'b0; // rising edge of the clock + logic [2:0] counter = 3'b000; - always begin - fork - begin : check1 - #delay1; - #1 disable check2; - fork - begin : check3 - #(delay2 - delay1); - clk_re <= 1'b0; - #1 disable check4; - if (counter < 3'b111) counter <= counter + 3'b001; - end - begin : check4 - @(posedge i_clk); - clk_re <= 1'b1; - counter <= 3'b000; - #1 disable check3; - end - join - end - begin : check2 - @(posedge i_clk); + always begin + fork + begin : check1 + #delay1; + #1 disable check2; + fork + begin : check3 + #(delay2 - delay1); clk_re <= 1'b0; - #1 disable check1; + #1 disable check4; if (counter < 3'b111) counter <= counter + 3'b001; - end - join - end + end + begin : check4 + @(posedge i_clk); + clk_re <= 1'b1; + counter <= 3'b000; + #1 disable check3; + end + join + end + begin : check2 + @(posedge i_clk); + clk_re <= 1'b0; + #1 disable check1; + if (counter < 3'b111) counter <= counter + 3'b001; + end + join + end - assign o_counter = counter; + assign o_counter = counter; endmodule // verilog_format: off @@ -57,30 +57,33 @@ endmodule // verilog_format: on module t; - logic clk; - logic [2:0] counter; + logic clk; + logic [2:0] counter; - task clk_cycle(input time half_period); - clk = 1'b1; - #half_period; - clk = 1'b0; - #half_period; - endtask : clk_cycle + task clk_cycle(input time half_period); + clk = 1'b1; + #half_period; + clk = 1'b0; + #half_period; + endtask : clk_cycle - initial begin - // Fast clock (period below delay1): every edge arrives before the - // min-period timeout, so the counter saturates at its max. - repeat (100) clk_cycle(200ns); - $display("Fast clock (200ns half-period): o_counter=%0d", counter); - `checkh(counter, 3'h7); - // Slow clock (period above delay2): the nested fork path runs, which - // only works if disabling check1 releases the inner fork..join. - repeat (100) clk_cycle(5400ns); - $display("Slow clock (5400ns half-period): o_counter=%0d", counter); - `checkh(counter, 3'h3); - $write("*-* All Finished *-*\n"); - $finish; - end + initial begin + // Fast clock (period below delay1): every edge arrives before the + // min-period timeout, so the counter saturates at its max. + repeat (100) clk_cycle(200ns); + $display("Fast clock (200ns half-period): o_counter=%0d", counter); + `checkh(counter, 3'h7); + // Slow clock (period above delay2): the nested fork path runs, which + // only works if disabling check1 releases the inner fork..join. + repeat (100) clk_cycle(5400ns); + $display("Slow clock (5400ns half-period): o_counter=%0d", counter); + `checkh(counter, 3'h3); + $write("*-* All Finished *-*\n"); + $finish; + end - disable_fork a_inst(.i_clk(clk), .o_counter(counter)); + disable_fork a_inst ( + .i_clk(clk), + .o_counter(counter) + ); endmodule diff --git a/test_regress/t/t_fsm_duplicate.v b/test_regress/t/t_fsm_duplicate.v index 20d7fd62e..c0edc5755 100644 --- a/test_regress/t/t_fsm_duplicate.v +++ b/test_regress/t/t_fsm_duplicate.v @@ -4,15 +4,14 @@ // SPDX-FileCopyrightText: 2026 Antmicro // SPDX-License-Identifier: CC0-1.0 -module rr -#( +module rr #( ) ( input logic clk, input logic rst, - input logic [7:0] data, - input logic data_q + input logic [7:0] data, + input logic data_q ); - logic a; + logic a; logic [15:0] dcnt; typedef enum logic [7:0] { S0, @@ -21,23 +20,21 @@ module rr S3 } state_t; state_t state_d, state_q; - always_ff @(posedge clk or negedge rst) - if (!rst) state_q <= S0; + always_ff @(posedge clk or negedge rst) if (!rst) state_q <= S0; always_ff @(posedge clk) unique case (state_q) - S1: if (a) dcnt[7:0] <= data; - S2: if (a) dcnt[15:8] <= data; - S3: if (data_q) dcnt <= dcnt - 1; + S1: if (a) dcnt[7:0] <= data; + S2: if (a) dcnt[15:8] <= data; + S3: if (data_q) dcnt <= dcnt - 1; default: dcnt <= dcnt; endcase endmodule -module re -#( +module re #( ) ( input logic clk, input logic rst, output logic o, - input unused0, /* block optimizations */ + input unused0, /* block optimizations */ input unused1, input unused2, input unused3, @@ -85,20 +82,18 @@ module re S1 } state_t; state_t state_d, state_q; - always_ff @(posedge clk or negedge rst) - if (!rst) state_q <= S0; + always_ff @(posedge clk or negedge rst) if (!rst) state_q <= S0; always_ff @(posedge clk) unique case (state_q) S1: o <= dcnt[0]; - default: o <= '0; + default: o <= '0; endcase initial begin $write("*-* All Finished *-*\n"); $finish; end endmodule -module rh -#( +module rh #( ) ( input logic clk ); @@ -110,24 +105,21 @@ module rh rr xrr ( .clk, .rst(rst), - .data (a), - .data_q (b & c) + .data(a), + .data_q(b & c) ); re xre ( .clk, .rst(rst), - .o (d) + .o(d) ); endmodule -module U -#( +module U #( ) ( input clk, input rst ); - rh xrh ( - .clk (clk) - ); + rh xrh (.clk(clk)); endmodule module C #( ) ( @@ -139,9 +131,7 @@ module C #( .rst ); endmodule -module A #( -) ( -); +module A #() (); logic clk; logic rst; C c0 ( @@ -153,9 +143,7 @@ module A #( .rst ); endmodule -module B #( -) ( -); +module B #() (); logic clk; logic rst; C xC ( @@ -163,11 +151,7 @@ module B #( .rst ); endmodule -module t #( -) ( -); - B b ( - ); - A a ( - ); +module t #() (); + B b (); + A a (); endmodule diff --git a/test_regress/t/t_property_s_eventually_iface_param.v b/test_regress/t/t_property_s_eventually_iface_param.v index 8d44f6373..6a76feabf 100644 --- a/test_regress/t/t_property_s_eventually_iface_param.v +++ b/test_regress/t/t_property_s_eventually_iface_param.v @@ -4,7 +4,11 @@ // SPDX-FileCopyrightText: 2026 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 -interface iface_if #(parameter int W = 8) (input bit clk); +interface iface_if #( + parameter int W = 8 +) ( + input bit clk +); logic [W-1:0] sig = 0; int passed = 0; assert property (@(posedge clk) s_eventually (sig == 1)) passed++; @@ -18,8 +22,8 @@ module t; // Two distinct specializations: V3Param clones the interface into two // modules, each with its own s_eventually tracking. The generated final // block must stay per-module. - iface_if #(.W(4)) a(.clk(clk)); - iface_if #(.W(8)) b(.clk(clk)); + iface_if #(.W(4)) a (.clk(clk)); + iface_if #(.W(8)) b (.clk(clk)); always @(posedge clk) begin ++cyc; diff --git a/test_regress/t/t_select_bound_side_effect.v b/test_regress/t/t_select_bound_side_effect.v index 5fd21bdc8..b6a182d04 100644 --- a/test_regress/t/t_select_bound_side_effect.v +++ b/test_regress/t/t_select_bound_side_effect.v @@ -32,10 +32,10 @@ module t; if (i < 5) `checkh(arr[i], expected); endtask - task automatic add_z(inout int a); - a += z; - z++; - endtask + task automatic add_z(inout int a); + a += z; + z++; + endtask task automatic assign_side_effect_inout(input int i, input int expected); if (i < 5) arr[i] = 1; @@ -63,8 +63,8 @@ module t; arr[get_y()] = i; if (y < 5) `checkh(arr[y], i); `checkh(y, 2 * i + 1); - arr[get_y() % (i + 1)] = i; - if (y % (i + 1) < 5) `checkh(arr[y % (i + 1)], i); + arr[get_y()%(i+1)] = i; + if (y % (i + 1) < 5) `checkh(arr[y%(i+1)], i); `checkh(y, 2 * (i + 1)); end diff --git a/test_regress/t/t_stream_unpacked_struct.v b/test_regress/t/t_stream_unpacked_struct.v index 509d8a035..8a169c20e 100644 --- a/test_regress/t/t_stream_unpacked_struct.v +++ b/test_regress/t/t_stream_unpacked_struct.v @@ -177,7 +177,8 @@ module t; if ($test$plusargs("t_stream_unpacked_struct_alt")) begin narrow_bits = 12'h123; - end else begin + end + else begin narrow_bits = 12'habd; end /* verilator lint_off WIDTHEXPAND */