From 42312101b5d253988a87a4cdec9962d3db3f84e9 Mon Sep 17 00:00:00 2001
From: Wilson Snyder <wsnyder@wsnyder.org>
Date: Wed, 3 Jun 2020 19:36:50 -0400
Subject: [PATCH] Tests: Add array OOB tests as unsupported (#792)

---
 test_regress/t/t_mem_bound_bad.pl | 21 +++++++++++++++++++++
 test_regress/t/t_mem_bound_bad.v  | 25 +++++++++++++++++++++++++
 2 files changed, 46 insertions(+)
 create mode 100755 test_regress/t/t_mem_bound_bad.pl
 create mode 100644 test_regress/t/t_mem_bound_bad.v

diff --git a/test_regress/t/t_mem_bound_bad.pl b/test_regress/t/t_mem_bound_bad.pl
new file mode 100755
index 000000000..6f9cc9875
--- /dev/null
+++ b/test_regress/t/t_mem_bound_bad.pl
@@ -0,0 +1,21 @@
+#!/usr/bin/env perl
+if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2003 by Wilson Snyder. This program is free software; you
+# can redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
+
+$Self->{vlt_all} and unsupported("Verilator unsupported, bug528");
+
+scenarios(linter => 1);
+
+lint(
+    fails => 1,
+    expect_filename => $Self->{golden_filename},
+    );
+
+ok(1);
+1;
diff --git a/test_regress/t/t_mem_bound_bad.v b/test_regress/t/t_mem_bound_bad.v
new file mode 100644
index 000000000..c2ec5fa16
--- /dev/null
+++ b/test_regress/t/t_mem_bound_bad.v
@@ -0,0 +1,25 @@
+// DESCRIPTION: Verilator: Verilog Test module
+//
+// This file ONLY is placed into the Public Domain, for any use,
+// without warranty, 2014 by Jie Xu
+// SPDX-License-Identifier: CC0-1.0
+
+module t(/*AUTOARG*/);
+   logic [1:0][31:0] tt;
+   logic [31:0]      a;
+   logic [31:0]      b;
+   logic [31:0]      c;
+
+   initial begin
+      a = 1;
+      b = 2;
+      c = 3;
+      tt[0] = a;
+      tt[1] = b;
+      tt[2] = c;  // Out of bounds
+      if (tt[0]!=a) $stop;
+      if (tt[1]!=b) $stop;
+      $write("*-* All Finished *-*\n");
+      $finish;
+   end
+endmodule