diff --git a/Changes b/Changes
index 8535878e6..d0db43c5e 100644
--- a/Changes
+++ b/Changes
@@ -17,6 +17,8 @@ The contributors that suggested a given feature are shown in []. Thanks!
 
 ****  Fix packages as enum base types, #2202. [Driss Hafdi]
 
+****  Fix duplicate typedefs in generate for, #2205. [hdzhangdoc]
+
 
 * Verilator 4.030 2020-03-08
 
diff --git a/src/V3Begin.cpp b/src/V3Begin.cpp
index 55b0e6596..8084dea5b 100644
--- a/src/V3Begin.cpp
+++ b/src/V3Begin.cpp
@@ -167,6 +167,18 @@ private:
             else m_modp->addStmtp(nodep);
         }
     }
+    virtual void visit(AstTypedef* nodep) VL_OVERRIDE {
+        if (m_unnamedScope != "") {
+            // Rename it
+            nodep->name(m_unnamedScope + "__DOT__" + nodep->name());
+            m_statep->userMarkChanged(nodep);
+            // Move to module
+            nodep->unlinkFrBack();
+            // Begins under funcs just move into the func
+            if (m_ftaskp) m_ftaskp->addStmtsp(nodep);
+            else m_modp->addStmtp(nodep);
+        }
+    }
     virtual void visit(AstCell* nodep) VL_OVERRIDE {
         UINFO(8,"   CELL "<<nodep<<endl);
         if (m_namedScope != "") {
diff --git a/test_regress/t/t_struct_genfor.pl b/test_regress/t/t_struct_genfor.pl
new file mode 100755
index 000000000..a4d74c0ba
--- /dev/null
+++ b/test_regress/t/t_struct_genfor.pl
@@ -0,0 +1,16 @@
+#!/usr/bin/perl
+if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2003 by Wilson Snyder. This program is free software; you
+# can redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
+
+scenarios(linter => 1);
+
+lint();
+
+ok(1);
+1;
diff --git a/test_regress/t/t_struct_genfor.v b/test_regress/t/t_struct_genfor.v
new file mode 100644
index 000000000..41af7634d
--- /dev/null
+++ b/test_regress/t/t_struct_genfor.v
@@ -0,0 +1,25 @@
+// DESCRIPTION: Verilator: Verilog Test module
+//
+// This file ONLY is placed under the Creative Commons Public Domain, for
+// any use, without warranty, 2013 by Wilson Snyder.
+// SPDX-License-Identifier: CC0-1.0
+
+module t ();
+
+   for (genvar g = 0; g < 2; ++g) begin : genfor
+      typedef struct packed {
+         logic [31:0] val1;
+         logic [31:0] val2;
+      } struct_t;
+      struct_t forvar;
+
+      initial begin
+         forvar.val1 = 1;
+         forvar.val2 = 2;
+         if (forvar.val1 != 1) $stop;
+         if (forvar.val2 != 2) $stop;
+         $write("*-* All Finished *-*\n");
+         $finish;
+      end
+   end
+endmodule