From 4070db99902f148e32ee349259021dcac55a6ae0 Mon Sep 17 00:00:00 2001
From: Igor Zaworski <izaworski@internships.antmicro.com>
Date: Thu, 4 Sep 2025 12:19:08 +0200
Subject: [PATCH] Fix rand variable inside constraint (#6315)

---
 src/V3Randomize.cpp                           |  6 ----
 .../t/t_randomize_from_randomized_class.py    | 21 +++++++++++++
 .../t/t_randomize_from_randomized_class.v     | 31 +++++++++++++++++++
 3 files changed, 52 insertions(+), 6 deletions(-)
 create mode 100755 test_regress/t/t_randomize_from_randomized_class.py
 create mode 100644 test_regress/t/t_randomize_from_randomized_class.v

diff --git a/src/V3Randomize.cpp b/src/V3Randomize.cpp
index 815a598a7..87d610dec 100644
--- a/src/V3Randomize.cpp
+++ b/src/V3Randomize.cpp
@@ -913,12 +913,6 @@ class ConstraintExprVisitor final : public VNVisitor {
         if (nodep->user1()) {
             nodep->v3warn(CONSTRAINTIGN, "Global constraints ignored (unsupported)");
         }
-        if (VN_IS(nodep->fromp(), NodeVarRef) && nodep->varp()->isRand() && m_inlineInitTaskp) {
-            iterateChildren(nodep);
-            nodep->replaceWith(nodep->fromp()->unlinkFrBack());
-            VL_DO_DANGLING(nodep->deleteTree(), nodep);
-            return;
-        }
         editFormat(nodep);
     }
     void visit(AstSFormatF* nodep) override {}
diff --git a/test_regress/t/t_randomize_from_randomized_class.py b/test_regress/t/t_randomize_from_randomized_class.py
new file mode 100755
index 000000000..466368b3d
--- /dev/null
+++ b/test_regress/t/t_randomize_from_randomized_class.py
@@ -0,0 +1,21 @@
+#!/usr/bin/env python3
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2025 by Wilson Snyder. This program is free software; you
+# can redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
+
+import vltest_bootstrap
+
+test.scenarios('simulator')
+
+if not test.have_solver:
+    test.skip("No constraint solver installed")
+
+test.compile()
+
+test.execute()
+
+test.passes()
diff --git a/test_regress/t/t_randomize_from_randomized_class.v b/test_regress/t/t_randomize_from_randomized_class.v
new file mode 100644
index 000000000..6ac6539f9
--- /dev/null
+++ b/test_regress/t/t_randomize_from_randomized_class.v
@@ -0,0 +1,31 @@
+// DESCRIPTION: Verilator: Verilog Test module
+//
+// This file ONLY is placed under the Creative Commons Public Domain, for
+// any use, without warranty, 2025 by Antmicro.
+// SPDX-License-Identifier: CC0-1.0
+
+class A;
+  rand int j;
+endclass
+
+class B;
+  A a;
+  rand int i;
+  function new();
+    a = new;
+    i = 7;
+  endfunction
+  task r();
+    if (a.randomize() with { j == i; } == 0) $stop;
+  endtask
+endclass
+
+module t;
+  initial begin
+    B b = new;
+    b.r();
+    if (b.a.j != 7) $stop;
+    $write("*-* All Finished *-*\n");
+    $finish;
+  end
+endmodule