From 4005cd33fba34dfe049cfd97aa955ce74f9c94e1 Mon Sep 17 00:00:00 2001 From: Matthew Ballance Date: Sat, 28 Feb 2026 20:49:22 +0000 Subject: [PATCH] Gate V3Covergroup pass on useCovergroup() flag Add v3Global.useCovergroup() flag (following the useRandSequence() pattern) that is set to true when a covergroup_declaration is parsed. Gate the V3Covergroup::covergroup() pass in Verilator.cpp on this flag so the pass is skipped entirely for designs with no covergroups. Co-authored-by: Copilot <223556219+Copilot@users.noreply.github.com> --- src/V3Global.h | 3 +++ src/Verilator.cpp | 2 +- src/verilog.y | 1 + 3 files changed, 5 insertions(+), 1 deletion(-) diff --git a/src/V3Global.h b/src/V3Global.h index 245cc05db..7e395eb31 100644 --- a/src/V3Global.h +++ b/src/V3Global.h @@ -130,6 +130,7 @@ class V3Global final { bool m_hasSystemCSections = false; // Has AstSystemCSection that need to be emitted bool m_useParallelBuild = false; // Use parallel build for model bool m_useRandSequence = false; // Has `randsequence` + bool m_useCovergroup = false; // Has covergroup declarations bool m_useRandomizeMethods = false; // Need to define randomize() class methods uint64_t m_currentHierBlockCost = 0; // Total cost of this hier block, used for scheduling @@ -213,6 +214,8 @@ public: void useParallelBuild(bool flag) { m_useParallelBuild = flag; } bool useRandSequence() const { return m_useRandSequence; } void useRandSequence(bool flag) { m_useRandSequence = flag; } + bool useCovergroup() const { return m_useCovergroup; } + void useCovergroup(bool flag) { m_useCovergroup = flag; } bool useRandomizeMethods() const { return m_useRandomizeMethods; } void useRandomizeMethods(bool flag) { m_useRandomizeMethods = flag; } void saveJsonPtrFieldName(const std::string& fieldName); diff --git a/src/Verilator.cpp b/src/Verilator.cpp index 03bbe29ff..61169eee3 100644 --- a/src/Verilator.cpp +++ b/src/Verilator.cpp @@ -226,7 +226,7 @@ static void process() { // Functional coverage code generation // Generate code for covergroups/coverpoints - V3Covergroup::covergroup(v3Global.rootp()); + if (v3Global.useCovergroup()) V3Covergroup::covergroup(v3Global.rootp()); // Resolve randsequence if they are used by the design if (v3Global.useRandSequence()) V3RandSequence::randSequenceNetlist(v3Global.rootp()); diff --git a/src/verilog.y b/src/verilog.y index 32a9d10ed..2350088cc 100644 --- a/src/verilog.y +++ b/src/verilog.y @@ -6907,6 +6907,7 @@ covergroup_declaration: // ==IEEE: covergroup_declaration /*cont*/ yENDGROUP endLabelE { AstClass *cgClassp = new AstClass{$2, *$2, PARSEP->libname()}; cgClassp->isCovergroup(true); + v3Global.useCovergroup(true); AstNode* sampleArgs = nullptr;