From 3f4fe7319101f1263d00e1ab0b02cca8b037f6f5 Mon Sep 17 00:00:00 2001
From: Wilson Snyder <wsnyder@wsnyder.org>
Date: Tue, 23 Dec 2025 19:20:36 -0500
Subject: [PATCH] Tests: Indent fixes

---
 test_regress/t/t_interface_modport_expr.v     |  4 +-
 .../t/t_interface_modport_expr_partsel.v      |  4 +-
 test_regress/t/t_interface_virtual_cond.v     |  2 +-
 test_regress/t/t_opt_inline_cfuncs.v          | 88 ++++++++++---------
 .../t/t_opt_inline_cfuncs_threshold.v         | 30 +++----
 5 files changed, 68 insertions(+), 60 deletions(-)

diff --git a/test_regress/t/t_interface_modport_expr.v b/test_regress/t/t_interface_modport_expr.v
index 112403ef7..9c69ed8c8 100644
--- a/test_regress/t/t_interface_modport_expr.v
+++ b/test_regress/t/t_interface_modport_expr.v
@@ -17,13 +17,13 @@ interface my_if;
 endinterface
 
 module mod1 (
-  my_if.mp1 i
+    my_if.mp1 i
 );
   assign i.b = i.a;
 endmodule
 
 module mod2 (
-  my_if.mp2 i
+    my_if.mp2 i
 );
   assign i.b = i.a;
 endmodule
diff --git a/test_regress/t/t_interface_modport_expr_partsel.v b/test_regress/t/t_interface_modport_expr_partsel.v
index e18b2bb43..b8b8f7f70 100644
--- a/test_regress/t/t_interface_modport_expr_partsel.v
+++ b/test_regress/t/t_interface_modport_expr_partsel.v
@@ -18,13 +18,13 @@ interface my_if;
 endinterface
 
 module mod1 (
-  my_if.mp1 i
+    my_if.mp1 i
 );
   assign i.out = i.in;
 endmodule
 
 module mod2 (
-  my_if.mp2 i
+    my_if.mp2 i
 );
   assign i.out = ~i.in;
 endmodule
diff --git a/test_regress/t/t_interface_virtual_cond.v b/test_regress/t/t_interface_virtual_cond.v
index 0f6824718..e0f74d1d0 100644
--- a/test_regress/t/t_interface_virtual_cond.v
+++ b/test_regress/t/t_interface_virtual_cond.v
@@ -9,7 +9,7 @@ interface Bus;
 endinterface
 
 module t;
-  Bus intf();
+  Bus intf ();
   virtual Bus vif;
 
   function logic get_vif(inout virtual Bus vif);
diff --git a/test_regress/t/t_opt_inline_cfuncs.v b/test_regress/t/t_opt_inline_cfuncs.v
index 6f95df5e6..b17dcce8f 100644
--- a/test_regress/t/t_opt_inline_cfuncs.v
+++ b/test_regress/t/t_opt_inline_cfuncs.v
@@ -6,53 +6,61 @@
 
 // Test module designed to generate multiple small CFuncs that can be inlined
 // Uses generate to create multiple sub-module instances
-module t (/*AUTOARG*/
-   // Inputs
-   clk
-   );
-   input clk;
+module t (  /*AUTOARG*/
+    // Inputs
+    clk
+);
+  input clk;
 
-   integer cyc = 0;
+  integer cyc = 0;
 
-   parameter CNT = 8;
+  parameter CNT = 8;
 
-   wire [31:0] w [CNT:0];
-   reg [31:0] w0;
-   assign w[0] = w0;
+  wire [31:0] w[CNT:0];
+  reg [31:0] w0;
+  assign w[0] = w0;
 
-   // Generate multiple sub-modules - each creates CFuncs that can be inlined
-   generate
-      for (genvar g=0; g<CNT; g++) begin : gen_sub
-         sub sub_inst (.clk(clk), .i(w[g]), .z(w[g+1]));
+  // Generate multiple sub-modules - each creates CFuncs that can be inlined
+  generate
+    for (genvar g = 0; g < CNT; g++) begin : gen_sub
+      sub sub_inst (
+          .clk(clk),
+          .i(w[g]),
+          .z(w[g+1])
+      );
+    end
+  endgenerate
+
+  // Test loop
+  always @(posedge clk) begin
+    cyc <= cyc + 1;
+    if (cyc == 0) begin
+      w0 <= 32'h10;
+    end
+    else if (cyc == 10) begin
+      // Each sub adds 1, so final value is 0x10 + 8 = 0x18
+      if (w[CNT] !== 32'h18) begin
+        $write("%%Error: w[CNT]=%0x, expected 0x18\n", w[CNT]);
+        $stop;
       end
-   endgenerate
-
-   // Test loop
-   always @ (posedge clk) begin
-      cyc <= cyc + 1;
-      if (cyc==0) begin
-         w0 <= 32'h10;
-      end
-      else if (cyc==10) begin
-         // Each sub adds 1, so final value is 0x10 + 8 = 0x18
-         if (w[CNT] !== 32'h18) begin
-            $write("%%Error: w[CNT]=%0x, expected 0x18\n", w[CNT]);
-            $stop;
-         end
-         $write("*-* All Finished *-*\n");
-         $finish;
-      end
-   end
+      $write("*-* All Finished *-*\n");
+      $finish;
+    end
+  end
 endmodule
 
 // Small sub-module that generates inlineable CFuncs
-module sub (input clk, input [31:0] i, output reg [31:0] z);
-   reg [7:0] local_a;
-   reg [7:0] local_b;
+module sub (
+    input clk,
+    input [31:0] i,
+    output reg [31:0] z
+);
+  reg [7:0] local_a;
+  reg [7:0] local_b;
 
-   always @(posedge clk) begin
-      local_a <= i[7:0];
-      local_b <= 8'd1;
-      z <= i + {24'b0, local_b};
-   end
+  always @(posedge clk) begin
+    local_a <= i[7:0];
+    local_b <= 8'd1;
+    z <= i + {24'b0, local_b};
+  end
 endmodule
diff --git a/test_regress/t/t_opt_inline_cfuncs_threshold.v b/test_regress/t/t_opt_inline_cfuncs_threshold.v
index 1970ece2e..8dd36ccd2 100644
--- a/test_regress/t/t_opt_inline_cfuncs_threshold.v
+++ b/test_regress/t/t_opt_inline_cfuncs_threshold.v
@@ -7,21 +7,21 @@
 // Test module to exercise threshold checking in CFunc inlining
 // With low thresholds, these functions should NOT be inlined
 module t;
-   reg [31:0] a, b, c, d, e, f, g, h;
+  reg [31:0] a, b, c, d, e, f, g, h;
 
-   initial begin
-      // Multiple operations to create larger CFuncs
-      a = 32'd1;
-      b = 32'd2;
-      c = a + b;
-      d = c * 2;
-      e = d - 1;
-      f = e + a;
-      g = f * b;
-      h = g + c + d + e + f;
+  initial begin
+    // Multiple operations to create larger CFuncs
+    a = 32'd1;
+    b = 32'd2;
+    c = a + b;
+    d = c * 2;
+    e = d - 1;
+    f = e + a;
+    g = f * b;
+    h = g + c + d + e + f;
 
-      if (h != 32'd32) $stop;
-      $write("*-* All Finished *-*\n");
-      $finish;
-   end
+    if (h != 32'd32) $stop;
+    $write("*-* All Finished *-*\n");
+    $finish;
+  end
 endmodule