diff --git a/test_regress/t/t_trace_array_saif.py b/test_regress/t/t_trace_array_saif.py
index 896cb0df9..9a271de06 100755
--- a/test_regress/t/t_trace_array_saif.py
+++ b/test_regress/t/t_trace_array_saif.py
@@ -1,8 +1,8 @@
 #!/usr/bin/env python3
-# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+# DESCRIPTION: Verilator: Verilog Test module
 #
-# Copyright 2024 by Wilson Snyder. This program is free software; you
-# can redistribute it and/or modify it under the terms of either the GNU
+# Copyright 2025 by Antmicro. This program is free software; you can
+# redistribute it and/or modify it under the terms of either the GNU
 # Lesser General Public License Version 3 or the Perl Artistic License
 # Version 2.0.
 # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
@@ -12,10 +12,11 @@ import vltest_bootstrap
 test.scenarios('vlt')
 test.top_filename = "t/t_trace_array.v"
 
-test.compile(verilator_flags2=['--cc --trace-saif --trace-structs'])
+test.compile(verilator_flags2=['--trace-saif --trace-structs'])
 
 test.execute()
 
-#test.fst_identical(test.trace_filename, test.golden_filename)
+#TODO: add checking if two SAIF files are identical
+#test.saif_identical(test.trace_filename, test.golden_filename)
 
 test.passes()