From 3aee7f918a13cd0ca5c87766c7f707f7f5a3901c Mon Sep 17 00:00:00 2001 From: Wilson Snyder Date: Wed, 16 May 2007 12:55:25 +0000 Subject: [PATCH] More cleanup to match VParse, and support celldefine properly git-svn-id: file://localhost/svn/verilator/trunk/verilator@922 77ca24e4-aefa-0310-84f0-b9a241c72d87 --- Changes | 2 ++ src/V3PreShell.cpp | 2 -- src/V3Read.h | 6 +++- src/verilog.l | 46 ++++++++++++++--------------- src/verilog.y | 72 +++++++++++++++++++++++++--------------------- 5 files changed, 70 insertions(+), 58 deletions(-) diff --git a/Changes b/Changes index 06d184de7..3d0c1f343 100644 --- a/Changes +++ b/Changes @@ -5,6 +5,8 @@ indicates the contributor was also the author of the fix; Thanks! * Verilator 3.65** +*** Treat modules within `celldefine and `endcelldefine as if in library. + **** Warn if flex is not installed. [Ralf Karge] * Verilator 3.650 4/20/2007 diff --git a/src/V3PreShell.cpp b/src/V3PreShell.cpp index 78207f31c..00e43ca06 100644 --- a/src/V3PreShell.cpp +++ b/src/V3PreShell.cpp @@ -62,8 +62,6 @@ protected: s_preprocp->define(prefl,"systemc_clock", "/*verilator systemc_clock*/"); s_preprocp->define(prefl,"coverage_block_off", "/*verilator coverage_block_off*/"); // Standards - We ignore - s_preprocp->define(prefl,"endcelldefine", ""); - s_preprocp->define(prefl,"celldefine", ""); s_preprocp->define(prefl,"resetall", ""); s_preprocp->define(prefl,"portcoerce", ""); s_preprocp->define(prefl,"inline", ""); diff --git a/src/V3Read.h b/src/V3Read.h index 46ff02c79..8e66dce17 100644 --- a/src/V3Read.h +++ b/src/V3Read.h @@ -38,7 +38,8 @@ class V3Read { V3Lexer* m_lexerp; // Current FlexLexer static V3Read* s_readp; // Current THIS, bison() isn't class based FileLine* m_fileline; // Filename/linenumber currently active - bool m_inLibrary; // Currently reading a library vs. regular file + bool m_inCellDefine; // Inside a `celldefine + bool m_inLibrary; // Currently reading a library vs. regular file int m_inBeginKwd; // Inside a `begin_keywords int m_lastVerilogState; // Last LEX state in `begin_keywords deque m_stringps; // Created strings for later cleanup @@ -92,6 +93,8 @@ public: // But for internal use only static FileLine* fileline() { return s_readp->m_fileline; } static AstNetlist* rootp() { return s_readp->m_rootp; } static FileLine* copyOrSameFileLine() { return s_readp->fileline()->copyOrSameFileLine(); } + static bool inCellDefine() { return s_readp->m_inCellDefine; } + static void inCellDefine(bool flag) { s_readp->m_inCellDefine = flag; } static bool inLibrary() { return s_readp->m_inLibrary; } static void stateExitPsl(); // Parser -> lexer communication static void statePushVlg(); // Parser -> lexer communication @@ -102,6 +105,7 @@ public: // CREATORS V3Read(AstNetlist* rootp) { m_rootp = rootp; m_lexerp = NULL; + m_inCellDefine = false; m_inLibrary = false; m_inBeginKwd = 0; m_lastVerilogState = stateVerilogRecent(); diff --git a/src/verilog.l b/src/verilog.l index 65c7d2f3f..6d559f346 100644 --- a/src/verilog.l +++ b/src/verilog.l @@ -109,6 +109,7 @@ void yyerrorf(const char* format, ...) { %s IGNORE ws [ \t\f\r]+ +wsnr [ \t\f]+ /* identifier */ id [a-zA-Z_][a-zA-Z0-9_$]* /* escaped identifier */ @@ -182,7 +183,7 @@ escid \\[^ \t\f\r\n]+ "not" {yylval.fileline = CRELINE(); return yNOT;} "or" {yylval.fileline = CRELINE(); return yOR;} "output" {yylval.fileline = CRELINE(); return yOUTPUT;} - "parameter" {yylval.fileline = CRELINE(); return yPARAM;} + "parameter" {yylval.fileline = CRELINE(); return yPARAMETER;} "posedge" {yylval.fileline = CRELINE(); return yPOSEDGE;} "reg" {yylval.fileline = CRELINE(); return yREG;} "scalared" {yylval.fileline = CRELINE(); return ySCALARED;} @@ -640,9 +641,6 @@ escid \\[^ \t\f\r\n]+ yylval.cdouble = 0; /* Only for delays, not used yet */ return yaFLOATNUM; } - - "`timescale"{ws}+[^\n]* {} - "`line"{ws}+[^\n]*\n {V3Read::ppline(yytext);} } /************************************************************************/ @@ -656,26 +654,29 @@ escid \\[^ \t\f\r\n]+ return yaSTRING; } /************************************************************************/ + /* Preprocessor*/ /* Common for all SYSC header states */ /* OPTIMIZE: we return one per line, make it one for the entire block */ { - [ \t]*"`verilog" { BEGIN V3Read::lastVerilogState(); } - [ \t]*"`psl" { if (V3Read::optPsl()) { BEGIN PSL; } else { BEGIN IGNORE; } } - [ \t]*"`systemc_header" { BEGIN SYSCHDR; } - [ \t]*"`systemc_ctor" { BEGIN SYSCCTOR; } - [ \t]*"`systemc_dtor" { BEGIN SYSCDTOR; } - [ \t]*"`systemc_interface" { BEGIN SYSCINT; } - [ \t]*"`systemc_implementation" { BEGIN SYSCIMP; } - [ \t]*"`systemc_imp_header" { BEGIN SYSCIMPH; } + "`celldefine" { V3Read::inCellDefine(true); } + "`endcelldefine" { V3Read::inCellDefine(false); } + "`line"{ws}+[^\n]*\n { V3Read::ppline(yytext); } + "`psl" { if (V3Read::optPsl()) { BEGIN PSL; } else { BEGIN IGNORE; } } + "`systemc_ctor" { BEGIN SYSCCTOR; } + "`systemc_dtor" { BEGIN SYSCDTOR; } + "`systemc_header" { BEGIN SYSCHDR; } + "`systemc_imp_header" { BEGIN SYSCIMPH; } + "`systemc_implementation" { BEGIN SYSCIMP; } + "`systemc_interface" { BEGIN SYSCINT; } + "`timescale"{ws}+[^\n]* {} + "`verilog" { BEGIN V3Read::lastVerilogState(); } - [ \t]*"`begin_keywords"[ \t]*\"1364-1995\" { yy_push_state(V95); V3Read::pushBeginKeywords(YY_START);} - [ \t]*"`begin_keywords"[ \t]*\"1364-2001\" { yy_push_state(V01); V3Read::pushBeginKeywords(YY_START);} - [ \t]*"`begin_keywords"[ \t]*\"1364-2001-noconfig\" { yy_push_state(V01); V3Read::pushBeginKeywords(YY_START);} - [ \t]*"`begin_keywords"[ \t]*\"1364-2005\" { yy_push_state(V05); V3Read::pushBeginKeywords(YY_START);} - [ \t]*"`begin_keywords"[ \t]*\"1800-2005\" { yy_push_state(S05); V3Read::pushBeginKeywords(YY_START);} - [ \t]*"`end_keywords" { yy_pop_state(); if (!V3Read::popBeginKeywords()) yyerrorf("`end_keywords when not inside `begin_keywords block"); } - - "`line"[ \t][^\n]*\n {V3Read::ppline(yytext);} + "`begin_keywords"[ \t]*\"1364-1995\" { yy_push_state(V95); V3Read::pushBeginKeywords(YY_START);} + "`begin_keywords"[ \t]*\"1364-2001\" { yy_push_state(V01); V3Read::pushBeginKeywords(YY_START);} + "`begin_keywords"[ \t]*\"1364-2001-noconfig\" { yy_push_state(V01); V3Read::pushBeginKeywords(YY_START);} + "`begin_keywords"[ \t]*\"1364-2005\" { yy_push_state(V05); V3Read::pushBeginKeywords(YY_START);} + "`begin_keywords"[ \t]*\"1800-2005\" { yy_push_state(S05); V3Read::pushBeginKeywords(YY_START);} + "`end_keywords" { yy_pop_state(); if (!V3Read::popBeginKeywords()) yyerrorf("`end_keywords when not inside `begin_keywords block"); } } [ \t]*[^` \t\n][^\n]*\n { NEXTLINE(); yylval.strp = V3Read::newString(yytext); return yaSCHDR;} @@ -688,7 +689,8 @@ escid \\[^ \t\f\r\n]+ /* Pick up text-type data */ { - [ \t]*\n { NEXTLINE(); yymore();} + {wsnr}* { yymore();} + \n { NEXTLINE(); yymore();} \r ; } @@ -697,9 +699,7 @@ escid \\[^ \t\f\r\n]+ { "`"[a-zA-Z_0-9]+ { yyerrorf("Define or directive not defined: %s",yytext); } - "//"[^\n]+ { } /* throw away single line comments */ - . {yylval.fileline = CRELINE(); return yytext[0];} /* return single char ops. */ } diff --git a/src/verilog.y b/src/verilog.y index 74ad2eebf..3fcb97e1e 100644 --- a/src/verilog.y +++ b/src/verilog.y @@ -30,7 +30,7 @@ #include "V3Ast.h" #include "V3Global.h" -#define YYERROR_VERBOSE +#define YYERROR_VERBOSE 1 #define YYMAXDEPTH 500 // Pick up new lexer @@ -83,11 +83,13 @@ AstVar* V3Parse::s_varAttrp = NULL; AstCase* V3Parse::s_caseAttrp = NULL; #define CRELINE() (V3Read::copyOrSameFileLine()) + #define VARRESET() { VARDECL(UNKNOWN); VARIO(UNKNOWN); VARSIGNED(false); VARRANGE(NULL); } #define VARDECL(type) { V3Parse::s_varDecl = AstVarType::type; } #define VARIO(type) { V3Parse::s_varIO = AstVarType::type; } #define VARSIGNED(value) { V3Parse::s_varSigned = value; } #define VARRANGE(range) { V3Parse::s_varRangep=(range); } + #define INSTPREP(modname,paramsp) { V3Parse::s_impliedDecl = true; V3Parse::s_instModule = modname; V3Parse::s_instParamp = paramsp; } //====================================================================== @@ -157,7 +159,7 @@ class AstSenTree; %token yDEFPARAM "defparam" %token yDO "do" %token yELSE "else" -%token yEND "bend" +%token yEND "end" %token yENDCASE "endcase" %token yENDFUNCTION "endfunction" %token yENDGENERATE "endgenerate" @@ -182,7 +184,7 @@ class AstSenTree; %token yNOT "not" %token yOR "or" %token yOUTPUT "output" -%token yPARAM "param" +%token yPARAMETER "parameter" %token yPOSEDGE "posedge" %token yPSL "psl" %token yREG "reg" @@ -295,9 +297,10 @@ class AstSenTree; %type netSig netSigList %type rangeListE regrangeE anyrange rangeList delayrange portRangeE %type param paramList +%type instDecl %type instnameList -%type instname -%type cellpinList cellpinItList cellpinitemE instparamListE +%type instnameParen +%type cellpinList cellpinItList cellpinItemE instparamListE %type defpList defpOne %type sensitivityE %type senList senitem senitemEdge @@ -339,18 +342,18 @@ class AstSenTree; //********************************************************************** // Feedback to the Lexer -stateExitPsl: { V3Read::stateExitPsl(); } +stateExitPsl: /* empty */ { V3Read::stateExitPsl(); } ; -statePushVlg: { V3Read::statePushVlg(); } +statePushVlg: /* empty */ { V3Read::statePushVlg(); } ; -statePop: { V3Read::statePop(); } +statePop: /* empty */ { V3Read::statePop(); } ; //********************************************************************** // Files -file: mod - | file mod +file: mod { } + | file mod { } ; //********************************************************************** @@ -362,19 +365,19 @@ mod: modHdr modParE modPortsE ';' modItemListE yENDMODULE ; modHdr: yMODULE { V3Parse::s_trace=v3Global.opt.trace();} - yaID { $$ = new AstModule($1,*$3); $$->inLibrary(V3Read::inLibrary()); + yaID { $$ = new AstModule($1,*$3); $$->inLibrary(V3Read::inLibrary()||V3Read::inCellDefine()); $$->modTrace(v3Global.opt.trace()); V3Read::rootp()->addModulep($$); } ; -modParE: /* empty */ { $$ = NULL; } - | '#' '(' ')' { $$ = NULL; } - | '#' '(' modParList ')' { $$ = $3; } - | '#' '(' modParList ';' ')' { $$ = $3; } +modParE: /* empty */ { $$ = NULL; } + | '#' '(' ')' { $$ = NULL; } + | '#' '(' modParList ')' { $$ = $3; } + | '#' '(' modParList ';' ')' { $$ = $3; } ; -modParList: modParDecl { $$ = $1; } - | modParList ';' modParDecl { $$ = $1->addNext($3); } +modParList: modParDecl { $$ = $1; } + | modParList ';' modParDecl { $$ = $1->addNext($3); } ; modPortsE: /* empty */ { $$ = NULL; } @@ -436,7 +439,7 @@ varNet: ySUPPLY0 { VARDECL(SUPPLY0); } | yWIRE { VARDECL(WIRE); } | yTRI { VARDECL(TRIWIRE); } ; -varGParam: yPARAM { VARDECL(GPARAM); } +varGParam: yPARAMETER { VARDECL(GPARAM); } ; varLParam: yLOCALPARAM { VARDECL(LPARAM); } ; @@ -498,12 +501,13 @@ modOrGenItem: yALWAYS sensitivityE stmtBlock { $$ = new AstAlways($1,$2,$3); } | yINITIAL stmtBlock { $$ = new AstInitial($1,$2); } | yASSIGN delayE assignList ';' { $$ = $3; } | yDEFPARAM defpList ';' { $$ = $2; } - | yaID instparamListE {INSTPREP(*$1,$2);} instnameList ';' { $$ = $4; V3Parse::s_impliedDecl=false;} + | instDecl { $$ = $1; } | taskDecl { $$ = $1; } | funcDecl { $$ = $1; } | gateDecl { $$ = $1; } | ioDecl { $$ = $1; } | varDecl { $$ = $1; } + //No: | tableDecl // Unsupported | pslStmt { $$ = $1; } ; @@ -570,8 +574,7 @@ dlyTerm: yaID { $$ = NULL; } | yaFLOATNUM { $$ = NULL; } ; -sigAndAttr: sigId { $$ = $1; } - | sigId sigAttrList { $$ = $1; } +sigAndAttr: sigId sigAttrListE { $$ = $1; } ; netSigList: netSig { $$ = $1; } @@ -598,11 +601,10 @@ sigList: sigAndAttr { $$ = $1; } | sigList ',' sigAndAttr { $$ = $1; $1->addNext($3); } ; -regsig: regSigId {} - | regSigId sigAttrList {} +regsig: regSigId sigAttrListE {} ; -sigAttrListE: /*empty*/ {} +sigAttrListE: /* empty */ {} | sigAttrList {} ; @@ -662,25 +664,27 @@ defpOne: yaID '.' yaID '=' expr { $$ = new AstDefParam($4,*$1,*$3,$5); } //************************************************ // Instances +instDecl: yaID instparamListE {INSTPREP(*$1,$2);} instnameList ';' { $$ = $4; V3Parse::s_impliedDecl=false;} + instparamListE: /* empty */ { $$ = NULL; } | '#' '(' cellpinList ')' { $$ = $3; } ; -instnameList: instname { $$ = $1; } - | instnameList ',' instname { $$ = $1->addNext($3); } +instnameList: instnameParen { $$ = $1; } + | instnameList ',' instnameParen { $$ = $1->addNext($3); } ; -instname: yaID funcRangeE '(' cellpinList ')' { $$ = new AstCell($3,*$1,V3Parse::s_instModule,$4,V3Parse::s_instParamp,$2); $$->pinStar(V3Parse::s_pinStar); } +instnameParen: yaID funcRangeE '(' cellpinList ')' { $$ = new AstCell($3,*$1,V3Parse::s_instModule,$4,V3Parse::s_instParamp,$2); $$->pinStar(V3Parse::s_pinStar); } ; cellpinList: {V3Parse::s_pinNum=1; V3Parse::s_pinStar=false; } cellpinItList { $$ = $2; } ; -cellpinItList: cellpinitemE { $$ = $1; } - | cellpinItList ',' cellpinitemE { $$ = $1->addNextNull($3)->castPin(); } +cellpinItList: cellpinItemE { $$ = $1; } + | cellpinItList ',' cellpinItemE { $$ = $1->addNextNull($3)->castPin(); } ; -cellpinitemE: /* empty */ { $$ = NULL; V3Parse::s_pinNum++; } +cellpinItemE: /* empty: ',,' is legal */ { $$ = NULL; V3Parse::s_pinNum++; } | '.' '*' { $$ = NULL; if (V3Parse::s_pinStar) $1->v3error("Duplicate .* in a cell"); V3Parse::s_pinStar=true; } | '.' yaID { $$ = new AstPin($1,V3Parse::s_pinNum++,*$2,new AstVarRef($1,*$2,false)); $$->svImplicit(true);} | '.' yaID '(' ')' { $$ = NULL; V3Parse::s_pinNum++; } @@ -1012,11 +1016,15 @@ gateXorPinList: expr { $$ = $1; } | gateXorPinList ',' expr { $$ = new AstXor($2,$1,$3); } ; +//************************************************ +// Tables +// Not supported + //************************************************ // Specify -specifyJunkList: specifyJunk /* ignored */ - | specifyJunkList specifyJunk /* ignored */ +specifyJunkList: specifyJunk {} /* ignored */ + | specifyJunkList specifyJunk {} /* ignored */ ; specifyJunk: dlyTerm {} /* ignored */